DSC encoder video input circuit, DSC encoder system and video input method

Abstract

This invention relates to the field of DSC encoder technology, and particularly to a video input circuit, DSC encoder system, and video input method for a DSC encoder. The circuit includes a pixel packetization module and a synchronous clock sampling module. The pixel packetization module generates a data packet every three pixel clock cycles, with each data packet having a width of three pixels. The synchronous clock sampling module generates a one-third pixel clock signal based on the clock signal in the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. This one-third pixel clock signal is used to directly sample the data packets generated by the pixel packetization module, and the sampled data packets are stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder. Compared to traditional asynchronous FIFOs, the synchronous clock sampling module of this solution eliminates read / write pointers and combinational logic, and also reduces the use of registers, thus saving chip area and chip cost.

Description

Technical Field

[0001] This invention relates to the field of DSC encoder technology, and in particular to a video input circuit, DSC encoder system, and video input method for a DSC encoder. Background Technology

[0002] Since DSC (Display Stream Compression) encoders typically operate in the one-third pixel clock domain, processing three pixels per clock cycle, while the video image data input to the DSC encoder typically operates in the pixel clock domain, outputting one pixel per clock cycle, a video input circuit is usually designed before the DSC encoder to complete the clock domain conversion.

[0003] However, existing DSC encoders typically use asynchronous FIFOs (first-in-first-out data buffers) to convert video data from the pixel clock domain to one-third of the pixel clock domain. To reduce the probability of metastability, asynchronous FIFOs are usually configured with multiple deep registers to slow down the rate of register changes, thereby reducing the probability of reading incorrect data when registers change. This requires more registers and combinational logic, resulting in a larger chip area and higher chip cost for the video input circuit of existing DSC encoders.

[0004] Therefore, there is an urgent need for a new video input circuit for a DSC encoder. Summary of the Invention

[0005] To address the issues of large chip area and high chip cost required for the video input circuit of existing DSC encoders, embodiments of the present invention provide a video input circuit, a DSC encoder system, and a video input method for a DSC encoder.

[0006] In a first aspect, embodiments of the present invention provide a video input circuit for a DSC encoder, comprising:

[0007] Pixel packing module and synchronous clock sampling module; among which,

[0008] The pixel packetization module is connected between the synchronous clock sampling module and the external video data input device; wherein, the video data input device operates in the pixel clock domain and is used to output one pixel data to the pixel packetization module at each pixel clock cycle; the pixel packetization module operates in the pixel clock domain and is used to generate a data packet every three pixel clock cycles, and the data width of each data packet is three pixels.

[0009] The synchronous clock sampling module is connected between the pixel packing module and the DSC encoder. The synchronous clock sampling module is used to generate a one-third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal is used to directly sample the data packet generated by the pixel packing module, and the sampled data packet is stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder. The number of the sampling registers is 1.

[0010] Secondly, embodiments of the present invention also provide a DSC encoder system, including: a video data input device, a DSC encoder, a DSC output module, and a video input circuit as described in any embodiment of this specification;

[0011] The video data input device is connected to the input terminal of the video input circuit and is used to output one pixel data to the video input circuit at each pixel clock cycle.

[0012] The DSC encoder is connected to the output terminal of the video input circuit and is used to encode the video data output by the video input circuit;

[0013] The DSC output module is connected to the DSC encoder and is used to perform clock domain conversion on the encoded data output by the DSC encoder.

[0014] Thirdly, embodiments of the present invention also provide a video input method based on the video input circuit described in any embodiment of this specification, including:

[0015] The pixel packing module is used to pack the pixel data input from the video data input device every three pixel clock cycles to generate several data packets with a data width of three pixels.

[0016] The synchronous clock sampling module generates a one-third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal is used to directly sample the data packet generated by the pixel packing module, and the sampled data packet is stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder; wherein, the number of the sampling registers is 1.

[0017] This invention provides a video input circuit, a DSC encoder system, and a video input method for a DSC encoder. The circuit includes a pixel packing module and a synchronous clock sampling module. First, the pixel packing module packs the pixel data input from the video data input device every three pixel clock cycles, generating several data packets with a data width of three pixels. Then, the synchronous clock sampling module generates a one-third pixel clock signal according to the clock signal in the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal can be used to directly sample the data packets generated by the pixel packing module in the pixel clock domain. Since the one-third pixel clock signal and the clock signal in the pixel clock domain are from the same clock source, as long as the frequency relationship between the one-third pixel clock signal and the pixel clock signal remains strictly unchanged, metastability can be avoided. Therefore, the synchronous clock sampling module only needs to be configured with one sampling register to store the sampled data of each one-third pixel clock cycle, so that the sampled data can be output to the DSC encoder in each cycle. As can be seen, compared with the asynchronous FIFO used in traditional video input circuits, the synchronous clock sampling module eliminates the asynchronous FIFO read / write pointers and combinational logic, and also reduces the use of registers. Therefore, this solution can save a lot of chip area, thereby saving chip cost and power consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the video input circuit of a DSC encoder in the prior art;

[0020] Figure 2 This is a waveform diagram of the video input circuit of a DSC encoder in the prior art;

[0021] Figure 3 This is a schematic diagram of an asynchronous FIFO storage method in the prior art;

[0022] Figure 4 This is a schematic diagram of the composition of a video input circuit of a DSC encoder according to an embodiment of the present invention;

[0023] Figure 5 This is a waveform diagram of a pixel packing module provided in an embodiment of the present invention;

[0024] Figure 6This is a waveform diagram of a video input circuit of a DSC encoder provided in an embodiment of the present invention;

[0025] Figure 7 This is a waveform diagram of the video input circuit of another DSC encoder provided in an embodiment of the present invention;

[0026] Figure 8 This is a waveform diagram of the video input circuit of another DSC encoder provided in an embodiment of the present invention;

[0027] Figure 9 This is a flowchart of a video input method provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0029] like Figure 1 As shown, the video input circuit of an existing DSC encoder typically includes a pixel packing module and an asynchronous FIFO. The pixel packing module includes a video receiving unit and a packing unit. (See reference...) Figure 2 The waveform diagram shows that `pixel_clock` is the pixel clock, `pixel_data` receives pixel data from a video data input device in each `pixel_clock` frame and transmits each received pixel data to the packetization unit, and `pixel_data_en` is a valid indication of received video data; `pixel_data` is valid only when `pixel_data_en` is high. `pixel_data_3p` and `pixel_data_en_3p` are the outputs of the packetization unit and also the inputs of the asynchronous FIFO. Here, `pixel_data_3p` and `pixel_data_en_3p` also operate in the pixel clock domain. The data width of `pixel_data_3p` is three times that of `pixel_data`, and it outputs 3 pixels only in the third of every 3 pixel clock frames. `pixel_data_en_3p` is a valid indication signal for `pixel_data_3p`; when `pixel_data_en_3p` is high, it indicates that the `pixel_data_3p` data is valid.

[0030] An asynchronous FIFO is a video data clock domain conversion module in the video input circuit of a traditional DSC encoder. The input port, i.e., the write port, of the asynchronous FIFO operates in the pixel clock domain. The write clock of the asynchronous FIFO input port is connected to the pixel_clock pixel clock, the write data port of the asynchronous FIFO input port is connected to the pixel_data_3p signal, and the write valid port of the asynchronous FIFO input port is connected to the pixel_data_en_3p signal. Figure 2 In this circuit, dsc_pixel_clock is the one-third pixel clock, which is connected to the read clock of the asynchronous FIFO output port. dsc_pixel_data is the read video data of the asynchronous FIFO output port, which operates in the one-third pixel clock domain. One clock cycle can output 3 pixels. dsc_data_en is the data validity indicator signal of the asynchronous FIFO output video data dsc_pixel_data, which also operates in the one-third pixel clock domain. dsc_pixel_data and dsc_data_en are also connected as output signals of the video input circuit to the DSC encoder, providing the DSC encoder with the video data to be encoded.

[0031] Typically, an asynchronous FIFO will receive two clock domain signals: one is the pixel clock domain, and the other is the one-third pixel clock domain. Since these two clock domain signals may not be from the same source, due to clock errors or error accumulation, the DSC encoder may sample data in a metastable state, i.e., reading data when the register changes. Therefore, it is necessary to set a multi-depth register to buffer data packets in order to reduce the probability of metastability.

[0032] For example, each dsc_pixel_data is stored sequentially in the asynchronous FIFO register in the output order, such as... Figure 3 As shown, the asynchronous FIFO has registers with 8 depths. Data packets (pixels 0, 1, 2) and (pixels 3, 4, 5) are written to registers 0 and 1 respectively, until the data packet is written to register 7. Then, it is written back to register 0, overwriting the video data originally stored in register 0. Similarly, reading data also starts from the beginning after one cycle. This asynchronous FIFO configuration with multiple register depths can slow down register changes. Originally, writing once per clock cycle meant that the data in the register changed once per clock cycle. Now, by writing in one cycle, the data in each register changes only once every eight clock cycles. This slows down register changes and avoids reading when registers are changing.

[0033] Therefore, traditional video input circuits use asynchronous FIFOs to complete the conversion of video data from the pixel clock domain to one-third of the pixel clock domain. In order to reduce the probability of metastability, asynchronous FIFOs are usually configured with multiple deep registers to slow down the change rate of the registers, thereby reducing the probability of reading incorrect data when the registers change. However, asynchronous FIFOs require more registers and combinational logic, which leads to a larger chip area and chip cost required for the video input circuit of existing DSC encoders.

[0034] To address the aforementioned technical issues, the inventors could consider generating a one-third pixel clock signal based on the pixel clock domain clock signal. By maintaining the frequency of this one-third pixel clock signal at one-third of the pixel clock signal's frequency, the DSC encoder can be precisely controlled to prevent data reading when the sampling register changes. This eliminates the need for multiple registers and control logic in an asynchronous FIFO to buffer data packets. Instead, the one-third pixel clock signal can be used to directly sample the data packets generated by the pixel packing module, and the sampled data packets can be stored in the single sampling register of the synchronous clock sampling module. This solution replaces the asynchronous FIFO with a synchronous clock sampling module and appropriately modifies the pixel packing module. The synchronous clock sampling module's internal implementation is very simple, far less complex than the asynchronous FIFO logic, and it directly samples three pixels of data width under the pixel clock domain using the one-third pixel clock signal. Taking a single pixel width of 24 bits as an example, the synchronous clock module only samples 3 pixels under each one-third pixel clock signal and buffers these 3 pixels for 1 clock cycle using a sampling register, which means there is only 1*3*24=72 bits of sampling register storage space. However, the depth of the asynchronous FIFO is usually set to 8, so the asynchronous FIFO requires 8*3*24=576 bits of register storage space. Moreover, the read / write pointers and control logic in the asynchronous FIFO also require a large number of registers and combinational logic. Therefore, this solution can greatly reduce the chip area, chip cost and power consumption of the video input circuit.

[0035] Please refer to Figure 4 This invention provides a video input circuit for a DSC encoder, comprising: a pixel packing module and a synchronous clock sampling module; wherein,

[0036] The pixel packetization module is connected between the synchronous clock sampling module and the external video data input device. The video data input device operates in the pixel clock domain and outputs one pixel data to the pixel packetization module at each pixel clock cycle. The pixel packetization module operates in the pixel clock domain and generates a data packet every three pixel clock cycles, with each data packet having a width of three pixels.

[0037] The synchronous clock sampling module is connected between the pixel packing module and the DSC encoder. The synchronous clock sampling module is used to generate a one-third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal is used to directly sample the data packets generated by the pixel packing module, and the sampled data packets are stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder. The number of sampling registers is 1.

[0038] In this embodiment of the invention, firstly, a pixel packing module packages the pixel data input from the video data input device every three pixel clock cycles, generating several data packets with a width of three pixels. Then, a synchronous clock sampling module generates a one-third pixel clock signal according to the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. This one-third pixel clock signal can then be used to directly sample the data packets generated by the pixel packing module in the pixel clock domain. Since the one-third pixel clock signal and the pixel clock domain clock signal share the same clock source, as long as the frequency relationship between the one-third pixel clock signal and the pixel clock signal remains strictly unchanged, metastability can be avoided. Therefore, the synchronous clock sampling module only needs to configure one sampling register to store the sampled data of each one-third pixel clock cycle, so that the sampled data can be output to the DSC encoder at each cycle. It is evident that compared to the asynchronous FIFO used in traditional video input circuits, the synchronous clock sampling module eliminates the asynchronous FIFO read / write pointers and combinational logic, and also reduces the use of registers. Therefore, this invention can save a significant amount of chip area, thereby saving chip cost and power consumption.

[0039] In some implementations, the pixel packing module is specifically used to store the three pixel data input from the video data input device every three pixel clock cycles into a three-pixel-wide register to output a data packet; at the same time, after the pixel data packing begins, a first indication signal indicating that the data packet is valid is output for each pixel clock cycle.

[0040] In this embodiment, reference can be made to Figure 5 The pixel packing module outputs a waveform. Figure 5 In this context, pixel_data_en is the first indicator signal, and pixel_data is the data packet. Figure 2Compared to the pixel_data and pixel_data_3p data in the previous embodiment, the pixel packetization module in this embodiment directly stores the three pixel data input from the video data input device into a three-pixel-wide register to generate a data packet. This data packet is valid for all three pixel clock cycles, allowing the synchronization clock sampling module to synchronously acquire the prioritized stored pixel data during the data packet generation process, unlike the previous method. Figure 2 The pixel packetization module shown needs to wait for the data packet to be generated before sending the write enable signal to the asynchronous FIFO. Furthermore, Figure 2 The pixel packing module first uses the video receiving unit to store each pixel data input from the video data input device separately, and then uses the packing unit to pack every three pixel data into a data packet at the last pixel clock. The pixel packing module in this embodiment does not require a video receiving unit, but directly writes every three pixel data into a three-pixel-wide register. Therefore, the pixel packing module in this embodiment eliminates the combinational logic of the video receiving unit and several single-pixel-width registers, reducing the chip area and chip cost.

[0041] In some implementations, the synchronous clock sampling module includes: a counting clock unit and a synchronous sampling unit;

[0042] The counting clock unit is connected to the pixel clock and is used to count the received clock signals. Every three clock signals are output as one-third pixel clock signals to the synchronous sampling unit.

[0043] The input of the synchronous sampling unit is connected to the pixel packing module and the counting clock unit, and the output is connected to the DSC encoder. The synchronous sampling unit is used to sample the data packets output by the pixel packing module based on the one-third pixel clock signal output by the counting clock unit and the first indication signal output by the pixel packing module, and stores the sampled data packets in the sampling register for output to the DSC encoder. At the same time, after sampling the data packets output by the pixel packing module, a second indication signal is output for each pixel clock after sampling to indicate that the video data in the sampling register is valid.

[0044] In this embodiment, the received clock signal is counted by the counting clock unit, and every three clock signals are output as one-third pixel clock signals to the synchronization sampling unit. The synchronization sampling unit samples the data packet generated by the pixel packing module based on the one-third pixel clock signal and the first indication signal, and generates a second indication signal.

[0045] In addition, the one-third pixel clock used by the DSC encoder and the one-third pixel clock of the synchronous clock sampling module are from the same clock source. It can be understood that the counting clock unit of the clock sampling module simultaneously transmits the generated one-third pixel clock signal to the DSC encoder as the working clock of the DSC encoder.

[0046] In this embodiment, a counter is used to generate a one-third pixel clock signal that is from the same source as the pixel clock domain. The logic of the counter method is relatively simple. It can be understood that, while ensuring a strict one-third clock ratio, other methods can also be used to generate the one-third pixel clock signal. For example, a phase-locked loop (PLL) can be used, with the input pixel clock configured to output a one-third pixel clock signal at one-third the frequency of the input clock, as long as the PLL is locked. Alternatively, a dedicated clock divider can be used to divide the pixel clock by three to generate the one-third pixel clock signal.

[0047] In embodiments of the present invention, the phase relationship between the pixel clock and the one-third pixel clock includes at least three typical types:

[0048] The first method: The rising edge of the clock signal for each third pixel of the counting clock unit is the rising edge of the clock signal for the second clock cycle of the corresponding data packet in the pixel packing module.

[0049] The first type is as follows Figure 6 As shown, each rising edge of the one-third pixel clock signal dsc_pixel_clock of the counting clock unit is the rising edge of the second clock signal of the corresponding data packet pixel_data in the pixel packing module. For example, after pixel0 is written to the three-pixel width register of the pixel packing module, the synchronous clock sampling module can start synchronous sampling to generate... Figure 6 The second indicator signal is dsc_pixel_data.

[0050] The second method: The rising edge of the clock signal for each third pixel of the counting clock unit is the rising edge of the clock signal for the third clock cycle of the corresponding data packet in the pixel packing module.

[0051] The second type is as follows Figure 7 As shown, each rising edge of the one-third pixel clock signal dsc_pixel_clock of the counting clock unit is the rising edge of the third clock signal of the corresponding data packet pixel_data in the pixel packing module. For example, after pixel1 is written to the three-pixel width register of the pixel packing module, the synchronous clock sampling module starts synchronous sampling to generate... Figure 7The second indicator signal is dsc_pixel_data.

[0052] The third type: The rising edge of the clock signal of each third pixel in the counting clock unit is the rising edge of the clock signal of the first clock of the next data packet in the corresponding data packet in the pixel packing module.

[0053] The third type, such as Figure 8 As shown, each rising edge of the one-third pixel clock signal dsc_pixel_clock of the counting clock unit is the rising edge of the third clock signal of the next data packet pixel_data in the pixel packing module. For example, after pixel2 is written to the three-pixel width register of the pixel packing module, the synchronous clock sampling module starts synchronous sampling to generate... Figure 8 The second indicator signal is dsc_pixel_data.

[0054] In some implementations, the sampling register needs to meet the setup and hold time requirements of the sampling register design.

[0055] In this embodiment, the synchronous clock sampling module must check the setup and hold times of the sampling register. That is, the pixel clock and the one-third pixel clock are synchronous clocks, and the sampling register located at the clock boundary between the pixel clock and the one-third pixel clock must meet the setup and hold time requirements of the register design so that the video data can be sampled correctly.

[0056] refer to Figure 4 The present invention also provides a DSC encoder system, including: a video data input device, a DSC encoder, a DSC output module, and a video input circuit as described in any embodiment of this specification;

[0057] The video data input device is connected to the input terminal of the video input circuit and is used to output one pixel data to the video input circuit at each pixel clock cycle.

[0058] The DSC encoder is connected to the output of the video input circuit and is used to encode the video data output by the video input circuit.

[0059] The DSC output module is connected to the DSC encoder and is used to perform clock domain conversion on the encoded data output by the DSC encoder.

[0060] Since the above system is based on the same concept as the circuit embodiment of the present invention, the specific details can be found in the description of the circuit embodiment of the present invention, and will not be repeated here.

[0061] like Figure 9 As shown, embodiments of the present invention also provide a video input method based on the video input circuit described in any embodiment of this specification, comprising:

[0062] Step 900: Use the pixel packing module to pack the pixel data input from the video data input device every three pixel clock cycles to generate several data packets with a data width of three pixels.

[0063] Step 902: The synchronous clock sampling module generates a one-third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal is used to directly sample the data packets generated by the pixel packing module, and the sampled data packets are stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder. The number of sampling registers is 1.

[0064] Since the above method is based on the same concept as the circuit embodiment of the present invention, the specific details can be found in the description of the circuit embodiment of the present invention, and will not be repeated here.

[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0066] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A video input circuit for a DSC encoder, characterized in that, include: Pixel packing module and synchronous clock sampling module; among which, The pixel packetization module is connected between the synchronous clock sampling module and the external video data input device; wherein, the video data input device operates in the pixel clock domain and is used to output one pixel data to the pixel packetization module at each pixel clock cycle; the pixel packetization module operates in the pixel clock domain and is used to generate a data packet every three pixel clock cycles, and the data width of each data packet is three pixels. The synchronous clock sampling module is connected between the pixel packing module and the DSC encoder. The synchronous clock sampling module is used to generate a one-third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal is used to directly sample the data packet generated by the pixel packing module, and the sampled data packet is stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder; wherein, the number of the sampling registers is 1. The pixel packing module is specifically used to store the three pixel data input from the video data input device every three pixel clock cycles into a three-pixel-wide register to output a data packet; at the same time, after the pixel data packing begins, a first indication signal indicating that the data packet is valid is output for each pixel clock cycle. The synchronous clock sampling module includes: a counting clock unit and a synchronous sampling unit; The counting clock unit is connected to the pixel clock and is used to count the received clock signals. Every three clock signals are output as one-third pixel clock signals to the synchronization sampling unit. The input of the synchronous sampling unit is connected to the pixel packing module and the counting clock unit, and the output is connected to the DSC encoder. The synchronous sampling unit is used to sample the data packets output by the pixel packing module based on the one-third pixel clock signal output by the counting clock unit and the first indication signal output by the pixel packing module, and store the sampled data packets in the sampling register for output to the DSC encoder. At the same time, after sampling the data packets output by the pixel packing module, a second indication signal is output for each pixel clock frame to indicate that the video data in the sampling register is valid.

2. The circuit according to claim 1, characterized in that, The rising edge of the first one-third pixel clock signal of the counting clock unit is the rising edge of the second clock signal of the corresponding data packet in the pixel packing module.

3. The circuit according to claim 1, characterized in that, The rising edge of each third pixel clock signal of the counting clock unit is the rising edge of the third clock signal of the corresponding data packet in the pixel packing module.

4. The circuit according to claim 1, characterized in that, The rising edge of the first clock signal of each third pixel in the counting clock unit is the rising edge of the first clock signal of the next data packet in the corresponding data packet in the pixel packing module.

5. The circuit according to any one of claims 1-4, characterized in that, The sampling register must meet the setup and hold time requirements of the sampling register design.

6. A DSC encoder system, characterized in that, include: Video data input device, DSC encoder, DSC output module and video input circuit as described in any one of claims 1-5; The video data input device is connected to the input terminal of the video input circuit and is used to output one pixel data to the video input circuit at each pixel clock cycle. The DSC encoder is connected to the output terminal of the video input circuit and is used to encode the video data output by the video input circuit; The DSC output module is connected to the DSC encoder and is used to perform clock domain conversion on the encoded data output by the DSC encoder.

7. A video input method based on the video input circuit according to any one of claims 1-5, characterized in that, include: The pixel packing module is used to pack the pixel data input from the video data input device every three pixel clock cycles to generate several data packets with a data width of three pixels. The synchronous clock sampling module generates a one-third pixel clock signal based on the clock signal of the pixel clock domain and the frequency relationship between the one-third pixel clock domain and the pixel clock domain. The one-third pixel clock signal is used to directly sample the data packet generated by the pixel packing module, and the sampled data packet is stored in the sampling register of the synchronous clock sampling module for output to the DSC encoder; wherein, the number of the sampling registers is 1.

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