A semiconductor integrated circuit and a method of manufacturing the same

Abstract

The application provides a semiconductor integrated circuit and a preparation method thereof. The semiconductor integrated circuit comprises a substrate, a peripheral circuit and a memory array which are stacked, one side of the substrate is provided with the peripheral circuit, the peripheral circuit is between the substrate and the memory array, and the substrate is provided with the peripheral circuit for controlling the memory array. The memory array comprises a plurality of memory cells, and the memory cell comprises a transistor structure. The transistor structure comprises a word line, a source, a first isolation layer and a drain which are sequentially stacked on a side of the peripheral circuit away from the substrate, and further comprises a channel. The channel is a hollow barrel structure, the inside of the channel is a gate, and the gate is connected with the word line. By using the stacking structure provided by the application, the memory density is directly improved by nearly one time without reducing the size of the transistor, thereby achieving the effect of evolution of traditional two to three generations of technology nodes.

Description

Technical Field

[0001] This article relates to, but is not limited to, a semiconductor integrated circuit and its fabrication method, and more particularly to, but is not limited to, a high-density dynamic random access memory (DRAM). Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of a cell array and peripheral circuitry, with the cell array occupying approximately 50% of the total chip area. The cell array and peripheral circuitry employ different transistor structures to achieve different functions. However, because current technologies use epitaxially grown single-crystal silicon as the channel material, the two types of transistors must be distributed on the same horizontal plane and processed using different fabrication processes. This structure has two significant drawbacks: first, the area utilization is relatively low, with the cell array occupying only half the area of ​​the entire chip; second, to balance the performance requirements of both types of transistors during planar fabrication, the fabrication process becomes complex, with numerous restrictions on process conditions and materials, resulting in a relatively small process window. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides a semiconductor integrated circuit, including: The substrate, peripheral circuitry, and memory array are stacked together. The memory array includes multiple memory cells, and each memory cell includes a transistor structure; The transistor structure includes: a word line, a source, a first isolation layer, and a drain, which are sequentially stacked on the side of the peripheral circuit away from the substrate, and also includes a channel; The channel has a hollow barrel-shaped structure, and the inside of the channel is a gate, which is connected to the word line. The channel passes through the surface of the source, the first isolation layer and the drain in sequence, and is connected to the drain. The channel is surrounded by the source, the first isolation layer and the drain.

[0005] In one embodiment provided in this application, the peripheral circuit is disposed on one side of the substrate, the peripheral circuit is located between the substrate and the memory array, or some or all of the peripheral circuit is disposed in the substrate.

[0006] In one embodiment provided in this application, the semiconductor integrated circuit further includes a third isolation layer located between the substrate and the memory array; The third isolation layer includes vias, through which the peripheral circuitry is connected to the memory array.

[0007] In one embodiment provided in this application, the channel is perpendicular to the substrate.

[0008] In one embodiment provided in this application, the transistor structure further includes a gate dielectric layer located between the channel and the gate.

[0009] In one embodiment provided in this application, the transistor structure further includes a second isolation layer, the second isolation layer being located on the surface of the word line and a third isolation layer not covered by the word line; The first isolation layer is located on the surface of the source electrode and the second isolation layer that is not covered by the source electrode.

[0010] In one embodiment provided in this application, the spacing between adjacent source electrodes is not less than the minimum feature size in the horizontal direction; the spacing between adjacent drain electrodes is not less than the minimum feature size in the horizontal direction; the spacing between adjacent word lines is not less than the minimum feature size in the horizontal direction; and the aperture in the channel is not less than the minimum feature size in the horizontal direction.

[0011] In one embodiment provided in this application, the materials of the source and the gate are each independently selected from any one or more of W, Mo, Al, W and Ta; The material of the channel is selected from any one or more of IGZO, ITO and IZO; The material of the gate dielectric layer is selected from silicon oxide and aluminum oxide, or one or more of them.

[0012] In one embodiment provided in this application, the storage array is stacked with the substrate in a direction perpendicular to the substrate.

[0013] In one embodiment provided in this application, a capacitor is provided on the side of the drain away from the substrate to form a DRAM structure with one transistor and one capacitor; or, a second transistor structure is provided on the side of the drain away from the substrate to form a DRAM structure with two transistors and zero capacitors. In one embodiment provided in this application, the capacitor or the second transistor structure may be coaxial with the channel.

[0014] In one embodiment provided in this application, the area of ​​the semiconductor structure projected onto the substrate is 4F. 2 F represents the minimum feature size in the horizontal direction of the semiconductor structure. In one embodiment provided in this application, the inner diameter of the channel is the minimum feature size.

[0015] In one embodiment provided in this application, the thickness and dimensions of the dielectric layer, the first isolation layer, the second isolation layer, and the third isolation layer can be determined according to actual needs.

[0016] Furthermore, this application provides a method for fabricating the aforementioned semiconductor integrated circuit, comprising the following steps: S10: Provides a substrate and sets up peripheral circuitry; S20: A word line, a source electrode, and a first isolation layer are sequentially stacked on one side of the peripheral circuit; S21: A through-hole is provided in the first isolation layer and the source electrode, and the through-hole ends at the surface of the word line; S22: An annular groove is provided on the inner wall of the opening; S23: A gate is disposed in the channel, and the gate is connected to the word line; S24: A channel material is provided on the gate surface, and the gate is surrounded by the channel; that is, the channel forms a hollow barrel shape, the gate material is inside the barrel structure, and the gate material is surrounded by the channel; the channel is perpendicular to the substrate or the channel is at a certain angle to the substrate; S30: The drain is disposed on the surface of the channel away from the substrate, such that the channel is surrounded by the drain, the first isolation layer, the source, the gate and the word line.

[0017] In one embodiment provided in this application, the method further includes the following after step S30: S31: A storage device is provided, wherein the storage device is electrically connected to the drain.

[0018] In one embodiment provided in this application, step S20 further includes: A third isolation layer is provided on the side of the substrate near the word line; A second isolation layer is disposed on the side of the word lines and the third isolation layer away from the substrate.

[0019] In one embodiment provided in this application, step S20 further includes: A via is provided on the third isolation layer, and the peripheral circuit is connected to the storage array through the via.

[0020] In one embodiment provided in this application, the step S22 of providing an annular channel on the inner wall of the opening includes: A groove is formed on the inner wall of the opening, and then the material covering the groove on the letter line is removed by anisotropic etching.

[0021] In one embodiment provided in this application, step S23 further includes: setting a gate dielectric layer, wherein the gate dielectric layer is located between the channel and the gate; Step S24 further includes: setting a gate dielectric layer, wherein the gate dielectric layer is located between the channel and the gate.

[0022] This application provides a novel DRAM memory cell structure, which constructs the memory array structure, which is originally on the same plane as the transistors in the peripheral circuit of the traditional DRAM, directly above the peripheral circuit, thereby greatly reducing the chip area. Furthermore, since the process flow does not need to take into account the limitations of the process materials, temperature and other conditions of the two types of transistors, the process flow is simplified and the process window is improved.

[0023] Currently, mainstream DRAM products at the tens of nanometers technology node achieve a storage density increase of about 20% to 30% with each generation of transistor miniaturization. By adopting the stacking structure provided in this application, the storage density can be nearly doubled without miniaturizing the transistor size, achieving the effect of traditional two to three generations of technology node evolution.

[0024] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application may be realized and obtained by means of the methods described in the description. Attached Figure Description

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0026] Figure 1 This is a schematic diagram of the substrate and the first isolation layer in the semiconductor integrated circuit provided in this application; Figure 2 A schematic diagram of the word line structure in the semiconductor integrated circuit provided in this application; Figure 3 A schematic diagram of word lines and bit lines in a semiconductor integrated circuit provided in this application; Figure 4 Schematic diagram of channel process in semiconductor integrated circuits provided in this application Figure 1 ; Figure 5 Schematic diagram of channel process in semiconductor integrated circuits provided in this application Figure 2 ; Figure 6 A schematic diagram of a semiconductor integrated circuit provided in this application.

[0027] Reference numerals: 1. Substrate; 101. Third isolation layer; 102. Via; 103. Second isolation layer; 104. First isolation layer; 2. Word line; 3. Bit line (source); 4. Gate; 401. Channel; 402. Gate dielectric layer. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application are described in detail below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0029] like Figures 1 to 6 As shown in the embodiments of this application, the method for fabricating a semiconductor integrated circuit includes the following steps: Step S10: Provide substrate 1.

[0030] For example, such as Figure 1 , 2 As shown in Figures 3 and 6, the substrate 1 serves as a support component for the dynamic random access memory (DRAM) and is used to support other components. Additionally, the substrate also contains peripheral circuitry for controlling the memory array. For example, the peripheral circuit can be disposed on the surface of one side of the substrate 1.

[0031] For example, the peripheral circuit transistor structure is formed using a standard silicon-based CMOS process. The transistor structure of the peripheral circuit can be selected from planar transistor structures, embedded word line transistor structures, fin field-effect transistor structures, or any other known type of silicon-based transistor structure.

[0032] Step S10 also includes S11: such as Figure 1 , 2 As shown in Figures 3 and 6, a third isolation layer 101 is provided on one side of the substrate 1, and a through-hole 102 is provided in the third isolation layer 101, through which the peripheral circuit is subsequently connected to the memory array.

[0033] For example, the third isolation layer 101 is disposed on the side that simplifies the connection between the substrate 1 and the memory array; For example, the material of the third isolation layer 101 can be any one or more of silicon nitride and silicon oxide.

[0034] S20: As Figure 2 and Figure 3 As shown, a fourth metal material is deposited on the side of the third isolation layer 101 away from the substrate 1 to form a fourth metal material layer, and the word line 2 is formed based on the fourth metal material layer.

[0035] For example, word lines 2 are formed on the fourth metal material layer by photolithography and etching, exposing the word line structure to the wafer surface and planarizing it, while avoiding photolithography and etching of the third isolation layer 101.

[0036] For example, the material of the fourth metal material layer is TiN, W, etc.

[0037] S21: As Figure 4 and Figure 5 As shown, a second isolation layer 103 is provided on the side of the third isolation layer 101 away from the substrate 1 and on the surface of the word line 2; the second isolation layer 103 is located on the surface of the word line 2 and the surface of the third isolation layer 101 not covered by the word line 2; For example, the material of the second isolation layer 103 can be any one or more of silicon nitride and silicon oxide; the material of the second isolation layer 101 and the third isolation layer 101 can be the same. For example, a second isolation layer 103 may be first disposed on the side of the third isolation layer 101 away from the substrate 1, and then a space for accommodating the fourth metal material may be etched in the second isolation layer 103, and then the fourth metal material may be deposited into the space (such as CMP damascene process) to form word lines 2.

[0038] S22: As Figure 3 , Figure 4 and Figure 5 As shown, a third metal material is deposited on the surface of the second isolation layer 103 on the side away from the substrate 1 to form a third metal material layer for forming bit line (source) 3.

[0039] For example, bit lines (sources) 3 are formed on the third metal material layer by photolithography and etching, while avoiding photolithography and etching of the second isolation layer 103.

[0040] For example, the third metal material is a metal material with low contact resistance to the channel material (the channel material can be IGZO, ITO, IZO, etc.), such as W, Mo, etc.

[0041] S23: As Figure 4 and Figure 5 As shown, a first isolation layer 104 is deposited on the surface of the bit line (source) 3 and the second isolation layer 104 not covered by the bit line (source) 3 on the side away from the substrate 1; For example, the material of the first isolation layer 104 can be any one or more of silicon nitride and silicon oxide.

[0042] For example, the material of the first isolation layer 104 may also be a low-K material or an air gap structure may be introduced to reduce crosstalk.

[0043] S24: As Figure 4 and Figure 5 As shown, a hole-like structure is formed, which sequentially penetrates the first isolation layer 104, the bit line (source) 3, and the second isolation layer 103, and terminates on the surface of the word line 2 away from the first isolation layer 104 or within the word line (word line) 2. For example, the hole structure is formed in the first isolation layer 104, the bit line (source) 3, the second isolation layer 103, and the word line 2 (or the surface of the word line 2 away from the first isolation layer 104) by photolithography and etching; S25: As Figure 4 and Figure 5 As shown, a channel 401 (metal oxide film), a gate dielectric layer 402, and a gate 4 are sequentially disposed on the inner surface of the hole structure, and the channel and the gate dielectric layer 402 do not cover the word line 2, and the word line 2 is connected to the gate 4.

[0044] For example, a channel 401 (metal oxide film), a gate dielectric layer 402 and a gate 4 are sequentially deposited on the inner surface of the porous structure to fill the porous structure.

[0045] For example, such as Figure 4 As shown, during the deposition of the channel 401 and the gate dielectric layer 402, the channel 401 or the gate dielectric layer 402 may cover the surface of the word line (gate to line segment) 2. The channel 401 (metal oxide film) and the gate dielectric layer 402 on the surface of the word line 2 can be removed by anisotropic etching, so that the gate 4 is directly connected to the word line 2.

[0046] For example, the material of the channel 401 (metal oxide film layer) can be IGZO, ITO, IZO, etc.

[0047] For example, the material of the gate dielectric layer 402 can be silicon oxide, aluminum oxide, hafnium oxide, etc.

[0048] For example, the material of the gate 4 is Al, W, Ta, etc.

[0049] For example, the excess material (material of channel 401 and material of gate dielectric layer 402) on the surface of the first isolation layer 104 and the surface of the hole structure is removed by CMP process, and the surface of the first isolation layer 104 is planarized.

[0050] S26: A gate dielectric layer 402 and a channel 401 (metal oxide film) are sequentially covered on the surface of the gate 4 on the side away from the substrate 1; so that the gate 4, except for the part connected to the word line 2, is sequentially surrounded by the gate dielectric layer 402 and the channel 401, forming a vertical annular channel transistor. S30: As Figure 6 As shown, a drain and a memory device are disposed on the surface of the channel 401 not covered by the first isolation layer 104. The memory device can be another transistor to form a 2T0C DRAM structure; or a capacitor to form a 1T1C DRAM structure. For example, the transistor and capacitor are fabricated using conventional fabrication processes in the art, and steps S10 to S26 can be repeated to fabricate a second transistor.

Claims

1. A semiconductor integrated circuit, characterized in that, include: The substrate, peripheral circuitry, and memory array are stacked together. The memory array includes multiple memory cells, and each memory cell includes a transistor structure; The transistor structure includes: a word line, a source, a first isolation layer, and a drain, which are sequentially stacked on the side of the peripheral circuit away from the substrate, and also includes a channel; The channel has a hollow barrel-shaped structure, and the inside of the channel is a gate, which is connected to the word line. The channel passes through the surface of the source, the first isolation layer and the drain in sequence, and is connected to the drain. The channel is surrounded by the source, the first isolation layer and the drain.

2. The semiconductor integrated circuit according to claim 1, wherein, The semiconductor integrated circuit further includes a third isolation layer located between the substrate and the memory array; The third isolation layer includes vias, through which the peripheral circuitry is connected to the memory array.

3. The semiconductor integrated circuit according to claim 2, wherein, The channel is perpendicular to the substrate.

4. The semiconductor integrated circuit according to claim 2, wherein, The transistor structure further includes a gate dielectric layer located between the channel and the gate.

5. The semiconductor integrated circuit according to claim 2, wherein, The transistor structure further includes a second isolation layer, which is located on the surface of the word line and a third isolation layer not covered by the word line; The first isolation layer is located on the surface of the source electrode and the second isolation layer that is not covered by the source electrode.

6. The semiconductor integrated circuit according to any one of claims 1 to 5, wherein, The spacing between adjacent source electrodes is not less than the minimum feature size in the horizontal direction; the spacing between adjacent drain electrodes is not less than the minimum feature size in the horizontal direction; the spacing between adjacent word lines is not less than the minimum feature size in the horizontal direction. The diameter of the aperture in the channel is not less than the minimum feature size in the horizontal direction.

7. The semiconductor integrated circuit according to claim 4, wherein, The source and the gate are each independently selected from any one or more of W, Mo, Al, W and Ta; The material of the channel is selected from any one or more of IGZO, ITO and IZO; The material of the gate dielectric layer is selected from silicon oxide and aluminum oxide, or one or more of them.

8. The semiconductor integrated circuit according to any one of claims 1 to 5, wherein the memory array is stacked with the substrate in a direction perpendicular to the substrate.

9. The semiconductor integrated circuit according to any one of claims 1 to 5, wherein, A DRAM structure with one transistor and one capacitor is formed by setting a capacitor on the side of the drain away from the substrate, or a second transistor structure is set on the side of the drain away from the substrate to form a DRAM structure with two transistors and zero capacitors. The capacitor or the second transistor structure is coaxial with the channel.

10. A method for fabricating a semiconductor integrated circuit according to any one of claims 1 to 9, characterized in that, Includes the following steps: S10: Provides a substrate and sets up peripheral circuitry; S20: A word line, a source electrode, and a first isolation layer are sequentially stacked on one side of the peripheral circuit; S21: A through-hole is provided in the first isolation layer and the source electrode, and the through-hole ends at the surface of the word line; S22: An annular groove is provided on the inner wall of the opening; S23: A gate is disposed in the channel, and the gate is connected to the word line; S24: A channel material is provided on the gate surface, and the gate is surrounded by the channel; S30: The drain is disposed on the surface of the channel away from the substrate, such that the channel is surrounded by the drain, the first isolation layer, the source, the gate and the word line.

11. The method for fabricating a semiconductor integrated circuit according to claim 10, wherein, The process after step S30 also includes: S31: A storage device is provided, wherein the storage device is connected to the drain.

12. The method for fabricating a semiconductor integrated circuit according to claim 11, wherein, Step S20 also includes: A third isolation layer is provided on the side of the substrate near the word line; A second isolation layer is disposed on the side of the word lines and the third isolation layer away from the substrate.

13. The method for fabricating a semiconductor integrated circuit according to claim 12, wherein, Step S20 also includes: A via is provided on the third isolation layer, and the peripheral circuit is connected to the storage array through the via.

14. The method for fabricating a semiconductor integrated circuit according to any one of claims 10 to 12, wherein, The step S22, which involves setting an annular channel on the inner wall of the opening, includes: A groove is formed on the inner wall of the opening, and then the material covering the groove on the letter line is removed by anisotropic etching.

15. The method for fabricating a semiconductor integrated circuit according to any one of claims 10 to 12, wherein, Step S23 further includes: setting a gate dielectric layer, wherein the gate dielectric layer is located between the channel and the gate; Step S24 further includes: setting a gate dielectric layer, wherein the gate dielectric layer is located between the channel and the gate.

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