NOR-type memory device, method of manufacturing the same, and electronic device

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a NOR type memory device, a preparation method thereof and an electronic device. The memory device comprises a substrate, a memory cell layer located above the substrate, the memory cell layer comprising a source / drain layer and a channel layer which are stacked in sequence, and a gate stack formed in the memory cell layer and vertically extending relative to the substrate to pass through the memory cell layer, the gate stack comprising a first gate conductor layer and a storage function layer arranged at the periphery of the first gate conductor layer, an epitaxial transistor being arranged below the gate stack, and a second gate conductor layer serving as a gate of the epitaxial transistor and being arranged in a circumferential direction of the epitaxial transistor. The epitaxial transistor is used for controlling and providing current loading of the first gate conductor layer in a non-working state. Under the large current, the first gate conductor layer conducts heat, the local temperature of the device is increased, the technical effect of annealing the storage function layer is achieved, the damage of the storage function layer is finally repaired, the data retention time is prolonged, and the reliability of the device is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a NOR type memory device, its fabrication method, and an electronic device. Background Technology

[0002] In horizontal devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), the source, gate, and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices are difficult to further miniaturize. In contrast, in vertical devices, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to integrate than horizontal devices.

[0003] The hierarchical structure composed of SRAM, DRAM and 3D NAND is the main storage device in modern computing systems. NOR memory has advantages such as fast random access speed, high reliability and long service life, and plays an irreplaceable role in artificial intelligence, automotive electronics and industrial fields.

[0004] However, due to continuous programming and erasing during use, the quality of the storage medium deteriorates, affecting the durability and data retention time of NOR storage devices. Summary of the Invention

[0005] The technical objective of this application is to at least solve the problem that the durability and data retention time of NOR-type memory devices are affected by continuous programming and erasure during use.

[0006] This objective is achieved through the following technical solutions:

[0007] In a first aspect, this application provides a NOR-type storage device, comprising:

[0008] Substrate;

[0009] Storage cell layer: consists of source / drain layers and channel layers stacked sequentially;

[0010] Gate stack: extending vertically relative to the substrate to pass through the memory cell layer; the gate stack includes a first gate conductor layer and a memory function layer disposed on the periphery of the first gate conductor layer;

[0011] Epitaxial transistor: disposed below the gate stack and connected to the first gate conductor layer;

[0012] Second gate conductor layer: disposed circumferentially around the epitaxial transistor;

[0013] The epitaxial transistor is used to control and provide current loading of the first gate conductor layer in the non-operating state.

[0014] The device designed in this application includes an epitaxial transistor located below the gate stack. This epitaxial transistor is used to control and provide current loading for the first gate conductor layer in the non-operating state. Under this large current, the first gate conductor conducts electricity and generates heat, and the local temperature of the device is increased, achieving the technical effect of annealing the storage function layer. Ultimately, the damage to the storage function layer is repaired and the data retention time is extended, thereby improving the reliability of the device.

[0015] In some embodiments of this application, the epitaxial transistor comprises a plurality of transistors, which are connected in parallel and controlled by the second gate conductor layer.

[0016] In some embodiments of this application, the epitaxial transistor includes an NPN type doped layer or a PNP type doped layer formed by sequentially stacking together;

[0017] Each doped layer is formed by in-situ doping using an epitaxial method.

[0018] In some embodiments of this application, the material of the epitaxial transistor includes any one of Si, Ge, and SiGe.

[0019] In some embodiments of this application, a contact layer is provided between the epitaxial transistor and the first gate conductor layer;

[0020] The contact layer is made of metal silicide.

[0021] In some embodiments of this application, a first conductive metal is provided at the top of the first gate conductor layer, and the first conductive metal is connected to a selection transistor.

[0022] In some embodiments of this application, one end of the selection transistor is connected to a high voltage and the other end is connected to a first conductive metal. By controlling the conduction of the selection transistor, current is applied to the first gate conductor layer to make it conductive and generate heat. The two ends of the selection transistor refer to its source and drain terminals, respectively.

[0023] In some embodiments of this application, the storage functional layer includes a tunneling layer, a storage layer, and a blocking layer;

[0024] The tunneling layer, storage layer, and barrier layer are formed by one or more of oxidation, atomic layer deposition, or chemical vapor deposition.

[0025] In some embodiments of this application, the first gate conductor layer and the second gate conductor layer are made of polycrystalline silicon or metal gate material, wherein the metal gate material comprises tungsten or aluminum.

[0026] In some embodiments of this application, the device further includes at least one contact portion distributed around the gate stack, each of the contact portions extending vertically relative to the substrate into the memory cell layer.

[0027] In some embodiments of this application, the device further includes a bit line and a source terminal;

[0028] The source / drain layer is led out through the contact portion and connected to the bit line / source terminal.

[0029] A second aspect of this application is to provide a method for fabricating a NOR-type memory device, comprising:

[0030] A sacrificial layer and a memory cell layer are sequentially disposed on a substrate, wherein the memory cell layer includes a source / drain layer and a channel layer stacked sequentially.

[0031] Forming gate holes that extend vertically relative to the substrate to pass through the memory cell layer;

[0032] An epitaxial transistor and a gate stack are sequentially formed within the gate hole. The gate stack includes a first gate conductor layer and a storage function layer disposed on the outer periphery of the first gate conductor layer. The epitaxial transistor is disposed below the gate stack and connected to the first gate conductor layer.

[0033] The sacrificial layer is etched away to form a second gate conductor layer, which serves as the gate of the epitaxial transistor and is disposed circumferentially around the epitaxial transistor.

[0034] The epitaxial transistor is used to control and provide current loading of the first gate conductor layer in the non-operating state.

[0035] A third aspect of this application is to provide an electronic device comprising the NOR-type memory device described in the first aspect or the NOR-type memory device prepared by the method described in the second aspect.

[0036] In some embodiments of this application, the electronic device includes a smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0037] The beneficial effects of the technical solution disclosed in this application are mainly reflected in the following:

[0038] The NOR-type memory device provided in this application includes an epitaxial transistor located below the gate stack. The epitaxial transistor is used to control and provide current loading of the first gate conductor layer in the non-operating state. Under this large current, the first gate conductor conducts electricity and generates heat, and the local temperature of the device is increased, achieving the technical effect of annealing the memory functional layer. Ultimately, it repairs the damage to the memory functional layer caused by continuous programming and erasing during use, which helps to extend the data retention time and improve the reliability of the device. Attached Figure Description

[0039] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0040] Figures 1 to 21 A schematic diagram illustrating some stages of the process for fabricating a NOR-type storage device according to an embodiment of this application is shown.

[0041] in, Figure 3 , Figure 4 , Figure 11 , Figure 16 A top view of a NOR-type memory device fabricated according to an embodiment of this application;

[0042] Figure 5 for Figure 4 Sectional view along line AA';

[0043] Figure 12 for Figure 11 Sectional view along line BB';

[0044] Figure 17 for Figure 16 A cross-sectional view along line CC';

[0045] Figure 21 A partial equivalent circuit diagram of a NOR-type memory device fabricated according to an embodiment of this application is schematically shown.

[0046] The labels in the attached diagram are as follows:

[0047] 100. Substrate;

[0048] 200. Support layer; 201. First support layer; 202. Second support layer;

[0049] 300. Sacrificial layer; 301. First sacrificial layer; 302. Second sacrificial layer;

[0050] 400, Source / Drain Layer;

[0051] 500, Channel Layer;

[0052] Device layers DL1 and DL2;

[0053] 600, hard mask layer;

[0054] 700, Groove;

[0055] 800, isolation layer; openings a, b, c, d;

[0056] 900, Gate via; 901, Gate via sidewall; 902, Epitaxial transistor; 903, Storage layer; 9031, Tunneling layer; 9032, Storage layer; 9033, Barrier layer; 904, First gate conductor layer; 905, First contact layer;

[0057] 1000, Contact hole; 1001, First contact hole; 1002, Second contact hole; 1003, Third contact hole; 1004, Fourth contact hole; 1005, Fifth contact hole; 1006, Sixth contact hole;

[0058] 1007. Contact hole sidewall; 1008. Second contact layer; 1009. Third gate conductor layer;

[0059] 2000, dielectric layer;

[0060] 3000, Second gate conductor layer;

[0061] 4000, conductive metal; first conductive metal 4001, second conductive metal 4002, third conductive metal 4003. Detailed Implementation

[0062] Existing NOR-type memories include charge-trapping memories, which have a gate stack structure. From bottom to top, they consist of a silicon substrate, a tunneling oxide layer, a storage layer, a barrier layer, and a gate electrode. During operation, the programming and erasing states are primarily distinguished by changes in the amount of charge trapped in the storage layer. During programming, a positive bias is applied to the gate. Electrons in the substrate are subjected to an electric field pointing from the gate to the substrate and tunnel through the tunneling oxide layer into the storage layer. They are trapped by the trap levels in the storage layer. Some electrons reach the interface between the storage layer and the barrier layer, where they are blocked by the potential barrier and cannot leak to the gate, remaining in the storage layer. Therefore, the threshold voltage of the device drifts positively. During erasing, a negative bias is applied to the gate. Electrons that entered the storage layer after programming pass through the tunneling layer into the substrate under the influence of the electric field. Some holes in the substrate enter the storage layer from the substrate. However, electrons at the gate cannot tunnel back into the storage layer due to the barrier between the barrier layer and the gate, causing the threshold voltage of the device to drift negatively. Because devices are constantly being programmed and erased, crosstalk between cells can easily occur and damage the tunneling layer dielectric, which in turn affects the device's durability and data retention time.

[0063] To address the aforementioned technical problems, this application provides a NOR-type memory device comprising an epitaxial transistor located below a gate stack. This epitaxial transistor controls and provides current loading to the first gate conductor layer in a non-operating state. Under this high current, the first gate conductor layer conducts electricity and generates heat, increasing the local temperature of the device. This achieves the technical effect of annealing the storage functional layer, ultimately repairing damage to the storage functional layer, which is beneficial for extending data retention time and improving the reliability of the device.

[0064] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0065] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0066] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0067] The memory device according to embodiments of this disclosure is based on a vertical device. The vertical device may include a memory cell layer disposed on a substrate in a vertical direction (generally perpendicular to the substrate surface). The memory cell layer includes source / drain layers and a channel layer stacked sequentially, wherein the channel layer forms a channel region located between the upper and lower source / drain layers, and the source / drain layers form source / drain regions. Conductive channels can be formed between the source / drain regions through the channel regions. Furthermore, the memory cell layer may be defined by a device layer on the substrate. The device layer may be a stack of semiconductor materials, with the doping concentration of each semiconductor material stack defined to form the source / drain layer and the channel layer. A gate stack extends vertically relative to the substrate to pass through the device layer, thereby allowing the device layer to surround the outer periphery of the gate stack. The gate stack includes a first gate conductor layer and a memory function layer, wherein the memory function layer is disposed around the outer periphery of the first gate conductor layer. The gate stack and each device layer cooperate to define a memory cell, which may be a flash memory cell. Multiple gate stacks can be configured to pass through the device layer. The intersection of the multiple gate stacks with the device layer defines multiple memory cells, which are arranged in an array (e.g., typically a two-dimensional array arranged in rows and columns) in the plane of the device layer.

[0068] Due to the ease with which vertical devices can be stacked, the storage devices according to embodiments of this disclosure can be three-dimensional (3D) arrays.

[0069] Meanwhile, the storage functional layer in the gate stack includes a tunneling layer, a storage layer, and a barrier layer, which can lead to the trapping of electrons or holes. The tunneling layer, storage layer, and barrier layer are formed by one or more of oxidation, atomic layer deposition, or chemical vapor deposition. Specifically, the tunneling layer is made of any material conventional in the art, such as silicon dioxide oxide, which can be formed by oxidation or atomic layer deposition (ALD). The storage layer is made of any material conventional in the art, such as silicon nitride nitride, which can be formed by chemical vapor deposition (CVD) or ALD. The barrier layer is made of any material conventional in the art, such as silicon oxide oxide, which can be formed by oxidation, CVD, or ALD. The first gate conductor layer in the gate stack is used to apply the gate voltage of the storage cell. The material of the first gate conductor layer can include, for example, polysilicon or a metal gate material, wherein the metal gate material includes tungsten, aluminum, etc.

[0070] An epitaxial transistor is disposed below the gate stack. To achieve a low-resistance connection between the gate stack and the epitaxial transistor, a contact layer is provided between the epitaxial transistor and the gate stack. The contact layer is made of metal silicide, and its thickness is a thickness conventional in the art that enables a good connection between the gate stack and the epitaxial transistor. Since there can be multiple gate stacks and multiple epitaxial transistors, the epitaxial transistors are interconnected in parallel and controlled by a second gate conductor layer. The second gate conductor layer is disposed circumferentially around the epitaxial transistors and is formed by etching a sacrificial layer located above the substrate. The material of the second gate conductor layer can be the same as that of the first gate conductor layer. The material and doping type of the epitaxial transistor are determined based on the substrate material. For example, if the substrate of this application is a p-type substrate, and the material includes any one of bulk Si, SOI, Ge, and SiGe, then the epitaxial transistor includes a first n-type doped layer, a p-type doped layer, and a second n-type doped layer stacked together in sequence to form an NPN type doped layer. Alternatively, when the substrate is an n-type substrate, the epitaxial transistor includes a first p-type doped layer, an n-type doped layer, and a second p-type doped layer stacked together in sequence to form a PNP type doped layer. Each doped layer in this epitaxial transistor is formed by in-situ doping using a selective epitaxial method conventional in the art.

[0071] To achieve the connection between the gate stack and the external circuit, a first conductive metal is provided at the top of the first gate conductor layer. The first conductive metal is connected to a selection transistor. The source terminal of the selection transistor is connected to a high voltage, such as 10V, and the drain terminal of the selection transistor is connected to the first conductive metal. By controlling the conduction of the selection transistor, current can be selectively applied to the first gate conductor layer and cause it to heat up. In conjunction with multiple parallel epitaxial transistors, a large current is provided in the non-operating state. Under this large current, the first gate conductor layer conducts electricity and heats up, and the local temperature of the device is increased, achieving the technical effect of annealing the storage function layer. Ultimately, this repairs the damage to the storage function layer caused by continuous programming and erasing during use, extends the data retention time, and improves the reliability of the device.

[0072] The device also includes at least one contact portion distributed around the gate stack, each contact portion extending vertically relative to the substrate into the memory cell layer, and each contact portion may have a stepped structure for connecting the source / drain layers.

[0073] To enable connection to external circuits, the device also includes bit lines and source terminals, wherein the source / drain layers are led out and connected to the bit lines / source terminals through the aforementioned contacts.

[0074] This application relates to the selection of various materials and selective etching for the fabrication of devices in the following description. The desired etching selectivity may or may not be specified in the following description. Those skilled in the art will understand that when the etching of a material layer is mentioned below, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching can be selective, and the material layer can possess etching selectivity relative to other layers exposed to the same etching formulation.

[0075] In some embodiments, such as Figure 1 As shown, a substrate 100 is provided. The substrate 100 can be a substrate of various forms, including but not limited to bulk semiconductor materials such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, or substrates of other materials such as germanium. In the following description, for ease of explanation, a bulk Si substrate such as a Si wafer will be used as an example.

[0076] On the substrate 100, a memory device, such as a NOR flash memory device, is formed. The memory cells in the memory device can be n-type or p-type devices. This application describes an n-type memory cell as an example. Therefore, a p-type substrate can be obtained by forming a p-type well in the substrate. The support layer 200 and the sacrificial layer 300 are alternately grown on the p-type substrate. This application preferably alternates the growth once, as illustrated in this application. Figure 1 The diagram shows a first support layer 201, a first sacrificial layer 301, and a second support layer 202 sequentially grown on a substrate 100. Each support layer 200 and each sacrificial layer 300 can have the same or similar thickness and / or material, or they can have different thicknesses and / or materials. For ease of device fabrication, this application assumes that the thickness of the second support layer 202 is greater than the thickness of the first support layer 201. Meanwhile, the growth method includes, but is not limited to, epitaxial growth. The sacrificial layer 300 can be replaced later with a dielectric layer for forming epitaxial transistors, etc. Considering the process of replacing the sacrificial layer 300, the sacrificial layer 300 can have etching selectivity relative to the support layer 200. For example, the material of the sacrificial layer 300 can include germanium silicon, and the thickness can be about 5 nm to 500 nm. The material of the first support layer 201 and the second support layer 202 can include Si, and the thickness can be about 10 nm to 800 nm. Meanwhile, the support layer 200 can be in-situ doped during growth. For example, for a p-type substrate, an n-type support layer can be formed by in-situ doping. The doping concentration includes any form conventional in the art.

[0077] like Figure 1As shown, a groove 700 is etched to form on the surface of the second support layer 202 away from the substrate 100. The groove 700 can be a square groove, and the formation of the groove 700 includes any etching method conventional in the art. The groove 700 is primarily used to fabricate... Figure 2 The second sacrificial layer 302 shown is used to facilitate the subsequent formation of the drain metal of the epitaxial transistor; the number of grooves 700 is affected by the number of epitaxial transistors and / or the number of gate holes subsequently fabricated, and the size of the grooves 700 is affected by the size of the gate holes. The attached drawings of this application only show a schematic diagram of the structure of one groove, but two or more grooves are also within the scope of protection of this application.

[0078] Specifically, a second sacrificial layer 302 is formed by epitaxy or deposition inside and outside the groove 700, and then smoothed by chemical mechanical polishing. This second sacrificial layer 302 completely fills the groove 700. The material of the second sacrificial layer 302 includes any material conventional in the art, such as being consistent with the first sacrificial layer 301. Figure 2 As shown, source / drain layers 400 and channel layers 500 continue to grow vertically above the second sacrificial layer 302, such that the upper and lower sides of each channel layer 500 are adjacent to the source / drain layer 400, and each channel layer 500, together with the upper and lower adjacent source / drain layers 400, can form a device layer DL. For example, this application forms device layers DL1 and DL2. In this application, considering the convenience of integration, the second support layer 202 is selected to have the same function as the source / drain layer 400, serving as both a support layer and the source / drain layer 400 of device layer DL2. At the same time, two or more device layers can form units and constitute an array of devices. The active region of the device can be defined by the corresponding device layer. Adjacent device layers can have a common source / drain layer and are therefore electrically connected to each other.

[0079] Figure 2The source / drain layer 400 shown can define the source / drain regions of the cell-based device. The thickness of the source / drain layer 400 can include any thickness conventional in the art, and the source / drain layer 400 can be formed by doping, such as in-situ doping during growth. For example, for a device composed of n-type cells, n-type doping can be performed using As or P, and the doping concentration includes any concentration conventional in the art. The channel layer 500 can define the channel region of the cell-based device, and its thickness can define the gate length of the cell-based device. The channel layer 500 can be undoped, or it can be doped in-situ or slightly doped during growth. For example, for a device composed of n-type cells, p-type doping can be performed using B, and the doping concentration includes any concentration conventional in the art. In addition, in order to optimize device performance, the doping concentration in the channel layer 500 can have a non-uniform distribution in the vertical direction, for example, a higher concentration near the drain region and a lower concentration near the source region. Furthermore, the source / drain layer 400 and the channel layer 500 may be made of, but are not limited to, Si or Ge, compound semiconductor materials such as SiGe. In this application, when the substrate 100 is selected as a silicon wafer, the source / drain layer 400 and the channel layer 500 may be made of silicon-based materials such as Si.

[0080] To facilitate subsequent etching, this application also includes forming a hard mask layer 600 on the surface of the aforementioned device layer. The material of the hard mask layer 600 includes, but is not limited to, silicon oxide, silicon nitride, silicon carbide, or other composite film layers conventional in the art. The thickness of the hard mask layer 600 includes any thickness conventional in the art.

[0081] To facilitate the fabrication of other semiconductor layers within the first sacrificial layer 301 located below the second sacrificial layer 302, such as... Figure 3 , Figure 4 As shown, the outer periphery of the device is etched along the surface of the hard mask layer 600 toward the substrate 100 until the substrate surface is reached to form an isolation trench. Alternatively, the etching can be performed to a certain position downwards from the substrate surface, such as slightly downwards. This downward position includes any position conventionally etched in the art. Then, an isolation material is deposited into the isolation trench to form an isolation layer 800. The isolation material includes conventional materials in the art, such as silicon oxide.

[0082] The epitaxial transistor 902 can be fabricated within a region defining the area for forming the gate aperture. For example, as... Figure 4 , Figure 5As shown, photoresist is formed on the surface of the hard mask layer 600 and patterned by photolithography to have a series of openings. These openings define the positions of the processing channels and correspond vertically to the second sacrificial layer 302. The openings can be of various suitable shapes, such as circles, rectangles, squares, polygons, etc., and have suitable sizes. Here, these openings (especially in the device area) can be arranged in an array, such as a two-dimensional array in the horizontal and vertical directions in a plane. This array can then define an array of cells constituting the device, although... Figure 4 The openings are shown as being formed on the substrate with a substantially uniform size and density, but the openings can have different layouts, sizes, and shapes. For ease of fabrication, the opening size is made smaller than the width of the plane containing the second sacrificial layer 302, or it can be made equal to the width of the plane containing the second sacrificial layer 302. For the sake of simplicity, the second sacrificial layers 302 corresponding to openings c and d are omitted from the diagram. As mentioned earlier, the groove 700 for depositing the second sacrificial layer 302 extends to a certain extent within the second support layer 202, such as... Figure 4 The openings a and b shown can share the same second sacrificial layer 302, while openings c and d need to form their own separate second sacrificial layers 302. Figure 2 Only one second sacrifice layer is reflected in it, and Figure 5 Only the diagram after etching of opening a is shown, but each sacrificial layer and each opening actually exist. The diagram in this application is only a simplified illustration.

[0083] like Figure 5 As shown, in order to Figure 4 The photoresist with the pattern shown serves as an etching mask. Anisotropic etching, such as reactive ion etching (RIE), is then used to etch the layers on the substrate to form gate holes 900 with openings a and b. The etching direction can be approximately vertical (e.g., perpendicular to the substrate surface) and can extend to the layers on the substrate surface. In this application, etching is performed to the surface of the first support layer 201 adjacent to the substrate 100. Alternatively, etching can be performed to a certain position downwards from the surface of the first support layer 201. This downward position includes any position conventionally etched in the art. This leaves a series of vertical gate holes 900 above the substrate 100, after which the photoresist can be removed. As mentioned earlier, for ease of fabrication, the opening size is made smaller than the width of the plane containing the second sacrificial layer 302. Therefore, after etching to form the gate holes 900, the remaining portions of the second sacrificial layer 302 at both ends along the vertical direction still contain unetched sacrificial layers.

[0084] like Figure 6 As shown, a gate hole sidewall 901 is formed by circumferential growth (deposition) on the inner sidewall of the gate hole 900, as follows: Figure 7As shown, an epitaxial transistor 902 is formed at the bottom of the gate aperture 900 located between the gate aperture sidewalls 901. This epitaxial transistor 902 is formed using conventional methods in the art, such as selective epitaxy. The material of the epitaxial transistor 902, from the first support layer 201 towards the second sacrificial layer 302, sequentially comprises n-type silicon + p-type silicon + n-type silicon, and the thickness of the p-type silicon in the epitaxial transistor 902 is comparable to, or approximately the same as, slightly larger than, or slightly smaller than, the thickness of the first sacrificial layer 301. The n-type silicon surface above the p-type silicon is located below the bottom surface of the second sacrificial layer 302. The design of this epitaxial transistor 902 and its electrical lead-out method enable selective control of the device heating circuit. Next, the other gate aperture sidewalls within the gate aperture 900, except for the epitaxial transistor 902, are etched away. Figure 8 As shown, further etching away Figure 7 The unetched portion of the second sacrificial layer shown is obtained Figure 8 The remaining space of the gate shown.

[0085] Further, it can be achieved through... Figure 8 The remaining space of the gate hole is used to stack gates to realize device storage. The gate stack extends along the extension direction of the gate hole and is columnar. The gate stack overlaps with multiple device layers, thereby defining multiple cells stacked on each other in the vertical direction to form a device. At the same time, the memory cells associated with a single gate stack pillar can form a memory cell string. Corresponding to the layout of the gate stack pillars, a two-dimensional array or a three-dimensional array of memory cells can be arranged on the substrate.

[0086] For example, the gate stack may include a storage structure, such as a charge trapping layer or a ferroelectric material. This application chooses to form a charge trapping layer, such as... Figure 9 , Figure 10 As shown, the storage functional layer 903 and the first gate conductor layer 904 can be formed sequentially by methods such as deposition or other conventional methods in the art. The formed storage functional layer 903 and the first gate conductor layer 904 can also be planarized, such as by chemical mechanical polishing, for example, stopping at a hard mask layer. The storage functional layer 903 can be formed in a generally conformal manner, and the first gate conductor layer 904 can fill the remaining voids after the storage functional layer 903 is formed. Figure 9 As shown, to enable the epitaxial transistor 902 to conduct, the portion of the storage functional layer 903 that contacts the epitaxial transistor 902 is etched to expose a portion of the surface of the epitaxial transistor 902. Then, a first contact layer 905 is formed on the exposed surface of the epitaxial transistor 902. Figure 10As shown, the thickness of the first contact layer 905 includes any thickness conventional in the art, and the material of the first contact layer 905 includes metal silicide. After the storage function layer 903 is formed above the first contact layer 905, the remaining gap is formed in the first gate conductor layer 904. The storage function layer 903 may have dielectric charge trapping, ferroelectric material effect or bandgap engineered charge storage, etc. For example, the storage layer 903 may include a tunneling layer 9031, a storage layer 9032, and a barrier layer 9033, and may also include other layers conventional in the art that can trap electrons or holes. The tunneling layer 9031 may be made of any material conventional in the art, such as silicon dioxide oxide, and may be formed by oxidation, low-pressure chemical vapor deposition, or atomic layer deposition (ALD). The storage layer 9032 may be made of any material conventional in the art, such as silicon nitride nitride, and may be formed by chemical vapor deposition (CVD) or ALD. The barrier layer 9033 may be made of any material conventional in the art, such as silicon oxide oxide, and may be formed by oxidation, CVD, or ALD. The first gate conductor layer 904 may be made of, for example, polysilicon or a metal gate material, wherein the metal gate material includes tungsten. Figure 10 As shown, the gate stack in the gate aperture 900 is surrounded by the device layer. The gate stack and the device layer cooperate to define the memory cell. For example, the channel region formed by the channel layer 500 can connect the source / drain regions on opposite sides. The channel region can be controlled by the gate stack. One of the source / drain regions at the top and bottom ends of a single memory cell is used as a source region and can be electrically connected to the source line. The other is used as a drain region and can be electrically connected to the bit line. For every two vertically adjacent memory cells, the source / drain region at the top end of the lower memory cell and the source / drain region at the bottom end of the upper memory cell can be used as source regions, so that they can share the same source line connection.

[0087] Combination Figure 4 As shown in the diagram, each opening a, b, c, and d can achieve the following: Figures 5 to 10 The operation thus forms one or more epitaxial transistors above the substrate 100, each epitaxial transistor being located below the gate stack and prepared for subsequent electrical connections.

[0088] Next, various electrical contacts can be fabricated to achieve the required electrical connections. Specifically, to achieve electrical connections to various device layers, a stepped structure can be formed on the substrate in areas other than the gate stack used to form electrical contacts. There are various ways to form such a stepped structure in the art. According to an embodiment of this application, the stepped structure can be formed in the following manner:

[0089] like Figure 11 , Figure 12As shown, similar to the formation method of the gate via, contact holes 1000 are formed with a stepped structure, exhibiting inconsistent etching depths from the hard mask layer towards the device layer. The formation depth and number of contact holes 1000 are related to the device layer. This application selects to form... Figure 12 The first contact hole 1001, the second contact hole 1002, the third contact hole 1003, the fourth contact hole 1004, the fifth contact hole 1005, and the sixth contact hole 1006 are shown, wherein the bottom end of the sixth contact hole 1006 extends into the first support layer 201. Next, as... Figure 13 As shown, contact hole sidewalls 1007 are formed by circumferential growth (deposition) along the sidewalls inside each contact hole 1000, such as... Figure 14 As shown, a second contact layer 1008 is formed at the bottom of each contact hole. The thickness of the second contact layer 1008 includes any thickness conventional in the art, and the material of the second contact layer 1008 includes metal silicide, such as... Figure 15 As shown, a third gate conductor layer 1009 is formed in the remaining gap after the formation of the contact hole sidewall 1007 above the second contact layer 1008. The material of the third gate conductor layer 1009 may include, for example, polysilicon or a metal gate material, wherein the metal gate material includes a conductive metal such as tungsten. The material of the contact hole sidewall 1007 includes materials conventional in the art, such as the same material as the gate hole sidewall 901, or, for example, a high-k dielectric material.

[0090] like Figure 16 , Figure 17 , Figure 18 As shown, the isolation layer 800 on the outer periphery of the device is first etched away, exposing the outer wall of the first sacrificial layer 301. The first sacrificial layer 301 is then etched further. (Not shown in the figure, the gate hole sidewall 901 can also be further etched to expose the surface of the epitaxial transistor 902.) The etching method can include any form conventional in the art. After etching away the isolation layer 800 and the first sacrificial layer 301, the device can achieve good support due to the presence of the epitaxial transistor 902 array. Specifically, the dielectric layer 2000 and the second gate conductor layer 3000 are sequentially deposited in the space vacated by the first sacrificial layer 301 and in the trench remaining after etching away the isolation layer 800. (Specific details are as follows...) Figure 19 As shown, the material of the dielectric layer 2000 includes, but is not limited to, conventional materials in the art, such as high-K dielectric layers, and the second gate conductor layer 3000 can be selected from metal gate materials, such as tungsten or aluminum.

[0091] Finally, as Figure 20 , Figure 21As shown, the first gate conductor layer at the top of the stacked gate is further led out through the first conductive metal 4001 and electrically connected to the word line WL. The word line WL is connected to the word line selection circuit. At the same time, the word line is also connected to the drain terminal of the selection transistor. A high voltage, such as 10V, can be set at the source terminal of the selection transistor. By controlling the conduction of the selection transistor, current can be applied to the first gate conductor layer to make it conductive and generate heat. Figure 21 The illustrated selection transistors S1 and S3 comprise any type of selection transistor conventional in the art. A third gate conductor layer at the top of the contact hole 1000 is led out through a second conductive metal 4002, and the second gate conductor layer is led out through a third conductive metal 4003. The conductive metal comprises any conductive material conventional in the art.

[0092] like Figure 21 As shown, a voltage such as 5V can be applied to the second gate conductor layer connected to the epitaxial transistors S2 and S4 to achieve the switching of the epitaxial transistors. When a high voltage is applied to the source terminal of the select transistor S1 or S3 and selective conduction is performed, the current passes through the first gate conductor layer, the parallel epitaxial transistors S2 and S4 in sequence, and finally leads to the ground line. Therefore, a large current loading of the first gate conductor layer can be achieved in the non-operating state. Under this large current, the first gate conductor conducts electricity and generates heat, and the local temperature of the device is increased, achieving the technical effect of annealing the storage function layer. Ultimately, the damage to the storage function layer is repaired, the data storage time is extended, and the reliability of the device is improved.

[0093] Combination Figure 21 ,right Figure 20 The source / drain layers are led out via the second conductive metal 4002 and electrically connected to the bit line BL, while the common source / drain layers can be electrically connected to the bit line BL or the source terminal SL. This application shows its electrical connection to the source terminal SL, thus a NOR type configuration can be obtained.

[0094] The storage device according to embodiments of this application can be applied to various electronic devices. For example, the storage device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that works in conjunction with the storage device. For example, the processor can operate the electronic device by running programs stored in the storage device. Such electronic devices include, for example, smartphones, personal computers (PCs), tablets, artificial intelligence devices, wearable devices, power banks, automotive electronics, communication devices, Internet of Things (IoT) devices, or headphones (e.g., true wireless stereo (TWS) headphones).

[0095] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0096] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A NOR-type storage device, characterized in that: include: Substrate; Storage cell layer: consists of source / drain layers and channel layers stacked sequentially; Gate stack: extending vertically relative to the substrate to pass through the memory cell layer; the gate stack includes a first gate conductor layer and a memory function layer disposed on the periphery of the first gate conductor layer; Epitaxial transistor: disposed below the gate stack and connected to the first gate conductor layer; Second gate conductor layer: disposed circumferentially around the epitaxial transistor; The epitaxial transistor comprises a plurality of transistors, and each of the epitaxial transistors is connected in parallel with each other and controlled by the second gate conductor layer; The epitaxial transistor is used to control and provide current loading of the first gate conductor layer in the non-operating state.

2. The device according to claim 1, characterized in that: The epitaxial transistor includes an NPN type doped layer or a PNP type doped layer formed by stacking them together in sequence; Each doped layer is formed by in-situ doping using an epitaxial method.

3. The device according to claim 2, characterized in that: The material of the epitaxial transistor includes any one of Si, Ge, and SiGe.

4. The device according to claim 1, characterized in that: A contact layer is provided between the epitaxial transistor and the first gate conductor layer; The contact layer is made of metal silicide.

5. The device according to claim 1, characterized in that: The top of the first gate conductor layer is provided with a first conductive metal, and the first conductive metal is connected to the selection transistor.

6. The device according to claim 5, characterized in that: One end of the selection transistor is connected to a high voltage, and the other end is connected to a first conductive metal. By controlling the conduction of the selection transistor, current can be selectively applied to the first gate conductor layer to make it conductive and generate heat.

7. The device according to claim 1, characterized in that: The storage function layer includes a tunneling layer, a storage layer, and a blocking layer; The tunneling layer, storage layer, and barrier layer are formed by one or more of oxidation, atomic layer deposition, or chemical vapor deposition.

8. The device according to claim 1, characterized in that: The first gate conductor layer and the second gate conductor layer are made of polycrystalline silicon or metal gate material, wherein the metal gate material contains tungsten or aluminum.

9. The device according to claim 1, characterized in that: The device further includes at least one contact portion distributed around the gate stack, each of the contact portions extending vertically relative to the substrate into the memory cell layer.

10. The device according to claim 9, characterized in that: The device also includes a bit line and a source terminal; The source / drain layer is led out through the contact portion and connected to the bit line / source terminal.

11. A method for fabricating NOR-type memory devices, characterized in that: include: A sacrificial layer and a memory cell layer are sequentially disposed on a substrate, wherein the memory cell layer includes a source / drain layer and a channel layer stacked sequentially. Forming gate holes that extend vertically relative to the substrate to pass through the memory cell layer; An epitaxial transistor and a gate stack are sequentially formed within the gate hole. The gate stack includes a first gate conductor layer and a storage function layer disposed on the outer periphery of the first gate conductor layer. The epitaxial transistor is disposed below the gate stack and connected to the first gate conductor layer. The sacrificial layer is etched away to form a second gate conductor layer, which serves as the gate of the epitaxial transistor and is disposed circumferentially around the epitaxial transistor. The epitaxial transistor is used to control and provide current loading of the first gate conductor layer in the non-operating state.

12. An electronic device, characterized in that, Includes the NOR type memory device according to any one of claims 1 to 10 or the NOR type memory device prepared by the method of claim 11.

13. The electronic device according to claim 12, characterized in that, The electronic device includes any one or more of the following: smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

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