Manufacturing method of magnetic flux regulation signal line and quantum computing chip

Abstract

The application discloses a manufacturing method of a magnetic flux regulation signal line, and belongs to the field of superconducting circuits. The manufacturing method comprises the following steps: forming a first superconducting layer on a substrate; patterning the first superconducting layer to obtain a coplanar waveguide transmission line; testing whether an electrical characteristic of a center conductor of the coplanar waveguide transmission line is abnormal; and when the electrical characteristic is not abnormal, forming a second superconducting layer to electrically connect the center conductor and the ground. In the related art, a one-time patterning is usually used to prepare a one-layer structure, and in the present application, the one-layer structure is divided into two layers and is prepared in steps, and the second layer is prepared when the electrical detection of the first layer is not abnormal, so that the influence of the grounding effect of the second layer on the electrical detection is avoided, and whether the magnetic flux regulation signal line is abnormal and short-circuited can be effectively determined.

Description

Technical Field

[0001] This application belongs to the field of superconducting circuits, especially the field of superconducting quantum computing technology. In particular, this application relates to a method for manufacturing a magnetic flux control signal line and a quantum computing chip. Background Technology

[0002] Quantum bits, located on a quantum chip, are the basic units for performing quantum computing. In a superconducting quantum computing system, various transmission lines with different functions exist around the qubits. To ensure the quality of the quantum chip, each transmission line generally needs to undergo electrical testing to determine if there are short circuits or open circuits. However, the magnetic flux control signal line of the qubit is designed with one end grounded. This structure is usually obtained by patterning the superconducting layer once during manufacturing. This introduces uncertainties to the electrical testing of the magnetic flux control signal line, especially making it difficult to determine if there is an abnormal grounding that could cause a short circuit. Invention Content

[0003] The purpose of this application is to provide a method for manufacturing a magnetic flux control signal line and a quantum computing chip. It divides the single-layer structure, which is usually manufactured in a single patterning process in related technologies, into a two-layer structure manufactured in steps, thereby facilitating electrical detection and solving the problem in the prior art that it is difficult to determine whether there is an abnormal grounding and short circuit.

[0004] One embodiment of this application provides a method for manufacturing a flux control signal line, including the following steps:

[0005] A first superconducting layer is formed on a substrate; the first superconducting layer is patterned to obtain a coplanar waveguide transmission line, the coplanar waveguide transmission line including a central conductor and ground on both sides of the central conductor; the electrical characteristics of the central conductor are tested to check for short-circuit anomalies; and when the electrical characteristics do not show short-circuit anomalies, a second superconducting layer is formed to electrically connect one end of the central conductor and the ground.

[0006] In some embodiments of the manufacturing method described above, while the first superconducting layer is patterned to obtain a coplanar waveguide transmission line, an extended connection region is obtained between one end of the central conductor and the ground; and the step of forming a second superconducting layer to electrically connect one end of the central conductor and the ground includes: forming a second superconducting layer in the extended connection region and electrically connecting the one end and the ground.

[0007] In some embodiments of the manufacturing method described above, the step of testing the electrical properties of the center conductor to check for short-circuit anomalies includes:

[0008] A test circuit is provided, wherein the access terminal of the test circuit includes two probes;

[0009] Move one of the probes to contact the ground, and move the other probe to contact the end of the center conductor.

[0010] The manufacturing method described above, in some embodiments, further includes:

[0011] When there is a short circuit anomaly in the electrical characteristics, the location of the short circuit anomaly is determined, and a conductive film is formed at the location that adheres the central conductor and the ground;

[0012] Perform a repair process to eliminate the short-circuit anomaly at the specified location;

[0013] A second superconducting layer is formed to electrically connect the central conductor and the ground.

[0014] In some embodiments of the manufacturing method described above, the repair process step for eliminating the short-circuit abnormality includes:

[0015] The exposure layout is determined based on the location of the short-circuit anomaly;

[0016] A mask is formed on the substrate, and the mask is patterned according to the exposure pattern; and,

[0017] The conductive film is removed by etching using the mask.

[0018] In some embodiments of the manufacturing method described above, the step of determining the location of the short-circuit anomaly includes:

[0019] Characteristic information of multiple locations of the gap is obtained along the extending direction of the gap between the central conductor and the ground; and,

[0020] The location of the conductive film is determined based on the fluctuation of the feature information as the location of the short circuit anomaly.

[0021] In some embodiments of the manufacturing method described above, the step of obtaining feature information of multiple locations of the gap includes:

[0022] Multiple locations of the gap are determined along the extension direction of the gap, and the multiple locations are scanned to obtain the film thickness at each location.

[0023] In some embodiments of the manufacturing method described above, the step of scanning the plurality of locations to obtain the film thickness at each location includes:

[0024] In a plane parallel to the coplanar waveguide transmission line, the probe is moved along the extension direction of the gap and a probe signal is emitted to various positions of the gap;

[0025] The film thickness at each location is determined based on the feedback signals from the detection signal at each location.

[0026] In some embodiments of the manufacturing method described above, the step of obtaining feature information of multiple locations of the gap includes:

[0027] A photograph of the coplanar waveguide transmission line generated on a substrate on which the coplanar waveguide transmission line is formed;

[0028] The photos are processed to grayscale to obtain comparison photos;

[0029] On the comparison photograph, multiple locations of the gap are determined along the extension direction of the gap, and the multiple locations are scanned to obtain the grayscale value of each location.

[0030] In some embodiments of the manufacturing method described above, the photographs include at least one of light micrographs and electron micrographs.

[0031] Another embodiment of this application provides a quantum computing chip comprising: a superconducting quantum interference device; and a magnetic flux control signal line manufactured according to the method described above, wherein a second superconducting layer is coupled to the superconducting quantum interference device to control the magnetic flux of the superconducting quantum interference device.

[0032] Compared with existing technologies, the method for manufacturing a flux-controlled signal line provided in this application involves first forming a first superconducting layer on a substrate, then patterning the first superconducting layer to obtain a coplanar waveguide transmission line, and then testing the electrical characteristics of the central conductor of the coplanar waveguide transmission line to check for short-circuit anomalies. If no short-circuit anomalies are found, a second superconducting layer is formed to electrically connect the central conductor and ground to obtain the flux-controlled signal line. This application divides the typically single-layer structure fabricated in related technologies into a two-layer structure fabricated in stages. Furthermore, the second layer is fabricated only after the central conductor of the first layer has been tested and found to be free of short-circuit anomalies. This effectively determines whether the flux-controlled signal line has an abnormal grounding and short circuit, avoiding the influence of grounding on the electrical characteristic testing. Attached Figure Description

[0033] Figure 1 A schematic diagram of the structure of a flux control signal line provided in one embodiment of this application;

[0034] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a flux control signal line according to an embodiment of this application.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1 - First superconducting layer, 11 - Central conductor, 12 - Ground, 111 - Grounding terminal, 112 - Pad;

[0037] 2 – Second superconducting layer, 3 – Extended connection region, 4 – Superconducting quantum interference device. Detailed Implementation

[0038] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the various embodiments may be combined with and referenced to each other without contradiction.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0042] Quantum computing is a new discipline that considers computational processes from the perspective of fundamental quantum mechanics principles. The realization of a quantum computer requires qubits (qubits) as basic units that obey the laws of quantum mechanics. A qubit, as a two-level system following the laws of quantum mechanics, can exist in any superposition of 0 and 1 states. Depending on the physical system used to construct the qubit, there are different physical implementation methods. Superconducting quantum chips include qubits and superconducting circuit structures such as microwave resonant cavities. A qubit is a two-level system constructed using a capacitor and a Josephson junction with nonlinear inductive properties.

[0043] Several transmission lines with different functions exist around qubits, such as the drive control signal line (xy-control line, also known as the xy control line or pulse modulation signal line) for XY rotation operations, the BUS line for coupling between qubits, and the readout signal line coupled to the readout resonant cavity of the qubit. Additionally, the control signal for Z rotation operations is located near the superconducting quantum interference device (squid), i.e., the flux control signal line (z-control line, also known as the z control signal line or frequency modulation signal line). This line is typically positioned near the squid and excited by a current, coupling with the squid through magnetic flux. To ensure the quality of the quantum chip, each transmission line generally needs to undergo electrical testing to determine if there are short circuits or open circuits. However, since the flux control signal line is designed with one end grounded, current manufacturing methods typically involve patterning the superconducting layer once to obtain a single-layer flux control signal line. This method introduces uncertainties into electrical testing, particularly making it difficult to determine if there are abnormal grounding or short circuits. Specifically, when one end of the magnetic flux control signal line is grounded, it is difficult to determine whether there are other grounded locations through electrical testing.

[0044] Therefore, embodiments of this application provide a method for manufacturing a flux control signal line. It divides a single-layer structure, which is usually patterned and prepared in one step in related technologies, into two-layer structures that are prepared in stages. The first-layer structure is tested, and if no short-circuit abnormality is found, the second layer is prepared. This method avoids the influence of grounding contact on the test and can effectively determine whether there is a short circuit caused by abnormal grounding.

[0045] Figure 1 A schematic diagram of the structure of a flux control signal line provided in one embodiment of this application;

[0046] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a flux control signal line according to an embodiment of this application.

[0047] Combination Figure 1and Figure 2 As shown, one embodiment of this application provides a method for manufacturing a flux control signal line, including the following steps S201 to S204:

[0048] S201. Form a first superconducting layer 1 on a substrate; S202. Pattern the first superconducting layer 1 to obtain a coplanar waveguide transmission line, the coplanar waveguide transmission line including a central conductor 11 and ground 12 located on both sides of the central conductor 11, the central conductor 11 having an end to be grounded, denoted as ground terminal 111; S203. Test the electrical characteristics of the central conductor 11 to see if there is a short circuit abnormality; S204. When there is no short circuit abnormality in the electrical characteristics, form a second superconducting layer 2 to electrically connect the ground terminal 111 and the ground 12. It should be emphasized that the second superconducting layer 2 is manufactured independently of the step of forming the coplanar waveguide transmission line.

[0049] The superconducting layer can be formed from superconducting materials that exhibit superconducting properties at temperatures equal to or below the critical temperature, such as about 10-100 milliklvin (mK) or about 4K, such as aluminum, niobium, tantalum, or titanium nitride, etc. In practice, it is not limited to these types. Any material that exhibits superconducting properties at temperatures equal to or below the critical temperature can be used to form the superconducting layer.

[0050] Compared to the related technologies described above, this embodiment first forms a first superconducting layer 1 on a substrate, then patterns the first superconducting layer 1 to obtain a coplanar waveguide transmission line to be grounded, and then tests the electrical characteristics of the center conductor 11 of the coplanar waveguide transmission line to test for short-circuit anomalies. When no short-circuit anomalies are found in the electrical characteristics, a second superconducting layer 2 is formed to electrically connect the ground terminal 111 of the center conductor 11 and ground 12. This embodiment divides the single-layer structure, which is usually patterned and prepared in one step in related technologies, into a two-layer structure prepared in stages. The second layer is prepared only after the electrical detection of the first layer shows no short-circuit anomalies, thereby avoiding the influence of the connection to ground 12 on the electrical detection. Based on this embodiment, it is possible to effectively determine whether the magnetic flux control signal line has an abnormal grounding and short circuit problem. It should be noted here that... Figure 1 The diagram schematically illustrates a portion of the structure of a coplanar waveguide transmission line. To highlight the key points of this application, the portion of the structure between the two dashed lines is omitted. In reality, the coplanar waveguide transmission line extends continuously between the two dashed lines, and its trajectory can be either a straight line or a smooth curve.

[0051] In some embodiments, in order to generate a magnetic field in a desired region, while patterning the first superconducting layer 1 to obtain a coplanar waveguide transmission line, an extended connection region 3 is obtained between the grounded end of the central conductor 11 and the ground 12; and the step of forming a second superconducting layer 2 to electrically connect the grounding end 111 and the ground 12 includes: forming a second superconducting layer 2 in the extended connection region 3, and electrically connecting the grounding end 111 and the ground 12. Figure 1 As shown, the flux control structure is typically positioned near the superconducting quantum interference device (SQU4) 4 to generate a magnetic field through the SQU4 via the flux control signal line. For this purpose, the extension direction of the extended connection region 3 can differ from the extension direction of the central conductor 11. The extension direction of the central conductor 11 can be determined by the line connecting its two ends, while the extension direction of the extended connection region 3 can be determined by its starting and ending positions. A pad 112 is formed at the other end of the central conductor 11, and the signal input terminal is led to the edge of the quantum chip via the central conductor 11. A magnetic field through the SQU4 is generated by the second superconducting layer 2 in the extended connection region 3. In one example, the SQU4 includes two Josephson junctions, and the extension direction of the extended connection region 3 can be parallel to the line connecting the locations of the two Josephson junctions.

[0052] To ensure good physical and electrical contact, the second superconducting layer 2 partially covers the ground terminal 111 and the ground 12. In one embodiment, the surfaces of the ground terminal 111 and the ground 12 covered do not contain an oxide film to avoid the oxide film blocking the electrical contact. Specifically, before forming the second superconducting layer 2, an ion etching process can be performed to remove the surface oxide film of the areas of the ground terminal 111 and the ground 12 covered.

[0053] In some embodiments, the step of testing whether the electrical characteristics of the center conductor are short-circuited includes: providing a test circuit, the access terminal of which includes two probes, and the test circuit may also include a test signal source, with both probes connected to the signal test source; moving one probe to contact the ground 12 and moving the other probe to contact the end of the center conductor 11, thereby connecting the portion between the two probe contact points to the test circuit using the probes, and using the signal source to test the electrical characteristics of this portion under certain conditions. For example, the signal source provides a constant current through this portion and measures the corresponding resistance, and determines whether there is a short-circuited abnormality between the center conductor 11 and the ground 12 based on the resistance value.

[0054] After testing confirms the presence of a short-circuit anomaly in the electrical characteristics, a targeted repair process can be used to eliminate the short-circuit anomaly. For example, this application embodiment may further include: when a short-circuit anomaly is present in the electrical characteristics, determining the location of the short-circuit anomaly, typically located in the gap between the lower conductor 11 and ground 12, where a conductive film is formed to adhere the central conductor 11 and the ground 12; performing a repair process to eliminate the short-circuit anomaly at the location; and forming a second superconducting layer to electrically connect the central conductor 11 and the ground 12. In some embodiments, the repair process to eliminate the short-circuit anomaly includes: determining an exposure pattern based on the location of the short-circuit anomaly; forming a mask on the substrate and patterning the mask according to the exposure pattern; and using the mask to etch and remove the conductive film. It is understood that the short-circuit anomaly is caused by the conductive film described above. The presence of the conductive film may be due to residues caused by process abnormalities during the patterning of the first superconducting layer. The repair process aims to remove this conductive film to eliminate the short-circuit anomaly. In some embodiments, along the extending direction of the central conductor 11, the coplanar waveguide transmission line further includes a repair section formed after a repair process, and the distance between the central conductor 11 and the ground 12 within the repair section is greater than the distance between the central conductor 11 and the ground 12 in other sections. In one embodiment, the ground 12 within the repair section is recessed towards the side away from the central conductor 11.

[0055] In order to detect whether the final magnetic flux control signal line meets the design requirements, in a specific implementation of this application, after the step of forming the second superconducting layer 2 and electrically connecting the grounding terminal 111 and the ground 12, the application further includes: testing the electrical characteristics of the central conductor 11 to determine whether there is a short circuit abnormality, so as to determine whether the formed second superconducting layer 2 achieves the connection and conduction between the central conductor 11 and the ground 12. If the connection and conduction are achieved, the magnetic flux control signal line formed based on the central conductor 11 and the second superconducting layer 2 meets the grounding design requirements.

[0056] In some embodiments, the step of determining the location of the short-circuit anomaly described above includes: acquiring feature information of multiple locations located in the gap along the extension direction of the gap between the central conductor 11 and the ground 12, the multiple locations being distributed along the extension direction of the gap; and determining the location of the conductive film as the location of the short-circuit anomaly based on the fluctuation of the feature information. The fluctuation can be whether the feature information is within a predetermined range, and determining the location within the predetermined range as the location of the short-circuit anomaly; the fluctuation can also be the magnitude of the difference between the feature information of a certain location and the feature information of several other locations (e.g., the remaining locations among the multiple locations, or adjacent locations of that location), and determining the location where the difference is greater than a preset threshold as the location of the short-circuit anomaly.

[0057] In one embodiment, the step of acquiring feature information of multiple locations of the gap may include: determining multiple locations located in the gap along the extension direction of the gap, and scanning the multiple locations to obtain the film thickness at each location. For example, the step of scanning the multiple locations to obtain the film thickness at each location includes: moving a probe along the extension direction of the gap in a plane parallel to the coplanar waveguide transmission line and emitting a probe signal to each location of the gap; and determining the film thickness at each location based on the feedback signal of the probe signal at each location. The probe signal may be a terahertz signal or a laser signal. Different feedback signals will be generated after the probe signal is reflected at different locations. The film thickness at the corresponding location can be obtained based on the acquisition and processing of the feedback signal. The probe signal may also be other signals that can realize the detection of thin-film circuit thickness or relative distance changes. It is understood that if there is an adhered conductive film at a certain location of the gap, it will cause a short circuit anomaly. By scanning the gap, the film thickness at multiple locations of the gap can be quickly determined. A film thickness of 0 indicates no short circuit anomaly, while a film thickness greater than a certain threshold will cause a short circuit anomaly.

[0058] In another embodiment, the step of obtaining feature information of multiple locations of the gap may include: after the step of patterning the first superconducting layer 1 to obtain a coplanar waveguide transmission line, generating a photograph of the coplanar waveguide transmission line based on a substrate on which the coplanar waveguide transmission line is formed; performing grayscale processing on the photograph to obtain a comparison photograph, i.e., converting the photograph to grayscale, and obtaining the comparison photograph after grayscale conversion; determining multiple locations of the gap along the extension direction of the gap on the comparison photograph, and scanning the multiple locations to obtain the grayscale value of each location. For example, the photograph includes at least one of an optical microscope photograph and an electron microscope photograph. A grayscale value is a parameter that measures the brightness of each pixel in a grayscale image. A specific grayscale value range represents the brightness of a pixel. For example, 0 to 255 represents a specific grayscale value range, where 0 represents the darkest and 255 represents the brightest. A larger grayscale value indicates a brighter image. In this embodiment, the grayscale value at each location may be the average of the grayscale values ​​of multiple pixels at the corresponding location.

[0059] It is understandable that the gray value of the location on the substrate with a thin film (the area where the center conductor is located in an ideal state) should be in the first range, and the gray value of the location without a thin film (the area where the gap is located in an ideal state) should be in the second range. The two ranges are clearly distinguishable and can be predetermined. After determining multiple locations of the gap and then obtaining the gray value of each location, the location of the gray value in the first range can be identified as the short location. The first range can be a preset range.

[0060] In specific implementation, determining multiple positions of the gap along its extension direction can include: providing a standard diagram, which includes a standard transmission line corresponding to the coplanar waveguide transmission line, and the standard transmission line includes a standard gap; determining multiple reference positions on the standard gap according to scanning requirements; and determining multiple positions corresponding to the gap and the multiple reference positions. The standard diagram may include at least one of a photograph of a standard chip or a design drawing of a standard chip. The photograph of the standard chip may include at least one of an optical microscope photograph or an electron microscope photograph. Using the standard transmission conductor and standard gap in the standard diagram as reference standards facilitates the early determination of the position information to be scanned, such as specific coordinates, to enable precise control of the scanning operation.

[0061] Based on the above description, the magnetic flux control signal line in the related technology usually adopts a single-layer structure manufactured in one pattern. However, the manufacturing method provided in this application divides the magnetic flux control signal line into a two-layer structure prepared in steps. After the central conductor 11 of the first superconducting layer 1 is tested and found to have no short circuit abnormality, the second superconducting layer 2 is then prepared. This can effectively determine whether the magnetic flux control signal line has an abnormal grounding and short circuit, thus avoiding the influence of grounding on the electrical characteristic test.

[0062] Another aspect of this application provides a quantum computing chip, including: a superconducting quantum interference device 4; and a magnetic flux control signal line manufactured according to the method described above, wherein a second superconducting layer 2 is coupled to the superconducting quantum interference device 4 to control the magnetic flux of the superconducting quantum interference device 4.

[0063] It should be noted that the above embodiments of the quantum computing chip have the same beneficial effects as the embodiments of the magnetic flux control signal line manufacturing method described above, and therefore will not be repeated. For technical details not disclosed in the embodiments of the quantum computing chip of this application, those skilled in the art should refer to the description of the above manufacturing method for understanding; for the sake of brevity, they will not be repeated here.

[0064] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0065] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for manufacturing a magnetic flux control signal line, characterized in that, include: A first superconducting layer is formed on the substrate; The first superconducting layer is graphically plotted to obtain a coplanar waveguide transmission line, which includes a central conductor and ground planes located on both sides of the central conductor. While plotting the first superconducting layer to obtain the coplanar waveguide transmission line, an extended connection region is obtained between one end of the central conductor and the ground plane. Test the electrical properties of the center conductor to check for short-circuit abnormalities; When there is no short-circuit anomaly in the electrical properties, a second superconducting layer is formed to electrically connect one end of the central conductor and the ground; When a short circuit anomaly is present in the electrical characteristics, the location of the short circuit anomaly is determined, and a conductive film is formed at the location to bond the central conductor and the ground; a repair process step to eliminate the short circuit anomaly is performed at the location. A second superconducting layer is formed to electrically connect the central conductor and the ground; The step of forming a second superconducting layer to electrically connect one end of the central conductor and the ground includes: forming a second superconducting layer in the extended connection region and electrically connecting the one end and the ground.

2. The method according to claim 1, characterized in that, The step of testing the electrical properties of the center conductor to check for short-circuit anomalies includes: A test circuit is provided, wherein the access terminal of the test circuit includes two probes; Move one of the probes to contact the ground, and move the other probe to contact the end of the center conductor.

3. The method according to claim 1, characterized in that, The repair process steps for eliminating the short-circuit anomaly include: The exposure layout is determined based on the location of the short-circuit anomaly; A mask is formed on the substrate, and the mask is patterned according to the exposure pattern; and, The conductive film is removed by etching using the mask.

4. The method according to claim 1, characterized in that, The step of determining the location of the short-circuit anomaly includes: Characteristic information of multiple locations of the gap is obtained along the extending direction of the gap between the central conductor and the ground; and, The location of the conductive film is determined based on the fluctuation of the feature information as the location of the short circuit anomaly.

5. The method according to claim 4, characterized in that, The step of obtaining feature information of multiple positions of the gap includes: Multiple locations of the gap are determined along the extension direction of the gap, and the multiple locations are scanned to obtain the film thickness at each location.

6. The method according to claim 5, characterized in that, The step of scanning the multiple locations to obtain the film thickness at each location includes: In a plane parallel to the coplanar waveguide transmission line, the probe is moved along the extension direction of the gap and a probe signal is emitted to various positions of the gap; The film thickness at each location is determined based on the feedback signals from the detection signal at each location.

7. The method according to claim 4, characterized in that, The step of obtaining feature information of multiple positions of the gap includes: A photograph of the coplanar waveguide transmission line generated on a substrate on which the coplanar waveguide transmission line is formed; The photos are processed to grayscale to obtain comparison photos; On the comparison photograph, multiple locations of the gap are determined along the extension direction of the gap, and the multiple locations are scanned to obtain the grayscale value of each location.

8. A quantum computing chip, characterized in that, include: Superconducting quantum interference device; as well as, A flux-controlled signal line manufactured by the method according to any one of claims 1 to 7, wherein the second superconducting layer is coupled to the superconducting quantum interference device to control the magnetic flux of the superconducting quantum interference device.

Images