Monitor exclusive instruction

Abstract

The present disclosure provides an apparatus comprising an instruction decoder (20) and processing circuitry (22). Monitoring circuitry (36) monitors for one or more events indicative of potential updates to data associated with any of a monitored set of addresses and enables software executing on the processing circuitry (22) to access a monitoring report indication indicating whether any events have occurred for at least one of the monitored set of addresses. In response to a decode of an exclusive state set instruction specifying a given address, the processing circuitry (22) sets an exclusive state associated with the given address. The exclusive state is cleared in response to detecting an event indicating a conflicting memory access to the given address. In response to a decode of a monitor exclusive instruction, the processing circuitry (22) determines whether the exclusive state is associated with a target address and, if so, assigns the target address as one of the monitored set of addresses.

Description

Technical Field

[0001] This technology relates to the field of data processing. Background Technology

[0002] Data processing systems may have multiple requesting devices that can share access to a shared memory system. Sometimes, in response to a request from another requesting device, processing performed on a given requesting device may need to wait for data in memory to be updated. For example, software executing on a CPU or other processing element may be waiting for a data queue in memory to be updated by an input / output device such as a network interface controller. Similar problems can occur when multiple processes executing on the same processing element use structures in memory to provide inter-process communication. If the number of different addresses in memory that need to be monitored by a given software process is large, performing this monitoring by repeatedly polling each address by the software may be inefficient. Summary of the Invention

[0003] At least some examples provide an apparatus comprising: an instruction decoder for decoding instructions; processing circuitry for performing data processing in response to the instructions decoded by the instruction decoder; and monitoring circuitry for monitoring one or more events indicating a potential update to data associated with any one of a monitored set of addresses, and for enabling software executing on the processing circuitry to access a monitoring report indication indicating whether any one of the one or more events has occurred for at least one of the monitored set of addresses; wherein: in response to the instruction decoding... The processor decodes an exclusive state setting instruction for a specified given address. The processing circuit is configured to set an exclusive state associated with the given address; the processing circuit is configured to clear the exclusive state associated with the given address in response to detecting an event indicating a conflicting memory access to the given address; and in response to the instruction decoder decoding a monitoring exclusive instruction, the processing circuit is configured to: determine whether the exclusive state is associated with a target address; and when the exclusive state is determined to be associated with the target address, allocate the target address as one of the monitored addresses from the monitored set of addresses for which the monitoring circuit monitors the one or more events.

[0004] At least some examples provide a method comprising: setting an exclusive state associated with a given address in response to decoding an exclusive state setting instruction for a specified given address; clearing the exclusive state associated with the given address in response to detecting an event indicating conflicting memory access to the given address; determining whether the exclusive state is associated with a target address in response to decoding a monitor exclusive instruction; and allocating the target address as an address in a monitored set of addresses when the exclusive state is determined to be associated with the target address; monitoring one or more events indicating a potential update to data associated with any address in the monitored set of addresses; and enabling software to access a monitoring report indication indicating whether any of the one or more events has occurred for at least one address in the monitored set of addresses.

[0005] At least some examples provide a computer program that, when executed on a host data processing device, controls the host data processing device to provide an instruction execution environment for executing instructions of object code. The computer program includes: instruction decoding program logic for decoding instructions of the object code to control the host data processing device to perform data processing corresponding to the instructions of the object code; and monitoring program logic for monitoring one or more events indicating a potential update to data associated with any one of a monitored set of addresses in a simulated address space, and for enabling the object code to access a monitoring report indication indicating whether any one of the one or more events has occurred for at least one address in the monitored set of addresses; wherein: in response to The target code contains an instruction to set an exclusive state for a given address in the simulated address space. The instruction decoding logic is configured to control the host data processing device to set an exclusive state associated with the given address. The computer program includes exclusive state clearing logic to clear the exclusive state associated with the given address in response to detecting an event indicating a conflicting memory access to the given address in the simulated address space. In response to a monitoring exclusive instruction in the target code, the instruction decoding logic is configured to control the host data processing device to: determine whether the exclusive state is associated with a target address in the simulated address space; and when the exclusive state is determined to be associated with the target address, allocate the target address as one of the monitored addresses from a set of monitored addresses for which the monitoring logic monitors the one or more events.

[0006] Computer programs may be stored on a computer-readable storage medium. This computer-readable storage medium may be a non-transitory storage medium. Attached Figure Description

[0007] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings, in which: Figure 1 An example of a data processing system is illustrated schematically, which has multiple requester devices and an interconnect for coupling the requester devices and controlling access to shared memory by the requester devices; Figure 2 An example of a processing element of a requester device is shown, which is provided with address monitoring circuitry. Figure 3 This illustrates the handling of load exclusive instructions; Figure 4 This demonstrates the clearing of the exclusive state; Figure 5 The processing of memory exclusive instructions is shown; Figure 6 Several variations of the monitor exclusive instruction and methods for processing monitor exclusive instructions are shown; Figure 7 The diagram illustrates the monitoring of potential updates to data associated with a set of monitored addresses; Figure 8 and Figure 9 An alternative example of an address tracing structure for use in address monitoring is shown; Figure 10 Two variations of the monitoring polling command and a method for processing the monitoring polling command are shown. Figure 11 The processing of monitoring polling commands is shown in more detail; and Figure 12 A simulation example is shown. Detailed Implementation

[0008] An apparatus may have an instruction decoder for decoding instructions and processing circuitry for performing data processing in response to instructions decoded by the instruction decoder. The instruction decoder and processing circuitry may support instructions defined according to a specific instruction set architecture (ISA).

[0009] Monitoring circuitry can be provided to monitor one or more events indicating a potential update to data associated with any one of the addresses in a monitored set of addresses. The monitoring circuitry enables software executing on processing circuitry to access monitoring report indicators that indicate whether any of the one or more events has occurred for at least one address in the monitored set of addresses. Such monitoring circuitry can be useful because it allows software to identify whether a particular address has been updated without the software explicitly polling the address by repeatedly issuing read requests to it. The monitoring circuitry may have circuit logic implemented in hardware that monitors relevant events indicating a potential update to one of the addresses in the monitored set of addresses and provides monitoring report information to the software when such an event has occurred. The monitored set of addresses may be software-configurable, and it may be possible to specify two or more addresses as the monitored set, thus not being limited to monitoring only a single address.

[0010] In systems with monitoring circuitry, there may be some performance overhead associated with the software configuring a set of addresses to be monitored to control which addresses will be monitored by the monitoring circuitry provided in the hardware. For example, the software might be monitoring updates to a large number of queues stored in memory, but not all queues may need to be monitored at a given time, and sometimes the software may want to evaluate certain state information about each queue, such as whether the queue is active or ready to receive updates, in order to decide whether it is necessary to monitor that queue. The software may need to prevent potential updates to the state information between the point where the state information is read and the point where a decision is made on whether to monitor the corresponding address. It should be understood that this example of monitoring queues and checking state information is only one potential use case that the software can implement (others will also exist), illustrating an exemplary scenario where there may be some overhead in establishing a set of addresses to be monitored for updates.

[0011] In the examples discussed below, the instruction decoder and processing circuitry support the processing of monitor-exclusive instructions. Monitor-exclusive instructions can be instructions defined by an ISA supported by the instruction decoder and processing circuitry. In response to the instruction decoder decoding the monitor-exclusive instruction, the processing determines whether an exclusive state is associated with a target address, and when the exclusive state is determined to be associated with a target address, assigns the target address to one of the monitored addresses from a set of addresses for which the control circuitry monitors the one or more events.

[0012] Exclusive states can be set for a specific address by executing exclusive state set instructions. In response to the instruction decoder decoding the exclusive state set instruction for a given address, the processing circuitry can set the exclusive state associated with that given address. The processing circuitry can clear the exclusive state associated with a given address in response to detecting an event indicating a conflicting memory access to that address. Detection of such events indicating conflicting memory accesses can be implemented in hardware and does not necessarily require explicit software instructions to be executed by the process executing the exclusive state set instructions. Exclusive state set instructions allow software to set exclusive states for a specific address, enabling it to check in subsequent instructions whether any conflicting memory accesses have occurred in the cycle between the exclusive state set instruction and subsequent instructions. However, in practice, processors supporting such exclusive state set instructions may often limit the setting of exclusive states to a relatively small number of addresses (in some cases, only a single address), and therefore, the exclusive state itself may be insufficient to handle multi-address monitoring use cases where the number of addresses to be monitored can be large (e.g., 50-100 or more), thus the monitoring circuitry may be better suited for problems involving multiple addresses to be monitored. However, support for assigning exclusive status to addresses could be useful for supporting monitoring exclusive instructions, which could improve the ease of configuring a set of addresses to be monitored by monitoring circuitry.

[0013] Therefore, in response to a monitor exclusive instruction, it is checked whether the exclusive state is associated with the target address, and if the exclusive state is still determined to be associated with the target address (indicating that there has been no conflicting memory access to the target address since the exclusive state was assigned), the target address is assigned as one of the monitored addresses in a set of addresses for which the control circuitry monitors the one or more events. This is useful for allowing any status information checks (used to determine whether a target address should be monitored) to be implemented atomically, even if they require more complex checks that cannot be performed in a single instruction.

[0014] For example, before assigning a specific address to a monitored set of addresses, software might need to check the state of some information in memory, and this can be done by loading data from a specific address, checking that data using a sequence of one or more instructions, and then, if the state of the data is as expected, initiating monitoring by assigning that address to the monitored set of addresses. However, to avoid race conditions (where the data at the checked address is updated by another process or device between the address being read and the result of the check being determined), these operations might need to be performed atomically. This can be relatively simple if the check is merely a single comparison of data with a known value, allowing a single instruction to load the address, compare it, and assign it to the monitored set of addresses if the comparison matches. However, the inventors recognize that in practice, software might want to test more than a single comparison condition associated with an address, such as potentially testing multiple elements at different parts of the addressed memory location, or applying comparison conditions more complex than a simple equality comparison, and therefore this might require more than one instruction to evaluate whether the conditions required to assign an address to the monitored set of addresses are met. The aforementioned support for monitor-exclusive instructions means that software can implement arbitrarily complex comparison conditions while avoiding race conditions by performing checks atomically. This is because the code sequence includes instructions to set the exclusive state, followed by instructions to perform checks. Then, the monitor-exclusive selection atomically checks the data, performs the necessary comparison operations, and, if successful, promotes the target address to a monitored set of addresses tracked by the monitoring circuitry. Therefore, providing ISA support for monitor-exclusive instructions simplifies the configuration of the monitored set of addresses for software management while still allowing for arbitrarily complex test conditions and providing support for atomic operations that avoid data race conditions.

[0015] Monitoring circuitry can be implemented in various ways to monitor one or more events that indicate a potential update to data associated with any of the addresses in a monitored set of addresses. In some cases, the monitoring circuitry can reuse functionality that may already be provided within the data processing system for managing consistency between caches in different requesting devices. Such a consistency scheme may, for example, require the exchange of certain consistency messages (e.g., memory access request / response or listener request / response) between the requesting device and the interconnect when data at a specific address needs to be accessed. The interconnect can then send listener requests to other requesting devices, if necessary, to maintain consistency between data cached at the same address at different locations in the system. In some cases, monitoring of events by the monitoring circuitry can be based on intercepting some listener messages exchanged within the system and detecting from the listener messages / responses when a given address may be updated. Alternatively, the monitoring circuitry can monitor transitions in cache consistency state within a cache associated with the processing circuitry to detect changes in cache consistency state that may be triggered by such listener requests (rather than examining the listener requests themselves). However, unlike traditional consistency mechanisms, where any change in the consistency state of data cached at a particular requester device and any exchange of listener messages between different devices to maintain consistency can be transparent to the software executing on the processing circuitry, such that accessing data cached at one device from another device does not notify the software, the monitoring circuitry enables the software executing on the processing circuitry to access monitoring report indications that indicate whether any events have occurred for one or more addresses in a monitored set of addresses.

[0016] For example, the monitoring report indication could be an interrupt sent to interrupt processing currently being performed on the processing circuitry, allowing the processing circuitry to then execute instructions (e.g., one or more instances of the monitoring polling instructions discussed below) to check which addresses may have been updated. It is not necessary for the monitoring report indication itself to identify a specific address in the monitored set of addresses that encountered the event. In some cases, the interrupt sent could be a general interrupt indicating that an event has occurred for any address in the monitored set of addresses, without distinguishing which address encountered the event. Alternatively, other methods can provide the monitoring report indication in the form of an interrupt, which is also associated with some status / verification information (e.g., stored in a software-accessible register and updated by the monitoring circuitry when an event occurs for a monitored address), which can be checked to determine which address has been updated. Other examples could not interrupt the processor when an event occurs, but could simply make data available in a software-accessible register that at least indicates whether any address in the monitored set of addresses has been updated, and optionally report which addresses have been updated. Therefore, it should be understood that there are various technologies that enable monitoring circuits to make monitoring report indications accessible to software.

[0017] In some cases, events detected by monitoring circuitry may include those that sometimes indicate data has been updated and are associated with one of the monitored addresses. However, this could also be a false alarm, which could be detected in another situation, even if the data has not actually been updated. Therefore, events detected by monitoring circuitry can be any event that, in at least some cases, indicates a risk that data may have been updated. It is not necessary for monitoring circuitry to actually detect whether data has indeed been updated. For example, sometimes monitoring circuitry may detect invalid cache entries or changes in the consistency state of cache entries. This might occur as a result of a listener request sent from another requesting device that may not have updated the corresponding data but may simply be starting the system to ensure there are no remaining conflicting copies of the data in other caches (e.g., preparing the other requesting device to have exclusive access to the data, allowing multiple subsequent updates to be performed more efficiently because it is not necessary to check the consistency state in other caches). In other cases, the same invalidation or consistency state transition of a cache entry could be caused by an actual update. Therefore, such an invalidation or consistency state transition could be an example of an event indicating a potential update, but it could be a false alarm because an update may not have occurred.

[0018] In response to the instruction decoder decoding the monitor exclusive instruction, the processing circuitry can return a monitor allocation status indicator accessible to the software. This indicator shows whether the target address was successfully allocated as an address in a monitored set of addresses in response to the monitor exclusive instruction. This is useful for the software to determine whether it is necessary to retry the operation used to allocate the target address to the monitored set of addresses.

[0019] When assigning a target address to one of the monitored addresses fails, a monitoring assignment status indicator can indicate the reason for the assignment failure. For example, the monitoring assignment status indicator can distinguish between at least two of the following reasons: an exclusive state is no longer set for the target address; an exclusive state is set for an address other than the target address; and the monitoring circuitry is unavailable or not yet configured to accept address assignments to the monitored set of addresses. For example, the monitoring assignment status indicator can be a multi-bit indicator with one code assigned to indicate a successful assignment and several other codes corresponding to different failure reasons. Distinguishing between different reasons helps the software determine how to proceed.

[0020] In some examples, the monitoring allocation status indicator can be made accessible to software by writing it into a software-accessible register. This software-accessible register can be a destination register specified by the register field of the monitoring exclusive instruction, or it can be a default register implicitly assumed to be used for writing the monitoring allocation status indicator, without an explicit register field recognizing that register as specified in the instruction code of the monitoring exclusive instruction.

[0021] The target address can be specified in different ways by a monitor-exclusive instruction. In one example, the monitor-exclusive instruction itself specifies the target address. For example, the encoding of the monitor-exclusive instruction may include operand information used to identify the target address. For example, the monitor-exclusive instruction may specify a register specifier that identifies the architecture register that provides address information used to determine the target address.

[0022] However, in other examples, the monitor exclusive instruction does not need to identify the target address itself, but can implicitly identify the target address as the address specified by the most recent exclusive state setting instruction preceding the monitor exclusive instruction. For example, circuit logic used to track the exclusive state associated with a particular address can maintain an indication of the address for which the exclusive state was most recently set, and then, when a monitor exclusive instruction is encountered, can assume that address is the target address for the monitor exclusive instruction. The indication of the most recently set exclusive address tracked by the exclusive state tracking hardware does not need to explicitly identify the address itself (although this is an option). Another option is to identify the address through other information associated with the address, such as information identifying the specific cache entry for the data associated with the address. It should be understood that the ISA definition of a monitor exclusive instruction can specify the target address as the most recent address for which the exclusive state was set by an earlier exclusive state setting instruction, but the specific way in which the hardware of the processing circuitry tracks which address is the most recent address with the exclusive state can be implemented in a specific way.

[0023] The advantage of implicitly defining the target address as a given address specified by the most recent exclusive state setting instruction is that it frees up bit space in the code of the monitor exclusive instruction that can be used for other purposes. Instruction encoding space can be very valuable in many ISAs, so any encoding efficiency can be worthwhile even if they save only a relatively small number of bits. For example, by not needing to encode the register field corresponding to the target address, the code of the monitor exclusive instruction can support register fields used to specify other information.

[0024] In some examples, in response to the instruction decoder decoding a monitor exclusive instruction, when the exclusive state is determined to be associated with a target address, the processing circuitry may assign an identifier value, designated as an operand of the monitor exclusive instruction, to an entry in the identifier storage structure corresponding to the target address. For example, the identifier value may be assigned an immediate value in the encoding of the monitor exclusive instruction, or it may be read from a register identified based on a register field specified in the encoding of the monitor exclusive instruction. This allows software to assign identifier values ​​(arbitrarily chosen by the software) to represent the target address allocated from a monitored set of addresses.

[0025] This can be useful because in many processing systems, monitoring software can use virtual addresses to identify specific data structures in memory, but monitoring can be based on physical addresses, for example, because monitoring can reuse information from consistency messages that identify addresses using physical addresses corresponding to specific locations in the memory system. In many systems, there may not be an efficient mechanism for reverse address translation to convert physical addresses back to virtual addresses. Therefore, when the monitoring circuitry has identified an update that has occurred for a specific monitored physical address, it may be necessary to provide a mechanism by which the monitoring circuitry can identify to the software which monitored address is one of a set of monitored addresses that encountered the event. For example, an identifier assigned by the software could identify one of several queues in the memory to be monitored, or it could be an array index used by the software to identify elements within an array structure (the precise meaning of the identifier depends on the software and is not a characteristic of the processor architecture or the hardware of the data processing device).

[0026] Therefore, when the monitoring circuitry detects that one or more events have occurred for a given monitored address, it enables the software to access an indication of an identifier stored in an entry of an identifier memory structure, corresponding to the given monitored address for which the event occurred. This helps the software identify which location in memory has been updated without requiring the implementation of a reverse translation mechanism (depending on its support in hardware or software), which could be more expensive in terms of circuit area and / or performance.

[0027] Identifier storage structures can be implemented in different ways. In some cases, the identifier storage structure may include a dedicated address monitoring trace structure with multiple entries, each entry tracking information associated with a corresponding set of addresses to be monitored. For example, the address monitoring trace structure may be a dedicated structure implemented in hardware separate from the data cache. The address monitoring trace structure may have entries large enough to accept software-defined identifiers associated with each monitored address. The address monitoring trace structure may also track other information, such as whether any events have occurred for the monitored address in a particular entry.

[0028] However, in other examples, the identifier storage structure may include a data structure stored in memory. For example, a monitor-exclusive instruction may specify a register field that identifies a register providing a memory address that specifies information used to identify the base address of the identifier storage structure (the value in the register may directly identify the base address, or may identify other information from which the base address can be determined—for example, where the base address of the identifier storage structure is at another address at a fixed, implicitly defined offset from that address). In response to the monitor-exclusive instruction, if the address allocation operation is successful, the processing circuitry can use the base address (and the offset derived from the target address or other information associated with the target address, such as cache set / path information indicating the cache entry corresponding to the target address) to identify the address of the relevant entry in the identifier storage structure to be updated with the identifier corresponding to the allocated target address.

[0029] By providing the identifier storage structure as a data structure stored in memory, the hardware cost supporting monitoring is lower because there is no need to provide a dedicated storage structure in the hardware for storing software-provided identifiers. It should be noted that the identifiers from the data structure representing the identifier storage structure can ultimately be stored in memory, but they can also be cached so that they can be accessed faster than the underlying memory (and in some cases, if cached in a write-back cache, it is not necessary for the backup storage in memory to be updated with the identifier when the monitoring circuit reads back the identifier later after an event has occurred for the monitored address). For example, the size of the identifier storage structure can be chosen such that it does not occupy the full capacity of the first-level (or subsequent-level) data cache, such that there is space in the first-level data cache for at least a portion of the identifier storage structure and a reasonable number of other data lines (such as cache lines corresponding to the data at the monitored address). The method where the identifier storage structure is a structure in memory (potentially cached) is more efficiently implemented in hardware.

[0030] The aforementioned variant of the monitor exclusive instruction, which implicitly specifies the target address as the given address specified by the most recent exclusive state setting instruction, is particularly useful for enabling the identifier storage structure to be implemented as a memory-based structure. This is because by avoiding the need to specify the target address itself as an operand of the monitor exclusive instruction, this frees up space in the instruction encoding for other information, such as register fields for identifying the base address of the identifier storage structure.

[0031] As mentioned above, monitoring report indications that enable software access when relevant events occur for a monitored set of addresses can take various forms. However, in some cases, the information provided may be relatively limited, and may, for example, only indicate that at least one event has occurred for any one of the monitored addresses, without specifically identifying further information about which address encountered the event. Therefore, in some implementations, it may be useful to support monitored polling instructions that can provide more information about which addresses encountered the event. In response to the instruction decoder decoding the monitoring polling instruction, at least one of the processing circuitry and the monitoring circuitry enables software access to monitoring polling information indicating which address in the monitored set of addresses has encountered one or more events. For example, monitoring polling information can be made accessible to software by writing it to a destination register identified by the monitoring polling instruction. The software can then include further instructions using that destination register as a source register to process the monitoring polling instruction and then determine how to respond based on which address in the monitored set of addresses encountered the event.

[0032] In a specific implementation where the monitor-exclusive instruction can specify a software-defined identifier, the identifier is assigned to the identifier storage structure when the address allocation operation described above is successful. The monitor polling information may then include an identifier value associated with at least one address from the monitored set of addresses for which the monitoring circuitry determines that one or more events have occurred. Therefore, the identifier value associated with the monitored address for which the event occurred need not be provided as an initial monitoring report instruction to notify the software that the event has occurred, but can be provided within the monitored polling information available to the software when the software subsequently executes the monitor polling instruction. To support this use case in implementations where the identifier storage structure is a memory-based structure, a variant of the monitor polling instruction can specify the information for specifying the base address of the identifier storage structure as one of its operands (in a manner similar to specifying the information for identifying the base address in the monitor-exclusive instruction described above).

[0033] Another piece of information that may be included in the monitoring polling information is a count value indicating the number of addresses in a monitored set of addresses for which one or more events have occurred. In some cases, this count value may indicate the total number of addresses for which an event has occurred, or it may indicate the number of remaining addresses in a monitored set of addresses for which one or more events have occurred, and the software has not yet triggered the return of information about that particular address by executing a monitoring polling instruction. For example, in some cases, the monitoring polling information returned in response to a single instance of a monitoring polling instruction may return information about a single monitored address at a time; therefore, if an event has occurred for more than one address in a monitored set of addresses, this may require executing multiple instances of the monitoring polling instruction to return identifiers or other information about the updated addresses for which the event occurred. For example, the software may include a loop that iterates over each monitored address for which it determines an event has occurred. Thus, by returning a count value indicating the total number or remaining number of addresses for which an event has occurred, the software can determine whether further iterations of the monitoring polling operation are still necessary.

[0034] An exclusive state set instruction can be any instruction capable of controlling the processing circuitry to set an exclusive state for a given address. However, in one example, the exclusive state set instruction is a load exclusive instruction. In response to the instruction decoder decoding the load exclusive instruction, the processing circuitry can load the data associated with the given address into at least one destination register specified by the load exclusive instruction and set the exclusive state associated with the given address. By supporting load exclusive instructions that both set an exclusive state and load the data associated with the address for which the exclusive state is set, this can be used to support atomic sets of operations, such as the set of operations discussed above for the configuration of a monitored set of addresses, because it is not necessary to issue a separate instruction to load data from a given address and mark it as exclusive.

[0035] Monitor exclusive instructions need not be the only type of instruction that uses exclusive states configurable by exclusive state setting instructions. Another type of instruction supported in the ISA can be a memory exclusive instruction that specifies a memory destination address and at least one source register. In response to the decoding of the memory exclusive instruction by the instruction decoder, the processing circuitry can determine whether an exclusive state is associated with a memory destination address, and if so, store data from at least one source register to the memory location associated with the memory destination address. Therefore, monitor exclusive instructions can reuse the same infrastructure to track exclusive states, which may already be supported for processing load / store exclusive instruction pairs, and thus can be implemented at a relatively low additional cost compared to architectures that already support load / store exclusive instructions.

[0036] The techniques discussed above can be implemented within a data processing device having hardware circuitry providing the instruction decoder, processing circuitry, and monitoring circuitry discussed above. However, the same techniques can also be implemented within a computer program that executes on a host data processing device to provide an instruction execution environment for executing target code. Such a computer program can control the host data processing device to simulate an architectural environment that will be provided on a hardware device that actually supports a specific instruction set architecture, even if the host data processing device itself does not support that architecture. Therefore, the computer program can include instruction decoding program logic that decodes the program instructions of the target code to control the host data processing device to perform data processing in response to the program instructions of the target code (e.g., mapping each instruction in the target code to a series of one or more instructions in the host's native instruction set to achieve equivalent functionality). The instruction decoding program logic can support monitor exclusive instructions and exclusive state setting instructions as described above. Furthermore, the instruction decoding program logic can support other instructions mentioned earlier (e.g., monitor polling instructions, load exclusive instructions, store exclusive instructions). The computational program may also include exclusive state clearing logic that clears the exclusive state in a manner corresponding to the clearing performed by the aforementioned processing circuitry, and monitoring program logic corresponding to the function of the aforementioned monitoring circuitry. In the simulation program, memory access can be simulated in a simulated manner because the address space addressed by the object code can be in a simulated address space, which may differ from the host address space used by the host processor. Furthermore, the simulation can use access to the host processor's host memory devices (e.g., host registers or host memory) to simulate registers defined by the simulated architecture. For example, such simulation programs are useful when executing legacy code written for one instruction set architecture on a host processor that supports different instruction set architectures. Additionally, simulation can allow software development for a newer version of the instruction set architecture to begin before the processing hardware supporting the new architecture version is ready, because execution of the software in the simulated execution environment allows software testing to be performed in parallel with ongoing development of hardware devices supporting the new architecture. The simulation program can be stored on a storage medium, which may be a non-transitory storage medium.

[0037] Figure 1 An example of a data processing system 2 (e.g., an integrated circuit or system-on-a-chip) is schematically shown, which includes multiple requesting devices 4, 6, 8 and an interconnect 10 for managing the consistency of data cached in cache 12 of the respective requesting devices. The interconnect 10 also controls access to shared memory 14. Figure 1As shown, more than one memory module 14 may be coupled to the interconnect 10, and this memory module may be accessed from any of the requester devices 4, 6, and 8. In this example, the requester device includes one or more processing elements 4 and 6, which are elements that support the execution of instructions defined according to a specific instruction set architecture (ISA). Processing elements 4 and 6 may include one or more caches 12 (although for simplicity...). Figure 1 Only a single cache is shown, but the cache can be implemented as a hierarchical structure with multiple levels of cache. Processing elements 4 and 6 can be, for example, a central processing unit (CPU) for performing general-purpose processing or a graphics processing unit (GPU) for performing graphics processing. The system may also include one or more requesting devices 8, which may not have their own cache 12, but may have direct memory access (DMA) to memory 14, allowing them to issue requests for memory access without being explicitly controlled to do so by processing elements 4 and 6. For example, device 8 can be an input / output (I / O) device, such as a network interface controller (NIC) for controlling the transmission and reception of data over a network, a display controller for controlling the display of data on a screen, a direct memory access (DMA) controller for controlling data transfer between memory and peripheral devices, to name just a few examples.

[0038] Interconnector 10 is responsible for maintaining consistency among cached data in cache 12. A consistency protocol can be used to define rules for managing how the system responds to a requester accessing a given address, ensuring that subsequent accesses to the same address from other requesters see data consistent with the result of the request from the first requester. For example, the consistency protocol can define multiple request and response messages and protocols for when different kinds of messages should be generated, as well as multiple consistency states that can be associated with data stored in cache 12 or in system cache 16 provided within interconnector 10 (system cache 16 is shared among requesters and provides faster access to data compared to if data must be retrieved from memory 14). For example, when a processing element 4 initiates a request to read or write data from a specific address in its cache 12, this can trigger various requests to the interconnector, which, if necessary, sends a listening request to cache 12 in other requesters to inquire about the consistency status of the data at that requester's cache or, if necessary, invalidates the data cached from that requester's cache. In some cases, the interconnector may have a listening filter (such as...). Figure 1As shown, it can be combined with system cache 16, but can also be a standalone element. This snooping filter can be used to at least partially track which requesters are caching data from a given address, allowing some snooping traffic to be eliminated if it is known that a requester's cache 12 does not cache data from a specific address. Any known consensus protocol can be used to maintain consistency. Examples of usable consensus protocols are provided by Arm, Cambridge, UK. ® AMBA provided by Limited Company ® 4. ACE and AMBA ® 5. CHI consensus protocol; however, it should be understood that other consensus protocols can also be used to maintain consistency.

[0039] In such Figure 1 In the system shown, interactions between different requesters can be performed by accessing shared data structures in the memory system. For example, if device 8 is a network interface controller, the data queue can be updated based on the received packets when data is received from the network. Software executing on one of the processing elements 4 and 6 may wish to check those queues to see if any data is available for processing, and if so, perform the corresponding action. If the number of queues to be monitored is not particularly large, it is feasible for the software to simply periodically execute load instructions to read the address in memory mapped to each queue and check if there are any changes that need to be processed. However, the number of queues to be monitored may be large, for example, more than 100, so such polling of addresses in memory can incur significant overhead. The following example discusses address monitoring functionality that can be supported in the hardware implementation architecture of processing elements 4 and 6 to reduce the performance and power costs of monitoring addresses in memory to check if those addresses have been updated. By providing some hardware that can be configured by software to monitor updates to specific addresses, such that when any of those addresses is updated, an indication is then provided to the software, this avoids the need for the software to explicitly read those addresses repeatedly. If there are no other processes to be performed, this allows processing elements 4 and 6 to enter a power-saving mode for a period of time, waiting for an event to be reported when one of the monitored addresses has been updated, thus saving power, which would not be possible if the software had to keep issuing explicit read requests to access the location in memory corresponding to the monitored address.

[0040] Although Figure 1The illustration shows a scenario where software executing on processing elements 4 and 6 is waiting for a data structure to be updated by another requesting device 8, such as a network controller. However, a similar address monitoring problem may arise when multiple software processes executing on the same processing elements 4 and 6 are communicating using updates to data at addresses in shared memory 14. Therefore, monitoring is not necessary for changes made by another requesting device.

[0041] Figure 2 The characteristics of one of the processing elements 4 and 6 are shown in more detail. It should be understood that all processing elements 4 and 6 within the system do not need to have the same design; for example, an asymmetric multiprocessor system could be provided that includes processing elements supporting the same ISA but with different microarchitectural implementations. Therefore, it is not necessary for each processing element to have... Figure 2 The features shown. For example, not every processing element needs to include address monitoring circuitry 36.

[0042] Processing elements 4 and 6 include an instruction decoder 20 for receiving program instructions (defined according to a specific instruction set architecture), which have been received from memory 14 or from an instruction cache (not in the instruction cache). Figure 1 and Figure 2 (As shown in the diagram, but may be provided within the processing element) The instruction is extracted. The instruction decoder 20 decodes the extracted instruction to generate control signals for controlling the processing circuit 22 to perform the operation represented by the instruction. The processing circuit 22 has access to register 24, which can be used to store the operands and results of the instructions processed by the processing circuit 22. The processing circuit 22 may include multiple execution units for executing different types of instructions, such as an arithmetic / logic unit (ALU) for executing arithmetic or logical instructions, or a branch unit for executing branch instructions. For simplicity, Figure 2 Different types of execution units are not shown, except for a load / store unit 26, which executes load instructions for loading data from the memory system (including main memory 14 and any caches 12, 16) into register 24 or store instructions for storing data from register 24 into memory systems 12, 14, 16. A memory management unit 28 may be provided to provide memory protection and / or address translation functions to control which addresses in the memory address space are allowed to be accessed by specific software executing on processing circuitry 22 and / or to manage the translation between software-specified virtual addresses and physical addresses used to identify locations within the memory system. Although Figure 2An example of a single data cache 12 as a cache for a processing element is shown, but it should be understood that multi-level caches dedicated to a particular processing element, such as a Level 1 data cache and a Level 2 cache (or an additional level cache), can be provided. Therefore, references to cache 12 can include multi-level cache hierarchies.

[0043] The processing element has an exclusive state tracking circuit 30 for tracking the exclusive state associated with a specific address. An exclusive state setting instruction can be executed on the processing circuit 22 (e.g., as described below regarding...). Figure 3 The described load exclusive instruction selects the address for the exclusive state. When an exclusive state setting instruction specifying a given address is executed, the tracked address indicator 32 indicating the given address is stored, and the exclusive state indicator 34 is set to indicate that the given address indicated by the tracked address indicator 32 has an exclusive state. Subsequently, the exclusive state tracking circuit 30 monitors for events indicating conflicting memory accesses to the tracked address, and if an event is detected, clears the exclusive state by changing the state of the exclusive state indicator 34. Certain instructions can test whether the tracked address is still indicated to have an exclusive state, and the processing circuit 22 can be controlled to perform operations conditionally based on whether the address is still indicated to have an exclusive state. This is useful for ensuring that certain instruction sequences are executed atomically between initial operations involving the tracked address and subsequent operations, which is useful for avoiding data race conditions when multiple requesters may make conflicting accesses to addresses in memory, resulting in the loss of one of those accesses or the access to outdated data.

[0044] However, the exclusive state tracking circuit 30 may be relatively limited in the number of addresses it can monitor, for example, limited to tracking a single address at a time. Therefore, an address monitoring circuit 36 ​​is also provided to perform monitoring of a wider set of monitored addresses and to report to the software when one of the previously configured set of monitored addresses has encountered an event indicating a potential update to the data at that address. For example, as Figure 2 As shown, the address monitoring circuit 36 ​​can send an interrupt signal to the processing circuit 22 to interrupt the currently executing processing (or alternatively, if the processing circuit is in a power-saving state, the interrupt can wake the processing circuit), allowing the software to respond to the interrupt by executing instructions to identify which address has changed state and to perform subsequent processing based on which address has been updated. This is useful for supporting the queue monitoring use cases discussed above, but it can also be used for other purposes. The address monitoring circuit 36 ​​will be discussed in more detail below, but first, exclusive state tracking will be discussed in more detail.

[0045] Figure 3The processing of the Load Exclusive instruction LDXR, an example of an exclusive state setting instruction, is shown. The Load Exclusive instruction specifies the destination register Xd and the address operand register Xn, which stores a value indicating the given address. Figure 3 In step S100, the instruction decoder 20 decodes the load exclusive instruction. In response to the load exclusive instruction, the instruction decoder controls the processing circuit 22 to execute... Figure 3 The subsequent steps. At step S102, the processing circuitry sets the exclusive state associated with the given address. For example, the tracked address indicator 32 may be updated to specify information that allows identification of the given address, and the exclusive state indicator 34 may be set to a specific value to indicate the presence of an exclusive state. In some cases, the tracked address indicator 32 may be updated to specify the physical address corresponding to the given address. However, it is also possible for the tracked address indicator to indirectly identify the given address, for example, by identifying a specific entry within the data cache 12 associated with the data at the given address. For example, the tracked address indicator 32 may be information specifying a cache set / path identifier for identifying the relevant entry in a cache implemented using a set-associated allocation strategy. In some implementations, this format for the tracked address indicator may be more simply compared with information returned from the cache when a snooping or consistency state transition to a specific address is detected to determine whether the exclusive state needs to be cleared. It should be understood that although the encoding of the load exclusive instruction and the exclusive state setting operation represented by that instruction can be specified in the ISA supported by the processing system, the exact format of the address indicator 32 and the exclusive state indicator 34 used to track whether an exclusive state is set for a specific address is not specified by the architecture and can vary from implementation to implementation. Therefore, the exact format of the address indicator 32 and the exclusive state indicator 34 is not a necessary feature. Generally, any information that allows the system to determine whether an exclusive state is still set for a given address can be stored.

[0046] At step S104, in response to a load exclusive instruction, the load / store unit 26 of the processing circuit 6 performs a load operation to load data associated with a given address from cache 12 or memory 14 into a destination register identified based on the register specifier Xd specified in the load exclusive instruction. Although Figure 3 Steps S102 and S104 are shown in sequence, but it should be understood that other specific implementations may perform these steps in reverse order or in parallel.

[0047] Figure 3 An example of a load exclusive instruction as an exclusive state setting instruction is shown. Some ISAs also support exclusive state setting instructions, which allow setting an exclusive state for an address without triggering the loading of data associated with the target address.

[0048] Figure 4 The steps are illustrated, performed by the exclusive state tracking circuit 30 to maintain the exclusive state indication 34 while monitoring for events that may indicate conflicting memory access. At step S110, the exclusive state tracking circuit 30 detects whether an event has been detected indicating a possible conflicting memory access to a given address indicated by the tracked address indication 32, for which an exclusive state has been set. For example, this event could be the detection of a listener request received from the interconnect 10, indicating that another requester has requested to write data to the location associated with the given address, or has requested to invalidate or clear any cached data from cache 12 that may already be cached with the given address. Furthermore, the event indicating a conflicting memory access can be an invalidation of a cache entry in data cache 12 associated with a given address (which may potentially have been triggered by a listener from another device capable of updating data for that address), or a transition in the consistency state of a cache entry associated with a given address (e.g., a transition from an "exclusive" consistency state to a "shared" or "invalid" consistency state, where an "exclusive" consistency state indicates that the corresponding cache data can be updated by the requester who owns the cache without listening to the interconnect to check if the corresponding cache data exists in other caches 12; a "shared" consistency state indicates that the corresponding cache data is valid, but updating the cache data by the requester who owns the cache would require sending a message to the interconnect 10 to allow checking if other requesters have maintained the corresponding data; and an "invalid" consistency state indicates that the cache does not maintain valid data for the corresponding address). It should be noted that the "exclusive" consistency state mentioned here refers to one of a set of consistency states defined by the consistency protocol used by the interconnect 10 and caches 12, 16, and is an orthogonal property of the exclusive states indicated by the exclusive state tracking circuitry 30. Therefore, even if the corresponding address is not tracked as exclusive by the exclusive state tracking circuit 30, the cache entry can still be marked as having an exclusive consistency state. Similarly, even if the corresponding cache data in cache 12 is not marked as having an exclusive consistency state, the address can still be tracked as exclusive by the exclusive state tracking circuit 30.

[0049] If any such event indicating a conflicting memory access to a given address for which an exclusive state has been set is detected at step S110, then at step S112, the exclusive state tracking circuit 30 clears the exclusive state for that address by toggling the state of the exclusive state indicator 34. This allows the processing circuitry to determine, for subsequent instructions encoded with codes indicating that an operation should be performed while the exclusive state is still set, that the operation should not be performed. This means that the execution of a conditional operation can depend on the absence of an intervening memory access to a given address due to a load exclusive instruction or other exclusive state setting instruction, which can be used to implement a set of atomic operations. It should be understood that an event indicating a conflicting memory access may not be the only type of event that can cause the exclusive state to be cleared for a tracked address. Since the exclusive state tracking circuit 30 may only have a limited capacity to track a limited number of addresses (e.g., in...), Figure 2 In the example, only a single address is in exclusive state. Therefore, the execution of another load exclusive instruction specifying a different address can cause the exclusive state of the previously tracked address to be cleared because the previously tracked address instruction 32 is overwritten with an instruction for the new address. Moreover, if an interrupt or exception occurs, this can cause the exclusive state tracking circuit 30 to clear the exclusive state for the previously tracked address. Therefore, in addition to conflicting memory accesses to the tracked address, there may be other events that could cause the exclusive state to be lost.

[0050] Figure 5The processing of a memory exclusive instruction STXR is illustrated, which can be used by software to request processing circuitry 22 to perform a memory operation to store data into memory system locations 12, 14, and 16 identified by a memory target address, wherein the storage is conditional upon the memory target address still being identified as exclusive by exclusive status tracking circuitry 30. At step S120, instruction decoder 20 decodes the memory exclusive instruction. The memory exclusive instruction specifies the destination register Xd, source register Xs, and address operand register Xn. The address operand register stores a value that can be used to determine the memory target address. In response to the memory exclusive instruction, at step S122, control processing circuitry 22 determines whether an exclusive status is still associated with the memory target address. Therefore, information in the tracked address indicator 32 can be compared with information derived from the memory target address to determine whether the tracked address matches the memory target address, and exclusive status indicator 34 is also checked to determine whether it has a value indicating that an exclusive status is set. If an exclusive state is set and the storage target address matches the address for which an exclusive state is set, then at step S124, load / store unit 26 continues the storage operation to store data from source register X to the memory location associated with the storage target address. At step S126, the exclusive state for the storage target address is cleared, and at step S128, the destination register Xd is set to a status value indicating a successful storage operation. In contrast, if it is determined at step S122 that the storage target address is not set to exclusive (e.g., the storage target address does not match the tracked address indicated by tracked address indicator 32, or if the exclusive state indicator 34 is cleared), then the storage operation is omitted at step S130, and at S132, the destination register Xd is set to a status value indicating an unsuccessful storage operation.

[0051] Therefore, the status value written to the destination register Xd can be used by software to determine whether the store was successful, and thus whether the store needs to be retried (and possibly earlier operations may also need to be retried) or whether processing can then continue outside of the store. This is useful for allowing the definition of a set of atomic operations bounded by load-exclusive instructions and store-exclusive instructions to ensure that the store only occurs if there has been no memory access since the load.

[0052] The exclusive state tracked by the exclusive state tracking circuit 30 can also be used to monitor exclusive instructions, which can be used to allow the software to configure the address monitoring circuit 36 ​​to monitor updates to a specific address. Figure 6 Three alternative variants of the monitor exclusive instruction MONX are shown. Different implementations may support different options, and therefore any one or more of these variants may be supported in a given implementation.

[0053] In the first variant, the monitor-exclusive instruction MONX specifies the destination register Xd to be updated with a status indicator. Similar to the memory-exclusive instructions discussed above, the status indicator provides an indication of whether the monitor-exclusive operation was successful. However, unlike the memory-exclusive instructions discussed above, for monitor-exclusive instructions, the status indicator may not only provide a pass / fail binary indication, but also provide information about the cause of failure in the case of failure, potentially distinguishing between two or more different possible causes of failure. In variant 1, the monitor-exclusive instruction also specifies a register field identifying the address register Xn, which stores information used to determine the target address that is attempted to be assigned to a monitored set of addresses tracked by the address monitoring circuitry 36.

[0054] For variant 2, the destination register Xd and address register Xn are the same as in variant 1, but the monitor exclusive instruction also specifies an additional source register Xs, which can be used to provide a software-defined identifier value that can be assigned to the identifier structure, so that when the address monitoring circuit 36 ​​recognizes that data has been updated for the monitored address, the software-defined identifier can be returned to allow the software to identify which address has changed.

[0055] Variant 3 of the monitor exclusive instruction MONX specifies the same destination register Xd and source register Xs as in Variant 2. However, in Variant 3, the address indicated by the address register Xn is used to indicate information about the base address of the identifier storage structure used to track software-defined identifiers, instead of indicating the destination address itself (as described below). Figure 9 (To be discussed further). In this example, the target address to be assigned to one of the monitored set of addresses is not encoded in the monitoring exclusive instruction itself, but is implicitly defined as the address specified by the most recently executed exclusive state setting instruction (e.g., the address specified by the most recently loaded exclusive instruction in the same thread as the monitoring exclusive instruction). For example, the target address may be identified based on the tracked address indication 32 identified by the exclusive state tracking circuit 30.

[0056] Figure 6 The flowchart illustrates the processing of any one of the three variations of the monitor exclusive instruction MONX. At step S150, the instruction decoder 20 decodes the monitor exclusive instruction and generates controls for the processing circuit 22 and other system components (such as the address monitoring circuit 36 ​​or the exclusive status tracking circuit 30) to execute. Figure 6 The signals for the operations shown in the remaining steps.

[0057] At step S152, in response to a monitor exclusive instruction, the processing circuitry determines whether the exclusive state is associated with the target address associated with the monitor exclusive instruction. For variants 1 and 2, the target address is identified based on the value stored in the address operand register Xn specified by the monitor exclusive instruction. For variant 3, the target address is a given address specified by the most recent exclusive state setting instruction. Therefore, for variants 1 or 2, a comparison can be performed between the tracked address indication 32 and the target address of the monitor exclusive instruction to check if they match, and the exclusive state indication 34 can also be checked to determine if the target address has an exclusive state. For variant 3, it may be implicit that the target address of the monitor exclusive instruction will match the most recently tracked exclusive address, so for variant 3, checking the exclusive state indication 34 may be sufficient without address comparison. In either case, if it is determined that the exclusive state is associated with the target address associated with the monitor exclusive instruction, at step S154, the processing circuitry also determines whether the address monitoring circuitry 36 is available and configured to accept address assignment to the monitored set of addresses. Some systems may allow the address monitoring circuit 36 ​​to be disabled or powered down to save power, and therefore it may not always be available. Moreover, in some cases, certain control parameters may need to be established before the address monitoring circuit 36 ​​can be used, so if this has not been completed, the monitoring circuit may not yet be configured to accept address assignments to the monitored set of addresses.

[0058] If the monitoring circuit is determined to be available and configured to accept address allocation to a monitored set of addresses at step S154, then the address allocation operation can be performed at step S156, and thus the target address can be allocated to one of the monitored addresses that will be subject to address monitoring by the address monitoring circuit 36. If the monitored exclusive instruction is variant 2 or 3, then at step S158, the processing circuit will also allocate the identifier value read from the source register Xs of the instruction to the entry in the identifier storage structure corresponding to the target address. (See below for details...) Figure 8 and Figure 9 The discussion may cover different ways of implementing this identifier storage structure. Furthermore, in the case of an executable address allocation operation, at step S160, the exclusive state tracked by the exclusive state tracking circuit 30 is cleared for the target address (because the monitoring exclusive instruction has completed the set of atomic operations managed using the exclusive state indicator). Moreover, at step S162, the instruction's destination register Xd is set to the monitoring allocation state indicator indicating that the address allocation operation was successful.

[0059] On the other hand, if it is determined at step S152 that the target address does not have an exclusive state, or at step S154 the monitoring circuit is unavailable or not configured to accept address allocation, the address allocation operation is omitted at step S164. Therefore, any one of steps S156, S158, S160 and S162 will not be executed, and instead, at step S166 the destination register Xd is set to a monitoring allocation status indicator with a different value indicating that the address allocation operation was unsuccessful.

[0060] In some cases, the monitoring allocation status indicator can be a unit value, which may have one value (e.g., 0) indicating a successful address allocation operation and another value (e.g., 1) indicating an unsuccessful address allocation operation.

[0061] However, multiple allocation status indicators can also be provided, which can provide more information about the reasons for failure in cases where the address allocation operation cannot be performed. For example, if the monitoring allocation status indicator is set to zero, this can indicate a successful address allocation operation, while a non-zero value can indicate a different reason for failure. For example, if the address allocation operation fails because it is determined that the exclusive state is not associated with the target address, the monitoring allocation status indicator can be set to 1, while monitoring allocation status indicators 2 or more can be used for other reasons, such as the monitoring circuit being determined to be unavailable or not configured at step S154, or, in the case of variant 1 or 2, the target address of the monitored exclusive instruction does not match the address tracked by the tracked address indicator 32 of the exclusive state tracking circuit 30. Of course, other codes for the monitoring allocation status indicator can be used.

[0062] Although Figure 6 The sequence of steps is shown, but it should be understood that the steps can be reordered or performed in parallel. For example, steps S152 and S154 can be interchanged or performed in parallel. Moreover, the various operations performed at steps S156, S158, S160, and S162 when the assignment operation is successful can be performed in any order, or in parallel as two or more of these steps.

[0063] This exclusive monitoring instruction can be used to allow software to perform more complex checks than simply comparing a single value at a given address to determine whether a specific address within a monitored set of addresses needs to be monitored. For example, this is useful for testing multiple elements of a data structure to determine whether a particular software queue in memory needs to be monitored. Such more complex checks may require relatively flexible comparison operations that cannot be performed in a single instruction. This can present challenges regarding how to perform those comparisons atomically, as data needs to be read from memory to perform the checks, and then by the time the checks are complete, the conclusions may only be reliable if no other requester has simultaneously updated some relevant data within the relevant data set.

[0064] Therefore, by defining instruction set architecture support for the monitoring exclusive instructions described here, the software can now define a series of codes as follows: • The load exclusive instruction described above can be used to load the data to be inspected and mark the relevant addresses as exclusive; • One or more additional instructions can be implemented to define the associated comparison operation. For example, this can include various arithmetic instructions, logical instructions, or comparison instructions.

[0065] • If the comparison operation is successful, the address associated with the load exclusive operation can be promoted to the address monitoring circuit 36 ​​using the monitor exclusive instruction, provided that the address is still marked as having an exclusive state.

[0066] The monitoring exclusive instruction does not need to be a unique instruction supported by the instruction decoder 20 and processing circuit 22 for assigning an address to a monitored set of addresses. It may also support instructions that assign an address to a monitored set of addresses regardless of whether the address is in an exclusive state, which can be used when the setting of the monitored address does not depend on a set of atomic operations on the state data in the comparison memory.

[0067] Figure 7 The monitoring performed by address monitoring circuit 36 ​​is illustrated. At step S170, address monitoring circuit 36 ​​detects an event indicating a potential update to data associated with any previously configured address in the monitored set of addresses. For example, the event detected by the monitoring circuit could be receiving a listen request from interconnect 10 indicating that the consistency state of the monitored address should change from "exclusive" to "invalid" or "shared," or detecting such a consistency state transition in cache 12. In response to detecting this event, at step S172, the monitoring circuit sets information indicating which address in the monitored set of addresses encountered the event detected at step S170. For example, as shown below, address monitoring circuit 36 ​​can maintain a data structure, either in hardware or using data stored in memory, that tracks which address in the monitored set of addresses encountered the event. At step S174, address monitoring circuit 36 ​​enables the software executing on processing circuit 22 to access monitoring report information indicating that the event has occurred. For example, this could be the generation of an interrupt that could wake up the processing circuitry 22 from a power-saving state or switch it to processing of an interrupt handler, so that software requiring a monitored address could then respond to an update.

[0068] An interrupt indicating that an event has occurred does not need to be generated every time an event has occurred. For example, if another event is detected for one of the monitored addresses after an interrupt has been triggered and before the processing circuitry has processed the interrupt and before the interrupt has been cleared, a second interrupt need not be generated. Moreover, in some implementations, in addition to triggering an interrupt, another mechanism can be used to notify the software that an event has occurred for the monitored address. For example, the information can be stored in a register that can be read by the software. However, an interrupt-based mechanism can be used to allow the processing circuitry 22 to use a "wait for event" instruction to signal that it should enter a power-saving mode until it receives an interrupt indicating that an event has occurred for one of the monitored addresses. This can be useful if the processing circuitry 22 has no other functional processing to perform until an event has occurred for one of the monitored addresses.

[0069] Figure 8 and Figure 9 Different ways of implementing the address monitoring circuit 36 ​​and various structures for tracking the monitored addresses are shown. It should be understood that these are merely two examples, and other ways of constructing information for tracking which addresses are being monitored and which of those addresses have encountered events may also exist.

[0070] Figure 8 A first method is shown, which can be used in specific implementations of variant 1 or 2 of the monitoring exclusive instruction, where specifying an address in memory to provide a metadata structure for tracking information about the monitored address is not supported. Therefore, in Figure 8 In the method shown, a dedicated buffer can be provided in hardware to act as an address tracking structure 200 for tracking information about the monitored address. Furthermore, the address monitoring circuit 36 ​​can use status information stored in the data cache 12 to monitor updates to data associated with certain addresses.

[0071] In this example, the data cache 12 includes multiple entries 13, each of which caches data 210 from a specific address in the memory system. A tag value 212 is stored with each entry to indicate information used to identify the address associated with the corresponding data, and a validity flag 214 may be provided in each entry to indicate whether the data is valid. Furthermore, each entry 13 may specify a consistency state 216, which is used to identify whether the data is clean or dirty, or whether the data is in an exclusive or shared consistency state as described above. In some cases, the consistency state 216 and the validity flag 214 may be combined into a single indicator (“invalid” is considered one of the consistency states indicated by the consistency state 216).

[0072] like Figure 8 As shown, a "monitored" indication 218 can also be provided to each cache entry, indicating whether the address associated with that cache entry is in a monitored set of addresses that has been previously configured by executing a monitor exclusive instruction or other instructions for allocating addresses to a monitored set. Therefore, in this example, when executing... Figure 6 In step S156, this may include setting a monitored indication 218 in a cache entry corresponding to data associated with the target address to indicate that the target address is in a monitored set of addresses.

[0073] The address monitoring circuit 36 ​​also maintains the address tracking structure 200 as a separate cache structure from the data cache 12 itself for tracking further information about each monitored address. For example, the address tracking structure may have a number of entries, each corresponding to a specific cache entry 13 that has been indicated as corresponding to a monitored address. The number of entries in the address tracking structure 200 may not be as large as the number of entries in the cache 12. Each entry in the address tracking structure may, for example, specify a cache entry identifier 220 that identifies the corresponding cache entry, which may be in… Figure 6 In step S158, a software identifier 222 for the identifier of the corresponding address is assigned to the identifier storage structure, and a "monitored" indication 224 indicates whether a relevant event (e.g., a consistency state transition triggered by a listener) has been detected for the corresponding monitored address. The address monitoring circuit 36 ​​may also maintain a counter value 230 that tracks how many addresses in the monitored group have encountered a listener event indicating that the corresponding address has been updated.

[0074] Therefore, when an address is assigned to a monitored set of addresses, a corresponding monitored indicator 228 can be set in the relevant cache entry, and a software-defined identifier value can also be assigned to the corresponding entry in the address tracking structure 200. The field 220 of the relevant address tracking structure entry can be set to cache set / path information, such as identifying the location of the corresponding cache entry within the data cache 12. If variant 1 of the monitored exclusive instruction is executed, support for the software identifier 222 is not required.

[0075] On the other hand, when the control circuitry logic 240 associated with the data cache detects a snoop received from the interconnect 10, the cache control logic 240 can check the data cache 12 to determine if there is a corresponding entry associated with the address specified by the snoop request (by comparing the tag field 212 of one or more cache entries). If the address specified by the snoop request matches a valid cache entry for which a monitored indication 218 has been set to indicate that the corresponding address is part of a monitored set of addresses, the address monitoring circuitry 36 generates an interrupt or other notification to the software to indicate that an event has occurred and increments the count 230 of the number of snooped addresses detected within the monitored set. Furthermore, the address monitoring circuitry 36 updates the snooped indication 224 in the entries of the address tracking structure 200, which corresponds to the snooped monitored address. This allows subsequent monitoring polling instructions to check which specific address is being snooped and obtain the corresponding software ID 222.

[0076] Figure 8 The method shown can be used to avoid consuming memory space used for address tracking, but may require hardware implementation to provide additional address tracking structures. Alternatively, although Figure 8 The address tracking structure 200 is shown separately from the data cache 12, but other implementations may provide each cache entry 13 with additional fields for tracking the software ID 222 and the indication 224 being monitored. Either way, this may require additional circuitry hardware.

[0077] Figure 9An alternative approach is shown, wherein instead, the address monitoring data structure can be stored in the memory system itself (cached in data cache 12 if necessary), eliminating the need for the additional address tracking structure 200. This can be supported in a specific implementation of variant 3 of the aforementioned monitor-exclusive instruction, where the instruction uses its address register Xn to identify information for specifying the base address 250 of the identifier storage structure 260 stored in the memory system. The identifier storage structure 260 may store a software identifier 222 allocated by variant 3 of the monitor-exclusive instruction for the corresponding monitored address. The identifier storage structure 260 may include the identifier for each cache line in data cache 12, and indexing into the structure may use an offset relative to the base address, determined based on the monitored entry in data cache 12 (or the entry to which the monitored address is allocated when the identifier 222 is stored in the identifier storage structure 260 when the address for monitoring is allocated). The address monitoring circuit 36 ​​can also maintain a "monitored" bitmap 270, which indicates whether each monitored address has been monitored or has otherwise encountered an event that needs to be reported to the software, as an additional data structure stored in memory and may be stored at an address determined relative to the identifier storage base address 250 specified for a given monitoring instruction. For example, the monitored bitmap 270 may follow continuously from the end of the identifier memory 160.

[0078] Therefore, in this way, the data cache 12 itself can be implemented with the same... Figure 8 Fields similar to those indicated in the document include monitored field 218, which tracks whether a given cache line is being monitored. When a new address is assigned to a monitored group, and then monitored field 218 is set for the relevant cache entry, the cache set / path ID of that cache entry can be used to derive the offset of the base address 250 to be added to the identifier memory, and the memory location with the address corresponding to the sum of the base address and the offset can be updated using a software-provided identifier provided by variant 3 of the monitored exclusive instruction.

[0079] When cache controller 240 detects a snooping from interconnect 10, causing a cache entry marked as monitored to change its consistency state 216 from exclusive to shared or invalid, this is signaled to address monitoring circuit 36. Address monitoring circuit (and interrupt handling circuit 22) increments its count 230 of the number of monitored addresses that have been snooped on, and also updates the relevant snooping indicator in bitmap 270 to indicate the specific monitored address that has been snooped on. Similarly, the relevant offsets used to identify the markers in the snooping bitmap 270 to be updated can be derived from the set and paths of cache entries corresponding to the monitored addresses being snooped on. When the monitoring polling instructions, discussed further below, are executed to poll for information about any addresses that may have encountered an event, the snooping bitmap 270 can be parsed to identify locations within identifier storage structure 260 for which software identifiers should be returned to the software corresponding to the monitored address that encountered the event.

[0080] Figure 9 The method shown refers to implementing a dedicated hardware architecture for address tracking (such as...) Figure 8 The address tracking structure 200 shown does not incur circuit area costs. The size of the structure to be stored in memory is relatively small compared to the total amount of data cached in data cache 12, allowing space in data cache 12 to store identifier storage structure 260, bitmap 270, and also a reasonable number of monitored cache lines themselves, which helps improve performance. For example, assuming a 64kB cache, this could have 1024 monitored cache lines. If it is desired to associate software-provided identifiers with each of these cache lines, this would require at least 10 bits for the identifier to distinguish the 1024 different cache lines; therefore, a 2-byte (16-bit) identifier could be used, for example. Assuming a 16-bit identifier, identifier storage structure 260 could occupy 2kB of memory space, and thus this could easily fit into a 64kB cache. Some additional space in the cache might also be needed for the listen bitmap 270, which could correspond to 128 bytes (1024 × 1 bit per monitored tag). In some instances, the count value 230 can also be pushed to memory and cached, but a significant amount of additional space can still be reserved in the Level 1 data cache for the monitored cache lines. This is due to... Figure 9 The shaded portion 300 indicates that it represents a portion of the cache corresponding to the maximum range of various address monitoring structures, leaving the remaining portion for monitored cache lines and additional data for unmonitored addresses. It should be understood that, although... Figure 9The shaded area is shown as a single contiguous block, but in practice, the address monitoring structure can be cached in multiple non-contiguous cache entries.

[0081] The above-described variant 3 instructions support... Figure 9 The use case shown is particularly useful. In variant 3, the target address is implicitly defined by referencing the address specified by the most recently encountered exclusive state-setting instruction. This frees up space in the instruction code used for register fields, instead providing the base address 250 of the identifier storage structure, making it possible to use... Figure 9 The method shown. However, in other examples, even if the target address is explicitly encoded in the instruction, examples of monitor exclusive instructions encoded with an explicitly indicated target address can also be used if there is sufficient space for an additional register field to identify the identifier structure base address. Figure 9 The method shown provides a data structure in memory for tracking software IDs.

[0082] Furthermore, while in the example above, in the Variant 3 monitor-exclusive instruction, the address in register Xn identifies the base address 250 of the identifier storage structure 260, in other examples, the value in this register can provide additional information that allows the determination of the identifier storage base address. For example, when the monitored bitmap 270, count value 230, and identifier storage structure 260 are located at fixed offsets relative to each other in the address space, the value in the register specified by the monitor-exclusive instruction can point to any of these structures, and the addresses of the other structures can be derived from the address in register Xn and the implicitly defined fixed offset.

[0083] Figure 10 The processing of a monitoring polling command is illustrated. This monitoring polling command can be used by software to request the address monitoring circuit 36 ​​to return information about any monitored addresses for any events detected by it. Figure 10 Two variations of the monitored polling instruction are shown. In the first variation, the instruction specifies a destination register Xd to which monitoring polling information is written in response to the monitoring polling instruction. In the second variation, in addition to the destination register Xd, the monitoring polling instruction also specifies an address register Xn, which provides information for identifying the polling information. Figure 9 The information discussed pertains to the base address of the identifier storage structure 260. This is done when it is desired to store the identifier storage structure in memory rather than as in... Figure 8 If a dedicated hardware architecture is provided as in the example, variant 2 can be supported. Variant 1 can be used with... Figure 8 Used together with the specific implementation shown.

[0084] For both variations, at step S200, the instruction decoder 20 decodes the monitored polling instruction, and in response, at step S202, controls the processing circuitry to enable the software to access monitoring polling information indicating which address in a monitored set of addresses has encountered one or more events indicating a potential update to data. The monitoring polling information can be written to the destination register Xd specified by the monitoring polling instruction.

[0085] Therefore, a monitoring polling instruction can be provided, which the software can execute after receiving an interrupt from address monitoring circuitry 36, which notifies the software of an update to any of the monitored addresses. Since the interrupt itself does not distinguish which specific address has been updated, the monitoring polling instruction can be used to return monitoring polling information to a destination register, which indicates more information about which address was updated.

[0086] In some implementations, it is possible for monitoring polling information to provide information about multiple distinct addresses within a monitored set of addresses, where an event has occurred at more than one address. However, in practice, this information may not fit within a single register, and collecting the corresponding software ID or other information about multiple addresses in a single instruction may not be efficient (due to circuit implementation and timing reasons). Therefore, in one example, a monitoring polling instruction might be designed to return a single data log associated with the single monitored address for which an event occurred, and if it is necessary to read information for multiple addresses from address monitoring, a loop of multiple monitoring polling instructions may be required.

[0087] Figure 11 This illustrates more details of the processing of the monitoring polling instruction in the scenario where, even if multiple monitored addresses have encountered events, the monitoring polling information will only return information about one monitored address. At step S210, the instruction decoder decodes the monitoring polling instruction again. In response, at step S212, the address monitoring circuit 36 ​​checks... Figure 8 The monitored indicator 224 in the address tracking structure 200 or Figure 9The monitored bitmap 270 is used to identify the next address in the monitored group for an event detected during monitoring. The address monitoring circuit reads the corresponding software identifier 222 (from an entry in the address tracking structure 200, provided as a dedicated memory structure in hardware, or from the relevant offset in the identifier storage structure 260 stored in memory or cache 12). In the case of the memory-based identifier storage structure 260, the offset within the identifier storage structure 260 corresponds to the position of the monitored bit read from the monitored bitmap 270. The software ID is included in the monitoring polling information written to the destination register Xd of the monitoring polling instruction. In one example, it is also possible to include other information as shown below. For example, it may be useful to provide an indication of whether any addresses other than the address for which the software identifier is returned have encountered one or more events, allowing the software to decide whether it is necessary to execute any additional instances of the monitoring polling instruction.

[0088] At step S214, the processing circuit also responds to the decoding of the monitoring polling instruction by clearing the indication that one or more events have occurred for the specific monitored address for which its returned identifier was obtained at step S212 (e.g., clearing the monitored field 224 of the relevant entry in the address tracking structure 200 or clearing the corresponding bit in the bitmap 270). Furthermore, if the counter 230 is tracking the number of remaining addresses that have not yet been polled by the monitoring polling instruction, the counter 230 may also be decremented at step S214, such that once the counter returns to 0, the software determines that no remaining addresses need to be polled.

[0089] An example format for the monitoring polling information returned in the destination register Xd can be as follows: | 63:48 monId | 47:32 logLen | 31:16 monLen | 15:0 status | Therefore, the software can read: monId - The identifier associated with the first entry that is marked as being monitored (e.g., 222), or a known default value (e.g., 0xffff) if an error has occurred for some reason. logLen - the number of remaining addresses marked as being monitored, including the address returned by identifier 222 from address tracking structure 200 and identifier storage structure 260.

[0090] monLen - The total number of addresses in a monitored set of addresses.

[0091] Status - Status information indicating whether the monitoring polling operation was successful (e.g., 0 for OK, 1 for Error; it is also possible to use different codes for the status field to indicate multiple error reasons).

[0092] Of course, this is just one example, and other implementations may return different types of monitoring polling information or return it in different formats.

[0093] Figure 12 A specific implementation of a usable simulator is illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as simulators, in part because they provide a software-based implementation of a hardware architecture. Types of simulator computer programs include emulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the simulator implementation can run on a host processor 330 that supports the simulator program 310, which optionally runs a host operating system 320. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide simulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the simulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0094] With respect to embodiments previously described with reference to specific hardware constructions or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. One or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 330), and where appropriate, some simulated embodiments may utilize the host hardware.

[0095] The simulator program 310 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 300 (which may include an application program, an operating system, and a management program), the same as the interface of the hardware architecture modeled by the simulator program 310. Therefore, the program instructions of the target code 300 (including the aforementioned monitor exclusive instructions, monitor polling instructions, exclusive status setting instructions (e.g., load exclusive instructions), and store exclusive instructions) can be executed from within the instruction execution environment using the simulator program 310, enabling the host computer 330, which does not actually possess the hardware features of the aforementioned device 2, to emulate these features.

[0096] The simulator program 310 may have instruction decoding program logic 311, which includes checking the instruction encoding of the program instructions of the target code 300 and mapping each type of instruction to a corresponding set of one or more program instructions in the native instruction set supported by the host hardware 330. These instructions implement functions corresponding to the functions represented by the decoded instructions. The instruction decoding program logic 311 supports the decoding of the various types of instructions mentioned above.

[0097] The simulator program 310 also includes register emulation logic 312, which may include an instruction set that maintains a register emulation data structure in the host storage device (e.g., the virtual address space of the host data processing device 330 or the registers of the host data processing device 330). The register emulation data structure represents the register contents of register 24, which the object code expects to be provided in hardware, but which may not actually be provided in the hardware of the host device 330. Instructions in the object code 300 (which are expected to reference certain registers in the emulation instruction set architecture) may cause the register emulation logic 312 to generate load / store instructions in the host device's native instruction set to request reading / writing of the corresponding emulated register states from the register emulation data structure stored in the host device's memory. Similarly, the emulation program 310 may include memory emulation program logic 313 to perform virtual-to-physical address translation (based on page table data) between the virtual address space used by the target code 300 and the simulated physical address space, which, from the perspective of the target code 300, is intended to refer to the actual physical memory storage device, but is actually mapped by the memory emulation program logic 313 to a region of virtual addresses within the virtual address space used by the actual host data processing device 330 (which itself may then undergo further address translation in the actual physical address space used to refer to the host memory).

[0098] Furthermore, the simulation code includes exclusive state clearing program logic 314 and monitoring program logic 315, both of which include a set of software instructions that control the host hardware 330 to execute functions equivalent to the exclusive state tracking circuit 30 and the address monitoring circuit 36, respectively.

[0099] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0100] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. An apparatus for data processing, the apparatus comprising: An instruction decoder, which is used to decode instructions; A processing circuit, the processing circuit being configured to perform data processing in response to an instruction decoded by the instruction decoder; and A monitoring circuit is configured to monitor one or more events indicating a potential update to data associated with any one of the monitored set of addresses, and to enable software executing on the processing circuit to access a monitoring report indication indicating whether any one of the one or more events has occurred for at least one of the monitored set of addresses; wherein: In response to the instruction decoder decoding an exclusive state setting instruction for a specified given address, the processing circuit is configured to set an exclusive state associated with the given address. The processing circuitry is configured to clear the exclusive state associated with the given address in response to detecting an event indicating a conflicting memory access to the given address; and In response to the instruction decoder decoding the monitoring exclusive instruction, the processing circuit is configured to: Determine whether the exclusive state is associated with the target address; and When the exclusive state is determined to be associated with the target address, the target address is assigned as one of the monitored addresses in the monitored set of addresses for which the monitoring circuit monitors the one or more events. In response to the instruction decoder decoding the monitoring exclusive instruction, the processing circuit is configured to return a monitoring allocation status indication accessible to the software, the monitoring allocation status indication indicating whether the target address has been successfully allocated as one of the monitored set of addresses in response to the monitoring exclusive instruction.

2. The apparatus according to claim 1, wherein, When it is unsuccessful to assign the target address to one of the monitored addresses, the monitoring assignment status indicates the reason for the assignment failure of the target address.

3. The apparatus of claim 2, wherein the monitoring allocation status indication is distinguished between at least two of the following reasons: The exclusive status is no longer set for the target address; The exclusive state is set for addresses other than the target address; and The monitoring circuit is unavailable or has not been configured to accept address assignments to the monitored set of addresses.

4. The apparatus according to any one of claims 1 to 3, wherein the monitoring exclusive instruction specifies the target address.

5. The apparatus according to any one of claims 1 to 3, wherein the target address includes the address specified as the given address by the most recent exclusive state setting instruction prior to the monitoring exclusive instruction.

6. The apparatus according to any one of claims 1 to 3, wherein: In response to the instruction decoder decoding the monitoring exclusive instruction, when the exclusive state is determined to be associated with the target address, the processing circuit is configured to allocate an identifier value designated as an operand of the monitoring exclusive instruction to an entry in the identifier storage structure corresponding to the target address.

7. The apparatus of claim 6, wherein the identifier storage structure includes a dedicated address monitoring and tracking structure, the dedicated address monitoring and tracking structure including a plurality of entries, each entry being used to track information associated with a corresponding address in the monitored set of addresses.

8. The apparatus of claim 6, wherein the identifier storage structure comprises a data structure stored in memory.

9. The apparatus of claim 8, wherein the monitoring exclusive instruction specifies information for identifying the base address of the identifier storage structure.

10. The apparatus of claim 6, wherein the monitoring circuitry is configured to enable software to access an indication of an identifier stored in an entry of the identifier storage structure, the identifier corresponding to an address for which the monitoring circuitry has detected any one of the one or more events having occurred from the monitored set of addresses.

11. The apparatus according to any one of claims 1 to 3, wherein in response to the instruction decoder decoding a monitoring polling instruction, at least one of the processing circuitry and the monitoring circuitry is configured to enable software to access monitoring polling information indicating which address in the monitored set of addresses has encountered the one or more events.

12. The apparatus of claim 11, wherein, in response to the instruction decoder decoding a monitoring exclusive instruction, when the exclusive state is determined to be associated with the target address, the processing circuitry is configured to allocate an identifier value designated as an operand of the monitoring exclusive instruction to an entry in the identifier storage structure corresponding to the target address; and The monitoring polling information includes the identifier value associated with one or more events from the monitored set of addresses for at least one address where the events occurred.

13. The apparatus of claim 12, wherein the identifier storage structure comprises a data structure stored in memory, and the monitoring polling instruction specifies the base address of the identifier storage structure.

14. The apparatus of claim 11, wherein the monitoring polling information includes a count value indicating the number of times the one or more events in the monitored set of addresses occur at the addresses for which they occur.

15. The apparatus of claim 11, wherein the processing circuitry is configured to make the monitoring polling information accessible to software by writing the monitoring polling information to a destination register identified by the monitoring polling instruction.

16. The apparatus of any one of claims 1 to 3, wherein the exclusive state setting instruction includes a load exclusive instruction, and in response to the instruction decoder decoding the load exclusive instruction, the processing circuitry is configured to load data associated with the given address into at least one destination register specified by the load exclusive instruction, and set the exclusive state associated with the given address.

17. The apparatus according to any one of claims 1 to 3, wherein in response to the instruction decoder decoding a memory exclusive instruction specifying a memory destination address and at least one source register, the processing circuitry is configured to: Determine whether the exclusive state is associated with the target storage address; and When the exclusive state is determined to be associated with the memory target address, data from the at least one source register is stored in the memory location associated with the memory target address.

18. A method for data processing, the method comprising: In response to decoding an instruction to set the exclusive state of a specified given address, the exclusive state associated with the given address is set. In response to detecting an event indicating a conflicting memory access to the given address, the exclusive state associated with the given address is cleared; In response to decoding the monitoring exclusive command: Determine whether the exclusive state is associated with the target address; as well as When the exclusive status is determined to be associated with the target address, the target address is assigned as one of the monitored addresses; and Returns a monitoring allocation status indicator that the software can access, indicating whether the target address has been successfully allocated as one of the monitored set of addresses in response to the monitoring exclusive instruction; The monitoring indicates one or more events that indicate a potential update to data associated with any one of the monitored addresses; as well as The software is enabled to access monitoring report indicators that indicate whether any one of the one or more events has occurred for at least one of the monitored set of addresses.

19. A computer-readable storage medium storing a computer program that, when executed on a host data processing device, controls the host data processing device: The instructions of the target code are decoded to control the host data processing device to perform data processing corresponding to the instructions of the target code; and The monitoring indicates one or more events of potential updates to data associated with any one of the monitored addresses in the simulated address space, and enables the target code to access monitoring report indicators indicating whether any one of the one or more events has occurred for at least one of the monitored addresses. in: In response to an exclusive state setting instruction from the object code specifying a given address in the simulated address space, the host data processing device is controlled to set an exclusive state associated with the given address, and in response to detecting an event indicating a conflicting memory access to the given address in the simulated address space, the host data processing device is controlled to clear the exclusive state associated with the given address; and In response to the monitoring exclusive command of the target code, the host data processing device is controlled to: Determine whether the exclusive state is associated with a target address in the simulated address space; and When the exclusive status is determined to be associated with the target address, the target address is assigned as one of the addresses in the monitored set of addresses to be monitored for the one or more events; and The software returns a monitoring allocation status indicator that indicates whether the target address has been successfully allocated as one of the monitored addresses in response to the monitoring exclusive instruction.

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