Display device

Abstract

Disclosed is a display device having improved luminous efficiency. The display device includes a plurality of pixels; a light emitting device disposed in each pixel, the light emitting device having a first surface and a second surface opposite to each other; a first electrode and a second electrode electrically connected to the first surface and the second surface of the light emitting device, respectively; and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern includes a first region and a second region. The first region surrounds the second region, and the second region has a contact hole exposing at least a portion of the second surface. The second electrode is coupled to the second surface through the contact hole, and the first region and the second region have different crystal phases from each other.

Description

Technical Field

[0001] This disclosure relates to a display device with improved luminous efficiency and a method for manufacturing the same. Background Technology

[0002] A display device includes a light-emitting device. The light-emitting device is electrically connected to an electrode and emits light in response to a voltage applied to the electrode. The light-emitting device may be formed directly on the electrode. Alternatively, the light-emitting device may be formed and then placed on the electrode.

[0003] A light-emitting device can be a light-emitting diode (LED). An LED is a semiconductor device that converts the energy generated by the recombination of holes and electrons when a forward voltage is applied to a pn-junction diode into light energy. LEDs can be classified as inorganic LEDs or organic LEDs. LEDs are used not only in small electronic products such as mobile phones, but also in large electronic products such as televisions. Summary of the Invention

[0004] Technical issues

[0005] The present invention provides a display device with improved luminous efficiency and a method for manufacturing the same.

[0006] Technical solution

[0007] According to embodiments of the present invention, a display device may include a plurality of pixels, a light-emitting device disposed in each of the plurality of pixels, a first electrode electrically connected to a first surface of the light-emitting device, a second electrode electrically connected to a second surface of the light-emitting device, and a metal oxide pattern between the second surface of the light-emitting device and the second electrode. The light-emitting device has a first surface and a second surface opposite to each other. The metal oxide pattern may include a first region and a second region, the first region surrounding the second region, and the second region may have contact holes exposing at least a portion of the second surface. The second electrode may be coupled to the second surface through the contact holes, and the first region and the second region may have different crystal phases from each other.

[0008] According to embodiments of the present invention, a display device may include a plurality of pixels and a light-emitting device disposed in each of the plurality of pixels. The light-emitting device may include a first surface and a second surface opposite to each other, and the light-emitting device may include a p-type first semiconductor layer, an active layer, and an n-type second semiconductor layer sequentially stacked. The first semiconductor layer may be adjacent to the first surface, and the second semiconductor layer may be adjacent to the second surface. The first surface may include a first region and a second region as its edge region and center region. The first surface may have a first width, and the second region may have a second width. The ratio of the second width to the first width may be in the range of 0.7 to 0.9, and the linear dislocation density in the first region may be higher than the linear dislocation density in the second region.

[0009] According to embodiments of the present invention, a display device may include a plurality of pixels on a substrate, a first light-emitting device and a second light-emitting device disposed on a first pixel (which is one of the pixels), a first electrode between the first and second light-emitting devices and the substrate, a second electrode on the first and second light-emitting devices, and a first metal oxide pattern and a second metal oxide pattern respectively disposed on the second surfaces of the first and second light-emitting devices. Each of the first and second light-emitting devices has a first surface and a second surface opposite to each other. The first surface and the second surface of the first light-emitting device may face the first electrode and the second electrode respectively, and the first surface and the second surface of the second light-emitting device may face the second electrode and the first electrode respectively. The first metal oxide pattern may be located between the second electrode and the second surface of the first light-emitting device, and the second metal oxide pattern may be located between the first electrode and the second surface of the second light-emitting device.

[0010] Beneficial effects

[0011] According to an embodiment of the present invention, a display device may be configured to include a light-emitting device with improved luminous efficiency. In a method of manufacturing a display device according to an embodiment of the present invention, a light-emitting device of a desired shape can be easily manufactured by adjusting the shape of a seed pattern. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0013] Figure 2 This is an equivalent circuit diagram of a pixel according to an embodiment of the concept of the present invention.

[0014] Figure 3 This is a plan view of the display panel of a display device according to an embodiment of the present invention.

[0015] Figure 4 It is along Figure 3 A sectional view taken by line A-A'.

[0016] Figure 5A is an illustration. Figure 3 Figure 5B is a perspective view of the light-emitting device illustrated in Figure 5A.

[0017] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 This is a plan view illustrating a method for manufacturing a light-emitting device according to an embodiment of the present invention.

[0018] Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 and Figure 19 They are along Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 A sectional view taken by line A-A'.

[0019] Figure 20 , Figure 21 and Figure 22 This is a cross-sectional view illustrating sequentially the steps of growing a light-emitting device (i.e., an epitaxial layer) on a sacrificial pattern via metal-organic chemical vapor deposition according to an embodiment of the present invention.

[0020] Figure 23 , Figure 24 and Figure 25 This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0021] Figure 26 This is a plan view of the display panel of a display device according to an embodiment of the present invention.

[0022] Figure 27 It is along Figure 26 A sectional view taken by line A-A'.

[0023] Figure 28 yes Figure 26 A magnified planar view of the first pixel. Detailed Implementation

[0024] To fully understand the configuration and effects of the inventive concept, some embodiments of the inventive concept will be described with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and can be implemented in various forms. Rather, exemplary embodiments are provided merely to disclose the inventive concept and to enable those skilled in the art to fully understand its scope.

[0025] In this description, it should be understood that when an element is referred to as being on another element, the element may be directly on the other element, or an intermediate element may exist therein. In the accompanying drawings, the thickness of some components is exaggerated for the purpose of effectively explaining the technical content. Throughout the specification, the same reference numerals refer to the same elements.

[0026] Some exemplary embodiments detailed herein will be discussed with reference to sectional views and / or plan views that serve as ideal exemplary views of the inventive concept. In the drawings, the thickness of layers and regions is exaggerated for the purpose of effectively explaining the technical content. Accordingly, the regions illustrated exemplary in the drawings have general properties, and the shapes of the regions illustrated exemplary in the drawings are used to exemplarily disclose specific shapes, but are not limited to the scope of the inventive concept. It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. The embodiments explained and illustrated herein include supplementary embodiments thereof.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular form is also intended to include the plural form. The terms “comprising / including” and / or “including…included / containing…included” as used in the specification do not exclude the presence or addition of one or more other components.

[0028] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0029] Reference Figure 1 The display device DD may include a display panel DP, a signal control unit TC or timing controller, a data driver DDV, and a scan driver GDV. Each of the signal control unit TC, the data driver DDV, and the scan driver GDV may include circuitry.

[0030] The display panel DP may include light-emitting devices. For example, the display panel DP may include micro LEDs. The display panel DP may include multiple data lines DL1 to DLm, multiple scan lines SL1 to SLn, and multiple pixels PX.

[0031] Data lines DL1 to DLm can extend in a first direction D1. Data lines DL1 to DLm can be arranged in a second direction D2 that intersects the first direction D1. Scan lines SL1 to SLn can extend in the second direction D2. Scan lines SL1 to SLn can be arranged in the first direction D1.

[0032] Each pixel PX may include a light-emitting device and pixel circuitry electrically connected to the light-emitting device. The pixel circuitry may include multiple transistors. A first power supply voltage ELVDD and a second power supply voltage ELVSS may be set in each pixel PX.

[0033] Pixels (PX) can be arranged on the surface of the display panel (DP) in a regular manner or according to a specific arrangement rule. Each pixel (PX) can be configured to display one of the primary colors or one of the mixed colors. Primary colors can include red, green, and blue. Mixed colors can include yellow, cyan, magenta, and white. However, the colors that can be displayed by pixels (PX) are not limited to the colors mentioned above.

[0034] The signal control unit TC can receive image data RGB provided from an external source. The signal control unit TC can be configured to convert the image data RGB into image data R'G'B' suitable for the operation of the display panel DP, and output the converted image data R'G'B' to the data driver DDV.

[0035] The signal control unit TC can receive control signals CS provided from an external source. The control signals CS may include a vertical synchronization signal, a horizontal synchronization signal, a master clock signal, and a data enable signal. The signal control unit TC can provide a first control signal CONT1 to the data driver DDV and a second control signal CONT2 to the scan driver GDV. The first control signal CONT1 can be used to control the data driver DDV, and the second control signal CONT2 can be used to control the scan driver GDV.

[0036] The data driver DDV can drive data lines DL1 to DLm in response to a first control signal CONT1 provided from the signal control unit TC. The data driver DDV can be provided as a separate integrated circuit, which can then be electrically connected to a portion of the display panel DP, or it can be directly mounted on the display panel DP. In embodiments, the data driver DDV can be provided as a single chip or multiple chips.

[0037] The scan driver GDV can drive scan lines SL1 to SLn in response to a second control signal CONT2 provided from the signal control unit TC. As an example, the scan driver GDV can be integrated on a region of the display panel DP. In this case, the scan driver GDV may include multiple thin-film transistors formed by the same process used for the driving circuitry of pixels PX (e.g., by low-temperature polycrystalline silicon (LTPS) processing or low-temperature polycrystalline oxide (LTPO) processing). Alternatively, the scan driver GDV can be provided as a separate integrated circuit chip, which can then be electrically connected to a portion of the display panel DP.

[0038] When a gate-on voltage is applied to one of the scan lines SL1 to SLn, the switching transistor in the connected row of pixels can be turned on. Here, the data driver DDV can provide a data drive signal to the data lines DL1 to DLm. The data drive signal provided to the data lines DL1 to DLm can be applied to the corresponding pixel through the turned-on switching transistor. The data drive signal can be an analog voltage corresponding to the grayscale level of the image data.

[0039] Figure 2 This is an equivalent circuit diagram of a pixel according to an embodiment of the concept of the present invention.

[0040] Reference Figure 2 Pixel PX can be connected to multiple signal lines. In this embodiment, the signal lines may include scan line SL, data line DL, first power line PL1, and second power line PL2.

[0041] A pixel PX may include a light-emitting device ED and a pixel circuit PXC. The pixel circuit PXC may include a first thin-film transistor TR1, a capacitor CAP, and a second thin-film transistor TR2.

[0042] The first thin-film transistor TR1 can be a switching transistor used to control the on / off operation of pixel PX. The first thin-film transistor TR1 can transmit or block data signals transmitted via data line DL in response to a gate signal transmitted via scan line GL.

[0043] A capacitor CAP can be disposed between and connected to the first thin-film transistor TR1 and the first power supply line PL1. The amount of charge stored in the capacitor CAP can vary depending on the voltage difference between the data signal transmitted from the first thin-film transistor TR1 and the first power supply voltage ELVDD applied to the first power supply line PL1.

[0044] The second thin-film transistor TR2 can be connected to the first thin-film transistor TR1, the capacitor CAP, and the light-emitting device ED. The second thin-film transistor TR2 can control the drive current flowing through the light-emitting device ED based on the amount of charge stored in the capacitor CAP. For example, the on-time of the second thin-film transistor TR2 can be determined based on the amount of charge stored in the capacitor CAP.

[0045] The first thin-film transistor TR1 and the second thin-film transistor TR2 can be either n-type or p-type thin-film transistors. Alternatively, at least one of the first thin-film transistor TR1 and the second thin-film transistor TR2 can be an n-type thin-film transistor, while the other can be a p-type thin-film transistor.

[0046] The light-emitting device ED can be disposed between and connected to the second thin-film transistor TR2 and the second power supply line PL2. The light-emitting device ED can emit light when there is a voltage difference between the signal transmitted through the second thin-film transistor TR2 and the second power supply voltage ELVSS received through the second power supply line PL2.

[0047] The light-emitting device (ED) can be an ultra-miniature LED device. An ultra-miniature LED device can be an LED device with a size ranging from a few nanometers to hundreds of micrometers. However, the size of an ultra-miniature LED device is merely an illustrative example and is not limited to the aforementioned size range.

[0048] exist Figure 2 The diagram illustrates an example where only one light-emitting device (ED) is positioned between the second thin-film transistor TR2 and the second power line PL2. However, in embodiments, multiple light-emitting devices (EDs) can be used. These multiple EDs can be connected in parallel with each other.

[0049] Figure 3 This is a plan view of the display panel of a display device according to an embodiment of the present invention. Figure 4 It is along Figure 3 The cross-sectional view taken by line A-A'. Figure 5A is the illustrated view. Figure 3 Figure 5B is a perspective view of the light-emitting device illustrated in Figure 5A.

[0050] Reference Figure 3 , Figure 4 As shown in Figures 5A and 5B, the first pixel PX1 to the fourth pixel PX4 can be disposed on the substrate 100. The substrate 100 may include a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stack comprising multiple insulating layers.

[0051] The first pixels PX1 to the fourth pixels PX4 can be arranged in two dimensions. The first pixel PX1 and the second pixel PX2 can be adjacent to each other in the second direction D2, and the third pixel PX3 and the fourth pixel PX4 can be adjacent to each other in the second direction D2. The first pixel PX1 and the third pixel PX3 can be adjacent to each other in the first direction D1, and the second pixel PX2 and the fourth pixel PX4 can be adjacent to each other in the first direction D1. Each of the first pixels PX1 to the fourth pixels PX4 may include a first thin-film transistor TR1, a second thin-film transistor TR2, and a light-emitting device ED. Hereinafter, one of the first pixels PX1 to the fourth pixels PX4 (e.g., the first pixel PX1) will be described exemplarily.

[0052] A first thin-film transistor TR1 and a second thin-film transistor TR2 can be placed on a substrate 100. The first thin-film transistor TR1 may include a first control electrode CE1, a first input electrode IE1, a first output electrode OE1, and a first semiconductor pattern SP1. The second thin-film transistor TR2 may include a second control electrode CE2, a second input electrode IE2, a second output electrode OE2, and a second semiconductor pattern SP2.

[0053] The first control electrode CE1 and the second control electrode CE2 can be disposed on the base layer 100. The first control electrode CE1 and the second control electrode CE2 can be formed of or include a conductive material. The first insulating layer 110 can be disposed on the base layer 100 to cover the first control electrode CE1 and the second control electrode CE2. In other words, the first control electrode CE1 and the second control electrode CE2 can be located between the first insulating layer 110 and the base layer 100.

[0054] The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be disposed on the first insulating layer 110. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of or include a semiconductor material. For example, the semiconductor material may include at least one of amorphous silicon, polycrystalline silicon, monocrystalline silicon, oxide semiconductor material, or compound semiconductor material. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include a channel region serving as a conduction path for electrons or holes and a first impurity region and a second impurity region spaced apart from each other, wherein the channel region is located between the first impurity region and the second impurity region.

[0055] A first input electrode IE1 and a first output electrode OE1 can be disposed on a first semiconductor pattern SP1. The first input electrode IE1 and the first output electrode OE1 can be connected to a first impurity region and a second impurity region of the first semiconductor pattern SP1, respectively. A second input electrode IE2 and a second output electrode OE2 can be disposed on a second semiconductor pattern SP2. The second input electrode IE2 and the second output electrode OE2 can be connected to a first impurity region and a second impurity region of the second semiconductor pattern SP2, respectively.

[0056] The second insulating layer 120 may be disposed on the first insulating layer 110 to cover the first semiconductor pattern SP1 and the second semiconductor pattern SP2, the first input electrode IE1 and the second input electrode IE2, and the first output electrode OE1 and the second output electrode OE2. In other words, the first semiconductor pattern SP1 and the second semiconductor pattern SP2, the first input electrode IE1 and the second input electrode IE2, and the first output electrode OE1 and the second output electrode OE2 may be located between the first insulating layer 110 and the second insulating layer 120.

[0057] A third insulating layer 130 may be disposed on the second insulating layer 120. The third insulating layer 130 may have a substantially flat top surface. A connection electrode CCE may be placed on the third insulating layer 130 to electrically connect the first output electrode OE1 to the second control electrode CE2. The connection electrode CCE may include a first contact configured to penetrate the second insulating layer 120 and the third insulating layer 130 and be coupled to the first output electrode OE1. Furthermore, the connection electrode CCE may include a second contact configured to penetrate the first insulating layer to the third insulating layers 110, 120, and 130 and be coupled to the second control electrode CE2.

[0058] A fourth insulating layer 140 may be disposed on the third insulating layer 130 to cover the connection electrode CCE. A first electrode E1 may be disposed on the fourth insulating layer 140. The first electrode E1 may include a third contact configured to penetrate the second to fourth insulating layers 120, 130 and 140 and be coupled to the second output electrode OE2.

[0059] A fifth insulating layer 150 may be disposed on the fourth insulating layer 140 to cover the first electrode E1. A light-emitting device ED may be disposed on the first electrode E1. The light-emitting device ED may be disposed within the fifth insulating layer 150. The light-emitting device ED may have a first surface SU1 and a second surface SU2 opposite to each other in a third direction D3. As an example, the first surface SU1 may be the bottom surface of the light-emitting device ED, and the second surface SU2 may be the top surface of the light-emitting device ED. The area of ​​the first surface SU1 may be smaller than the area of ​​the second surface SU2. In an embodiment, the p-type semiconductor layer of the light-emitting device ED may be adjacent to the first surface SU1, and the n-type semiconductor layer of the light-emitting device ED may be adjacent to the second surface SU2.

[0060] The connection pattern CP can be located between the light-emitting device ED and the first electrode E1. The connection pattern CP can be disposed on the first surface SU1 of the light-emitting device ED. The connection pattern CP can be formed of or include at least one metallic material with a low melting temperature (e.g., Ni, Au, an alloy of Ni and Au, or a multilayer Ni / Au layer).

[0061] The light-emitting device ED and the first electrode E1 can be electrically connected to each other via a connection pattern CP. For example, the light-emitting device ED may include a first semiconductor layer SL1, as described below, and the first electrode E1 may be connected to the first semiconductor layer SL1 of the light-emitting device ED. The first electrode E1 may be electrically connected to the previously referenced... Figure 2 The first power line described is PL1. In other words, Figure 2 The first power supply voltage ELVDD can be applied to the first electrode E1.

[0062] A light-emitting device (ED) may include a first semiconductor layer SL1, an active layer ACT, a second semiconductor layer SL2, and a third semiconductor layer SL3, stacked sequentially. The active layer ACT and the first to third semiconductor layers SL1, SL2, and SL3 may be formed of or include at least one III-V compound semiconductor material. The active layer ACT and the first to third semiconductor layers SL1, SL2, and SL3 may be formed of or include at least one GaN-based semiconductor material. In embodiments, the active layer ACT and the first to third semiconductor layers SL1, SL2, and SL3 may be formed of at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, or combinations thereof, or may include at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, or combinations thereof.

[0063] The first to third semiconductor layers SL1, SL2, and SL3 can be formed of or comprise the same GaN semiconductor material. As an example, the first to third semiconductor layers SL1, SL2, and SL3 can be formed of or comprise GaN. The first semiconductor layer SL1 can be a p-type semiconductor layer. The first semiconductor layer SL1 can contain impurities such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba). The second semiconductor layer SL2 can be an n-type semiconductor layer. The second semiconductor layer SL2 can contain impurities such as silicon (Si), germanium (Ge), tin (Sn), selenium (Se), or tellurium (Te). The third semiconductor layer SL3 can be an undoped semiconductor layer.

[0064] The active layer ACT can be located between a first semiconductor layer SL1 and a second semiconductor layer SL2. The active layer ACT can be a region where holes injected through the first semiconductor layer SL1 recombine with electrons injected through the second semiconductor layer SL2. As a result of electron-hole recombination, light can be emitted from the active layer ACT. The active layer ACT can have at least one of a single quantum well structure, a multiple quantum well structure, a quantum wire structure, or a quantum dot structure. As an example, the active layer ACT can have a multiple quantum well structure comprising InGaN and GaN.

[0065] The first semiconductor layer SL1, the active layer ACT, the second semiconductor layer SL2, and the third semiconductor layer SL3 can be sequentially stacked on the first surface SU1 of the light-emitting device ED. Furthermore, the first semiconductor layer SL1, the active layer ACT, the second semiconductor layer SL2, and the third semiconductor layer SL3 can be sequentially stacked on the sidewalls SW of the light-emitting device ED. In other words, each of the first semiconductor layer SL1, the active layer ACT, and the second semiconductor layer SL2 can have a U-shaped cross-section. Each of the first semiconductor layer SL1, the active layer ACT, and the second semiconductor layer SL2 can have a shape that surrounds the bottom surface and side surfaces of the third semiconductor layer SL3.

[0066] The active layer ACT adjacent to the sidewall SW of the light-emitting device (ED) can be located between the first semiconductor layer SL1 and the second semiconductor layer SL2. In other words, the active layer ACT adjacent to the sidewall SW of the ED can be shielded by the first semiconductor layer SL1 and is not exposed to the outside. The first semiconductor layer SL1 adjacent to the sidewall SW of the ED can passivate the active layer ACT. Since the active layer ACT is protected by the first semiconductor layer SL1, the electrical characteristics of the active layer ACT can be improved, thereby improving the luminous efficiency of the light-emitting device (ED).

[0067] The thickness of the first semiconductor layer SL1 on the third-direction D3 can be greater than the thickness of the first semiconductor layer SL1 on the sidewall SW of the light-emitting device ED. Similarly, the thickness of the second semiconductor layer SL2 on the third-direction D3 can be greater than the thickness of the second semiconductor layer SL2 on the sidewall SW of the light-emitting device ED. This is because the GaN growth rate is highest on the third-direction D3 during the growth of the light-emitting device ED, which will be described below.

[0068] When viewed in a plan view, the light-emitting device (ED) can have a hexagonal shape. The ED can also have a truncated-inverted-pyramid shape. Furthermore, the ED can be a truncated polygonal prism shape (see, for example, Figures 5A and 5B).

[0069] The light-emitting device ED may also have sidewalls SW extending obliquely from the first surface SU1 to the second surface SU2. The sidewalls SW may include first crystal planes FA1 to sixth crystal planes FA6. The first crystal planes FA1 to sixth crystal planes FA6 may be arranged in a clockwise order along the six edges of the second surface SU2 (e.g., see Figure 5A). The first crystal planes FA1 to sixth crystal planes FA6 may be arranged in a counterclockwise order along the six edges of the first surface SU1 (e.g., see Figure 5B).

[0070] The sidewalls SW of the light-emitting device ED may also include vertices VER. Vertex VER may be defined by two adjacent crystal planes that intersect each other, from the first crystal plane FA1 to the sixth crystal plane FA6. Vertex VER may extend from the first surface SU1 of the light-emitting device ED to the second surface SU2 (see, for example, Figure 5A).

[0071] The light-emitting device (ED) can have a wurtzite crystal structure. Each of the first surface SU1 and the second surface SU2 of the ED can be a c-plane serving as a polar plane. Each of the first surface SU1 and the second surface SU2 can be a {0001} crystal plane. The polar plane or the c-plane can be a surface composed of only one type of atom. In an embodiment, the polar plane or the c-plane can be a surface composed only of gallium (Ga) atoms or only of nitrogen (N) atoms.

[0072] Each of the first crystal planes FA1 to the sixth crystal plane FA6 may be tilted at a certain angle relative to the first surface SU1 and the second surface SU2. In an embodiment, the first crystal planes FA1 to the sixth crystal plane FA6 may have the same angle. In other words, the first crystal planes FA1 to the sixth crystal plane FA6 may be tilted at the same angle relative to the first surface SU1. For example, refer to... Figure 4The first crystal plane FA1 can be tilted relative to the first surface SU1 at a first angle θ1, and the fourth crystal plane FA4 can be tilted relative to the first surface SU1 at a second angle θ2. Here, the first angle θ1 and the second angle θ2 can be substantially equal to each other. Due to the tilted profiles of the first crystal plane FA1 to the sixth crystal plane FA6, the width of the light-emitting device ED can increase with the distance from the substrate 100.

[0073] Alternatively, at least one of the first crystal planes FA1 to the sixth crystal plane FA6 may be tilted at an angle relative to the other crystal planes. For example, the first angle θ1 and the second angle θ2, as described above, may be different from each other.

[0074] Each of the first to sixth crystal planes FA1 to FA6 of the light-emitting device (ED) can be a semi-polar plane. For example, each of the first to sixth crystal planes FA1 to FA6 can be a {nn 0k} crystal plane. Here, each of the indices n and k is an integer of 1 or greater. In one embodiment, each of the first to sixth crystal planes FA1 to FA6 can be a {1 -1 0 1} crystal plane. In another embodiment, each of the first to sixth crystal planes FA1 to FA6 can be a {n 0-nk} crystal plane or a {nn-2n k} crystal plane. Here, each of the indices n and k is an integer of 1 or greater.

[0075] If the sidewall SW of the light-emitting device ED is perpendicular to the first surface SU1 (e.g., if angles θ1 and θ2 are approximately 90°), light generated in the active layer ACT may leak through the sidewall SW, and in this case, the light extraction efficiency may be reduced. However, according to embodiments conceived in the present invention, since the light-emitting device ED has sidewall SW tilted at a certain angle, light leakage through the sidewall SW can be effectively prevented. Accordingly, the light-emitting device ED can have a very high light extraction efficiency.

[0076] Referring back to Figure 5B, the first surface SU1 of the light-emitting device ED may include an edge region (hereinafter referred to as the third region RG3) and a central region (hereinafter referred to as the fourth region RG4). The third region RG3 of the first surface SU1 may be adjacent to the first crystal plane FA1 to the sixth crystal plane FA6. The fourth region RG4 of the first surface SU1 may be surrounded by the third region RG3. In an embodiment, the ratio of the area of ​​the fourth region RG4 to the total area of ​​the first surface SU1 may be in the range of 0.5 to 0.8.

[0077] The first surface SU1 may have a third width W3 in the first direction D1. The fourth region RG4 may have a fourth width W4 in the first direction D1. The ratio of the fourth width W4 to the third width W3 (i.e., W4 / W3) may be in the range of 0.7 to 0.9. The fourth region RG4 may perpendicularly overlap with the second region RG2 of the metal oxide pattern MOP, as will be described below. Apart from the fourth region RG4, the remaining regions of the first surface SU1 may be the third region RG3.

[0078] Linear dislocations (TDLs) in a light-emitting device (ED) can extend to appear on the first surface SU1 of the ED. TDLs can be crystal defects in the ED, and when the density of TDLs in the ED is high, the luminous efficiency of the ED may decrease.

[0079] According to an embodiment of the present invention, the density of linear dislocations TDL in the fourth region RG4 of the first surface SU1 can be lower than the density of linear dislocations TDL in the third region RG3 of the first surface SU1. That is, according to an embodiment of the present invention, the density of linear dislocations TDL in the central region of the light-emitting device ED can be relatively low.

[0080] According to embodiments of the present invention, the density of linear dislocations (TDLs), given as a count of the number of linear dislocations (TDLs) per unit area on the first surface SU1, can have a relatively low value. For example, in a light-emitting device (ED), the linear dislocation density can be 3 × 10⁻⁶. 6 / cm 2 Up to 3×10 8 / cm 2 Within the range.

[0081] Return to reference Figure 3 , Figure 4 As shown in Figures 5A and 5B, the reflective pattern RP can be positioned between the light-emitting device ED and the fifth insulating layer 150. The reflective pattern RP can directly cover the sidewall SW of the light-emitting device ED. The reflective pattern RP can prevent light generated in the active layer ACT from leaking through the sidewall SW of the light-emitting device ED. In other words, the reflective pattern RP can be configured to reflect light generated in the active layer ACT and guide the light to the second surface SU2 of the light-emitting device ED, so that light can be emitted through the second surface SU2 of the light-emitting device ED.

[0082] A metal oxide pattern (MOP) can be disposed on the second surface SU2 of the light-emitting device (ED). The metal oxide pattern (MOP) can directly cover the second surface SU2 of the ED. In one embodiment, the metal oxide pattern (MOP) can be configured to completely cover the second surface SU2. In another embodiment, the metal oxide pattern (MOP) can be configured to cover a portion of the second surface SU2 and expose the remaining portion of the second surface SU2. The metal oxide pattern (MOP) can be formed of or comprise at least one insulating material (such as a metal oxide), and in an embodiment, the metal oxide pattern (MOP) can be formed of or comprise aluminum oxide (i.e., aluminum oxide). The metal oxide pattern (MOP) can be used as a passivation layer covering the second surface SU2.

[0083] The metal oxide patterned MOP may include an edge region (hereinafter referred to as the first region RG1) and a central region (hereinafter referred to as the second region RG2). The first region RG1 of the metal oxide patterned MOP may be adjacent to the first crystal plane FA1 to the sixth crystal plane FA6. A contact hole CTH may be defined at the center of the second region RG2 of the metal oxide patterned MOP. The contact hole CTH may be configured to penetrate the second region RG2 of the metal oxide patterned MOP and expose at least a portion of the second surface SU2 of the light-emitting device ED. The first region RG1 may surround the second region RG2. In embodiments, the ratio of the area of ​​the second region RG2 to the total area of ​​the metal oxide patterned MOP may be in the range of 0.2 to 0.7.

[0084] The metal oxide pattern MOP can have a first width W1 in the first direction D1. The second region RG2 can have a second width W2 in the first direction D1. The ratio of the second width W2 to the first width W1 (i.e., W2 / W1) can be in the range of 0.4 to 0.8. Except for the second region RG2, the remaining regions of the metal oxide pattern MOP can be the first region RG1.

[0085] The first region RG1 and the second region RG2 of the metal oxide patterned MOP can have different crystal phases from each other. For example, the first region RG1 of the metal oxide patterned MOP can have a single-crystal α phase. The second region RG2 of the metal oxide patterned MOP can have a polycrystalline γ phase. Although the first region RG1 and the second region RG2 of the metal oxide patterned MOP have different crystal phases, they can be formed from or comprise the same material (e.g., Al2O3) and can have the same thickness.

[0086] The first region RG1 of the metal oxide patterned MOP can have a higher density than the second region RG2 of the metal oxide patterned MOP. For example, the density of the first region RG1 of the metal oxide patterned MOP can be 3.97 g / cm³. 3 Furthermore, the density of the second region RG2 of the metal oxide pattern MOP can be 3.65 g / cm³. 3 .

[0087] The first region RG1 of the metal oxide patterned MOP can have a cubic crystal structure, while the second region RG2 can have a rhombic crystal structure. Accordingly, there may be differences in the diffraction patterns between the first region RG1 and the second region RG2 of the metal oxide patterned MOP.

[0088] The crystallization temperature of the first region RG1 in a metal oxide pattern (MOP) can differ from the crystallization temperature of the second region RG2. The crystallization temperature of the first region RG1 can be higher than that of the second region RG2. For example, the crystallization temperature of the first region RG1 can be approximately 1200°C, and the crystallization temperature of the second region RG2 can be approximately 500°C.

[0089] The second electrode E2 can be disposed on the fifth insulating layer 150. The second electrode E2 can extend in the first direction D1 on the top surface of the metal oxide pattern MOP. The second electrode E2 can be connected to the second surface SU2 of the light-emitting device ED through the contact hole CTH of the metal oxide pattern MOP. In other words, the second electrode E2 can be electrically connected to the third semiconductor layer SL3 of the light-emitting device ED through the contact hole CTH. The second electrode E2 can be electrically connected to the previously referenced... Figure 2 The second power supply line described is PL2. In other words, Figure 2 The second power supply voltage ELVSS can be applied to the second electrode E2.

[0090] Each of the first electrode E1 and the second electrode E2 may be formed of or include at least one conductive material. The conductive material may include indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium zinc gallium oxide (IGZO), or combinations thereof. However, the inventive concept is not limited to this example. Alternatively, the conductive material may include metallic materials, including molybdenum, silver, titanium, copper, aluminum, or alloys thereof.

[0091] An electrical signal can be applied to the first surface SU1 of the light-emitting device ED through the first electrode E1 and the connecting pattern CP. The connecting pattern CP can contact the first surface SU1 of the light-emitting device ED, but not the sidewall SW of the light-emitting device ED. Therefore, the electrical signal applied to the first electrode E1 can be excluded from supplying the sidewall SW of the light-emitting device ED.

[0092] The second electrode E2 can be spaced apart from a portion of the second surface SU2 of the light-emitting device ED by means of a metal oxide pattern MOP, which serves as an insulating material. The second electrode E2 can contact only the central region of the second surface SU2 exposed through the contact hole CTH. Accordingly, the electrical signal supplied to the second electrode E2 can be applied only locally to the central region of the second surface SU2.

[0093] Therefore, according to an embodiment of the present invention, the current between the first electrode E1 and the second electrode E2 can flow from the first surface SU1 of the light-emitting device ED to the second surface SU2 in the vertical direction (i.e., the third direction D3).

[0094] In a light-emitting device (ED), light can be primarily generated in the c-plane, which serves as the polar plane. In an embodiment, since current flows from the first surface SU1 (i.e., the c-plane) to the second surface SU2 (i.e., the c-plane), the current can be concentrated on the c-plane in the ED. Therefore, the luminous efficiency of the ED can be improved. Furthermore, current leakage through the edge region or sidewall SW of the second surface SU2 of the ED can be prevented, and this reduction in leakage current can further improve the luminous efficiency of the ED.

[0095] Due to the location of the contact hole CTH, a main current path can be formed from the central region of the light-emitting device (ED) in the vertical direction (e.g., the third direction D3). This can further improve the luminous efficiency of the ED, because, as mentioned above, the linear dislocation density has a relatively low value in the central region of the ED.

[0096] A light-blocking pattern BM and a color filter CF can be disposed on the second electrode E2. The light-blocking pattern BM can have an opening that is perpendicularly overlapped with the light-emitting device ED, and the color filter CF can be disposed in the opening. The light-blocking pattern BM can be a black matrix.

[0097] The color filter CF can include at least one of a red color filter, a green color filter, or a blue color filter. The color filter CF can be configured to transmit only a specific wavelength of light emitted from the light-emitting device ED. As an example, the color filter CF can include quantum dots. That is, the color filter CF can be a quantum dot color filter.

[0098] As an example, a color filter CF can include transparent material. If the light emitted from the light-emitting device ED is blue light, the color filter CF for the blue pixel can consist only of transparent material, without quantum dots.

[0099] A cover layer (CV) can be applied to the light-blocking pattern (BM) and the color filter (CF). The cover layer (CV) can be formed of or comprise transparent glass or transparent plastic. The cover layer (CV) protects the color filter (CF) and the light-emitting device (ED).

[0100] When viewed in a plan view, the light-emitting device (ED) according to this embodiment can have a honeycomb shape. Therefore, the ED can be placed on the display panel in a two-dimensional and efficient manner. In other words, the integration density of the ED on the display panel can be increased. Furthermore, due to its honeycomb shape, the ED according to this embodiment can be applied to flexible display devices.

[0101] Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 This is a plan view illustrating a method for manufacturing a light-emitting device according to an embodiment of the present invention. Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 and Figure 19 They are along Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 and Figure 18 A sectional view taken by line A-A'.

[0102] Reference Figure 6 and Figure 7 Multiple sacrificial patterned sacrificial alumina (SAPs) can be formed on a substrate SUB. The substrate SUB can be a sapphire substrate, a silicon substrate, a SiC substrate, or a GaAs substrate. As an example, the substrate SUB can be a sapphire substrate. For instance, the substrate SUB can be formed from or include a single-crystal α-phase alumina.

[0103] The formation of a sacrificial patterned SAP may include forming a photoresist layer on a substrate SUB and performing exposure and development processes on the photoresist layer. In other words, the sacrificial patterned SAP may include a photoresist material. The sacrificial patterned SAP may be arranged two-dimensionally on the substrate SUB.

[0104] When viewed in a plan view, each sacrificial pattern SAP can be configured as a regular hexagon. The angle between adjacent sides of the sacrificial pattern SAP can be approximately 120°. In other words, the sacrificial pattern SAPs can be arranged to form a honeycomb shape.

[0105] Each sacrificial pattern SAP can have a fifth width W5 in the first direction D1. The shortest distance between adjacent sacrificial pattern SAPs can be a first length L1. Here, the ratio of the first length L1 to the fifth width W5 can be in the range of 0.01 to 0.2. In an embodiment, if the fifth width W5 has a relatively small value of about 5 μm, then the first length L1 can be about 500 nm. In other words, in the method of manufacturing a light-emitting device according to an embodiment of the present invention, even as the size of the light-emitting device becomes smaller, conventional cutting processes cannot be used to separate the light-emitting device, thus overcoming the limitation of cut loss.

[0106] Reference Figure 8 and Figure 9 The inorganic layer IL can be conformally formed on the substrate SUB. The formation of the inorganic layer IL may include performing atomic layer deposition or chemical vapor deposition. The inorganic layer IL can be formed from or include at least one of silicon dioxide (SiO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), zirconium oxide (ZrO2), yttrium oxide (Y2O3)-zirconium oxide, copper oxide, tantalum oxide, aluminum nitride (AlN), or silicon nitride (Si3N4). As an example, the inorganic layer IL can be formed from or include amorphous aluminum oxide.

[0107] The inorganic layer IL can cover the top surface of the substrate SUB and the surface of each sacrificial pattern SAP. In other words, a portion of the inorganic layer IL can cover the surface of the sacrificial pattern SAP. The inorganic layer IL covering the surface of the sacrificial pattern SAP can be defined as the seed pattern SEP.

[0108] The planar shape of the seed pattern SEP can be determined by the sacrificial pattern SAP. For example, the seed pattern SEP can have a planar shape that is substantially the same as that of the sacrificial pattern SAP. Therefore, the planar shape of the seed pattern SEP can be hexagonal.

[0109] Reference Figure 10 and Figure 11 A photoresist layer (PRL) can be formed on the inorganic layer (IL). The PRL can be formed to completely cover the seed pattern (SEP). Subsequently, exposure and development processes can be performed on the PRL to form openings (OPs) within it. The openings (OPs) can be formed to overlap with the central regions of the seed pattern (SEP). In other words, the openings (OPs) can be formed to expose the central regions of the seed pattern (SEP).

[0110] Reference Figure 12 and Figure 13A photoresist layer (PRL) can be used as an etching mask to selectively etch the exposed portions of the seed pattern (SEP). Correspondingly, the sacrificial pattern (SAP) can be exposed through the opening (OP). Simultaneously, as a result of the etching process, contact holes (CTHs) can be formed in the central region of each seed pattern (SEP). The contact holes (CTHs) can be perpendicularly overlapped with the openings (OPs).

[0111] The photoresist layer PRL and the exposed sacrificial pattern SAP can be selectively removed. For example, the photoresist layer PRL and the sacrificial pattern SAP can be removed by pyrolysis through a heat treatment process. Therefore, only the inorganic layer IL, including the seed pattern SEP, can remain on the substrate SUB. The blank space ES can be defined between the seed pattern SEP and the substrate SUB.

[0112] Reference Figure 14 and Figure 15 A first heat treatment process can be performed on the inorganic layer IL to crystallize the seed pattern SEP. In an embodiment, the first heat treatment process can be performed at a temperature of 750°C to 900°C. The first heat treatment process can be performed at a temperature at which the amorphous alumina layer can transform into a polycrystalline γ phase. The first heat treatment process can be performed until all seed pattern SEPs have a polycrystalline γ phase.

[0113] Reference Figure 16 and Figure 17 A second heat treatment process can be performed on the inorganic layer IL to crystallize at least a portion of the seed pattern SEP into a single-crystal phase. For example, the second heat treatment process can be performed at a temperature of 1100°C to 1200°C. At this temperature, the inorganic layer IL can be crystallized into a single-crystal α phase due to the crystal structure of the substrate SUB (e.g., a sapphire substrate).

[0114] During the second heat treatment, crystallization can proceed from the inorganic layer IL adjacent to the substrate SUB towards the seed pattern SEP farther from the substrate SUB. In other words, crystallization during the second heat treatment can... Figure 17 The crystallization direction shown is towards the central region of the seed pattern SEP on the CRY.

[0115] If the first region RG1, which serves as the edge region of the seed pattern SEP, crystallizes into a single-crystal structure, the second heat treatment process can be terminated. That is, as a result of the second heat treatment process, the first region RG1 (single-crystal α-phase) and the second region RG2 (polycrystalline γ-phase) can be formed in the seed pattern SEP. The second region RG2 can be the central region of the seed pattern SEP and can be a region whose crystal structure has not changed to a single-crystal structure during the second heat treatment process. The second region RG2 can be adjacent to the contact hole CTH.

[0116] According to an embodiment of the present invention, as a result of the aforementioned partial single crystallization, the seed pattern SEP may include two regions having different crystal structures from each other. The seed pattern SEP can be used as a seed pattern for growing a light-emitting device ED on a first region RG1 and a second region RG2, as will be described below.

[0117] Reference Figure 18 and Figure 19 The light-emitting devices (EDs) can be individually formed on the seed pattern (SEP). Multiple EDs can be formed in two dimensions to correspond to the two-dimensional arrangement of the seed pattern (SEP).

[0118] In this embodiment, the light-emitting devices (EDs) can be grown to have the same planar shape as the seed pattern (SEP). In other words, each ED can have a hexagonal shape. In this case, the EDs can be arranged to form a honeycomb shape.

[0119] The formation of a light-emitting device (ED) may include performing a metal-organic chemical vapor deposition (MOCVD) process. For example, an MOCVD process may be performed in which the top surface of a seed pattern SEP is used as a seed to grow the ED on the seed pattern SEP. The ED may be formed of or include at least one III-V compound semiconductor material (e.g., GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, or combinations thereof).

[0120] Multilayer light-emitting devices (EDs) can be formed by adjusting the source gas, processing temperature, and chamber pressure during MOCVD processing. For example, the formation of an ED may include forming a third semiconductor layer SL3 on a seed pattern SEP, forming a second semiconductor layer SL2 on the third semiconductor layer SL3, forming an active layer ACT on the second semiconductor layer SL2, and forming a first semiconductor layer SL1 on the active layer ACT.

[0121] Specifically, the third semiconductor layer SL3 can be formed as a GaN layer. The second semiconductor layer SL2 can be formed as a GaN layer doped with impurities (e.g., silicon (Si), germanium (Ge), tin (Sn), selenium (Se), or tellurium (Te)). The active layer ACT can be formed as a multi-quantum-well structure having InGaN and GaN layers. The first semiconductor layer SL1 can be formed as a GaN layer doped with impurities (e.g., magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba)). The active layer ACT and the first to third semiconductor layers SL1, SL2, and SL3 can be formed sequentially in a single deposition chamber.

[0122] The light-emitting device (ED) may have a second surface SU2 in contact with a seed pattern SEP, a first surface SU1 opposite to the second surface SU2 on a third direction D3, and a sidewall SW extending obliquely from the second surface SU2 to the first surface SU1. The sidewall SW may include first crystal planes FA1 to sixth crystal planes FA6. Each of the first crystal planes FA1 to sixth crystal planes FA6 may be a non-etched surface formed by epitaxial growth rather than by etching.

[0123] In a comparative example, a light-emitting device can be formed by patterning a GaN layer grown epitaxially using a plasma etching method. In this case, the sidewalls of the light-emitting device can be etched surfaces formed by the etching method, and can differ from the crystal planes in the aforementioned embodiments. For example, when the sidewalls of the light-emitting device are formed by a plasma etching method, defects such as nonradiative recombination may occur on the resulting etched surface. Such defects may lead to a deterioration in the performance of the light-emitting device (e.g., external quantum efficiency (EQE)). As the size of the light-emitting device decreases, the deterioration of EQE characteristics may become increasingly problematic. Furthermore, when the sidewalls of the light-emitting device are etched surfaces, leakage current problems may occur in the light-emitting device.

[0124] According to an embodiment of the present invention, the sidewalls SW of the light-emitting device (ED) can be formed by epitaxial growth rather than by plasma etching. This means that each of the first to sixth crystal planes FA1 to FA6 of the sidewall SW is a substantially perfect crystal plane that has not been damaged by plasma. Therefore, in the light-emitting device (ED) according to this embodiment, improved performance and prevention of leakage current problems can be achieved.

[0125] Figure 20 , Figure 21 and Figure 22This is a cross-sectional view illustrating sequentially the steps of growing a light-emitting device (ED) (e.g., an epitaxial layer EPL) on a sacrificial pattern SAP via metal-organic chemical vapor deposition, according to an embodiment of the present invention.

[0126] Reference Figure 20 The epitaxial layer EPL can be grown on a sacrificial patterned SAP via metal-organic chemical vapor deposition. As described above, the sacrificial patterned SAP may include a first region RG1 having a single-crystal α phase and a second region RG2 having a polycrystalline γ phase. The growth rate of the epitaxial layer EPL on the first region RG1 may differ from the growth rate of the epitaxial layer EPL on the second region RG2.

[0127] In detail, the epitaxial growth of the epitaxial layer EPL on the first region RG1 can be faster than on the second region RG2. For example, on the first region RG1, the epitaxial layer EPL can be grown in the form of layers, while on the second region RG2, the grain ISL (e.g., GaN grain ISL) can be grown in the form of islands. On the first region RG1, the epitaxial layer EPL can grow rapidly in the

[0001] direction (e.g., the third direction D3).

[0128] Reference Figure 21 If the metal-organic chemical vapor deposition process continues, the epitaxial layer EPL on the first region RG1 can be grown horizontally toward the second region RG2. For example, the epitaxial layer EPL on the first region RG1 can be grown not only in the third direction D3, but also in the first direction D1. Accordingly, the second region RG2 can be covered by the epitaxial layer EPL. Furthermore, horizontal growth of the epitaxial layer EPL can be performed such that a portion of the epitaxial layer EPL is formed on the contact hole CTH, and in this case, the epitaxial layer EPL can be formed over the entire area of ​​the seed pattern SEP.

[0129] Figure 22 The diagram illustrates the final structure of the epitaxial layer EPL formed after the metal-organic chemical vapor deposition process is completed. The epitaxial layer EPL may have a second surface SU2 in contact with the seed pattern SEP and a first surface SU1 opposite the second surface SU2 on a third direction D3.

[0130] The epitaxial layer EPL may include linear dislocations TDL extending from the second surface SU2 to the first surface SU1 on the third direction D3. The linear dislocations TDL may be crystal defects formed during the growth of the epitaxial layer EPL. As described above, since the epitaxial layer EPL on the first region RG1 is mainly grown on the third direction D3, most of the linear dislocations TDL can be formed on the first region RG1.

[0131] Simultaneously, the epitaxial layer EPL on the second region RG2 can be generated by horizontal growth in the first direction D1, rather than by horizontal growth in the third direction D3. Therefore, crystal defects (i.e., linear dislocations TDL) on the second region RG2 will not form continuously from the second surface SU2 to the first surface SU1. As a result, the epitaxial layer EPL on the second region RG2 can have a relatively low density of linear dislocations TDL. In this case, the bus dislocation density of the light-emitting device ED can be reduced, thereby improving the luminous efficiency of the light-emitting device ED.

[0132] Figure 23 , Figure 24 and Figure 25 This is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment of the present invention.

[0133] Reference Figure 23 A first thin-film transistor TR1 and a second thin-film transistor TR2 can be formed on the substrate 100. The formation of the first thin-film transistor TR1 and the second thin-film transistor TR2 may include performing an LTPS process or an LTPO process. A connection electrode CCE can be formed to electrically connect the first thin-film transistor TR1 and the second thin-film transistor TR2 to each other. A first electrode E1 can be formed on the connection electrode CCE. The first electrode E1 can be electrically connected to the second thin-film transistor TR2. The first electrode E1 can be exposed to the outside.

[0134] Reference Figure 24 The reflection pattern RP and the connection pattern CP can be formed on the reference. Figure 18 and Figure 19 The described light-emitting device ED. The reflective pattern RP can be formed to selectively cover only the sidewalls SW of the light-emitting device ED. The connecting pattern CP can be formed to selectively cover only the first surface SU1 of the light-emitting device ED.

[0135] The light-emitting device (ED) can be separated from the substrate (SUB). Separation of the ED can be achieved using a mechanical lift-off method. In an embodiment, during the mechanical lift-off process, the seed pattern (SEP) on the second surface (SU2) of the ED remains intact, thereby forming a metal oxide pattern (MOP) covering the second surface (SU2).

[0136] The separate light-emitting device ED can be mounted on the first electrode E1. The separate light-emitting device ED can be inverted and then placed with its connecting pattern CP placed on the first electrode E1.

[0137] Reference Figure 25The fifth insulating layer 150 can be formed to cover the first electrode E1 and the light-emitting device ED. The second electrode E2 can be formed on the fifth insulating layer 150. The second electrode E2 can be connected to the third semiconductor layer SL3 of the light-emitting device ED through the contact hole CTH of the metal oxide pattern MOP.

[0138] Return to reference Figure 3 and Figure 4 The light-blocking pattern BM and the color filter CF can be formed on the second electrode E2. The light-blocking pattern BM can be a black matrix. The color filter CF can include at least one of a red color filter, a green color filter, or a blue color filter. The capping layer CV can be formed on the light-blocking pattern BM and the color filter CF.

[0139] In a method for manufacturing a display device according to an embodiment of the present invention, the light-emitting device (ED) and the substrate (SUB) can be easily separated from each other by a mechanical peeling method. Even when the ED is separated from the substrate (SUB), the metal oxide pattern (MOP) can still be attached to or remain on the second surface (SU2). In other words, the metal oxide pattern (MOP) does not need to be removed, and the ED with the metal oxide pattern (MOP) can be directly used as part of the display device. Therefore, the additional process of removing the metal oxide pattern (MOP) is unnecessary, and this can reduce the manufacturing cost of the ED. This metal oxide pattern (MOP) can be used to passivate the second surface (SU2) of the ED and can also provide an n-type contact through the contact hole (CTH).

[0140] Figure 26 This is a plan view of the display panel of a display device according to an embodiment of the present invention. Figure 27 It is along Figure 26 A sectional view taken by line A-A'. Figure 28 yes Figure 26 A magnified planar view of the first pixel. In the following description of the display device according to this embodiment, reference is made to the preceding text. Figure 3 , Figure 4 The elements described in Figures 5A and 5B may be identified using the same reference numerals without repeating their overlapping descriptions.

[0141] Reference Figure 26 and Figure 27 The first pixel PX1 to the third pixel PX3 can be disposed on the substrate 100. The substrate 100 may include a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stack containing multiple insulating layers.

[0142] The first pixel PX1 to the third pixel PX3 can be arranged in a two-dimensional manner. As an example, the first pixel PX1 to the third pixel PX3 can be arranged in the second direction D2. Although not shown, additional pixels can be additionally disposed on the base layer 100 to form a two-dimensional pixel arrangement.

[0143] Each of the first pixel PX1 to the third pixel PX3 may include a first thin-film transistor TR1, a second thin-film transistor TR2, and a plurality of light-emitting devices ED. In the following, one of the first pixel PX1 to the third pixel PX3 (e.g., the first pixel PX1) will be described by way of example.

[0144] The first thin-film transistor TR1 and the second thin-film transistor TR2 can be placed on the substrate 100. The first thin-film transistor TR1 and the second thin-film transistor TR2 can be configured to have a reference... Figure 3 and Figure 4 The features described are basically the same.

[0145] A partition wall structure PAR can be disposed on the fourth insulating layer 140. The partition wall structure PAR can have a bottom surface coplanar with the bottom surface of the first electrode E1. The partition wall structure PAR can define a recessed region RS that exposes the top surface of the first electrode E1. For example, the recessed region RS can be defined by the inner sidewall of the partition wall structure PAR and the top surface of the first electrode E1. The recessed region RS can be configured to have a specific depth DEP when measured from the top surface of the partition wall structure PAR.

[0146] Multiple light-emitting devices (EDs) can be disposed on the first electrode E1 in the recessed region RS. Each ED can be configured to have a reference electrode. Figure 3 , Figure 4 Figures 5A and 5B describe the same basic features.

[0147] The light-emitting device (ED) may include an active light-emitting device (EDa) and a dummy light-emitting device (EDd). Each active light-emitting device (EDa) may be positioned with its first surface SU1 facing the first electrode E1 or the substrate 100. A connection pattern CP may be positioned between the active light-emitting device (EDa) and the first electrode E1. The first surface SU1 of the active light-emitting device (EDa) may be electrically connected to the first electrode E1 via the connection pattern CP. Each dummy light-emitting device (EDd) may be positioned with its second surface SU2 facing the first electrode E1 or the substrate 100. The second surface SU2 of the dummy light-emitting device (EDd) may be spaced from the first electrode E1 via a metal oxide pattern MOP.

[0148] The ratio of the number of active light-emitting devices (EDa) to the total number of light-emitting devices (ED) can range from approximately 40% to approximately 60%. The ratio of the number of dummy light-emitting devices (EDd) to the total number of light-emitting devices (ED) can range from approximately 60% to approximately 40%. The number of active light-emitting devices (EDa) can be substantially equal to the number of dummy light-emitting devices (EDd), but in embodiments, they can differ from each other.

[0149] In this embodiment, the ratio of the number of active light-emitting devices (EDa) to the total number of light-emitting devices (ED) can be in the range of approximately 60% to approximately 100%. In other words, the number of active light-emitting devices (EDa) can be greater than the number of dummy light-emitting devices (EDd).

[0150] A fifth insulating layer 150 may be disposed on the fourth insulating layer 140 to fill the area between the light-emitting devices ED. A second electrode E2 may be disposed on the fifth insulating layer 150 and the light-emitting devices ED. The metal oxide pattern MOP covering the second surface SU2 of the active light-emitting device EDa may have a contact hole CTH exposing the central region of the second surface SU2. The second electrode E2 may contact the second surface SU2 of the active light-emitting device EDa.

[0151] According to an embodiment of the present invention, the first electrode E1 can be a p-type electrode, and the second electrode E2 can be an n-type electrode. In the active light-emitting device EDa, the p-type electrode or the first electrode E1 can be electrically connected to a p-type semiconductor layer adjacent to the first surface SU1 via a connection pattern CP, and the n-type electrode or the second electrode E2 can be electrically connected to an n-type semiconductor layer adjacent to the second surface SU2. Therefore, the active light-emitting device EDa can be used to emit light during the operation of the display device.

[0152] In contrast, for the dummy light-emitting device EDd, the metal oxide pattern MOP prevents the first electrode E1 from contacting the second surface SU2, while the n-type or second electrode E2 is connected to the p-type semiconductor layer adjacent to the first surface SU1. Therefore, the dummy light-emitting device EDd can not emit any light during operation of the display device. Since the active light-emitting device EDa accounts for approximately 40% to 60% of the light-emitting device ED, each of the pixels PX1 to PX3 can be used as a regular pixel.

[0153] A sixth insulating layer 160 may be disposed on the second electrode E2. The sixth insulating layer 160 may have a flat top surface. A light-blocking pattern BM and a color filter CF may be disposed on the sixth insulating layer 160. The light-blocking pattern BM may have an opening that perpendicularly overlaps with the recessed region RS, and the color filter CF may be disposed in the opening. A cover layer CV may be disposed on the light-blocking pattern BM and the color filter CF.

[0154] Will refer again Figure 28The light-emitting devices ED are described in more detail in the recessed region RS of the first pixel PX1. The light-emitting devices ED of the first pixel PX1 may include first light-emitting devices ED1 to eighth light-emitting devices ED8. Each of the first light-emitting devices ED1 to eighth light-emitting devices ED8 may have a center CG. As an example, the center CG of the light-emitting device ED may be the centroid of the light-emitting device ED.

[0155] The first center line CL1 can be defined as passing through the center CG of the first light-emitting device ED1. When viewed in a plan view, the first center line CL1 can be perpendicular to the first crystal plane FA1 and the fourth crystal plane FA4 of the first light-emitting device ED1. The second center lines CL2 to the fourth center line CL4 of the second light-emitting device ED2 to the fourth light-emitting device ED4 can be defined in the same manner as the first center line CL1 of the first light-emitting device ED1.

[0156] The first center lines CL1 to the fourth center lines CL4 may not be parallel to each other. In other words, since the light-emitting devices (EDs) are randomly arranged, the first center lines CL1 to the fourth center lines CL4 may not be parallel to each other. The first center lines CL1 to the fourth center lines CL4 may intersect each other. As an example, the first center line CL1 may be tilted at a third angle θ3 relative to the second direction D2, the second center line CL2 may be tilted at a fourth angle θ4 relative to the second direction D2, the third center line CL3 may be tilted at a fifth angle θ5 relative to the second direction D2, and the fourth center line CL4 may be tilted at a sixth angle θ6 relative to the second direction D2. The third angle θ3 to the sixth angle θ6 may be different from each other.

[0157] The fifth light-emitting device ED5, the sixth light-emitting device ED6, and the eighth light-emitting device ED8 can be configured to be adjacent to the seventh light-emitting device ED7. A first virtual line VL1 can be defined as a line connecting the center CG of the seventh light-emitting device ED7 to the center CG of the fifth light-emitting device ED5, a second virtual line VL2 can be defined as a line connecting the center CG of the seventh light-emitting device ED7 to the center CG of the sixth light-emitting device ED6, and a third virtual line VL3 can be defined as a line connecting the center CG of the seventh light-emitting device ED7 to the center CG of the eighth light-emitting device ED8.

[0158] The first virtual line VL1, the second virtual line VL2, and the third virtual line VL3 can have different lengths. In other words, the distances from the fifth light-emitting device ED5, the sixth light-emitting device ED6, and the eighth light-emitting device ED8 to the seventh light-emitting device ED7 can be different from each other.

[0159] The angle between the first virtual line VL1 and the second virtual line VL2 can be the seventh angle θ7, and the angle between the second virtual line VL2 and the third virtual line VL3 can be the eighth angle θ8. The seventh angle θ7 and the eighth angle θ8 can be different from each other.

[0160] The method of manufacturing a display device according to this embodiment may include randomly scattering micro-LED flakes on the pixels of the display device.

[0161] The material can be separated by mechanical peeling. Figures 6 to 19 The light-emitting devices (EDs) are fabricated on a substrate SUB, and then the separated EDs are collected to prepare a micro-LED wafer. In other words, each wafer in the micro-LED wafer can be a ED according to an embodiment of the concept of the present invention.

[0162] Since the micro-LED flakes are randomly distributed on the pixels, the light-emitting devices on the first electrode E1 can be arranged in a two-dimensional random pattern. In an embodiment, each light-emitting device ED on the first electrode E1 has a 50% probability of being an active light-emitting device EDa, or a 50% probability of being a dummy light-emitting device EDd.

[0163] According to this embodiment, the display device can be implemented by randomly arranging light-emitting devices on pixels. Since the maximum width-to-height ratio of the light-emitting devices on a pixel is large, approximately 50% of the light-emitting devices can be used as active light-emitting devices. Because the light-emitting devices are arranged randomly rather than regularly on the pixels, large-area display panels can be manufactured quickly and economically.

[0164] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A display device, comprising: Multiple pixels; A light-emitting device is disposed in each of the plurality of pixels, the light-emitting device having a first surface and a second surface opposite to each other; The first electrode is electrically connected to the first surface of the light-emitting device; The second electrode is electrically connected to the second surface of the light-emitting device; as well as A metal oxide pattern is positioned between the second surface of the light-emitting device and the second electrode. The metal oxide pattern includes a first region and a second region. The first area surrounds the second area. The second region has contact holes that expose at least a portion of the second surface. The second electrode is coupled to the second surface through the contact hole, and The first and second regions have different crystal phases from each other.

2. The display device according to claim 1, wherein, The density in the first region is higher than that in the second region.

3. The display device according to claim 1, wherein, The crystallization temperature of the first region is higher than that of the second region.

4. The display device according to claim 1, wherein, The first region includes single-crystal α-phase alumina, and The second region includes polycrystalline γ-phase alumina.

5. The display device according to claim 1, wherein, The first surface includes a third region and a fourth region as its edge region and center region, and The linear dislocation density in the third region is higher than that in the fourth region.

6. The display device according to claim 1, wherein, The light-emitting device further includes a sidewall extending from the first surface to the second surface, and The sidewalls comprise {n - n 0 k} crystal planes, where each of the indices n and k is an integer of 1 or greater.

7. The display device according to claim 6, wherein, When viewed in a plan view, the light-emitting device has a hexagonal shape. The sidewalls include a first crystal plane to a sixth crystal plane, and The first to sixth crystal planes are arranged along the edges of the light-emitting device that defines the hexagonal shape.

8. The display device according to claim 1, wherein, The area of ​​the second surface is greater than the area of ​​the first surface.

9. The display device according to claim 1, wherein, The light-emitting device comprises a p-type first semiconductor layer, an active layer, and an n-type second semiconductor layer stacked sequentially. The first semiconductor layer is adjacent to the first surface, and The second semiconductor layer is adjacent to the second surface.

10. The display device according to claim 1, wherein, The light-emitting device includes at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, or combinations thereof.

11. A display device, comprising: Multiple pixels; as well as The light-emitting device is disposed in each of the plurality of pixels. The light-emitting device includes a first surface and a second surface that are opposite to each other. The light-emitting device comprises a p-type first semiconductor layer, an active layer, and an n-type second semiconductor layer stacked sequentially. The first semiconductor layer is adjacent to the first surface. The second semiconductor layer is adjacent to the second surface. The first surface includes a first region and a second region, which are its edge region and center region, respectively. The first surface has a first width. The second region has a second width. The ratio of the second width to the first width is in the range of 0.7 to 0.9, and The linear dislocation density in the first region is higher than that in the second region.

12. The display device of claim 11, further comprising a metal oxide pattern covering a second surface of the light-emitting device. in, The metal oxide pattern includes a third region and a fourth region, which serve as its edge region and center region, respectively. The fourth region has a contact hole that exposes at least a portion of the second surface, and The third and fourth regions have different crystal phases from each other.

13. The display device according to claim 12, wherein, The second and fourth regions overlap vertically with each other.

14. The display device according to claim 11, wherein, The linear dislocation density on the first surface is 3 × 10⁻⁶. 6 / cm 2 Up to 3×10 8 / cm 2 Within the range.

15. The display device according to claim 11, wherein, The light-emitting device further includes a sidewall extending from the first surface to the second surface, and The sidewalls comprise {n - n 0 k} crystal planes, where each of the indices n and k is an integer of 1 or greater.

16. A light-emitting device having a first surface and a second surface facing each other, comprising: First semiconductor layer; The active layer is disposed on the first semiconductor layer; A second semiconductor layer is disposed on the active layer; as well as A metal oxide pattern is disposed on the second semiconductor layer; In this configuration, the first semiconductor layer is adjacent to the first surface, and the second semiconductor layer is adjacent to the second surface. The metal oxide pattern includes a first region and a second region. The first region surrounds the second region. The first region and the second region have different crystal phases.

17. The light-emitting device according to claim 16, wherein, The density in the first region is higher than that in the second region.

18. The light-emitting device according to claim 16, wherein, The second region has contact holes that expose at least a portion of the second surface.

19. The light-emitting device according to claim 16, wherein, The first region includes single-crystal α-phase alumina, and The second region includes polycrystalline γ-phase alumina.

20. The light-emitting device according to claim 16, wherein, The first surface includes a third region and a fourth region as its edge region and center region, and The linear dislocation density in the third region is higher than that in the fourth region.

21. The light-emitting device according to claim 16, wherein, The light-emitting device further includes a sidewall extending from the first surface to the second surface, and The sidewalls comprise {n - n 0 k} crystal planes, where each of the indices n and k is an integer of 1 or greater.

22. The light-emitting device according to claim 21, wherein, When viewed in a plan view, the light-emitting device has a hexagonal shape. The sidewalls include a first crystal plane to a sixth crystal plane, and The first to sixth crystal planes are arranged along the edges of the light-emitting device that defines the hexagonal shape.

23. The light-emitting device according to claim 16, wherein, The area of ​​the second surface is greater than the area of ​​the first surface.

24. The light-emitting device according to claim 16, wherein, The first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer.

25. The light-emitting device according to claim 16, wherein, The light-emitting device includes at least one of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, and combinations thereof.

Images