Data analysis method, device and storage medium

Abstract

Embodiments of the present disclosure relate to a data analysis method and device, and a storage medium. The method comprises: obtaining a single shmoo graph of each pin of a single storage grain; and constructing an integrated shmoo graph of the storage grain based on the single shmoo graph of each pin, wherein each test point of the integrated shmoo graph is marked with a pass ratio, and the pass ratio is used to represent the proportion of the number of single shmoo graphs passing at the corresponding test point to the total number of single shmoo graphs. The embodiments avoid introducing artificial operation errors, and improve the efficiency and intelligence of the analysis of the test data of the storage grain.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of semiconductor storage technology, specifically to a data analysis method, apparatus, and storage medium. Background Technology

[0002] With the rapid development of integrated circuit manufacturing processes, the market has placed higher demands on the shipping efficiency and quality of semiconductor memory products. To improve the shipping quality of semiconductor memory products, batch testing is generally conducted on products before they leave the factory.

[0003] However, the test data for different pins of semiconductor memory chips is very complex. Traditional methods of manually comparing and analyzing test data are difficult to quickly distinguish the differences in characteristics between different memory chips and trace the root cause of the differences. On the other hand, they inevitably introduce human error, resulting in low data analysis efficiency and extending the product testing and delivery cycle. Summary of the Invention

[0004] This disclosure provides a data analysis method, apparatus, and storage medium that can automatically generate an integrated shmoo diagram of a single storage chip and display the pass rate of test data for different pins on the integrated shmoo diagram. This intuitively presents the patterns and differences in the test data, making it easier for relevant personnel to quickly identify the characteristic differences of different storage chips and trace the root cause of the differences. This avoids introducing human operation errors and improves the efficiency and intelligence of storage chip test data analysis.

[0005] According to some embodiments, a first aspect of this disclosure provides a data analysis method, comprising: acquiring individual shmoo plots of each pin of a single memory chip; constructing an integrated shmoo plot of the memory chip based on the individual shmoo plots of each pin, wherein each test point of the integrated shmoo plot is marked with a pass ratio, the pass ratio being used to characterize the proportion of the number of individual shmoo plots passing at the corresponding test point to the total number of individual shmoo plots. Since the integrated shmoo plot of the memory chip is automatically generated from the individual shmoo plots of each pin of the single memory chip, the pass ratio of each test point in the integrated shmoo plot intuitively presents to relevant personnel the proportion of the number of individual shmoo plots passing at the corresponding test point to the total number of individual shmoo plots. This facilitates relevant personnel in judging the common characteristics or regularities of the test data based on repeated pass ratios or trends in pass ratios in the integrated shmoo plot, and in judging the differences in the characteristics of different pins of the memory chip based on the differences in pass ratios in the integrated shmoo plot, and tracing the root cause of the differences, avoiding the introduction of human error, and improving the efficiency and intelligence of memory chip test data analysis.

[0006] In some embodiments, the integrated shmoo map includes partially overlapping feature regions and passing regions. The passing regions include common passing regions of each of the individual shmoo maps. The pass rate of the test points in the common passing regions is 100%. The pass rate of each test point in the feature regions is greater than 0 and less than 100%. This embodiment facilitates relevant personnel to discover common features of test data based on the common passing regions of each individual shmoo map, to determine the performance of storage particles, and to determine the differences in the characteristics of different pins of storage particles based on the differences in the pass rates in the feature regions, and to trace the root cause of the differences.

[0007] In some embodiments, the feature region has at least two first identifiers for representing the throughput ratio, with different first identifiers representing different throughput ratios, so that relevant personnel can compare the first identifiers, such as numerical identifiers, and determine the differences in the characteristics of different pins of the storage particles based on the comparison results, so as to trace the root cause of the differences.

[0008] In some embodiments, the first identifier includes a numerical identifier, and the method further includes the step of determining the pin uniformity of the storage particle as follows: obtaining the difference between the numerical identifiers of any adjacent test points in the feature region; if at least one of the differences is greater than or equal to a preset difference threshold, the pin uniformity of the storage particle is determined to be poor; otherwise, the pin uniformity of the storage particle is determined to be good; or obtaining the minimum value of each numerical identifier; if the minimum value is greater than or equal to a preset standard threshold, the pin uniformity of the storage particle is determined to be good; otherwise, the pin uniformity of the storage particle is determined to be poor. In this embodiment, the pass rate numerical identifiers of test points corresponding to different pins can be displayed intuitively within the integrated SHMO diagram feature region, and the pin uniformity of the storage particle can be intelligently determined based on the comparison results by comparing the difference between the numerical identifiers of adjacent test points with a preset difference threshold, or comparing the minimum value of each numerical identifier with a preset standard threshold, effectively improving the intelligence and efficiency of data analysis.

[0009] In some embodiments, each test point in the feature region is also marked with a second identifier corresponding to the pin, such as a name identifier, to facilitate relevant personnel to intuitively distinguish different pins, so as to judge the difference characteristics of different pins of storage particles based on the difference in proportion in the feature region, and trace the root cause of the difference.

[0010] In some embodiments, the data analysis method further includes the step of determining whether the storage particle has edge defects: obtaining the standard pass-through region of the integrated shmoo image of the storage particle; determining the axis of symmetry extending along the frequency scanning direction of the standard pass-through region as a first coordinate axis, and determining the straight line containing the axis of symmetry extending along the voltage scanning direction or the boundary line extending along the voltage scanning direction of the standard pass-through region as a second coordinate axis; obtaining the intersection point of the boundary line of the feature region and the first coordinate axis, and obtaining the distance value between the intersection point and the perpendicular point of the coordinate axis, wherein the perpendicular point of the coordinate axis is the perpendicular point between the first coordinate axis and the second coordinate axis; if the distance value is greater than or equal to a preset distance threshold, it is determined that an edge defect exists. This embodiment realizes intelligent determination of whether the storage particle has edge defects based on the integrated shmoo image of the storage particle.

[0011] In some embodiments, the data analysis method further includes the step of determining whether the memory chip has a void defect: determining whether there is a test failure region within the passed region, the test failure region comprising a plurality of consecutive test failure points; if so, determining whether any of the test failure regions includes at least two consecutive test failure points in the voltage scan direction and at least two consecutive test failure points in the frequency scan direction; if so, determining that a void defect exists. This embodiment realizes intelligent determination of whether the memory chip has a void defect based on the integrated SHMO diagram of the memory chip.

[0012] In some embodiments, the data analysis method further includes the step of determining whether the memory chip has a voltage linearity defect: determining whether there is a voltage linearity defect region in the integrated shmoo plot, wherein the voltage linearity defect region includes at least one voltage failure line extending along the frequency scanning direction and intersecting with two opposite boundary lines of the integrated shmoo plot, and each test point located on the voltage failure line is a test failure point; if so, it is determined that a voltage linearity defect exists. This embodiment realizes intelligent determination of whether the memory chip has a voltage linearity defect based on the integrated shmoo plot of the memory chip.

[0013] In some embodiments, the data analysis method further includes the step of determining whether the memory chip has a frequency linearity defect: determining whether there is a frequency linearity defect region in the integrated shmoo plot, wherein the frequency linearity defect region includes at least one frequency failure line extending along the voltage scan direction and intersecting with two opposite boundary lines of the integrated shmoo plot, and each test point located on the frequency failure line is a test failure point; if so, it is determined that a frequency linearity defect exists. This embodiment realizes intelligent determination of whether the memory chip has a frequency linearity defect based on the integrated shmoo plot of the memory chip.

[0014] A second aspect of this disclosure provides a data analysis method, comprising: acquiring a single shmoo map of any storage particle among a plurality of storage particles; constructing an integrated shmoo map of the memory based on the single shmoo maps of each storage particle, wherein each test point of the integrated shmoo map is labeled with a third identifier, the third identifier being used to characterize the encoding of the storage particle passing through the corresponding test point. This embodiment facilitates the intuitive discovery of edge differences between different storage particles through the integrated shmoo map of the memory.

[0015] A third aspect of this disclosure provides a data analysis apparatus, including a single shmoo map acquisition module and an integrated shmoo map construction module. The single shmoo map acquisition module is used to acquire single shmoo maps of each pin of a single memory chip. The integrated shmoo map construction module is used to construct an integrated shmoo map of the memory chip based on the single shmoo maps of each pin. Each test point of the integrated shmoo map is marked with a pass rate, and the pass rate is used to characterize the proportion of the number of single shmoo maps that pass at the corresponding test point to the total number of single shmoo maps. Because the integrated shmoo diagram construction module automatically generates the integrated shmoo diagram of a storage chip based on the individual shmoo diagrams of each pin, the pass rate of each test point in the integrated shmoo diagram intuitively presents to relevant personnel the proportion of the number of individual shmoo diagrams that passed at the corresponding test point to the total number of individual shmoo diagrams. This facilitates relevant personnel in judging the common or regular characteristics of the test data based on the repeated pass rates or the changing trends of the pass rates in the integrated shmoo diagram, and in judging the differences between different pins of the storage chip based on the differences in the pass rates in the integrated shmoo diagram, tracing the root cause of the differences, avoiding the introduction of human operation errors, and improving the efficiency and intelligence of storage chip test data analysis.

[0016] In some embodiments, the integrated shmoo map includes partially overlapping feature regions and pass regions. The pass regions include common pass regions shared by each of the individual shmoo maps. The pass rate of the test points in the common pass regions is 100%. The pass rate of each test point in the feature regions is greater than 0 and less than 100%. The feature regions have at least two first identifiers for representing the pass rates, with different first identifiers representing different pass rates. This embodiment facilitates relevant personnel in discovering common features of test data based on the common pass regions of each individual shmoo map, judging the performance of storage particles, and judging the differences in the characteristics of different pins of storage particles based on the differences in the pass rates in the feature regions, and tracing the root cause of the differences.

[0017] In some embodiments, the first identifier includes a digital identifier, and the data analysis device further includes a pin uniformity judgment module. The pin uniformity judgment module is used to compare the digital identifiers of adjacent test points in the feature region, or to obtain the minimum value of each digital identifier and compare the minimum value with a preset standard threshold. Based on the comparison result, the pin uniformity of the storage particle is judged, which effectively improves the intelligence and efficiency of data analysis.

[0018] In some embodiments, each test point in the feature region is also marked with a second identifier corresponding to the pin, such as a name identifier, to facilitate relevant personnel to intuitively distinguish different pins, so as to judge the difference characteristics of different pins of storage particles based on the difference in proportion in the feature region, and to trace the root cause of the difference.

[0019] In some embodiments, the data analysis device further includes a standard pass-through region acquisition unit, a coordinate axis acquisition unit, and an edge defect judgment unit. The standard pass-through region acquisition unit is used to acquire the standard pass-through region of the integrated SHmoo map of the storage particle. The coordinate axis acquisition unit is used to determine the axis of symmetry extending along the frequency scanning direction of the standard pass-through region as a first coordinate axis, and the straight line containing the axis of symmetry extending along the voltage scanning direction or the boundary line extending along the voltage scanning direction of the standard pass-through region as a second coordinate axis. The edge defect judgment unit is used to acquire the intersection point of the boundary line of the feature region and the first coordinate axis, and to acquire the distance value between the intersection point and the perpendicular point of the coordinate axis, wherein the perpendicular point of the coordinate axis is the perpendicular point between the first coordinate axis and the second coordinate axis; and if the distance value is greater than or equal to a preset distance threshold, it is determined that an edge defect exists. This embodiment realizes intelligent judgment of whether there is an edge defect in the storage particle based on the integrated SHmoo map of the storage particle.

[0020] In some embodiments, the data analysis device further includes a void defect determination module, which is used to determine whether there is a test failure region within the passed region, wherein the test failure region includes a plurality of consecutive test failure points; if so, it determines whether any of the test failure regions includes at least two consecutive test failure points in the voltage scanning direction and at least two consecutive test failure points in the frequency scanning direction; if so, it determines that a void defect exists. This embodiment realizes intelligent determination of whether there is a void defect in the memory chip based on the integrated SHMO diagram of the memory chip.

[0021] In some embodiments, the data analysis device further includes a voltage linearity defect determination module. This module determines whether a voltage linearity defect region exists in the integrated shmoo plot. The voltage linearity defect region includes at least one voltage failure line extending along the frequency scanning direction and intersecting with two opposing boundary lines of the integrated shmoo plot. Each test point located on the voltage failure line is a test failure point. If so, a voltage linearity defect is determined to exist. This embodiment intelligently determines whether a storage chip has a voltage linearity defect based on the integrated shmoo plot of the storage chip.

[0022] In some embodiments, the data analysis device further includes a frequency linearity defect determination module. This module determines whether a frequency linearity defect region exists in the integrated shmoo plot. The frequency linearity defect region includes at least one frequency failure line extending along the voltage scan direction and intersecting with two opposing boundary lines of the integrated shmoo plot. Each test point located on the frequency failure line is a test failure point. If so, a frequency linearity defect is determined to exist. This embodiment intelligently determines whether a memory chip has a frequency linearity defect based on its integrated shmoo plot.

[0023] A fourth aspect of this disclosure provides a storage device including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the program to implement the steps of the method described in any embodiment of this disclosure.

[0024] A fifth aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any embodiment of this disclosure. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic flowchart illustrating a data analysis method provided in one embodiment of the present disclosure;

[0027] Figure 2a A schematic diagram of the original SHMOO diagram for a single pin of a single memory chip;

[0028] Figure 2b This diagram illustrates the integration of a single storage chip in one embodiment.

[0029] Figure 3 A schematic flowchart illustrating a data analysis method in another embodiment of this disclosure;

[0030] Figure 4a This illustrates an integrated shmoo diagram of a single storage particle in another embodiment;

[0031] Figure 4b This diagram illustrates the integration of a single storage chip in another embodiment.

[0032] Figure 4c This illustrates an integrated Shmoo diagram of a single storage chip in yet another embodiment;

[0033] Figure 5 A schematic flowchart illustrating the data analysis method in another embodiment of this disclosure;

[0034] Figure 6a This illustration shows an integrated Shmoo diagram of a memory chip with edge defects in one embodiment.

[0035] Figure 6b This illustrates an integrated Shmoo diagram of a memory chip with edge defects in another embodiment.

[0036] Figure 7 This diagram illustrates an integrated Shmoo diagram of a memory chip with void defects in one embodiment.

[0037] Figure 8 This illustration shows an integrated SHMO diagram of a memory chip with voltage linearity defects in one embodiment.

[0038] Figure 9 This illustration shows an integrated shmoo diagram of a memory chip exhibiting frequency linearity defects in one embodiment.

[0039] Figure 10 An integrated Shmoo diagram illustrating a memory chip exhibiting void defects and voltage linearity defects in one embodiment.

[0040] Figure 11 A schematic flowchart illustrating a data analysis method in yet another embodiment of this disclosure;

[0041] Figure 12a This illustration shows a single shmoo diagram of the storage particles in one embodiment;

[0042] Figure 12b This diagram illustrates the integrated shmoo diagram of the memory in one embodiment;

[0043] Figure 13 This is a schematic diagram illustrating the structure of a data analysis device in one embodiment of the present disclosure;

[0044] Figure 14 This diagram illustrates the structure of the data analysis device in another embodiment of the present disclosure.

[0045] Figure 15 This is a schematic diagram illustrating the structure of a data analysis device in another embodiment of the present disclosure.

[0046] Figure labels and descriptions:

[0047] 11. Passing Area; 111. Test Failure Area; 12. Feature Area; 121. First Sub-feature Area; 122. Second Sub-feature Area; 112. Voltage Linearity Defect Area; 113. Frequency Linearity Defect Area; 20. Data Analysis Device; 21. Single SHMOO Diagram Acquisition Module; 22. Integrated SHMOO Diagram Construction Module; 23. Pin Uniformity Judgment Module; 24. Defect Type Judgment Module; 241. Edge Defect Judgment Module; 2411. Standard Passing Area Acquisition Unit; 2412. Coordinate Axis Acquisition Unit; 2413. Edge Defect Judgment Unit; 242. Void Defect Judgment Module; 243. Voltage Linearity Defect Judgment Module; 244. Frequency Linearity Defect Judgment Module. Detailed Implementation

[0048] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough and complete understanding of the disclosure will be achieved.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0051] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0052] In the description of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0053] It should be noted that in this disclosure, the term "memory particle" can include any one of memory chips, memory, and storage devices, and the term "pin" can be the data transmission port of the "memory particle".

[0054] Shmoo plots are an effective tool for analyzing memory chip characteristics. In failure analysis, by comparing the numerical curves between different parameters, such as scan voltage and scan frequency (the scan frequency being the reciprocal of the scan cycle), they can help pinpoint the root cause of failures and identify potential problems in the chip design. However, because the Shmoo data for a single memory chip, such as different pins, is extremely complex, manually drawing individual Shmoo plots for each pin is a very arduous task, introducing an unavoidable amount of human error. This makes it difficult to quickly distinguish the characteristic differences between different pins and trace the root cause. The accuracy of the test results also depends on the experience and skill level of the test engineer, resulting in low efficiency and difficulty in guaranteeing the accuracy of failure analysis results.

[0055] The embodiments disclosed herein aim to provide a data analysis method, apparatus, and storage medium that can automatically generate an integrated shmoo diagram of a single storage chip and display the pass rate of test data for different pins on the integrated shmoo diagram. This intuitively presents the patterns and differences in the test data, facilitating relevant personnel to quickly identify the characteristic differences of different storage chips and trace the root cause of the differences. It avoids introducing human operation errors and improves the efficiency and intelligence of storage chip test data analysis.

[0056] For example, please refer to Figure 1 A data analysis method includes the following steps:

[0057] Step S110: Obtain a single shmoo image of each pin of a single storage chip;

[0058] Step S120: Construct an integrated shmoo map of the storage particle based on the individual shmoo maps of each pin. Each test point of the integrated shmoo map is marked with a pass rate, which is used to characterize the proportion of the number of individual shmoo maps that pass at the corresponding test point to the total number of individual shmoo maps.

[0059] Specifically, an integrated shmoo map of a memory chip is automatically constructed based on the individual shmoo maps of each pin. Each test point in the integrated shmoo map is marked with a pass rate, which can be represented by a number and / or pin name. The pass rate at least represents the proportion of the number of individual shmoo maps that pass at the corresponding test point to the total number of individual shmoo maps. For example, if the total number of individual shmoo maps of each pin of a single memory chip is N, then the pass rate for any test point in the integrated shmoo map at least includes the proportion R of the number (M) of individual shmoo maps that pass at that test point to the total number (N) of individual shmoo maps, where R = M / N, M and N are both positive integers, and R ∈ [0, 1]. Whether a single shmoo plot passes the test can be determined by judging whether the area of ​​the passing region in the single shmoo plot exceeds the preset standard area; specifically, a single shmoo plot whose passing region area is greater than or equal to the preset standard area can be determined as a single shmoo plot that passes the test, and a single shmoo plot whose passing region area is less than the preset standard area can be determined as a single shmoo plot that fails the test.

[0060] Because the integrated shmoo map of a memory chip is automatically generated from the individual shmoo maps of each pin, human error is avoided and testing efficiency is improved. The pass rate of each test point in the integrated shmoo map is presented intuitively to relevant personnel, showing the proportion of individual shmoo maps that pass the corresponding test point out of the total number of individual shmoo maps. This allows relevant personnel to determine the common or regular characteristics of the test data based on the repeated pass rates or the changing trends of the pass rates in the integrated shmoo map, and to determine the differences between different pins of the memory chip based on the differences in the pass rates in the integrated shmoo map, tracing the root cause of the differences, such as design defects or manufacturing defects, thus improving the efficiency and intelligence of memory chip test data analysis.

[0061] For example, please refer to Figure 2a , Figure 2a This illustrates a single SHMO diagram of a single pin of a single memory chip, also called the raw SHMO diagram. In the raw SHMO diagram, all through-regions are test points. The raw SHMO diagram uses... The test points are marked with "pass" and the test points are marked with "fail". Since the original SHMO diagram can only roughly show the two test results of passing and failing the test points, and a single memory chip has multiple different pins, there are a large number of original SHMO diagrams for different pins of a single memory chip. It is difficult for testers to quickly distinguish the characteristic differences between different memory chips and trace the root cause of the differences. Due to the large differences in the work proficiency, experience and personal standards of different staff, human operation errors are inevitable in the analysis results of the original SHMO diagram. In addition, manual data analysis is inefficient and prolongs the product testing cycle and delivery cycle.

[0062] For example, please refer to Figure 2b , Figure 2b This diagram illustrates the construction of an integrated shmoo map for a single memory chip based on the individual shmoo maps of each pin. Each test point in the integrated shmoo map is marked with a pass rate, which characterizes the proportion of individual shmoo maps passing at the corresponding test point relative to the total number of individual shmoo maps. The integrated shmoo map includes partially overlapping feature regions 12 and passing regions 11. Passing regions 11 include common passing areas for all individual shmoo maps. The pass rate for each test point in passing regions 11 is 100%. " " indicates a passed test point; the pass rate of each test point in feature region 12 is greater than 0 and less than 100%, and feature region 12 has at least two first identifiers for representing the pass rate, such as numerical identifiers, with different first identifiers representing different pass rates; " " indicates a failed test point, and the pass rate of a failed test point is 0. This embodiment facilitates relevant personnel to discover common features of test data based on the common pass regions of each individual SHMO diagram, and to determine the performance of storage particles, as well as to determine the differences in the characteristics of different pins of storage particles based on the differences in the pass rates in feature regions, and to trace the root cause of the differences.

[0063] As an example, please continue to refer to Figure 2bIt can control the display of corresponding numerical identifiers for each test point in feature area 12. For example, it can control the display of "0" for test points with a pass rate greater than 0 and less than 10%; "1" for test points with a pass rate greater than or equal to 10% and less than 20%; "2" for test points with a pass rate greater than or equal to 20% and less than 30%; "3" for test points with a pass rate greater than or equal to 30% and less than 40%; "4" for test points with a pass rate greater than or equal to 40% and less than 50%; "5" for test points with a pass rate greater than or equal to 50% and less than 60%; "6" for test points with a pass rate greater than or equal to 60% and less than 70%; "7" for test points with a pass rate greater than or equal to 70% and less than 80%; "8" for test points with a pass rate greater than or equal to 80% and less than 90%; and "9" for test points with a pass rate greater than or equal to 90% and less than 100%. This embodiment facilitates relevant personnel to compare the digital identifiers of test points and determine the differences in the pin characteristics of different storage particles based on the comparison results, so as to trace the root cause of the differences.

[0064] For example, please refer to Figure 3 The data analysis method also includes the following steps to determine the pin uniformity of the storage particles:

[0065] Step S130: Obtain the difference between the digital identifiers of any adjacent test points in the feature region. If at least one of the differences is greater than or equal to a preset difference threshold, the pin uniformity of the storage particle is determined to be poor; otherwise, the pin uniformity of the storage particle is determined to be good. Alternatively, obtain the minimum value of each digital identifier in the feature region. If the minimum value is greater than or equal to a preset standard threshold, the pin uniformity of the storage particle is determined to be good; otherwise, the pin uniformity of the storage particle is determined to be poor.

[0066] For details, please refer to Figure 4a After each test point in the control feature area 12 displays its corresponding digital identifier, the difference between the digital identifiers of any adjacent test points in the feature area is obtained. If at least one of the differences is greater than or equal to a preset difference threshold, such as 4, for example, if the difference between adjacent test points in the first sub-feature area 121 is 5, which is greater than the preset difference threshold of 4, then the pin uniformity of the storage particle is determined to be poor; otherwise, the pin uniformity of the storage particle is determined to be good, which effectively improves the intelligence and efficiency of data analysis.

[0067] For details, please refer to Figure 4bFor example, if the preset standard threshold is 5, after the corresponding digital identifier is displayed at each test point in the control feature area 12, the minimum value of each digital identifier in the feature area is obtained as 1. If it is less than the preset standard threshold of 5, it is determined that the pin uniformity of the storage particle is poor; otherwise, it is determined that the pin uniformity of the storage particle is good, which effectively improves the intelligence and efficiency of data analysis.

[0068] For details, please refer to Figure 4c For example, if the preset difference threshold is 4 and the preset standard threshold is 5, and the difference between adjacent test points in the second sub-feature region 122 is 6, which is greater than the preset difference threshold of 4, and the minimum value of each number identifier in the feature region is 2, which is less than the preset standard threshold of 5, then it is determined that the pin uniformity of the storage particle is poor, which effectively improves the intelligence and efficiency of data analysis.

[0069] Those skilled in the art can undoubtedly determine that the specific values ​​of the preset difference threshold or preset standard threshold given in the above embodiments are intended to illustrate the point, and different values ​​may exist in different embodiments.

[0070] For example, please refer to Figure 5 Data analysis methods also include the following steps:

[0071] Step S140: Determine whether the storage particle has at least one of the known defect types, including edge defects, void defects, voltage linearity defects and frequency linearity defects.

[0072] Specifically, in some embodiments, before executing step S140, the area of ​​the standard pass-through region pre-stored in the storage particle mode register can be obtained, and it can be further determined whether the area of ​​the pass-through region of the integrated shmoo map exceeds the area of ​​the standard pass-through region. If the area of ​​the pass-through region of the integrated shmoo map is smaller than the area of ​​the standard pass-through region, it can be determined that the storage particle has a defect, and then step S140 is executed to determine whether the storage particle has at least one of the known defect types, including edge defects, void defects, voltage linearity defects, and frequency linearity defects.

[0073] As an example, the data analysis method also includes the following steps to determine whether there are edge defects in the storage particles:

[0074] Step S1411: Obtain the standard pass-through region of the integrated shmoo map of the storage particles;

[0075] Step S1412: The axis of symmetry extending along the frequency scanning direction of the standard passing area is determined as the first coordinate axis (horizontal axis), and the straight line containing the axis of symmetry extending along the voltage scanning direction or the boundary line extending along the voltage scanning direction of the standard passing area is determined as the second coordinate axis (vertical axis).

[0076] Step S1413: Obtain the intersection point of the boundary line of the feature region and the first coordinate axis, and obtain the distance value between the intersection point and the perpendicular point of the coordinate axis. The perpendicular point of the coordinate axis is the perpendicular point or intersection point of the first coordinate axis and the second coordinate axis.

[0077] Step S1414: If the distance value is greater than or equal to the corresponding preset distance threshold, then it is determined that there is an edge defect.

[0078] For details, please refer to Figure 6a The standard pass region (not shown) of the integrated shmoo map of the storage chip is obtained. The axis of symmetry extending along the frequency scanning direction (ox direction) of the standard pass region is determined as the first coordinate axis a1, and the axis of symmetry extending along the voltage scanning direction (oy direction) of the standard pass region is determined as the second coordinate axis a2. The intersection point c of the boundary line of the feature region 12 and the first coordinate axis a1 is obtained, as well as the distance value d1 between the intersection point c and the perpendicular point b of the coordinate axis, where the perpendicular point b is the point perpendicular to or intersecting between the first coordinate axis a1 and the second coordinate axis a2. If the distance value d1 is greater than or equal to a preset distance threshold d0, an edge defect is determined to exist. This embodiment realizes intelligent determination of whether there is an edge defect in the storage chip based on the integrated shmoo map of the storage chip.

[0079] For example, please refer to Figure 6b The presence of edge defects can be determined by performing the following steps: Obtain the standard pass-through region (not shown) of the integrated shmoo map of the storage chip; define the axis of symmetry extending along the frequency scanning direction (ox direction) of the standard pass-through region as the first coordinate axis a1; define the straight line containing the boundary line extending along the voltage scanning direction (oy direction) of the standard pass-through region as the second coordinate axis a2; obtain the intersection point c of the boundary line of the feature region 12 and the first coordinate axis a1, and obtain the distance value d1 between the intersection point c and the perpendicular point b of the coordinate axis, where the perpendicular point b is the point perpendicular to the first coordinate axis a1 and the second coordinate axis a2; if the distance value d1 is greater than or equal to the corresponding preset distance threshold, then an edge defect is determined to exist. This embodiment intelligently determines whether the storage chip has edge defects based on the integrated shmoo map of the storage chip.

[0080] As an example, the data analysis method also includes the following steps to determine whether there are void defects in the storage particles:

[0081] Step S1421: Determine whether there is a failed test area within the passed area. A failed test area contains multiple consecutive failed test points.

[0082] Step S1422: If yes, then determine whether any test failure area includes at least two consecutive test failure points in the voltage scanning direction and at least two consecutive test failure points in the frequency scanning direction.

[0083] Step S1423: If yes, then it is determined that there is a void defect.

[0084] For example, please refer to Figure 7 The system determines whether a test failure region 111 exists within the passed region 11. A test failure region 111 contains multiple consecutive test failure points, denoted by “”, with a pass rate of 0. If so, it determines whether any test failure region 111 includes at least two consecutive test failure points in the voltage scan direction (oy direction) and at least two consecutive test failure points in the frequency scan direction (ox direction), where the frequency is the reciprocal of the period. If so, a void defect is determined to exist. This embodiment intelligently determines whether a storage chip has a void defect based on the integrated SHMO diagram of the storage chip.

[0085] As an example, the data analysis method also includes the following steps to determine whether the memory chip has a voltage linearity defect:

[0086] Step S1431: Determine whether there is a voltage linearity defect region in the integrated shmoo diagram. The voltage linearity defect region includes at least one voltage failure line that extends along the frequency scanning direction and intersects with two opposite boundary lines of the integrated shmoo diagram. Each test point located on the voltage failure line is a test failure point.

[0087] Step S1432: If yes, then it is determined that there is a voltage linearity defect.

[0088] For example, please refer to Figure 8 The method determines whether a voltage linearity defect region 112 exists in the integrated shmoo plot. The voltage linearity defect region 112 includes at least one voltage failure line v1 extending along the frequency scanning direction (ox direction) and intersecting both the left boundary line m1 and the right boundary line m2 of the integrated shmoo plot. The right boundary line m2 is the boundary line of the characteristic region of the memory chip's integrated shmoo plot near the test failure region. Each test point located on the voltage failure line v1 is a test failure point, indicated by “”, and the pass rate of the test failure points is 0. If so, a voltage linearity defect is determined to exist. This embodiment intelligently determines whether a memory chip has a voltage linearity defect based on its integrated shmoo plot. As an example, the data analysis method also includes the following step of determining whether a memory chip has a frequency linearity defect:

[0089] Step S1441: Determine whether there is a frequency linearity defect region in the integrated shmoo diagram. The frequency linearity defect region includes at least one frequency failure line that extends along the voltage scanning direction and intersects with two opposite boundary lines of the integrated shmoo diagram. Each test point located on the frequency failure line is a test failure point.

[0090] Step S1442: If yes, then it is determined that there is a frequency linearity defect.

[0091] For example, please refer to Figure 9 The system determines whether a frequency linearity defect region 113 exists in the integrated SHmoo plot. The frequency linearity defect region 113 includes at least one frequency failure line f1 extending along the voltage scan direction (oy direction) and intersecting both the upper boundary line m3 and the lower boundary line m4 of the integrated SHmoo plot. Each test point located on the frequency failure line f1 is a test failure point, indicated by “”, and the pass rate of a test failure point is 0. If such a point exists, a frequency linearity defect is determined to exist. This embodiment intelligently determines whether a memory chip has a frequency linearity defect based on the integrated SHmoo plot of the memory chip.

[0092] For example, please refer to Figure 10 In determining whether a memory chip has at least one of the known defect types, including edge defects, void defects, voltage linearity defects, and frequency linearity defects, it is determined that there is a test failure region 111 within the pass area. The test failure region 111 contains multiple consecutive test failure points, and includes at least two consecutive test failure points in the voltage scanning direction (oy direction) and at least two consecutive test failure points in the frequency scanning direction (ox direction). Test failure points are represented by “”, and the pass rate of test failure points is 0. It is also determined that there is a voltage linearity defect region 112 in the integrated shmoo diagram. The voltage linearity defect region 112 includes at least one voltage failure line v1 extending along the frequency scanning direction (ox direction) and intersecting with both the left boundary line m1 and the right boundary line m2 of the integrated shmoo diagram. Each test point on the voltage failure line v1 is a test failure point. Therefore, it is determined that the memory chip has both void defects and voltage linearity defects.

[0093] For example, please refer to Figure 11 A data analysis method includes the following steps:

[0094] Step S310: Obtain a single shmoo image of any storage particle among multiple storage particles;

[0095] Step S320: Construct an integrated shmoo graph of the memory based on the individual shmoo graphs of each memory chip, wherein each test point of the integrated shmoo graph of the memory is marked with a third identifier, which is used to characterize the encoding of the memory chip that passes the corresponding test point.

[0096] Specifically, after obtaining a single shmoo graph of any storage particle among multiple storage particles, Figure 12a This illustrates a single shmoo graph of a memory chip; the integrated shmoo graph of the memory is constructed based on the single shmoo graphs of each memory chip, as shown below. Figure 12b As shown, each test point in the integrated shmoo diagram of the memory is marked with a third identifier. This third identifier characterizes the code of the memory chip that passed the test point. For example, code A and code B represent codes of two different memory chips. The pass rate of the test points in the integrated shmoo diagram of the memory can be 100%. " " indicates a passed test point; " " indicates a failed test point, and the pass rate for failed test points can be 0. This embodiment facilitates the intuitive discovery of edge differences between different memory chips through the integrated shmoo graph of the memory.

[0097] For example, please refer to Figure 13 A data analysis device 20 includes a single shmoo map acquisition module 21 and an integrated shmoo map construction module 22. The single shmoo map acquisition module 21 is used to acquire single shmoo maps of each pin of a single memory chip. The integrated shmoo map construction module 22 is used to construct an integrated shmoo map of the memory chip based on the single shmoo maps of each pin. Each test point of the integrated shmoo map is marked with a pass rate, which is used to characterize the proportion of the number of single shmoo maps that pass at the corresponding test point to the total number of single shmoo maps. Because the integrated shmoo diagram construction module automatically generates the integrated shmoo diagram of a storage chip based on the individual shmoo diagrams of each pin, the pass rate of each test point in the integrated shmoo diagram intuitively presents to relevant personnel the proportion of the number of individual shmoo diagrams that passed at the corresponding test point to the total number of individual shmoo diagrams. This facilitates relevant personnel in judging the common or regular characteristics of the test data based on the repeated pass rates or the changing trends of the pass rates in the integrated shmoo diagram, and in judging the differences between different pins of the storage chip based on the differences in the pass rates in the integrated shmoo diagram, tracing the root cause of the differences, avoiding the introduction of human operation errors, and improving the efficiency and intelligence of storage chip test data analysis.

[0098] As an example, the integrated shmoo image includes partially overlapping feature regions and pass regions. The pass regions include common pass regions of each individual shmoo image; the pass rate of the test points in the common pass regions is 100%; the pass rate of each test point in the feature regions is greater than 0 and less than 100%; the feature regions have at least two first identifiers for representing the pass rate, such as numerical identifiers, with different first identifiers representing different pass rates. This embodiment facilitates relevant personnel to discover common features of test data based on the common pass regions of each individual shmoo image, and to determine the performance of storage chips, as well as to determine the differences in the characteristics of different pins of storage chips based on the differences in the pass rates in the feature regions, and to trace the root cause of the differences.

[0099] For example, please refer to Figure 14 The first identifier includes a digital identifier. The data analysis device 20 also includes a pin uniformity judgment module 23. The pin uniformity judgment module 23 is used to compare the digital identifiers of adjacent test points in the feature area, or to obtain the minimum value of each digital identifier and compare the minimum value with a preset standard threshold. Based on the comparison result, the pin uniformity of the storage particle is judged, which effectively improves the intelligence and efficiency of data analysis. For example, you can control the display of "0" for test points with a pass rate greater than 0 and less than 10%; "1" for test points with a pass rate greater than or equal to 10% and less than 20%; "2" for test points with a pass rate greater than or equal to 20% and less than 30%; "3" for test points with a pass rate greater than or equal to 30% and less than 40%; "4" for test points with a pass rate greater than or equal to 40% and less than 50%; "5" for test points with a pass rate greater than or equal to 50% and less than 60%; "6" for test points with a pass rate greater than or equal to 60% and less than 70%; "7" for test points with a pass rate greater than or equal to 70% and less than 80%; "8" for test points with a pass rate greater than or equal to 80% and less than 90%; and "9" for test points with a pass rate greater than or equal to 90% and less than 100%. Obtain the difference between the digital identifiers of any adjacent test points in the feature region. If at least one of the differences is greater than or equal to a preset difference threshold, such as 4, the pin uniformity of the storage chip is determined to be poor; otherwise, the pin uniformity of the storage chip is determined to be good. Alternatively, obtain the minimum value of each digital identifier in the feature region. If the minimum value is greater than or equal to a preset standard threshold, such as 5, the pin uniformity of the storage chip is determined to be good; otherwise, the pin uniformity of the storage chip is determined to be poor.

[0100] As an example, each test point in the feature area is also marked with a second identifier for the corresponding pin, such as a name identifier, so that relevant staff can intuitively distinguish different pins, judge the differences in the characteristics of different pins of storage particles based on the differences in proportion in the feature area, and trace the root cause of the differences.

[0101] For example, please refer to Figure 15 The defect type judgment module 24 includes an edge defect judgment module 241, which comprises a standard pass-through area acquisition unit 2411, a coordinate axis acquisition unit 2412, and an edge defect judgment unit 2413. The standard pass-through area acquisition unit 2411 acquires the standard pass-through area of ​​the integrated SHMO map of the storage chip. The coordinate axis acquisition unit 2412 determines the axis of symmetry extending along the frequency scanning direction of the standard pass-through area as the first coordinate axis, and determines the axis of symmetry extending along the voltage scanning direction of the standard pass-through area, or the straight line containing the boundary line extending along the voltage scanning direction, as the second coordinate axis. The edge defect judgment unit 2413 acquires the intersection point of the boundary line of the feature area with the first coordinate axis, and acquires the distance value between the intersection point and the perpendicular point of the coordinate axis, where the perpendicular point is the point perpendicular to the first coordinate axis and the second coordinate axis. If the distance value is greater than or equal to a preset distance threshold, an edge defect is determined to exist. This embodiment intelligently determines whether an edge defect exists in the storage chip based on the integrated SHMO map of the storage chip.

[0102] As an example, please continue to refer to Figure 15 The data analysis device also includes a void defect judgment module 242, which is used to determine whether there is a test failure area within the pass area. A test failure area contains multiple consecutive test failure points. If so, it determines whether any test failure area includes at least two consecutive test failure points in the voltage scanning direction and at least two consecutive test failure points in the frequency scanning direction. If so, it determines that a void defect exists. This embodiment realizes intelligent determination of whether a memory chip has a void defect based on the integrated SHMO diagram of the memory chip.

[0103] As an example, please continue to refer to Figure 15 The data analysis device also includes a voltage linearity defect judgment module 243. This module 243 is used to determine whether a voltage linearity defect region exists in the integrated SHmoo plot. The voltage linearity defect region includes at least one voltage failure line extending along the frequency scanning direction and intersecting with two opposing boundary lines of the integrated SHmoo plot. Each test point located on the voltage failure line is a test failure point. If so, a voltage linearity defect is determined to exist. This embodiment intelligently determines whether a storage chip has a voltage linearity defect based on the integrated SHmoo plot of the storage chip.

[0104] As an example, please continue to refer to Figure 15 The data analysis device also includes a frequency linearity defect judgment module 244, which is used to determine whether a frequency linearity defect region exists in the integrated SHmoo plot. The frequency linearity defect region includes at least one frequency failure line extending along the voltage scan direction and intersecting with two opposite boundary lines of the integrated SHmoo plot. Each test point located on the frequency failure line is a test failure point; if so, a frequency linearity defect is determined to exist. This embodiment realizes intelligent determination of whether a memory chip has a frequency linearity defect based on the integrated SHmoo plot of the memory chip.

[0105] In one embodiment of this disclosure, a storage device is provided, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the program to implement the steps of the method described in any embodiment of this disclosure.

[0106] In one embodiment of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any embodiment of this disclosure.

[0107] Although Figure 1 , Figure 3 , Figure 5 and Figure 11 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the exact order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be executed in other sequences. Moreover, although Figure 1 , Figure 3 , Figure 5 and Figure 11 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0108] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Furthermore, any references to memory, storage, databases, or other media used in the embodiments provided in this disclosure can include non-volatile and / or volatile memory.

[0109] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0110] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A data analysis method, characterized in that, include: Obtain a single SHMO diagram of each pin of a single storage chip; An integrated shmoo map of the memory chip is constructed based on the individual shmoo maps of each pin. The integrated shmoo map includes partially overlapping feature regions and pass regions. The pass regions include common pass regions of each of the individual shmoo maps. The pass rate of the common pass regions for the test points is 100%. The pass rate of each test point in the feature regions is greater than 0 and less than 100%. Each test point of the integrated shmoo map is marked with a pass rate, which is used to characterize the proportion of the number of individual shmoo maps passing at the corresponding test point to the total number of individual shmoo maps of each pin of the single memory chip.

2. The data analysis method according to claim 1, characterized in that, The feature region has at least two first identifiers for representing the passage ratio, with different first identifiers representing different passage ratios.

3. The data analysis method according to claim 2, characterized in that, The first identifier includes a numerical identifier, and the method further includes the step of determining the pin uniformity of the storage particle: Obtain the difference between the digital identifiers of any adjacent test points in the feature region. If at least one of the differences is greater than or equal to a preset difference threshold, it is determined that the pin uniformity of the storage particle is poor. Conversely, if the pin uniformity of the storage particles is good, it is determined that the pin uniformity is good. or Obtain the minimum value of each of the aforementioned digital identifiers. If the minimum value is greater than or equal to a preset standard threshold, the pin uniformity of the storage particle is determined to be good; otherwise, the pin uniformity of the storage particle is determined to be poor.

4. The data analysis method according to any one of claims 1-3, characterized in that, Each test point in the feature area is also marked with a second identifier corresponding to the pin.

5. The data analysis method according to any one of claims 1-3, characterized in that, The method further includes the step of determining whether the storage particle has edge defects: Obtain the standard pass region of the integrated shmoo map of the storage particle, wherein the standard pass region is the pass region pre-stored in the mode register of the storage particle; The axis of symmetry extending along the frequency scanning direction of the region through which the standard passes is determined as the first coordinate axis, and the axis of symmetry extending along the voltage scanning direction of the region through which the standard passes, or the straight line containing the boundary line extending along the voltage scanning direction, is determined as the second coordinate axis. Obtain the intersection point of the boundary line of the feature region and the first coordinate axis, and obtain the distance value between the intersection point and the perpendicular point of the coordinate axis, wherein the perpendicular point of the coordinate axis is the point perpendicular to the first coordinate axis and the second coordinate axis; If the distance value is greater than or equal to a preset distance threshold, then an edge defect is determined to exist.

6. The data analysis method according to any one of claims 1-3, further comprising the step of determining whether the storage particle has void defects: Determine whether there is a test failure area within the passed area, wherein the test failure area contains multiple consecutive test failure points; If so, determine whether any of the aforementioned test failure areas includes at least two consecutive test failure points in the voltage scanning direction and at least two consecutive test failure points in the frequency scanning direction; If so, then it is determined that there is a void defect.

7. The data analysis method according to any one of claims 1-3, further comprising the step of determining whether the storage particle has a voltage linearity defect: Determine whether there is a voltage linearity defect region in the integrated shmoo diagram. The voltage linearity defect region includes at least one voltage failure line that extends along the frequency scanning direction and intersects with two opposite boundary lines of the integrated shmoo diagram. Each test point located on the voltage failure line is a test failure point. If so, then a voltage linearity defect is determined to exist.

8. The data analysis method according to any one of claims 1-3, further comprising the step of determining whether the storage particle has a frequency linearity defect: Determine whether there is a frequency linearity defect region in the integrated shmoo diagram. The frequency linearity defect region includes at least one frequency failure line that extends along the voltage scanning direction and intersects with two opposite boundary lines of the integrated shmoo diagram. Each test point located on the frequency failure line is a test failure point. If so, then a frequency linearity defect is determined to exist.

9. A data analysis method, characterized in that, include: Obtain a single shmoo graph of any storage particle from multiple storage particles; An integrated shmoo map of the memory is constructed based on the individual shmoo maps of each of the aforementioned memory chips. The integrated shmoo map includes partially overlapping feature regions and pass regions. The pass regions include common pass regions of each of the individual shmoo maps. The pass rate of the test points in the common pass regions is 100%. The pass rate of each test point in the feature regions is greater than 0 and less than 100%. Each test point in the integrated shmoo map is marked with a third identifier, which is used to characterize the encoding of the memory chip that passes at the corresponding test point.

10. A data analysis device, characterized in that, include: The single shmoo image acquisition module is used to acquire the single shmoo image of each pin of a single storage chip; An integrated shmoo map construction module is used to construct an integrated shmoo map of the storage chip based on the individual shmoo maps of each pin. The integrated shmoo map includes partially overlapping feature regions and passing regions. The passing regions include common passing regions of each of the individual shmoo maps. The pass rate of the common passing regions for the test points is 100%. The pass rate of each test point in the feature regions is greater than 0 and less than 100%. Each test point of the integrated shmoo map is marked with a pass rate, which is used to characterize the proportion of the number of individual shmoo maps passing at the corresponding test point to the total number of individual shmoo maps of each pin of the single storage chip.

11. The data analysis apparatus according to claim 10, characterized in that, The feature region has at least two first identifiers for representing the passage ratio, with different first identifiers representing different passage ratios.

12. The data analysis apparatus according to claim 11, characterized in that, The first identifier includes a numerical identifier, and the device further includes: The pin uniformity judgment module is used to compare the digital identifiers of adjacent test points in the feature region, or to obtain the minimum value of each digital identifier and compare the minimum value with a preset standard threshold, and to judge the pin uniformity of the storage particle based on the comparison result.

13. The data analysis device according to claim 12, characterized in that, Each test point in the feature area is also marked with a second identifier corresponding to the pin.

14. The data analysis apparatus according to any one of claims 10-13, characterized in that, The device further includes: The standard pass region acquisition unit is used to acquire the standard pass region of the integrated shmoo map of the storage particle, wherein the standard pass region is a pass region pre-stored in the mode register of the storage particle; The coordinate axis acquisition unit is used to determine the axis of symmetry of the standard passing through the region along the frequency scanning direction as the first coordinate axis, and to determine the axis of symmetry of the standard passing through the region along the voltage scanning direction or the straight line containing the boundary line along the voltage scanning direction as the second coordinate axis. An edge defect determination unit is used to obtain the intersection point of the boundary line of the feature region and the first coordinate axis, and to obtain the distance value between the intersection point and the perpendicular point of the coordinate axis, wherein the perpendicular point of the coordinate axis is the perpendicular point of the first coordinate axis and the second coordinate axis; and if the distance value is greater than or equal to a preset distance threshold, it is determined that an edge defect exists.

15. The data analysis apparatus according to any one of claims 11-13, characterized in that, The device further includes: A void defect detection module is used to determine whether there is a test failure area within the passed area, wherein the test failure area contains multiple consecutive test failure points; if so, it determines whether any of the test failure areas includes at least two consecutive test failure points in the voltage scanning direction and at least two consecutive test failure points in the frequency scanning direction; if so, it determines that a void defect exists.

16. The data analysis apparatus according to any one of claims 11-13, characterized in that, The device further includes: The voltage linearity defect judgment module is used to determine whether there is a voltage linearity defect region in the integrated shmoo diagram. The voltage linearity defect region includes at least one voltage failure line that extends along the frequency scanning direction and intersects with two opposite boundary lines of the integrated shmoo diagram. Each test point located on the voltage failure line is a test failure point. If so, it is determined that there is a voltage linearity defect.

17. The data analysis apparatus according to any one of claims 11-13, characterized in that, The device further includes: The frequency linearity defect judgment module is used to determine whether there is a frequency linearity defect region in the integrated shmoo diagram. The frequency linearity defect region includes at least one frequency failure line that extends along the voltage scanning direction and intersects with two opposite boundary lines of the integrated shmoo diagram. Each test point located on the frequency failure line is a test failure point. If so, it is determined that there is a frequency linearity defect.

18. A storage device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1-9.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-9.

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