Boundary scan chain self-test logic circuit and self-test method

Abstract

The application discloses a boundary scan chain self-detection logic circuit and a self-detection method, which comprises a boundary scan controller and a scan chain composed of DUMMY cards in cascade; the application can perform self-detection on the complete boundary scan chain through the IO of the controller once; when the complete boundary scan chain is tested to be faulty, in order to accurately locate the fault point, the method of gradually increasing the length of the boundary scan chain is adopted to perform the fault self-detection on the JTAG connector circuit and the DUMMY card step by step and eliminate the faults, and finally the fault self-detection on the JTAG connector circuit and the DUMMY card of the whole chain is completed, and the reliability is high; after the self-detection is completed, the boundary scan test state of the to-be-tested board is entered; in the case that the boundary scan chain is not faulty, in order to save time, the self-detection can be skipped after the complete boundary scan chain is turned on, and the normal boundary scan test state of the to-be-tested board is directly entered.

Description

Technical Field

[0001] This invention relates to the technical field of boundary scan test fixtures, specifically to a boundary scan chain self-testing logic circuit and self-testing method. Background Technology

[0002] In the field of boundary scan test fixtures, a boundary scan chain is typically connected to a set of JTAG interfaces on the controller. A boundary scan chain consists of multiple dummy cards cascaded via JTAG connectors. On the one hand, because the JTAG connectors and pins of the board under test (DUT) need to connect to many dummy cards for boundary scan testing, and the controller's JTAG interfaces are limited, boundary scan chains are often quite long. On the other hand, by assembling multiple dummy cards into a boundary scan chain, multiple data entries can be continuously sent to the boundary scan chain's data register via a single JTAG interface on the controller, according to the boundary scan protocol, reducing JTAG switching time and improving testing efficiency. In practical testing applications, because boundary scan chains are often long, possibly consisting of a dozen or even dozens of cascaded dummy cards, if a fault occurs in the dummy card JTAG chain, and the location of the fault on the chain cannot be quickly located and resolved, it causes significant trouble for customers in on-site fault detection, wastes a lot of troubleshooting time, and affects the operational efficiency of the automated boundary scan fixture.

[0003] There are two main types of faults in the boundary scan chain. One is a circuit fault in the external JTAG connector of the DUMMY card. When the DUMMY card of the automated fixture is continuously plugged and pulled into the board under test for a long time, the JTAG connector may become loose or the wire may be pulled, leading to malfunctions. If this can be quickly located and eliminated in time, it will facilitate troubleshooting and improve production efficiency. The other type is a DUMMY card fault. When the DUMMY card on the boundary scan chain is continuously subjected to boundary scan automated testing for a long time, the logic devices or boundary scan chips inside the DUMMY card may be faulty or damaged. If the faulty DUMMY card can be accurately located, a new DUMMY card can be replaced with a new one in time to ensure the continuity of production. The replaced faulty card can be repaired in time for backup, reducing troubleshooting costs and improving production efficiency.

[0004] For self-detection of external JTAG connector circuit faults, existing methods include connecting the JTAG signal lines of each DUMMY card in parallel and then connecting them to the controller for testing. This method requires a lot of wiring and wiring space, and the DUMMY cards of the fixture need to be connected to the boundary scan test board by plugging and unplugging. The wiring is prone to disturbance, making implementation difficult and reliability low.

[0005] For DUMMY card fault self-detection, existing methods include sequentially connecting the boundary scan chip inside each DUMMY card to the boundary scan chain once, while shorting the TDI and TDO of the remaining DUMMY cards for physical pass-through testing. However, this method has limitations. It can only detect whether a connected DUMMY card is faulty when the external JTAG connector line is normal. When the JTAG connector line is faulty, the boundary scan chain is interrupted, and the boundary scan test for the entire chain cannot be performed normally. Therefore, it is impossible to locate whether the JTAG connector line or the DUMMY card is faulty. Therefore, there is an urgent need to propose a boundary scan chain self-detection logic circuit and self-detection method to solve the above technical problems. Summary of the Invention

[0006] To address the limitations of existing methods, such as sequentially connecting the boundary scan chip inside each DUMMY card to the boundary scan chain and shorting the TDI and TDO of the remaining DUMMY cards for physical pass-through testing, this method has its limitations. It can only detect whether the connected DUMMY card is faulty when the external JTAG connector line is normal. When the JTAG connector line is faulty, the boundary scan chain is not connected, and the boundary scan test of the entire chain cannot be performed normally. It cannot locate whether the JTAG connector line is faulty or whether the DUMMY card is faulty. This invention provides a boundary scan chain self-testing logic circuit and self-testing method.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: This invention provides a boundary scan chain self-detection logic circuit, comprising a boundary scan controller and a scan chain composed of several cascaded DUMMY cards; The DUMMY card includes a first JTAG connector, a second JTAG connector, a first D flip-flop, a second D flip-flop, a first analog switch, a second analog switch, a third analog switch, a boundary scan chip, an inductor L1, an inductor L2, a resistor R1, and an inverter. The boundary scan controller is provided with control IO pins IO_0, IO_1, and IO_2.1; the boundary scan controller is also provided with JTAG signal pins TCK, TMS, TDI_IN1, and TDO. The IO_0 pin on the boundary scan controller is connected to the second JTAG connector via the first JTAG connector, and is also connected to the preset inputs of the first and second D flip-flops. Pin; the IO_1 pin on the boundary scan controller is connected to the second JTAG connector via the first JTAG connector, and is also connected to the clear input of the first D flip-flop and the second D flip-flop. pins; The IO_2.1 pin on the boundary scan controller is connected to the level input D of the first D flip-flop and one end of the inductor L1 via the first JTAG connector. The other end of the inductor L1 is connected to the clock input CP of the first D flip-flop. Additionally, the IO_2.1 pin is also connected to the input of an inverter and the fixed pin A of the third analog switch. Furthermore, the input of the inverter is pulled down by a resistor R1, and the output of the inverter is connected to the level input D of the second D flip-flop and one end of the inductor L2. The other end of the inductor L2 is connected to the clock input CP of the second D flip-flop. The output Q of the first D flip-flop is connected to the switch control pin S of the first analog switch and also to the switch control pin S of the second analog switch. The output Q of the second D flip-flop is connected to the switch control pin S of the third analog switch. The TDI_IN1 pin of the boundary scan controller is connected to the gating pin B0 of the first analog switch via the first JTAG connector and also to the data input TDI_1 of the boundary scan chip. The fixed input A of the first analog switch is connected to the data output line TDO, and returns to the boundary scan controller through the first JTAG connector; the JTAG clock signal TCK and the JTAG status signal TMS are connected to the clock signal TCK and status signal TMS pins of the boundary scan chip, respectively; the data output TDO_1 of the boundary scan chip is connected to the fixed pin of the second analog switch, and the gating pin B1 of the second analog switch is connected to the second JTAG connector; the output pin B1 of the third analog switch is connected to the second JTAG connector.

[0008] In a preferred embodiment of the present invention, all components of the plurality of DUMMY cards are identical except for the boundary scan chip.

[0009] As a preferred embodiment of the present invention, the first D flip-flops in the plurality of DUMMY cards are named sequentially as D flip-flop 1.1, D flip-flop 2.1, ..., D flip-flop n.1 according to the chain order; The second D flip-flops in several of the DUMMY cards are named D flip-flop 1.2, D flip-flop 2.2, ... D flip-flop n.2 in the order of the chain.

[0010] As a preferred embodiment of the present invention, the first analog switches in the plurality of DUMMY cards are named in the order of the chain as analog switch 1.1, D flip-flop 2.1, ..., D flip-flop 3.1; The second analog switches in several of the aforementioned DUMMY cards are named sequentially in chain order: Analog Switch 1.2, D Flip-Flop 2.2, ..., D Flip-Flop 3.2; The third analog switches in several DUMMY cards are named analog switch 1.3, D flip-flop 2.3, ... D flip-flop 3.3 in a chain order. Following this numbering method, the first JTAG connector, second JTAG connector, boundary scan chip, inductor L1, inductor L2, resistor R1 and inverter in several DUMMY cards are labeled.

[0011] As a preferred technical solution of the present invention, a self-testing method for a boundary scan chain self-testing logic circuit is provided to perform a complete boundary scan test. The boundary scan controller first controls IO_0 to output a low level and IO_1 to output a high level. At this time, D flip-flops 1.1 to D flip-flop n.1 and D flip-flop 1.2 to D flip-flop n.2 output a high level, and the fixed pins A of analog switches 1.1 to analog switch n.1 and analog switches 1.2 to analog switch n.2 are all connected to B1. At this time, analog switches 1.1 to analog switch n.1 are all disconnected in the boundary scan logic circuit. The boundary scan chips 1.1 to boundary scan chips n.1 of the first DUMMY card to the nth DUMMY card are all connected to form a complete boundary scan chain. Boundary scan self-test is performed on this complete chain. Specifically, The boundary scan controller first sends the complete link IDCODE command, then sends 32*n bits of DR data to TDI_IN. If the 32*n bits of IDCODE data are correctly output, it indicates a link failure.

[0012] As a preferred technical solution of the present invention, a step-by-step self-test of the boundary scan chain is performed; The boundary scan controller first controls IO_0 to output a high level and IO_1 to output a low level. At this time, D flip-flops 1.1 to D flip-flop n.1 and D flip-flop 1.2 to D flip-flop n.2 output a low level, and the fixed pin A of analog switches 1.1 to analog switch n.1 and analog switches 1.2 to analog switch n.2 are all connected to B0. At this time, analog switches 1.1 to analog switch n.1 are all connected in the boundary scan logic circuit, and the boundary scan chips 1.1 to nth boundary scan chip n.1 of this DUMMY card 1.1 to the nth boundary scan chip n.1 are all disconnected in the chain. At this time, the boundary scan link is connected one by one, completing the step-by-step self-test, as shown in the following figure. With IO_0 output high and IO_1 output low, analog switches 1.2 to n.2 are all disconnected to prevent the outputs of TDO_1 to TDO_n from boundary scan chips 1.1 to n.1 from interfering with the return path TDO. A and B0 of analog switch 1.1 are connected, forming a straight path from TDI_IN1 of JTAG connector 1.1 to analog switch 1.1 and then to TDO of JTAG connector 1.1. During boundary scan, as long as the JTAG clock signal and the status signal TMS are activated, the boundary scan chips TDO_1 to TDO_n may output data. Therefore, the boundary scan chips 1.1 to n.1 are disconnected through analog switches 1.2 to n.2 to ensure the reliability of the pass-through path test. A self-test was performed on this pass-through path. Following the JTAG state machine protocol, under the influence of the JTAG clock signal and TMS signal, the controller sent a string of data to TDI_IN1. This string of data could not be all zeros or all ones. Since it's a pass-through path, there was no fixed bit length requirement; sending more bits was acceptable, for example, sending 0101010101. If the TDO of the JTAG return path detected this string of data as 0101010101, it indicated that the wiring between the boundary scan controller and the JTAG connector 1.1 of the DUMMY card 1 was fault-free. If an error was detected, it indicated that the connection between the boundary scan controller and the DUMMY card 1 was fault-free. The wiring of JTAG connector 1.1 on card 1.1 may be faulty. In this case, stop the test and check the wiring between the boundary scan controller and the JTAG connector 1.1 on the DUMMY card 1.1. Check the 3 control IOs and the 4 signal lines of JTAG. After troubleshooting, run the previous test. If the test still fails, it indicates that the DUMMY card 1.1 is faulty. The cause of the fault may be that analog switch 1.1 or analog switch 1.2 is not controlled, or the boundary scan chip 1.1 is damaged. Replace the faulty DUMMY card 1.1 with a DUMMY card that has passed offline testing. The faulty DUMMY card 1.1 should be repaired offline for backup. After the test is successful or the fault is resolved, output IO_2.1 low, then output IO_0 and IO_1 high. The D flip-flop 1.1 will then stably enter the ready-to-trigger state. When IO_2.1 changes from a low level to a high level, the output Q of D flip-flop 1.1 changes from 0 to 1. Analog switches 1.1 and 1.2 of DUMMY card 1.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 1.1 is disconnected from DUMMY card 1.1, and analog switch 1.2 is connected from DUMMY card 1.1. In addition, analog switch 2.1 of DUMMY card 2.1 is connected in the boundary scan chain. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then back to analog switch 2.1, and then back to JTAG connector 2.1 to access the return path TDO, forming a boundary scan single chain connected to boundary scan chip 1.1. To perform a self-test on the boundary scan single chain, the boundary scan controller first sends the IDCODE instruction of the boundary scan chip 1.1 to TDI_IN1, and then arbitrarily sends 32-bit DR data to TDI_IN1. If the 32-bit IDCODE data is correctly shifted and output under the action of the data being sent, it indicates that the link is fault-free. If the 32-bit IDCODE data is not correctly output, it indicates that the link is faulty. There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 1.1 and DUMMY card 1.2; it could be that analog switch 1.1 or analog switch 1.2 of DUMMY card 1.1 is out of control or the boundary scan chip 1.1 is damaged; or it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged. First, rule out a line fault between JTAG connectors 1.2 and 2.1 between DUMMY cards 1.1 and 2.1. Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates that the previous fault was a JTAG line fault and the fault has been cleared. If the IDCODE is not correctly ejected, it indicates that the fault still exists, and at least one of DUMMY cards 1.1 and 1.2 is faulty. Replace DUMMY card 1.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates that the original DUMMY card 1.1 was faulty and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 2.1 with a DUMMY card that has passed offline testing. If the IDCODE data is correctly ejected, it indicates that the original DUMMY card 2.1 was faulty and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use. Next, IO_2.1 transitions from high to low. At this time, under the opposite effect of the inverter 1.1, the trigger input of D flip-flop 1.2 transitions from low to high, causing the output D of D flip-flop 1.2 to transition from low to high. Simultaneously, the fixed pin A of analog switch 1.3 is connected to the strobe pin B1. The low level of IO_2.1 passes through analog switch 1.3 and then through JTAG connector 1.2 to the input signal IO_2.2 of the JTAG connector 2.1 of DUMMY card 2.1. The pull-down resistor R2 at the input of inverter 2.1 of DUMMY card 2.1 ensures that the output of inverter 2.1 is high by default, thus preventing false triggering of D flip-flop 2.2 when the low-level signal of IO_2.1 of DUMMY card 1.1 is transmitted to the input signal IO_2.2 of DUMMY card 2.1. Next, since the fixed pin A of analog switch 1.3 is connected to the strobe pin B1, when the boundary scan controller controls IO_2.1 to change its output from low to high, IO_2.2 also changes from low to high. At this time, the output Q of D flip-flop 2.1 changes from 0 to 1. The analog switches 2.1 and 2.2 of DUMMY card 2.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 2.1 is disconnected from the DUMMY card, and analog switch 2.2 is disconnected from the DUMMY card. The MMY card is connected, and the analog switch 3.1 of the DUMMY card 3.1 is connected in the boundary scan link. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then to boundary scan chip 2.1, then to analog switch 2.2, then to JTAG connector 2.2, then to JTAG connector 3.1, then to analog switch 3.1, and then back to JTAG connector 3.1 to access the return path TDO, forming a boundary scan dual chain that accesses boundary scan chip 1.1 and boundary scan chip 2.1; To perform a self-test on the boundary scan dual-link, the boundary scan controller first sends the IDCODE instruction of the combination of boundary scan chip 1.1 and boundary scan chip 2.1, and then sends arbitrarily 32*2 bits of data. If the 32*2 bits of IDCODE data are correctly shifted and output under the action of the data being sent, it indicates that the link is fault-free. If the 32*2 bits of IDCODE data are not correctly output, it indicates that the link is faulty. There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 2.1 and DUMMY card 3.1; it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged; or it could be that analog switch 3.1 or analog switch 3.2 of DUMMY card 3.1 is out of control or the boundary scan chip 3.1 is damaged. First, rule out a line fault between JTAG connectors 2.2 and 3.1 (DUMMY cards 2.1 and 3.1). Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates a line fault between JTAG connectors 2.2 and 3.1, and the fault has been cleared. If the IDCODE is not correctly ejected, the fault persists, and at least one of DUMMY cards 2.1 or 3.1 is faulty. Replace DUMMY card 2.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates the original DUMMY card 2.1 was faulty, and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 3.1 with a DUMMY card that has passed offline testing. If the IDCODE is correctly ejected, it indicates the original DUMMY card 3.1 was faulty, and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use. Next, IO_2.1 is connected to IO_2.3 to complete the step-by-step transmission of the self-test signal, completing the fault test between DUMMY card 3 and DUMMY card 4.1; By analogy, the self-test of the n DUMMY cards in the complete boundary scan chain is completed. Once the self-test is complete, the boundary scan chips 1.1 to n.1 of DUMMY card 1.1 to n.1 form a complete chain and enter the boundary scan test state of the normal test board.

[0013] The pull-down resistors R1 to Rn of inverters 1.1 to n.1 ensure that the outputs of inverters 1.1 to n.1 are high by default, thereby preventing false triggering caused by the arrival of a low-level signal from the previous stage.

[0014] The beneficial effects of this invention are: This boundary scan chain self-testing logic circuit and method simultaneously possesses the ability to self-detect faults in the wiring between external JTAG connectors and in the DUMMY card. It can quickly locate faults in the wiring between JTAG connectors and in the DUMMY card, making it easy to implement and facilitating timely troubleshooting during field maintenance, reducing troubleshooting costs and improving boundary scan testing efficiency. Furthermore, this invention considers the consistency of the two JTAG connectors preceding and following each DUMMY card, ensuring that different DUMMY cards can be arbitrarily and flexibly arranged to form a boundary scan chain. It also ensures that the cascading relationship of each DUMMY card is synchronized with the cascading relationship of the JTAG signals, enabling implementation according to the JTAG connector cascading method. This invention adds only 3 IO control pins to the existing JTAG connectors without increasing the number of JTAG connectors on the DUMMY card. It can perform self-testing by connecting the entire boundary scan chain at once via the controller's IO. When the complete boundary scan chain test fails, to accurately locate the fault point, the fault self-testing of the JTAG connector lines and DUMMY card is performed step by step by gradually increasing the length of the boundary scan chain, ultimately completing the self-testing of the entire chain's JTAG connector lines and DUMMY card, resulting in high reliability. After self-testing, it enters the boundary scan test state of the board under test. If the boundary scan chain is functioning correctly, to save time, after connecting the complete boundary scan chain, the self-testing can be skipped, and the board under test can directly enter the normal boundary scan test state. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a partial structural schematic diagram of a boundary scan chain self-detection logic circuit and self-detection method according to the present invention; Figure 2 This is a schematic diagram of the overall structure of a boundary scan chain self-detection logic circuit and self-detection method according to the present invention; Figure 3 This is a simplified circuit diagram of a boundary scan chain self-detection logic circuit and self-detection method according to the present invention; Figure 4 This is a schematic diagram of the signal transmission of a boundary scan chain self-detection logic circuit and self-detection method according to the present invention; Figure 5 This invention relates to a D flip-flop logic state table for a boundary scan chain self-detection logic circuit and self-detection method.

[0016] In the diagram: 1. Boundary scan controller; 2. DUMMY card; 3. First JTAG connector; 4. Second JTAG connector; 5. First D flip-flop; 6. Second D flip-flop; 7. First analog switch; 8. Second analog switch; 9. Third analog switch; 10. Boundary scan chip; 12. Inverter. Detailed Implementation

[0017] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0018] Example: Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, the present invention provides a boundary scan chain self-detection logic circuit, including a boundary scan controller 1 and a scan chain composed of several cascaded DUMMY cards 2; The DUMMY card 2 includes a first JTAG connector 3, a second JTAG connector 4, a first D flip-flop 5, a second D flip-flop 6, a first analog switch 7, a second analog switch 8, a third analog switch 9, a boundary scan chip 10, an inductor L1, an inductor L2, a resistor R1, and an inverter 12. The boundary scan controller 1 is provided with control IO pins IO_0, IO_1, and IO_2.1; the boundary scan controller 1 is also provided with JTAG signal pins TCK, TMS, TDI_IN1, and TDO; The IO_0 pin on the boundary scan controller 1 is connected to the second JTAG connector 4 via the first JTAG connector 3, and is also connected to the preset inputs of the first D flip-flop 5 and the second D flip-flop 6. Pin; the IO_1 pin on the boundary scan controller 1 is connected to the second JTAG connector 4 via the first JTAG connector 3, and is also connected to the clear input of the first D flip-flop 5 and the second D flip-flop 6. pins; The IO_2.1 pin on the boundary scan controller 1 is connected to the level input D of the first D flip-flop 5 and one end of the inductor L1 via the first JTAG connector 3. The other end of the inductor L1 is connected to the clock input CP of the first D flip-flop 5. Additionally, the IO_2.1 pin is also connected to the input of the inverter 12 and the fixed pin A of the third analog switch 9. Furthermore, the input of the inverter 12 is pulled down by the resistor R1, and the output of the inverter 12 is connected to the level input D of the second D flip-flop 6 and one end of the inductor L2. The other end of the inductor L2 is connected to the clock input CP of the second D flip-flop 6. The output Q of the first D flip-flop 5 is connected to the switch control pin S of the first analog switch 7 and also to the switch control pin S of the second analog switch 8. The output Q of the second D flip-flop 6 is connected to the switch control pin S of the third analog switch 9. The TDI_IN1 pin of the boundary scan controller 1 is connected to the gating pin B0 of the first analog switch 7 via the first JTAG connector 3 and also to the data input TDI_1 of the boundary scan chip 10. The fixed input A of the first analog switch 7 is connected to the data output line TDO, and returns to the boundary scan controller 1 through the first JTAG connector 3; the JTAG clock signal TCK and the JTAG status signal TMS are respectively connected to the clock signal TCK and status signal TMS pins of the boundary scan chip 10; the data output TDO_1 of the boundary scan chip 10 is connected to the fixed pin of the second analog switch 8, and the gating pin B1 of the second analog switch 8 is connected to the second JTAG connector 4; the output pin B1 of the third analog switch 9 is connected to the second JTAG connector 4.

[0019] A standard D flip-flop has an initial output setting pin and a preset input pin. and clear input These two pins have higher priority than the clock input CP of the D flip-flop. When Low level, When the voltage level is high, the D flip-flop outputs Q as high; when... High level When the voltage level is low, the D flip-flop outputs Q as low; when... High level When S is low, the trigger-ready mode is enabled. At this time, the rising edge of the clock input will change the output state. Inductors L1.1 and L1.2 are suitable inductors. Their purpose is to make the rising edge of CP lag behind the level input D when the level input D of the D flip-flop changes from low to high in the trigger-ready mode, thereby completing the change of the level output Q from 0 to 1. Analog switches 1.1, 1.2, and 1.3 are the same analog switches. When S is low, A and B0 are connected. When S is high, A and B1 are connected.

[0020] Consider the contents of n DUMMY cards, including: The self-test logic circuits of DUMMY cards 1.1 to n.1 are connected in series to form a boundary scan self-test chain. Except for the boundary scan chip, the self-test logic circuits of DUMMY cards 2.1 to n.1 are the same as those of DUMMY card 1.1. The control I / O lines of the boundary scan controller, including IO_0 and IO_1, and the JTAG signal lines of the boundary scan controller, including TCK, TMS, and TDO, run through the entire self-test chain and are connected in series through the JTAG connectors of DUMMY cards 1 to n. The signal TDI_IN1 of DUMMY card 1.1 is named accordingly, and the signal of DUMMY cards 2.1 to n.1 is named according to the chain sequence. The signals are sequentially named TDI_IN2, TDI_IN3, ..., TDI_INn; following the naming convention of IO_2.1 in DUMMY card 1.1, the signals from DUMMY card 2.1 to DUMMY card n.1 are named IO_2.2, IO_2.3, ..., IO_2.n in chain order; following the naming convention of TDI_1 and TDO_1 in DUMMY card 1.1, the signals from DUMMY card 2.1 to DUMMY card n.1 are named TDI_2 and TDO_2, TDI_3 and TDO_3, ..., TDI_n and TDO_n in chain order; following the naming convention of inverter 1.1 in DUMMY card 1.1, the signals from DUMMY card 2.1 to DUMMY card n.1 are named TDI_2 and TDO_2, TDI_3 and TDO_3, ..., TDI_n and TDO_n in chain order; following the naming convention of inverter 1.1 in DUMMY card 1.1, the signals from DUMMY card 2.1 to DUMMY card n.1 are named TDI_IN2, TDI_IN3, ..., TDI_INn in chain order; following the naming convention of inverter 1.1 in DUMMY card 1.1, the signals from DUMMY card 2.1 to DUMMY card n.1 are named TDI_IN2, TDI_IN3, ..., TDI_INn in chain order. The component in card n.1 is named inverter 2.1, inverter 3.1, ... inverter n.1 in chain order; referring to the naming of resistor R1 in DUMMY card 1.1, the component in DUMMY cards 2.1 to n.1 is named R2, R3, ... Rn in chain order; referring to the naming of inductors L1.1 and L1.2 in DUMMY card 1.1, the component in DUMMY cards 2.1 to n.1 is named L2.1 and L2.2, L3.1 and L3.2, ... Ln.1 and Ln.2 in chain order; referring to the naming of inductors L1.1 and L1.2 in DUMMY card 1.1, the component in DUMMY cards 2.1 to n.1 is named L2.1 and L2.2, L3.1 and L3.2, ... Ln.1 and Ln.2 in chain order; referring to the naming of inductors L1.1 and L1.2 in DUMMY card 1.1, the component in DUMMY cards 2.1 to n.1... The components are named L2.1 and L2.2, L3.1 and L3.2, ..., Ln.1 and Ln.2 in chain order; referring to the naming of D flip-flops 1.1 and 1.2 of DUMMY card 1, the components of DUMMY cards 2.1 to n.1 are named D flip-flops 2.1 and 2.2, 3.1 and 3.2, ..., n.1 and n.2 in chain order; referring to the naming of analog switches 1.1 to 1.3 of DUMMY card 1.1, the components of DUMMY cards 2.1 to n.1 are named analog switches 2.1 to 2.3, and analog switch 3 in chain order.Analog switches 1 through 3.3, ..., analog switches n.1 through n.3; referring to the naming of boundary scan chip 1.1, the components of DUMMY cards 2.1 through n.1 are named sequentially as boundary scan chip 2.1, boundary scan chip 3.1, ..., boundary scan chip n.1; referring to the naming of connectors 1.1 and 1.2 of DUMMY card 1.1, the components of DUMMY cards 2.1 through n.1 are named sequentially as connectors 2.1 and 2.2, connectors 3.1 and 3.2, ..., connectors n.1 and n.2. The boundary scan controller mates with connector 1.1 of DUMMY card 1.1; connector 1.2 of DUMMY card 1.1 mates with connector 2.1 of DUMMY card 2.1; connector 2.2 of DUMMY card 2.1 mates with connector 3.1 of DUMMY card 3.1, and so on. Finally, connector (n-1).2 of DUMMY card (n-1).1 mates with connector n.1 of DUMMY card n.1; the B1 output of analog switch n.2 of DUMMY card n.1 is connected to the JTAG signal output TDO through connector n.2; the above is the connection relationship of the boundary scan chain self-detection logic circuit of this invention. The matching resistors or signal driving or enhancement between JTAG signals of each DUMMY card in this invention are relatively flexible and conventional, and only the content related to the self-testing logic circuit and self-testing method of this invention is provided. There are no restrictions on the design of the logic circuit of this invention. For example, an analog switch can be replaced by a suitable relay with a driver, and an inductor can be replaced by a delay device or circuit. As long as the self-detection logic and method are the same, they are all within the protection scope of this invention.

[0021] A self-testing method for a boundary scan chain self-testing logic circuit includes complete boundary scan chain testing and boundary scan chain step-by-step self-testing; Full Boundary Scan Chain Test Boundary scan controller 1 first controls IO_0 to output a low level and IO_1 to output a high level. At this time, D flip-flops 1.1 to D flip-flop n.1 and D flip-flop 1.2 to D flip-flop n.2 output a high level, and the fixed pins A of analog switches 1.1 to analog switch n.1 and analog switches 1.2 to analog switch n.2 are all connected to B1. At this time, analog switches 1.1 to analog switch n.1 are all disconnected in the boundary scan logic circuit. The boundary scan chips 1.1 to boundary scan chips n.1 of the first DUMMY card to the nth DUMMY card are all connected to form a complete boundary scan chain. Boundary scan self-test is performed on this complete chain. Specifically, The boundary scan controller first sends the complete link IDCODE instruction, and then sends 32*n bits of DR data to TDI_IN. If the 32*n bits of IDCODE data are correctly output, it indicates that the link is fault-free. If the 32*n bits of IDCODE data are not correctly output, it indicates that the link is faulty. The above tests show complete link faults, but cannot pinpoint the exact location of external connector line faults or DUMMY card faults. Therefore, a step-by-step self-test of the boundary scan chain is required.

[0022] Boundary scan controller 1 first controls IO_0 to output a high level and IO_1 to output a low level. At this time, D flip-flops 1.1 to D flip-flop n.1 and D flip-flop 1.2 to D flip-flop n.2 output a low level, and the fixed pin A of analog switches 1.1 to analog switch n.1 and analog switches 1.2 to analog switch n.2 are all connected to B0. At this time, analog switches 1.1 to analog switch n.1 are all connected in the boundary scan logic circuit, and the boundary scan chips 1.1 to nth boundary scan chip n.1 of this DUMMY card 1.1 to the nth boundary scan chip n.1 are all disconnected in the chain. At this time, the DUMMY cards are connected to the boundary scan link one by one to complete the step-by-step self-test, as shown in the following figure. With IO_0 output high and IO_1 output low, analog switches 1.2 to n.2 are all disconnected to prevent the outputs of TDO_1 to TDO_n from boundary scan chips 1.1 to n.1 from interfering with the return path TDO. A and B0 of analog switch 1.1 are connected, forming a straight path from TDI_IN1 of JTAG connector 1.1 to analog switch 1.1 and then to TDO of JTAG connector 1.1. During boundary scan, as long as the JTAG clock signal and the status signal TMS are activated, the boundary scan chips TDO_1 to TDO_n may output data. Therefore, the boundary scan chips 1.1 to n.1 are disconnected through analog switches 1.2 to n.2 to ensure the reliability of the pass-through path test. A self-test was performed on this pass-through path. The test method followed the JTAG state machine protocol. Under the influence of the JTAG clock signal and the TMS signal, the controller sent a string of data to TDI_IN1. This string of data could not be all 0s or all 1s. Since it was a pass-through path, there was no fixed bit length requirement; sending more bits was acceptable, for example, sending 0101010101. If the TDO of the JTAG return path detected the data string as 0101010101, it indicated that the wiring between the boundary scan controller and the JTAG connector 1.1 of the DUMMY card 1.1 was fault-free. If an error was detected, it indicated that the connection between the boundary scan controller and the DUMM... The wiring of JTAG connector 1.1 on the Y card 1.1 may be faulty. In this case, stop the test and check the wiring between the boundary scan controller and the JTAG connector 1.1 on the DUMMY card 1.1. Check the three control I / Os and the four JTAG signal lines. After troubleshooting, run the previous test. If the test still fails, it indicates that the DUMMY card 1.1 is faulty. The cause of the fault may be that analog switch 1.1 or analog switch 1.2 is not controlled, or the boundary scan chip 1.1 is damaged. Replace the faulty DUMMY card 1.1 with a DUMMY card that has passed offline testing. The faulty DUMMY card 1.1 should be repaired offline for backup. After the test is successful or the fault is resolved, output IO_2.1 low, then output IO_0 and IO_1 high. The D flip-flop 1.1 will then stably enter the ready-to-trigger state. When IO_2.1 changes from a low level to a high level, the output Q of D flip-flop 1.1 changes from 0 to 1. Analog switches 1.1 and 1.2 of DUMMY card 1.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 1.1 is disconnected from DUMMY card 1.1, and analog switch 1.2 is connected from DUMMY card 1.1. In addition, analog switch 2.1 of DUMMY card 2.1 is connected in the boundary scan chain. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then back to analog switch 2.1, and then back to JTAG connector 2.1 to access the return path TDO, forming a boundary scan single chain connected to boundary scan chip 1.1. To perform a self-test on the boundary scan single chain, the boundary scan controller first sends the IDCODE instruction of the boundary scan chip 1 to TDI_IN1, and then arbitrarily sends 32-bit DR data to TDI_IN1. If the 32-bit IDCODE data is correctly shifted and output under the action of the data being sent, it indicates that the link is fault-free. If the 32-bit IDCODE data is not correctly output, it indicates that the link is faulty. There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 1.1 and DUMMY card 1.2; it could be that analog switch 1.1 or analog switch 1.2 of DUMMY card 1.1 is out of control or the boundary scan chip 1.1 is damaged; or it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged. First, rule out a line fault between JTAG connectors 1.2 and 2.1 between DUMMY cards 1.1 and 2.1. Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates that the previous fault was a JTAG line fault and the fault has been cleared. If the IDCODE is not correctly ejected, it indicates that the fault still exists, and at least one of DUMMY cards 1.1 and 1.2 is faulty. Replace DUMMY card 1.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates that the original DUMMY card 1.1 was faulty and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 2.1 with a DUMMY card that has passed offline testing. If the IDCODE data is correctly ejected, it indicates that the original DUMMY card 2.1 was faulty and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use. Next, IO_2.1 transitions from high to low. At this time, under the opposite effect of the inverter 1.1, the trigger input of D flip-flop 1.2 transitions from low to high, causing the output D of D flip-flop 1.2 to transition from low to high. Simultaneously, the fixed pin A of analog switch 1.3 is connected to the strobe pin B1. The low level of IO_2.1 passes through analog switch 1.3 and then through JTAG connector 1.2 to the input signal IO_2.2 of the JTAG connector 2.1 of DUMMY card 2.1. The pull-down resistor R2 at the input of inverter 2.1 of DUMMY card 2.1 ensures that the output of inverter 2.1 is high by default, thus preventing false triggering of D flip-flop 2.2 when the low-level signal of IO_2.1 of DUMMY card 1.1 is transmitted to the input signal IO_2.2 of DUMMY card 2.1. Next, since the fixed pin A of analog switch 1.3 is connected to the strobe pin B1, when the boundary scan controller controls IO_2.1 to change its output from low to high, IO_2.2 also changes from low to high. At this time, the output Q of D flip-flop 2.1 changes from 0 to 1. The analog switches 2.1 and 2.2 of DUMMY card 2.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 2.1 is disconnected from the DUMMY card, and analog switch 2.2 is disconnected from the DUMMY card. The MMY card is connected, and the analog switch 3.1 of the DUMMY card 3.1 is connected in the boundary scan link. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then to boundary scan chip 2.1, then to analog switch 2.2, then to JTAG connector 2.2, then to JTAG connector 3.1, then to analog switch 3.1, and then back to JTAG connector 3.1 to access the return path TDO, forming a boundary scan dual chain that accesses boundary scan chip 1.1 and boundary scan chip 2.1; To perform a self-test on the boundary scan dual-link, the boundary scan controller first sends the IDCODE instruction of the combination of boundary scan chip 1.1 and boundary scan chip 2.1, and then sends arbitrarily 32*2 bits of data. If the 32*2 bits of IDCODE data are correctly shifted and output under the action of the data being sent, it indicates that the link is fault-free. If the 32*2 bits of IDCODE data are not correctly output, it indicates that the link is faulty. There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 2.1 and DUMMY card 3.1; it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged; or it could be that analog switch 3.1 or analog switch 3.2 of DUMMY card 3.1 is out of control or the boundary scan chip 3.1 is damaged. First, rule out a line fault between JTAG connectors 2.2 and 3.1 (DUMMY cards 2.1 and 3.1). Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates a line fault between JTAG connectors 2.2 and 3.1, and the fault has been cleared. If the IDCODE is not correctly ejected, the fault persists, and at least one of DUMMY cards 2.1 or 3.1 is faulty. Replace DUMMY card 2.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates the original DUMMY card 2.1 was faulty, and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 3.1 with a DUMMY card that has passed offline testing. If the IDCODE is correctly ejected, it indicates the original DUMMY card 3.1 was faulty, and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use. Next, IO_2.1 is connected to IO_2.3 to complete the step-by-step transmission of the self-test signal, completing the fault test between DUMMY card 3 and DUMMY card 4.1; By analogy, the self-test of the n DUMMY cards in the complete boundary scan chain is completed. Once the self-test is complete, the boundary scan chips 1.1 to n.1 of DUMMY card 1.1 to n.1 form a complete chain and enter the boundary scan test state of the normal test board.

[0023] The pull-down resistors R1 to Rn of inverters 1.1 to n.1 ensure that the outputs of inverters 1.1 to n.1 are high by default, thereby preventing false triggering caused by the arrival of a low-level signal from the previous stage.

[0024] This invention proposes a boundary scan chain self-testing logic circuit and self-testing method. The logic circuit of this invention simultaneously possesses self-testing capabilities for faults in the external JTAG connector wiring and DUMMY card faults. It can quickly locate faults in the wiring between JTAG connectors and in the DUMMY card within the boundary scan chain. It is easy to implement, facilitating timely troubleshooting during field maintenance, reducing troubleshooting costs, and improving boundary scan testing efficiency. Furthermore, this invention considers the consistency of the two JTAG connectors preceding and following each DUMMY card, ensuring that different DUMMY cards can be arbitrarily and flexibly arranged to form a boundary scan chain. It also ensures that the newly added cascading relationship of the self-testing logic circuit of each DUMMY card is synchronized with the cascading relationship of the JTAG signals, enabling implementation according to the JTAG connector cascading method. The original DUMMY card only adds 3 IO control pins to each JTAG connector without increasing the number of DUMMY card connectors. This invention can connect the entire boundary scan chain at once via the controller's IO for self-testing. When the complete boundary scan chain test fails, in order to accurately locate the fault point, the fault self-testing of the JTAG connector lines and DUMMY cards will be performed step by step by gradually increasing the length of the boundary scan chain, and the fault self-testing of the JTAG connector lines and DUMMY cards will be completed step by step, ultimately completing the fault self-testing of the entire chain of JTAG connector lines and DUMMY cards, with high reliability. After the self-test is completed, the board under test enters the boundary scan test state. If there is no problem with the boundary scan chain, in order to save time, the self-test can be skipped after connecting the complete boundary scan chain, and the board under test can directly enter the normal boundary scan test state.

[0025] Test preparation: The boundary scan chain switches 1.1 to n.1 are synchronously turned on, and the switches 1.2 to n.2 are synchronously turned off.

[0026] Combination Figure 3 As shown, In the first step of the test, the boundary scan chain switch state remains unchanged. Starting from TDI_IN, the test proceeds to switch 1.1 and then to TDO, completing the self-test between the controller and DUMMY1. The test includes checking the wiring between the controller and DUMMY1 card 1.1 and whether DUMMY1 card 1.1 itself is faulty. In the second step of the test, switch 1.1 is open and switch 1.2 is on. The states of the other switches in the boundary scan chain remain unchanged. Starting from TDI_IN, the signal goes to boundary scan chip 1, then to switch 1.2, then to switch 2.1, and finally to TDO, forming a single chain connected to boundary scan chip 1. This completes the self-test between DUMMY card 1.1 and DUMMY card 2.1. The test includes checking the wiring between the controller and DUMMY card 1.1 and DUMMY card 2.1, as well as whether DUMMY card 1.1 and DUMMY card 2.1 themselves are faulty. In step 3, switch 2.1 is turned off and switch 2.2 is turned on. The remaining switch states of the boundary scan chain remain unchanged from step 2. Starting from TDI_IN, the signal goes to boundary scan chip 1.1, then to switch 1.2, then to boundary scan chip 2.1, then to switch 2.2, then to switch 3.1, and finally to TDO, forming a dual chain connecting boundary scan chip 1.1 and boundary scan chip 2.1. This completes the self-test between DUMMY card 2.1 and DUMMY card 3.1. The test includes checking the wiring between the controller and DUMMY card 2.1 and DUMMY card 3.1, as well as whether DUMMY card 2.1 and DUMMY card 3.1 themselves are faulty. And so on, In step (n+1), switch n.1 is open, switch n.2 is open, and the remaining switches in the boundary scan chain remain unchanged from step n, forming a complete multi-chain from boundary scan chip 1 to boundary scan chip n.1. This completes the self-test between DUMMY card (n-1).1 and DUMMY card n.1, detecting the lines between the controller and DUMMY card (n-1).1 and DUMMY card n.1, as well as whether DUMMY card (n-1).1 and DUMMY card n.1 themselves are faulty. Each JTAG signal is accompanied by a clock signal TCK and a status signal TMS. The newly added control IO signals, as well as the stored logic and signal propagation logic, are omitted in the simplified diagram here. The self-test logic circuit of this invention can achieve the above test conditions and test results.

[0027] Combination Figure 4 The diagram shown is a schematic diagram of the signal transmission of the self-detection logic circuit of the present invention. In the initial state, switches 1.3 to n.3 are open. IO_2.1 starts with a state of 0 and proceeds to step 1 of the test. IO_2.1 jumps from 0 to 1, proceeding to step 2 of the test; IO_2.1 then transitions from 1 to 0, turning on switch 1.3 and transmitting a low level to the next stage; IO_2.1 then jumps from 0 to 1, proceeding to step 3 of the test; IO_2.1 then transitions from 1 to 0, turning on switch 2.3 and transmitting a low level to the next stage; And so on, IO_2.1 then transitions from 1 to 0, turning on switch n.3 and transmitting a low level to the next stage; IO_2.1 then jumps from 0 to 1 to perform the (n+1)th test.

[0028] A typical D flip-flop chip includes a level input D, a level output Q, a clock input CP, and a preset input to set the initial state. and clear input Combining Figure 1 and Figure 5 As shown, when Low level, When the voltage level is high, the D flip-flop outputs Q as high; when... High level When the voltage is low, the D flip-flop outputs Q low; thus, the initial high and low voltage levels of D flip-flops 1.1 and 1.2 can be controlled; when... High level When the level is low, the trigger-ready mode is enabled, and the output state will be changed when the rising edge of the clock input arrives. A suitable inductor L1.1 is added between IO_2.1 and the clock input CP of D flip-flop 1.1. Under the action of inductor L1.1, when IO_2.1 jumps from low level to high level, the rising edge of the clock input CP lags behind the level input of D, thus completing the trigger output of D flip-flop 1.1. That is, at the rising edge of CP, the output of D flip-flop changes from the initial low level to the high level.

[0029] IO_2.1 is connected to the input of inverter 1. When IO_2.1 changes from high level to low level, the output of inverter 1 jumps from low level to high level. Similarly, due to the effect of the inductor connected to CP, the rising edge of the clock input CP lags behind the level input of D, thus completing the trigger output of D flip-flop 1.2. The output Q of D flip-flop 1.2 also changes from the initial low level to high level. When the control pin S of analog switches 1.1, 1.2, and 1.3 is low, A and B0 are connected, and A and B1 are disconnected; when the control pin S is high, A and B0 are disconnected, and A and B1 are connected. When the output Q of D flip-flop 1.1 is low, it acts on the control pin S of analog switches 1.1 and 1.2. At this time, pins A and B0 of analog switches 1.1 and 1.2 are connected, and A is disconnected from B1. When the output Q of D flip-flop 1.1 is high, pins A and B1 of analog switches 1.1 and 1.2 are connected, and A is disconnected from B0. Similarly, if the output level Q of D flip-flop 1.2 is low, it acts on the control pin S of analog switch 1.3. At this time, pins A and B0 of analog switch 1.3 are connected, and A is disconnected from B1. If the output level Q of D flip-flop 1.2 is high, it acts on the switch control pin S of analog switch 1.3. At this time, pins A and B1 of analog switch 1.3 are connected, and A is disconnected from B0. In the logic circuit of the boundary scan chain, since the switching control pins S of analog switches 1.1 and 1.2 are controlled by the same output Q of the D flip-flop, and since the gating pin B0 of analog switch 1.1 is connected to the circuit and the gating pin B1 of analog switch 1.2 is connected to the circuit, analog switches 1.1 and 1.2 are complementary in conducting and connected to the circuit. When pins A and B0 of analog switches 1.1 and 1.2 are connected and pins A and B1 are disconnected, under the action of analog switch 1.1, TDI_IN and TDO are shorted, and boundary scan chip 1 is not connected to the link. IO_0, IO_1, and IO_2.1 are the internal IOs of the boundary scan controller. This invention achieves the above technical objectives through the three IOs of the controller.

[0030] In the field of boundary scan testing, the IDCODE instructions of different boundary scan chips vary in length, but the IDCODE data of different boundary scan chips is a fixed 32 bits; for the same boundary scan chip, its IDCODE instructions and IDCODE data are fixed and can be obtained by looking up the BSDL file of the boundary scan chip. As shown in Table 1, boundary scan chip 2.1 and boundary scan chip 3.1 are the same, having the same IDCODE instructions and IDCODE data. Boundary scan chip 1.1 is different from boundary scan chips 2.1 and 3.1, so its IDCODE instructions and IDCODE data are different. When the boundary scan chain consists of n boundary scan chips, the IDCODE instructions of the n boundary scan chips are sequentially sent to TDI_IN from right to left, connected end to end according to the chip order. After sending the instructions, DR data is sent to TDI_IN. Since the register containing the IDCODE data is a read-only register, for a chain of one boundary scan chip, the DR data sent to TDI_IN is any 32-bit data, which can be shifted to output a fixed 32-bit IDCODE data. For a chain of n boundary scan chips, the DR data sent to TDI_IN is any 32*n-bit data, which can be shifted to output a fixed 32*n-bit IDCODE data. If the shifted IDCODE is correct, it indicates no fault; if the shifted IDCODE is incorrect, it indicates a fault. Will Figure 3 Taking n=3, and using boundary scan chip 1.1, boundary scan chip 2.1, and boundary scan chip 3.1 provided in Table 1 as examples, the boundary scan chain self-detection logic circuit and self-detection method of the present invention are described in complete and detailed manner. First, perform a self-test on the complete boundary scan chain; The boundary scan controller first controls IO_0 to output a low level and IO_1 to output a high level. At this time, D flip-flops 1.1 to 3.1 and D flip-flops 1.2 to 3.2 output high levels, and the fixed pins A of analog switches 1.1 to 3.1 and 1.2 to 3.2 are all connected to B1. At this time, analog switches 1.1 to 3.1 are all disconnected in the boundary scan logic circuit, and the boundary scan chips 1.1 to 3.1 of DUMMY cards 1.1 to 3.1 are all connected to form a complete boundary scan chain. Boundary scan self-test is performed on this complete chain. Specifically, The boundary scan controller first sends the complete chain of IDCODE instructions sequentially from right to left. The IDCODE instruction is 0000000110 00010 00010. After sending the instruction, it then sends arbitrarily 32*3 bits of DR data to TDI_IN1. The DR data is 11111111000000001111111100000000 11111111000000001111111100000000 1111111100000000 11111111000000001111111100000000. If the 32*3 bits of IDCODE data are correctly extracted, the extracted data, arranged from right to left, is: 00000010110100010010000011011101 00000010100000100000000011001011 0000001010000010000000011001011 indicates that the link is fault-free. If the output 32*3 bit IDCODE data is incorrect, it indicates that the link is faulty. The above measures a complete fault detection of the boundary scan chain, but it cannot determine the specific location of the external connector line fault or the DUMMY card fault. Therefore, it is necessary to perform a step-by-step self-test on the boundary scan chain. Then, perform step-by-step self-testing on the boundary scan chain; The boundary scan controller first controls IO_0 to output a high level and IO_1 to output a low level. At this time, D flip-flops 1.1 to 3.1 and D flip-flops 1.2 to 3.2 output a low level, and the fixed pins A of analog switches 1.1 to 3.1 and 1.2 to 3.2 are all connected to B0. At this time, analog switches 1.1 to 3.1 are all connected in the boundary scan logic circuit, and the boundary scan chips 1 to 3.1 of this DUMMY card 1.1 to DUMMY card 3.1 are all disconnected in the chain. At this time, the boundary scan chain is connected one by one for DUMMY cards, completing the step-by-step self-test. Specifically, With IO_0 output high and IO_1 output low, analog switches 1.2 to 3.2 are all disconnected to prevent the outputs of TDO_1 to TDO_n from boundary scan chips 1.1 to 3.1 from interfering with the return path TDO. Analog switches A and B0 are connected, forming a straight-through path from TDI_IN1 of JTAG connector 1.1 to analog switch 1.1, and then to TDO of JTAG connector 1.1. It should be added here that as long as the JTAG clock signal and the status signal TMS are activated during boundary scan, boundary scan chips TDO_1 to TDO_3 may output data. Therefore, boundary scan chips 1 to 3 are disconnected through analog switches 1.2 to 3.2 to ensure the reliability of the pass-through path test. The pass-through path is self-tested. Following the JTAG state machine protocol, under the influence of the JTAG clock signal and TMS signal, the controller sends a string of data to TDI_IN1. For ease of judgment, this string of data cannot be all 0s or all 1s. Since it is a pass-through path, there is no fixed bit length requirement; sending more bits is acceptable, such as 0101010101. If the TDO of the JTAG return path detects this string of data as 0101010101, it indicates that the wiring from the boundary scan controller to the JTAG connector 1.1 of the DUMMY card 1.1 is fault-free; if an error is detected, it indicates that the wiring from the boundary scan controller to the JTAG connector 1.1 of the DUMMY card 1.1 is fault-free. If there is a fault in the wiring of DUMMY card 1.1, stop the test and check the wiring between the boundary scan controller and the JTAG connector 1.1 of DUMMY card 1.1. Check the three control I / Os and the four signal lines of JTAG. After troubleshooting, run the previous test. If the test still fails, it indicates that DUMMY card 1.1 is faulty. The cause of the fault may be that analog switch 1.1 or analog switch 1.2 is not controlled, or the boundary scan chip 1 is damaged. Replace the faulty DUMMY card 1.1 with a DUMMY card that has passed offline testing. The faulty DUMMY card 1.1 is repaired offline for backup. The fault can be eliminated in time without affecting the automated production of boundary scan, thus improving the efficiency of fault diagnosis. After the test is successful or the fault is resolved, output IO_2.1 low, then output IO_0 and IO_1 high. The D flip-flop 1.1 will then stably enter the ready-to-trigger state. When IO_2.1 is changed from a low level to a high level, the output Q of D flip-flop 1.1 changes from 0 to 1. The analog switches 1.1 and 1.2 of DUMMY card 1.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 1.1 is disconnected in the self-test logic circuit, and analog switch 1.2 is connected in the self-test logic circuit. In addition, analog switch 2.1 of DUMMY card 2.1 is connected in the boundary scan chain. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then to analog switch 2.1, and then back to JTAG connector 2.1 to access the return path TDO, forming a boundary scan single chain connected to boundary scan chip 1. The boundary scan single chain is self-tested. At this time, the boundary scan controller first sends the IDCODE instruction of the boundary scan chip 1.1 to TDI_IN1 from right to left. The instruction is 0000000110. Then, it sends arbitrarily 32-bit DR data to TDI_IN1. The data is 11111111000000001111111100000000. Under the action of sending data, if the IDCODE data is arranged from right to left in the shifted-out order as 00000010110100010010000011011101, it indicates that the link is fault-free. If the shifted-out 32-bit IDCODE data is incorrect, it indicates that the link is faulty. There are three possible causes for this link failure: a faulty JTAG connector line between DUMMY Card 1 and DUMMY Card 2; an uncontrolled analog switch 1.1 or analog switch 1.2 of DUMMY Card 1 or a damaged boundary scan chip 1; or an uncontrolled analog switch 2.1 or analog switch 2.2 of DUMMY Card 2 or a damaged boundary scan chip 2.

[0031] First, troubleshoot the wiring fault between JTAG connectors 1.2 and 2.1 between DUMMY cards 1 and 2. Rerun the test at the fault location. If the ID code is correctly ejected, the previous fault was a JTAG wiring fault and has been cleared. If the ID code is not ejected correctly, the fault persists, and at least one of DUMMY cards 1.1 or 2.1 is faulty. Replace DUMMY card 1.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the ID code is correctly ejected, the original DUMMY card 1.1 was faulty and the fault has been cleared. If the ID code cannot be ejected correctly, replace DUMMY card 2.1 with a DUMMY card that has passed offline testing. If the ID code is correctly ejected, the original DUMMY card 2.1 was faulty and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use to ensure the automated boundary scan fixture operates normally and improves production efficiency.

[0032] Next, IO_2.1 transitions from high to low. At this time, due to the opposite effect of the inverter 1, the trigger input of D flip-flop 1.2 transitions from low to high, causing the output D of D flip-flop 1.2 to transition from low to high. Simultaneously, the fixed pin A of analog switch 1.3 is connected to the strobe pin B1. The low level of IO_2.1 passes through analog switch 1.3 and then through JTAG connector 1.2 to the input signal IO_2.2 of JTAG connector 2.1 of DUMMY card 2. The pull-down resistor R2 at the input of inverter 2 of DUMMY card 2.1 ensures that the output of inverter 2 is high by default, thus preventing false triggering of D flip-flop 2.2 when the low-level signal of IO_2.1 of DUMMY card 1.1 is transmitted to the input signal IO_2.2 of DUMMY card 2.1.

[0033] Next, since the fixed pin A of analog switch 1.3 is connected to the strobe pin B1, when the boundary scan controller controls IO_2.1 to change from low to high, IO_2.2 also changes from low to high. At this time, the output Q of D flip-flop 2.1 changes from 0 to 1. The analog switches 2.1 and 2.2 of DUMMY card 2 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 2.1 is disconnected in the self-test logic circuit, and analog switch 2.2 is in the self-test state. When the logic circuit is connected, the analog switch 3.1 of the DUMMY card 3.1 is connected in the boundary scan link. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then to boundary scan chip 2, then to analog switch 2.2, then to JTAG connector 2.2, then to JTAG connector 3.1, then to analog switch 3.1, and then back to JTAG connector 3.1 to access the return path TDO, forming a boundary scan dual chain that accesses boundary scan chip 1.1 and boundary scan chip 2.1.

[0034] A self-test is performed on the boundary scan dual-chain. The boundary scan controller first sends the combined IDCODE instruction of boundary scan chip 1 and boundary scan chip 2 to TDI_IN1, with the instruction being 0000000110 00010. Then, it sends arbitrary 32*2 bits of DR data to TDI_IN1, with the data being 11111111000000001111111100000000 11111111000000001111111100000000. Under the influence of the sent data, if the IDCODE data is arranged from right to left according to the shifted-out order, it becomes 00000010110100010010000011011101. 00000010100000100000000011001011 indicates that the link is fault-free. If the 32*2 bit IDCODE data is incorrectly shifted out, it indicates that the link is faulty.

[0035] There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 2.1 and DUMMY card 3.1; it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged; or it could be that analog switch 3.1 or analog switch 3.2 of DUMMY card 3.1 is out of control or the boundary scan chip 3 is damaged.

[0036] First, troubleshoot the wiring fault between JTAG connectors 2.2 and 3.1 (DUMMY cards 2.1 and 3.1). Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates a wiring fault between JTAG connectors 2.2 and 3.1, and the fault has been cleared. If the IDCODE is not correctly ejected, the fault persists, and at least one of DUMMY cards 2.1 or 3.1 is faulty. Replace DUMMY card 2.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates the original DUMMY card 2.1 was faulty, and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 3.1 with a DUMMY card that has passed offline testing. If the IDCODE is correctly ejected, it indicates the original DUMMY card 3.1 was faulty, and the fault has been cleared. The replaced DUMMY card is then inspected and verified offline for future use to ensure that the fault clearing time of the boundary scan automated fixture is short enough to improve production efficiency.

[0037] Next, IO_2.1 transitions from high to low. At this time, due to the opposite effect of inverter 2, the trigger input of D flip-flop 2.2 transitions from low to high, causing the output D of D flip-flop 2.2 to transition from low to high. Simultaneously, the fixed pin A of analog switch 2.3 is connected to the strobe pin B1. The low level of IO_2.1 passes through analog switch 1.3, then analog switch 2.3, and then through JTAG connector 2.2 to the input signal IO_2.3 of the JTAG connector 3.1 of DUMMY card 3.1. The pull-down resistor R3 at the input of inverter 3 of DUMMY card 3.1 ensures that the output of inverter 3 is high by default, thus preventing false triggering of D flip-flop 3.2 when the low level signal of IO_2.2 of DUMMY card 2 is transmitted to the input signal IO_2.3 of DUMMY card 3.1.

[0038] Next, since the fixed pin A of analog switch 2.3 is connected to the strobe pin B1, when the boundary scan controller controls IO_2.1 to change from low to high, IO_2.3 also changes from low to high. At this time, the output Q of D flip-flop 3.1 changes from 0 to 1. The analog switches 3.1 and 3.2 of DUMMY card 3.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the remaining analog switches in the boundary scan chain remain unchanged. In this state, analog switch 3.1 is disconnected in the self-test logic circuit, and analog switch 3.2 is connected in the self-test logic circuit. In addition, DUMMY card 3.1 is the last... First, the strobe pin B1 of analog switch 3.2 is shorted to TDO through JTAG connector 3.2. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then to boundary scan chip 2.1, then to analog switch 2.2, then to JTAG connector 2.2, then to JTAG connector 3.1, then to boundary scan chip 3.1, then to analog switch 3.2, then to JTAG connector 3.2, and then through JTAG connector 3.2 to access the return path TDO, forming a boundary scan multi-chain consisting of boundary scan chips 1.1, 2.1 and 3.1.

[0039] A self-test is performed on the boundary scan multi-chain. The boundary scan controller first sends a combination of IDCODE instructions (0000000110 00010 00010) from boundary scan chips 1.1, 2.1, and 3.1 to TDI_IN1. Then, it sends arbitrary 32*3 bits of DR data to TDI_IN1, with the data format: 11111111000000001111111100000000 11111111000000001111111100000000 1111111100000000 11111111000000001111111100000000. Under the influence of the sent data, if the IDCODE data is arranged from right to left according to the shifted-out order, it becomes: 00000010110100010010000011011101 00000010100000100000000011001011 0000001010000010000000011001011 indicates that the link is fault-free. If the 32*3 bit IDCODE data is incorrectly shifted out, it indicates that the link is faulty.

[0040] Since the DUMMY card 3.1 is the last stage of the link, the cause of the fault may be a shorting fault in the JTAG connector 3.2 of the DUMMY card 3.1, or it may be that the analog switch 3.1 or analog switch 3.2 of the DUMMY card 3.1 is not controlled, or the boundary scan chip 3.1 is damaged.

[0041] First, troubleshoot the shorting wire fault of JTAG connector 3.2 on DUMMY card 3.1 and rerun the test to the fault location. If the IDCODE is correctly output, it indicates that the shorting wire fault on JTAG connector 3.2 of DUMMY card 3.1 has been cleared. If the IDCODE data is not correctly output, the fault still exists. Replace DUMMY card 3.1 with a DUMMY card that has passed offline testing and rerun the test to the fault location. If the IDCODE is correctly output, it indicates that the original DUMMY card 3.1 was faulty and the fault has been cleared. The replaced DUMMY card is then offline inspected and verified for backup to ensure that the fault clearing time of the boundary scan automated fixture is short enough to improve production efficiency. After troubleshooting, proceed to the normal boundary scan test state of the link.

[0042] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A boundary scan chain self-detection logic circuit, characterized in that, It includes a boundary scan controller (1) and a scan chain consisting of several cascaded DUMMY cards (2); The DUMMY card (2) includes a first JTAG connector (3), a second JTAG connector (4), a first D flip-flop (5), a second D flip-flop (6), a first analog switch (7), a second analog switch (8), a third analog switch (9), a boundary scan chip (10), an inductor L1, an inductor L2, a resistor R1, and an inverter (12). The boundary scan controller (1) is provided with control IO pins IO_0, IO_1, and IO_2.1; the boundary scan controller (1) is also provided with JTAG signal pins TCK, TMS, TDI_IN1, and TDO; The IO_0 pin on the boundary scan controller (1) is connected to the second JTAG connector (4) via the first JTAG connector (3), and is also connected to the preset inputs of the first D flip-flop (5) and the second D flip-flop (6). Pin; the IO_1 pin on the boundary scan controller (1) is connected to the second JTAG connector (4) via the first JTAG connector (3), and is also connected to the clear input of the first D flip-flop (5) and the second D flip-flop (6). pins; The IO_2.1 pin on the boundary scan controller (1) is connected to the level input D of the first D flip-flop (5) and one end of the inductor L1 via the first JTAG connector (3). The other end of the inductor L1 is connected to the clock input CP of the first D flip-flop (5). In addition, the IO_2.1 pin is also connected to the input of the inverter (12) and the fixed pin A of the third analog switch (9). Furthermore, the input of the inverter (12) is pulled down by the resistor R1, and the output of the inverter (12) is connected to the level input D of the second D flip-flop (6) and the inductor L2. One end of the inductor L2 is connected to the clock input CP of the second D flip-flop (6); the output Q of the first D flip-flop (5) is connected to the switch control pin S of the first analog switch (7) and also to the switch control pin S of the second analog switch (8); the output Q of the second D flip-flop (6) is connected to the switch control pin S of the third analog switch (9); the TDI_IN1 pin of the boundary scan controller (1) is connected to the gating pin B0 of the first analog switch (7) through the first JTAG connector (3) and also to the data input TDI_1 of the boundary scan chip (10); The fixed input A of the first analog switch (7) is connected to the data output line TDO and returns to the boundary scan controller (1) through the first JTAG connector (3); the JTAG clock signal TCK and the JTAG status signal TMS are respectively connected to the clock signal TCK and status signal TMS pins of the boundary scan chip (10); the data output TDO_1 of the boundary scan chip (10) is connected to the fixed pin of the second analog switch (8), and the gating pin B1 of the second analog switch (8) is connected to the second JTAG connector (4); the output pin B1 of the third analog switch (9) is connected to the second JTAG connector (4).

2. The boundary scan chain self-detection logic circuit according to claim 1, characterized in that, All components of the several DUMMY cards (2) are identical except for the boundary scan chip.

3. The boundary scan chain self-detection logic circuit according to claim 1, characterized in that, The first D flip-flops (5) in several of the DUMMY cards (2) are named in the chain order as D flip-flop 1.1, D flip-flop 2.1, ... D flip-flop n.1; The second D flip-flops (6) in several of the DUMMY cards (2) are named in the chain order as D flip-flop 1.2, D flip-flop 2.2, ... D flip-flop n.

2.

4. The boundary scan chain self-detection logic circuit according to claim 1, characterized in that, The first analog switches (7) in several of the DUMMY cards (2) are named in the chain order as analog switch 1.1, D flip-flop 2.1, ..., D flip-flop 3.1; The second analog switches (8) in several of the DUMMY cards (2) are named in the chain order as analog switch 1.2, D flip-flop 2.2, ..., D flip-flop 3.2; The third analog switches (9) in several DUMMY cards (2) are named analog switch 1.3, D flip-flop 2.3, ... D flip-flop 3.3 in the chain order. The first JTAG connector (3), second JTAG connector (4), boundary scan chip (10), inductor L1, inductor L2, resistor R1 and inverter (12) in several DUMMY cards (2) are labeled in this way.

5. A self-testing method for a boundary scan chain self-testing logic circuit according to any one of claims 1 to 4, characterized in that, Perform a full boundary scan test; The boundary scan controller (1) first controls IO_0 to output a low level and IO_1 to output a high level. At this time, D flip-flops 1.1 to D flip-flop n.1 and D flip-flops 1.2 to D flip-flop n.2 output a high level. The fixed pins A of analog switches 1.1 to analog switch n.1 and analog switches 1.2 to analog switch n.2 are all connected to B1. At this time, analog switches 1.1 to analog switch n.1 are all disconnected in the boundary scan logic circuit. The boundary scan chips 1.1 to boundary scan chips n.1 of the first DUMMY card to the nth DUMMY card are all connected to form a complete boundary scan chain. The boundary scan self-test is performed on the complete chain. Specifically, The boundary scan controller first sends the complete link IDCODE instruction, and then sends 32*n bits of DR data to TDI_IN. If the 32*n bits of IDCODE data are correctly output, it indicates that the link is fault-free. If the 32*n bits of IDCODE data are incorrectly output, it indicates that the link is faulty.

6. The self-testing method for a boundary scan chain self-testing logic circuit according to claim 5, characterized in that, Perform step-by-step self-testing of the boundary scan chain; The boundary scan controller (1) first controls IO_0 to output a high level and IO_1 to output a low level. At this time, D flip-flops 1.1 to D flip-flop n.1 and D flip-flops 1.2 to D flip-flop n.2 output a low level, and the fixed pins A of analog switches 1.1 to analog switch n.1 and analog switches 1.2 to analog switch n.2 are all connected to B0. At this time, analog switches 1.1 to analog switch n.1 are all connected in the boundary scan logic circuit, and the boundary scan chips 1.1 to nth boundary scan chip n.1 of this DUMMY card 1.1 to the nth boundary scan chip n.1 are all disconnected in the chain. At this time, the DUMMY cards are connected to the boundary scan link one by one to complete the step-by-step self-test, as shown below. With IO_0 output high and IO_1 output low, analog switches 1.2 to n.2 are all disconnected to prevent the outputs of TDO_1 to TDO_n from boundary scan chips 1.1 to n.1 from interfering with the return path TDO. A and B0 of analog switch 1.1 are connected, forming a straight path from TDI_IN1 of JTAG connector 1.1 to analog switch 1.1 and then to TDO of JTAG connector 1.

1. During boundary scan, as long as the JTAG clock signal and the status signal TMS are activated, the boundary scan chips TDO_1 to TDO_n may output data. Therefore, the boundary scan chips 1.1 to n.1 are disconnected through analog switches 1.2 to n.2 to ensure the reliability of the pass-through path test. A self-test was performed on this pass-through path. Following the JTAG state machine protocol, under the influence of the JTAG clock signal and TMS signal, the controller sent a string of data to TDI_IN1. This string of data could not be all 0s or all 1s. Since it was a pass-through path, there was no fixed bit length requirement; sending more bits was sufficient, i.e., sending 0101010101. If the TDO of the JTAG return path detected this string of data as 0101010101, it indicated that the wiring between the boundary scan controller and the JTAG connector 1.1 of the DUMMY card was fault-free; if an error was detected, it indicated that the connection between the boundary scan controller and the DUMMY card was fault-free. The wiring of JTAG connector 1.1 on card 1.1 may be faulty. In this case, stop the test and check the wiring between the boundary scan controller and the JTAG connector 1.1 on the DUMMY card 1.

1. Check the 3 control IOs and the 4 signal lines of JTAG. After troubleshooting, run the previous test. If the test still fails, it indicates that the DUMMY card 1.1 is faulty. The cause of the fault may be that analog switch 1.1 or analog switch 1.2 is not controlled, or the boundary scan chip 1.1 is damaged. Replace the faulty DUMMY card 1.1 with a DUMMY card that has passed offline testing. The faulty DUMMY card 1.1 should be repaired offline for backup. After the test is successful or the fault is resolved, output IO_2.1 low, then output IO_0 and IO_1 high. The D flip-flop 1.1 will then stably enter the ready-to-trigger state. When IO_2.1 changes from a low level to a high level, the output Q of D flip-flop 1.1 changes from 0 to 1. Analog switches 1.1 and 1.2 of DUMMY card 1.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 1.1 is disconnected from DUMMY card 1.1, and analog switch 1.2 is connected from DUMMY card 1.

1. In addition, analog switch 2.1 of DUMMY card 2.1 is connected in the boundary scan chain. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then back to analog switch 2.1, and then back to JTAG connector 2.1 to access the return path TDO, forming a boundary scan single chain connected to boundary scan chip 1.

1. To perform a self-test on the boundary scan single chain, the boundary scan controller first sends the IDCODE instruction of the boundary scan chip 1.1 to TDI_IN1, and then arbitrarily sends 32-bit DR data to TDI_IN1. If the 32-bit IDCODE data is correctly shifted and output under the action of the data being sent, it indicates that the link is fault-free. If the 32-bit IDCODE data is not correctly output, it indicates that the link is faulty. There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 1.1 and DUMMY card 1.2; it could be that analog switch 1.1 or analog switch 1.2 of DUMMY card 1.1 is out of control or the boundary scan chip 1.1 is damaged; or it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged. First, rule out a line fault between JTAG connectors 1.2 and 2.1 between DUMMY cards 1.1 and 2.

1. Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates that the previous fault was a JTAG line fault and the fault has been cleared. If the IDCODE is not correctly ejected, it indicates that the fault still exists, and at least one of DUMMY cards 1.1 and 1.2 is faulty. Replace DUMMY card 1.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates that the original DUMMY card 1.1 was faulty and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 2.1 with a DUMMY card that has passed offline testing. If the IDCODE data is correctly ejected, it indicates that the original DUMMY card 2.1 was faulty and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use. Next, IO_2.1 transitions from high to low. At this time, under the opposite effect of the inverter 1.1, the trigger input of D flip-flop 1.2 transitions from low to high, causing the output D of D flip-flop 1.2 to transition from low to high. Simultaneously, the fixed pin A of analog switch 1.3 is connected to the strobe pin B1. The low level of IO_2.1 passes through analog switch 1.3 and then through JTAG connector 1.2 to the input signal IO_2.2 of the JTAG connector 2.1 of DUMMY card 2.

1. The pull-down resistor R2 at the input of inverter 2.1 of DUMMY card 2.1 ensures that the output of inverter 2.1 is high by default, thus preventing false triggering of D flip-flop 2.2 when the low-level signal of IO_2.1 of DUMMY card 1.1 is transmitted to the input signal IO_2.2 of DUMMY card 2.

1. Next, since the fixed pin A of analog switch 1.3 is connected to the strobe pin B1, when the boundary scan controller controls IO_2.1 to change its output from low to high, IO_2.2 also changes from low to high. At this time, the output Q of D flip-flop 2.1 changes from 0 to 1. The analog switches 2.1 and 2.2 of DUMMY card 2.1 change from being connected to fixed pin A and strobe pin B0 to being connected to fixed pin A and strobe pin B1. Analysis shows that the states of the other analog switches in the boundary scan chain remain unchanged. In this state, analog switch 2.1 is disconnected from the DUMMY card, and analog switch 2.2 is disconnected from the DUMMY card. The MMY card is connected, and the analog switch 3.1 of the DUMMY card 3.1 is connected in the boundary scan link. At this time, starting from TDI_IN1 of JTAG connector 1.1, it goes to boundary scan chip 1.1, then to analog switch 1.2, then to JTAG connector 1.2, then to JTAG connector 2.1, then to boundary scan chip 2.1, then to analog switch 2.2, then to JTAG connector 2.2, then to JTAG connector 3.1, then to analog switch 3.1, and then back to JTAG connector 3.1 to access the return path TDO, forming a boundary scan dual chain that accesses boundary scan chip 1.1 and boundary scan chip 2.1; To perform a self-test on the boundary scan dual-link, the boundary scan controller first sends the IDCODE instruction of the combination of boundary scan chip 1.1 and boundary scan chip 2.1, and then sends arbitrarily 32*2 bits of data. If the 32*2 bits of IDCODE data are correctly shifted and output under the action of the data being sent, it indicates that the link is fault-free. If the 32*2 bits of IDCODE data are not correctly output, it indicates that the link is faulty. There are three possible causes for this link failure: it could be a fault in the JTAG connector line between DUMMY card 2.1 and DUMMY card 3.1; it could be that analog switch 2.1 or analog switch 2.2 of DUMMY card 2.1 is out of control or the boundary scan chip 2.1 is damaged; or it could be that analog switch 3.1 or analog switch 3.2 of DUMMY card 3.1 is out of control or the boundary scan chip 3.1 is damaged. First, rule out a line fault between JTAG connectors 2.2 and 3.1 (DUMMY cards 2.1 and 3.1). Rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates a line fault between JTAG connectors 2.2 and 3.1, and the fault has been cleared. If the IDCODE is not correctly ejected, the fault persists, and at least one of DUMMY cards 2.1 or 3.1 is faulty. Replace DUMMY card 2.1 with a DUMMY card that has passed offline testing and rerun the test at the fault location. If the IDCODE is correctly ejected, it indicates the original DUMMY card 2.1 was faulty, and the fault has been cleared. If the IDCODE cannot be correctly ejected, replace DUMMY card 3.1 with a DUMMY card that has passed offline testing. If the IDCODE is correctly ejected, it indicates the original DUMMY card 3.1 was faulty, and the fault has been cleared. The replaced DUMMY card should be inspected and verified offline for future use. Next, IO_2.1 is connected to IO_2.3 to complete the step-by-step transmission of the self-test signal, thus completing the fault test between DUMMY card 3.1 and DUMMY card 4.1; By analogy, the self-test of the n DUMMY cards in the complete boundary scan chain is completed. After the self-test is completed, the boundary scan chips 1.1 to n.1 of DUMMY card 1.1 to DUMMY card n.1 form a complete chain and enter the boundary scan test state of the normal test board. The pull-down resistors R1 to Rn of inverters 1.1 to n.1 ensure that the outputs of inverters 1.1 to n.1 are high by default, thereby preventing false triggering caused by the arrival of a low-level signal from the previous stage.

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