Design circuit based on Feiteng D2000 large capacity memory

Abstract

The application relates to a large-capacity memory design circuit based on Feiteng D2000, and belongs to the field of computer mainboard hardware design. The application adopts a Feiteng D2000 processor-based double-RANK DDR4 particle hardware design, overcomes related problems in schematic design and PCBlayout, guarantees the integrity of DDR signals, guarantees the data transmission rate, and adjusts computer mainboard firmware related parameters to adapt to the current hardware state. The application achieves the effect of doubling the memory capacity through revision design under the original hardware design. The double-RANK memory module design can be used on other domestic processors that can support double-RANK and support the DDR particle model. The hardware design circuit diagram and PCBlayout can be solidified as a classic circuit and directly transplanted in other scenes with the same demand.

Description

Technical Field

[0001] This invention belongs to the field of computer motherboard hardware design, specifically relating to a circuit design based on Phytium D2000 large-capacity memory. Background Technology

[0002] With the development of information technology, the volume of data is increasing exponentially. This places increasingly stringent demands on the hardware performance parameters of computers. Memory, as the bridge between the CPU and peripheral devices, primarily provides temporary storage for data to be processed by the CPU and facilitates data exchange with external storage. The transfer rate and capacity supported by DDR4 memory chips directly affect the CPU's ability to process large amounts of data. Memory capacity, a core indicator of computer memory performance, is limited by the number of channels and supported RANKs of the CPU's memory controller, often employing a single-RANK design. This design approach cannot meet the needs of certain scenarios with large data volumes. Furthermore, the demand for domestic production of electronic components exacerbates these challenges.

[0003] Tianjin Phytium Technology Co., Ltd.'s newly launched industrial-grade D2000 processor features a 2.0GHz clock speed and includes two 72-bit DDR4 and LPDDR4 controllers, supporting multi-rank hardware designs. It can double the memory capacity of computer motherboards, thus addressing the 32GB memory requirement under the context of domestic production and meeting the hardware demands of upper-layer applications. Due to semiconductor technology limitations, the DDR4 data transfer rate in this design can only support up to 2666MT / s. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] The technical problem to be solved by this invention is how to provide a high-capacity memory design circuit based on Phytium D2000 to meet the demand for 32GB memory capacity under the background of domestic production.

[0006] (II) Technical Solution

[0007] To solve the above-mentioned technical problems, this invention proposes a high-capacity memory design circuit based on Phytium D2000. The circuit includes: one Phytium D2000 chip and 36 CXDQ3A8AM-WG DDR4 chips. The D2000 chip includes memory controller A and memory controller B.

[0008] The D2000's memory controller A connects to the first group of 18 DDR4 chips, specifically:

[0009] The 22-bit address lines MEM0_ADDR0~MEM0_ADDR17, FT_MEM0_BA0~FT_MEM0_BA1, and FT_MEM0_BG0~FT_MEM0_BG1 of the D2000 memory controller A are sequentially connected in series to the corresponding address pins of the first group of 18 DDR4 chips in the FIY_BY topology.

[0010] The D2000's memory controller A has 72 data lines FT_MEM0_DQ0~FT_MEM0_DQ71, 9 pairs of data gating differential signals FT_MEM0_DQS_C_0 / T_0~FT_MEM0_DQS_C_8 / T_8, and 9 data mask ECC signals FT_MEM0_DM0~FT_MEM0_DM08. Each set of 8 data lines, 1 pair of data gating differential signal lines, and 1 data mask ECC signal is collectively referred to as... One slice, the above signals can be divided into 9 slices in total; each slice has a total of 11 signal lines that connect to two DDR4 chips at the same time, 8 data lines are connected to the C2, D2, D3, E3, B7, D7, E7, D8 pins of the two chips respectively, the wire order can be arbitrarily changed for easy PCB routing, 1 ECC signal line is connected to the A7 pin of the two DDR4 chips, and 1 pair of data strobe differential signal lines are connected to the C3 and B3 pins of the two DDR4 chips;

[0011] The nine control lines of the D2000 memory controller A are also connected in series with the corresponding signal pins of the 18 DDR4 chips in the FIY_BY topology. The correspondence between the control line signals and the DDR4 chip pins is as follows: MEM0_ACT_N corresponds to H3, MEM0_ALERT_N corresponds to L9, MEM0_PAR corresponds to N3; MEM0_RST_N corresponds to L1, MEM0_ODT0 corresponds to F3, MEM0_CKE0 corresponds to G3, MEM0_CS#0 corresponds to G7, MEM0_CLKT0 corresponds to F7, and MEM0_CLKC0 corresponds to F8.

[0012] The D2000's memory controller B connects to the second group of 18 DDR4 chips, specifically:

[0013] The 22-bit address lines MEM1_ADDR1~MEM1_ADDR17, FT_MEM1_BA0~FT_MEM1_BA1, and FT_MEM1_BG0~FT_MEM1_BG1 of the D2000 memory controller B are sequentially connected in series to the corresponding address pins of the second group of 18 DDR4 chips in the FIY_BY topology.

[0014] The D2000's memory controller A has 72 data lines FT_MEM1_DQ0~FT_MEM1_DQ71, 9 pairs of data gating differential signals FT_MEM1_DQS_C_0 / T_0~FT_MEM1_DQS_C_8 / T_8, and 9 data mask ECC signals FT_MEM1_DM0~FT_MEM1_DM08. Each set of 8 data lines, 1 pair of data gating differential signal lines, and 1 data mask ECC signal is collectively referred to as... One slice, the above signals can be divided into 9 slices in total; each slice has a total of 11 signal lines that connect to two DDR4 chips at the same time, 8 data lines are connected to the C2, D2, D3, E3, B7, D7, E7, D8 pins of the two chips respectively, the wire order can be arbitrarily changed for easy PCB routing, 1 ECC signal line is connected to the A7 pin of the two DDR4 chips, and 1 pair of data strobe differential signal lines are connected to the C3 and B3 pins of the two DDR4 chips;

[0015] The nine control lines of the D2000 memory controller B are also connected in series with the corresponding signal pins of the 18 DDR4 chips in the FIY_BY topology. The correspondence between the control line signals and the DDR4 chip pins is as follows: MEM0_ACT_N corresponds to H3, MEM0_ALERT_N corresponds to L9, MEM0_PAR corresponds to N3; MEM0_RST_N corresponds to L1, MEM0_ODT0 corresponds to F3, MEM0_CKE0 corresponds to G3, MEM0_CS#0 corresponds to G7, MEM0_CLKT0 corresponds to F7, and MEM0_CLKC0 corresponds to F8.

[0016] (III) Beneficial Effects

[0017] This invention proposes a high-capacity memory design circuit based on the Phytium D2000 processor. The circuit utilizes a dual-RANKDDR4 memory chip hardware design based on the Phytium D2000 processor. This invention overcomes issues related to schematic design and PCB layout, ensures the integrity of DDR signals, guarantees data transfer rates, and adjusts relevant parameters of the computer motherboard firmware to adapt to the current hardware configuration. This invention increases the memory capacity of computer motherboards and addresses the demand for 32GB memory capacity in the context of domestic production.

[0018] Compared with existing technologies, the technical solution proposed in this invention can be modified based on the original hardware design to achieve a doubling of memory capacity. This dual-RANK memory module design is applicable to other domestically produced processors that support dual-RANK and this DDR chip model. The hardware design circuit diagram and PCB layout for this part can be solidified as a classic circuit and directly ported to other scenarios with similar requirements. Attached Figure Description

[0019] Figure 1 Supported parameters and configuration diagram for memory control of the D2000 processor;

[0020] Figure 2 Parameter diagram of CXDQ3A8AM-WG DDR4 chip;

[0021] Figure 3 Schematic diagram of the interconnection between memory controller A and DDR4;

[0022] Figure 4 This is a schematic diagram of the A signal of the D2000 memory controller;

[0023] Figure 5 The connection method for the termination resistor of memory channel A;

[0024] Figure 6 Wiring impedance and constraint diagram;

[0025] Figure 7 DDR4 selection interface;

[0026] Figure 8 DDR4 parameter configuration interface;

[0027] Figure 9 Configure the interface for other parameters. Detailed Implementation

[0028] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0029] This invention belongs to the field of computer motherboard hardware design and relates to a method for increasing the single-channel memory capacity of Phytium D2000 CPU.

[0030] This invention employs a hardware design based on the Phytium D2000 processor and dual-RANK DDR4 memory chips, thereby increasing the memory capacity of computer motherboards. It addresses the bottleneck of data larger than 16GB that cannot be cached and processed. However, this invention presents significant challenges for schematic design and PCB layout, such as ensuring DDR4 signal integrity, maintaining data transfer rates, and adjusting motherboard firmware parameters to adapt to the current hardware configuration.

[0031] The Phytium D2000 processor is primarily targeted at desktop applications, high-end embedded systems, and low-end servers. The D2000 processor includes two off-chip high-capacity memory controllers, A and B, with each channel containing 64 data bits and 8 ECC parity bits. It supports DDR4 and LPDDR4 protocols and supports device types including X4, X8, X16, DDR4, X16, and X32 LPDDR4.

[0032] like Figure 1 As shown, the DDR controller is an off-chip high-capacity memory control unit in the D2000, responsible for managing the entire chip's main memory space. Its main characteristics are as follows:

[0033] Supports DDR4 and LPDDR4 protocols;

[0034] ·Support DDR4 UDIMM, SODIMM, RDIMM, LRDIMM;

[0035] • Supported device types: DDR4: x4, x8, x16; LPDDR4: x16, x32;

[0036] • Supported maximum speeds: DDR4 – 3200MT / s; LPDDR4 – 3200MT / s;

[0037] Supported interface voltages: DDR4—1.2V; LPDDR4—1.1V;

[0038] • Supports 1 / 2 / 4 ranks;

[0039] • Supports two DDR access channels, each containing 64 data bits and 8 ECC parity bits. Note: Due to the address mapping method of the interconnect network, the storage capacity on both channels must be consistent when using two DDR channels;

[0040] • Supports a variety of low-power functions, including DRAM self-refresh, DDR controller clock shutdown, and power-off;

[0041] • Supports 3DS and DBI in DDR4 mode;

[0042] This invention uses domestically produced DDR4 chips adapted for the D2000 processor, specifically Changxin Memory's CXDQ3A8AM-WG, with specific parameters as follows: Figure 2 .

[0043] Due to limitations in the manufacturing process of domestically produced DDR4 chips and compatibility with Phytium, the maximum capacity of surface-mount chips is only 1GB. The specific model is Changxin CXDQ3A8AM-WG, which has an 8-bit bus width and a data transfer rate of 2666Mbps.

[0044] This invention's dual-rank design uses one Phytium D2000 chip and 36 Changxin CXDQ3A8AM-WG DDR4 chips, of which 4 DDR4 chips are used for ECC data verification. The schematic diagram of the interconnection between memory controller A and the DDR4 chips is shown below. Figure 3 This diagram does not include the minimum system design for normal D2000 operation; it only describes the interconnection between the dual-rank DDR4 chips and the D2000 memory controller. The interconnection between memory controller A and DDR4 is the same, as is the interconnection between memory controller B and DDR4.

[0045] The present invention relates to a high-capacity memory design circuit based on Phytium D2000, comprising: one Phytium D2000 chip and 36 Changxin CXDQ3A8AM-WG DDR4 chips, wherein the D2000 chip includes memory controller A and memory controller B;

[0046] like Figure 4 As shown, the D2000's memory controller A is connected to the first group of 18 DDR4 chips, specifically:

[0047] The 22-bit address lines MEM0_ADDR0~MEM0_ADDR17, FT_MEM0_BA0~FT_MEM0_BA1, and FT_MEM0_BG0~FT_MEM0_BG1 of the D2000 memory controller A are sequentially connected in series to the corresponding address pins of the first group of 18 DDR4 chips in the FIY_BY topology.

[0048] The D2000's memory controller A has 72 data lines FT_MEM0_DQ0~FT_MEM0_DQ71, 9 pairs of data gating differential signals FT_MEM0_DQS_C_0 / T_0~FT_MEM0_DQS_C_8 / T_8, and 9 data mask ECC signals FT_MEM0_DM0~FT_MEM0_DM08. Each set of 8 data lines, 1 pair of data gating differential signal lines, and 1 data mask ECC signal is collectively referred to as... One slice, the above signals can be divided into 9 slices in total; each slice has a total of 11 signal lines that connect to two DDR4 chips at the same time, 8 data lines are connected to the C2, D2, D3, E3, B7, D7, E7, D8 pins of the two chips respectively, the wire order can be arbitrarily changed for easy PCB routing, 1 ECC signal line is connected to the A7 pin of the two DDR4 chips, and 1 pair of data strobe differential signal lines are connected to the C3 and B3 pins of the two DDR4 chips;

[0049] The nine control lines of the D2000 memory controller A are also connected in series with the corresponding signal pins of the 18 DDR4 chips in the FIY_BY topology. The correspondence between the control line signals and the DDR4 chip pins is as follows: MEM0_ACT_N corresponds to H3, MEM0_ALERT_N corresponds to L9, MEM0_PAR corresponds to N3; MEM0_RST_N corresponds to L1, MEM0_ODT0 corresponds to F3, MEM0_CKE0 corresponds to G3, MEM0_CS#0 corresponds to G7, MEM0_CLKT0 corresponds to F7, and MEM0_CLKC0 corresponds to F8.

[0050] The D2000's memory controller B connects to the second group of 18 DDR4 chips, specifically:

[0051] The 22-bit address lines MEM1_ADDR1~MEM1_ADDR17, FT_MEM1_BA0~FT_MEM1_BA1, and FT_MEM1_BG0~FT_MEM1_BG1 of the D2000 memory controller B are sequentially connected in series to the corresponding address pins of the second group of 18 DDR4 chips in the FIY_BY topology.

[0052] The D2000's memory controller A has 72 data lines FT_MEM1_DQ0~FT_MEM1_DQ71, 9 pairs of data gating differential signals FT_MEM1_DQS_C_0 / T_0~FT_MEM1_DQS_C_8 / T_8, and 9 data mask ECC signals FT_MEM1_DM0~FT_MEM1_DM08. Each set of 8 data lines, 1 pair of data gating differential signal lines, and 1 data mask ECC signal is collectively referred to as... One slice, the above signals can be divided into 9 slices in total; each slice has a total of 11 signal lines that connect to two DDR4 chips at the same time, 8 data lines are connected to the C2, D2, D3, E3, B7, D7, E7, D8 pins of the two chips respectively, the wire order can be arbitrarily changed for easy PCB routing, 1 ECC signal line is connected to the A7 pin of the two DDR4 chips, and 1 pair of data strobe differential signal lines are connected to the C3 and B3 pins of the two DDR4 chips;

[0053] The nine control lines of the D2000 memory controller B are also connected in series with the corresponding signal pins of the 18 DDR4 chips in the FIY_BY topology. The correspondence between the control line signals and the DDR4 chip pins is as follows: MEM0_ACT_N corresponds to H3, MEM0_ALERT_N corresponds to L9, MEM0_PAR corresponds to N3; MEM0_RST_N corresponds to L1, MEM0_ODT0 corresponds to F3, MEM0_CKE0 corresponds to G3, MEM0_CS#0 corresponds to G7, MEM0_CLKT0 corresponds to F7, and MEM0_CLKC0 corresponds to F8.

[0054] All control and address lines are pulled up to VTT via 39R resistors in series to absorb charge on the lines and prevent signal reflection. This design avoids signal integrity issues. Figure 5 The diagram shows the resistor connection method for memory controller A; memory controller B has the same design.

[0055] When laying out DDR4 chips on a PCB, the address lines, data lines, and control lines are all routed in a fly-by topology. The routing impedance and related constraints are as follows: Figure 6 ;

[0056] The Clock signal is a differential clock signal line sent from the controller inside the D2000 to the DDR4 chip. The wiring impedance requirement is 75Ω, and the length deviation between differential pairs is <4mils.

[0057] CS, ODT, CKE, and CM / ADDR are single signal lines for control commands on the memory controller. The wiring impedance requirement is 45Ω, and the length deviation from the signal Clock is <80mils.

[0058] DQ is the memory data line, with a wiring impedance requirement of 45Ω. The deviation of DQ relative to DQS within the same slice is <80mils, and the maximum length is 6000mils.

[0059] DQS is the data strobe signal line, with a wiring impedance requirement of 75Ω. clock L is the total length of the clock signal. DQS The total length of the DQS signal, with a length deviation between differential pairs < 4 mils; 0 <= L clock -L DQS <= 7.5 inches.

[0060] In addition, it should be noted that the signal line must maintain a complete reference plane and must not cross the reference plane. When changing layers by drilling vias for the signal line, it is necessary to ensure that the reference plane remains consistent after the layer change. If they are inconsistent, a reflow port is required to connect the reference planes before and after the layer change.

[0061] Phytium provides a dedicated firmware configuration platform, allowing users to customize and adjust firmware parameters such as... Figure 7 As shown;

[0062] Depending on the type of video memory used by the motherboard, if it is DDR4, first enter the MCU configuration interface, select DIMM InfoCFG configuration, and then select DDR4_TYPE.

[0063] Enter the DDR4 parameter configuration interface. The configuration method is the same as for the D2000. Refer to the memory chip manual for your motherboard to fill in the memory parameter information. Figure 8 As shown.

[0064] After configuring the DDR4 chip parameters, exit using Exit. You will then enter the memory configuration interface, which is identical to that of D2000. Figure 9 As shown.

[0065] The schematic and PCB sections have been modularized, and this design has been verified on a large number of boards, demonstrating a certain degree of reliability. Subsequent similar designs can directly port this modular design. This approach not only meets the requirements for large-capacity memory but also avoids design risks.

[0066] This invention proposes a high-capacity memory design circuit based on the Phytium D2000 processor. Utilizing a dual-RANKDDR4 chip hardware design based on the Phytium D2000 processor, this invention overcomes issues related to schematic design and PCB layout, ensuring the integrity of DDR signals and guaranteeing data transfer rates. Furthermore, it adjusts relevant parameters of the computer motherboard firmware to adapt to the current hardware configuration. This invention increases the memory capacity of the computer motherboard and resolves the bottleneck of not being able to cache data larger than 16GB.

[0067] Compared with existing technologies, the technical solution proposed in this invention can be modified based on the original hardware design to achieve a doubling of memory capacity. This dual-RANK memory module design is applicable to other domestically produced processors that support dual-RANK and this DDR chip model. The hardware design circuit diagram and PCB layout for this part can be solidified as a classic circuit and directly ported to other scenarios with similar requirements.

[0068] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A circuit design based on Phytium D2000 high-capacity memory, characterized in that, The circuit includes: one Phytium D2000 chip and 36 CXDQ3A8AM-WG DDR4 chips. The D2000 chip includes memory controller A and memory controller B. The D2000's memory controller A connects to the first group of 18 DDR4 chips, specifically: The 22-bit address lines MEM0_ADDR0~MEM0_ADDR17, FT_MEM0_BA0~FT_MEM0_BA1, and FT_MEM0_BG0~FT_MEM0_BG1 of the D2000 memory controller A are sequentially connected in series to the corresponding address pins of the first group of 18 DDR4 chips in the FIY_BY topology. The D2000's memory controller A has 72 data lines FT_MEM0_DQ0~FT_MEM0_DQ71, 9 pairs of data gating differential signals FT_MEM0_DQS_C_0 / T_0~FT_MEM0_DQS_C_8 / T_8, and 9 data mask ECC signals FT_MEM0_DM0~FT_MEM0_DM08. Each set of 8 data lines, 1 pair of data gating differential signal lines, and 1 data mask ECC signal is collectively referred to as... One slice, the above signals can be divided into 9 slices in total; each slice has a total of 11 signal lines that connect to two DDR4 chips at the same time, 8 data lines are connected to the C2, D2, D3, E3, B7, D7, E7, D8 pins of the two chips respectively, the wire order can be arbitrarily changed for easy PCB routing, 1 ECC signal line is connected to the A7 pin of the two DDR4 chips, and 1 pair of data strobe differential signal lines are connected to the C3 and B3 pins of the two DDR4 chips; The nine control lines of the D2000 memory controller A are also connected in series to the corresponding signal pins of the 18 DDR4 chips in the FIY_BY topology. The correspondence between the control line signals and the DDR4 chip pins is as follows: MEM0_ACT_N corresponds to H3. 、 MEM0_ALERT_N corresponds to L9, MEM0_PAR corresponds to N3; MEM0_RST_N corresponds to L1, MEM0_ODT0 corresponds to F3, MEM0_CKE0 corresponds to G3, MEM0_CS#0 corresponds to G7, MEM0_CLKT0 corresponds to F7, and MEM0_CLKC0 corresponds to F8; The D2000's memory controller B connects to the second group of 18 DDR4 chips, specifically: The 22-bit address lines MEM1_ADDR1~MEM1_ADDR17, FT_MEM1_BA0~FT_MEM1_BA1, and FT_MEM1_BG0~FT_MEM1_BG1 of the D2000 memory controller B are connected in series with the corresponding address pins of the second group of 18 DDR4 chips in the FIY_BY topology. The D2000's memory controller A has 72 data lines FT_MEM1_DQ0~FT_MEM1_DQ71, 9 pairs of data gating differential signals FT_MEM1_DQS_C_0 / T_0~FT_MEM1_DQS_C_8 / T_8, and 9 data mask ECC signals FT_MEM1_DM0~FT_MEM1_DM08. Each set of 8 data lines, 1 pair of data gating differential signal lines, and 1 data mask ECC signal is collectively referred to as... One slice, the above signals can be divided into 9 slices in total; each slice has a total of 11 signal lines that connect to two DDR4 chips at the same time, 8 data lines are connected to the C2, D2, D3, E3, B7, D7, E7, D8 pins of the two chips respectively, the wire order can be arbitrarily changed for easy PCB routing, 1 ECC signal line is connected to the A7 pin of the two DDR4 chips, and 1 pair of data strobe differential signal lines are connected to the C3 and B3 pins of the two DDR4 chips; The nine control lines of the D2000 memory controller B are also connected in series with the corresponding signal pins of the 18 DDR4 chips in the FIY_BY topology. The correspondence between the control line signals and the DDR4 chip pins is as follows: MEM0_ACT_N corresponds to H3. 、 MEM0_ALERT_N corresponds to L9, MEM0_PAR corresponds to N3; MEM0_RST_N corresponds to L1, MEM0_ODT0 corresponds to F3, MEM0_CKE0 corresponds to G3, MEM0_CS#0 corresponds to G7, MEM0_CLKT0 corresponds to F7, and MEM0_CLKC0 corresponds to F8.

2. The circuit design based on Phytium D2000 high-capacity memory as described in claim 1, characterized in that, Of the 36 Changxin CXDQ3A8AM-WG DDR4 chips, 4 DDR4 chips are used for ECC data verification.

3. The circuit design based on Phytium D2000 high-capacity memory as described in claim 1, characterized in that, All control and address lines are pulled up to VTT by a 39R resistor in series to absorb charge on the lines and prevent signal reflection.

4. The circuit design based on Phytium D2000 high-capacity memory as described in claim 1, characterized in that, When laying out DDR4 chips on a PCB, the address lines, data lines, and control lines are all routed in a fly-by topology.

5. The circuit design based on Phytium D2000 large-capacity memory as described in claim 4, characterized in that, The wiring impedance and constraints include: the Clock signal is a differential clock signal line from the controller inside the D2000 to the DDR4 chip, the wiring impedance requirement is 75Ω, and the length deviation between differential pairs is <4mils.

6. The circuit design based on Phytium D2000 large-capacity memory as described in claim 4, characterized in that, The wiring impedance and constraints include: CS, ODT, CKE, and CM / ADDR are single signal lines for control commands on the memory controller. The wiring impedance requirement is 45Ω, and the length deviation from the signal Clock is <80mils.

7. The circuit design based on Phytium D2000 large-capacity memory as described in claim 4, characterized in that, DQS is the data strobe signal line, with a wiring impedance requirement of 75Ω. clock L is the total length of the clock signal. DQS The total length of the DQS signal, with a length deviation between differential pairs < 4 mils; 0 <= L clock -L DQS <= 7.5 inches.

8. The circuit design based on Phytium D2000 large-capacity memory as described in claim 4, characterized in that, The wiring impedance and constraints include: DQ is the memory data line, the wiring impedance requirement is 45Ω, the deviation of DQ relative to DQS within the same slice is <80mils, and the maximum length is 6000mils.

9. The circuit design based on Phytium D2000 large-capacity memory as described in any one of claims 5-8, characterized in that, Signal lines must maintain a complete reference plane and must not cross the reference plane. When changing layers by drilling vias for signal lines, ensure that the reference plane remains consistent after the layer change. If they are inconsistent, a reflow port is required to connect the reference planes before and after the layer change.

10. The high-capacity memory design circuit based on Phytium D2000 as described in claim 9, characterized in that, Depending on the type of video memory used by the motherboard, if it is DDR4, first enter the MCU configuration interface, select DIMM Info CFG configuration, and select DDR4_TYPE; enter the DDR4 parameter configuration interface, refer to the video memory chip manual used by the motherboard to fill in the video memory parameter information; after configuring the DDR4 chip parameter information, exit.

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