A multi-channel pipeline FFT processor based on FPGA

Abstract

The present application relates to the technical field of mobile communication signal processing, and particularly relates to a multi-channel pipeline FFT processor based on FPGA, which comprises: an input data storage module, used for storing multi-channel input data to be subjected to FFT transformation; a calculation control module, used for generating a control signal of FFT transformation; a cascaded twiddle factor storage module, used for storing twiddle factors of butterfly transformation modules; a butterfly transformation unit, composed of a plurality of butterfly transformation modules, used for completing FFT butterfly transformation calculation; and an output data storage module, used for storing butterfly transformation data and completing multi-channel data output processing. The technical scheme of the present application can realize pipeline FFT processing of multi-channel data, improve the efficiency of multi-channel FFT processing, and reduce FPGA resource consumption. The technical scheme of the present application can be widely applied in the fields of 4G / 5G mobile communication and signal processing of monitoring receivers.

Description

Technical Field

[0001] This invention relates to the field of mobile communication signal processing technology, and more specifically to a multi-channel pipelined FFT processor based on FPGA. Background Technology

[0002] The Fast Fourier Transform (FFT) algorithm is widely used in mobile communications to convert signals from the time domain to the frequency domain. OFDM-based communication systems use the FFT algorithm to convert time-domain signals to frequency-domain signals. Currently, the 5G NR communication standard uses OFDM technology, and the FFT calculation results directly affect the performance of the entire 5G communication system.

[0003] The FFT algorithm can be implemented in FFT processor hardware, which mainly employs four methods: sequential processing, pipelined processing, parallel processing, and array processing. Among these, pipelined architecture is the primary method in current communication systems. This method offers high processing speed, low resource consumption, and is suitable for large-scale circuit implementations. However, in current 5G NR communication, with the application of MIMO technology, the demand for multi-antenna transmission and reception has increased. This necessitates the creation of multiple FFT processing pipelines when processing multi-antenna services, leading to a significant increase in resource consumption and substantial hardware overhead.

[0004] For the design of FFT processor hardware for communication signal processing, FPGAs are currently widely used. However, due to the limited resources of FPGAs, multi-channel parallel computing cannot be arranged without limit. To achieve multi-channel computing performance, the hardware resource overhead is also very high. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel pipelined FFT processor based on FPGA, which performs FFT processing with a multi-channel data serial pipeline, greatly reducing FPGA resource consumption.

[0006] To achieve the above objectives, an FPGA-based multi-channel pipelined FFT processor is provided, comprising an input data storage module, a calculation control module, a cascaded twitch factor storage module, a butterfly transform unit, and an output data storage module, wherein the butterfly transform unit comprises several serially connected butterfly transform modules.

[0007] Input data storage module: used to receive input multi-channel parallel data and configuration parameters, perform parallel-to-serial conversion of multi-channel parallel data, and transform the multi-channel parallel data according to the configured extraction method to obtain a new data sequence arranged serially in channel order;

[0008] The calculation control module is used to generate the reference data address and control signal required for the butterfly transformation unit to perform butterfly transformation, as well as the read and write signals of the cascaded rotation factor memory, based on the configuration parameters and the new data sequence.

[0009] Cascaded Rotation Factor Storage Module: Used to store the cascaded rotation factor coefficients of each butterfly transformation module for butterfly transformation;

[0010] The butterfly transform unit is used to process new data sequences through butterfly transform modules one by one. Each butterfly transform module is connected in parallel to the calculation control module and performs calculations according to the control signals of the calculation control module. It is also used to read the cascade rotation factor coefficients from the cascade rotation factor storage module according to the cascade rotation factor storage module read / write signals after each butterfly transform module has completed its calculation and before it is transmitted to the next butterfly transform module, and to multiply the calculation result of the current butterfly transform module by the cascade rotation factor coefficients.

[0011] Output data storage module: used to temporarily store the output data processed by the butterfly transformation unit, transform the output data according to the configured extraction method, and perform serial-to-parallel conversion of multi-channel data.

[0012] Furthermore, the FFT processor implements an N-point radix rFFT processor for parallel input multi-channel parallel data, where N = 2. M M is a positive integer, r is the transform base of the FFT processor, and the configuration parameters include the channel number, data address, and data validity flag signal corresponding to the multi-channel parallel data; the input data storage module converts the multi-channel parallel data of length N points into a new data sequence arranged serially according to the channel order.

[0013] Furthermore, the decimation method includes time-decimation method (DIT) and frequency-domain decimation method (DIF). For the operation of time-decimation method (DIT), the data input to the butterfly transform unit is in reverse order, and the output is in forward order, finally obtaining a new data sequence. For the operation of frequency-domain decimation method (DIF), the data input to the butterfly transform unit is in forward order, and the output is in reverse order, finally obtaining a new data sequence.

[0014] Furthermore, several butterfly transformation modules in the butterfly transformation unit are all radix-L level butterfly transformation modules, and are connected sequentially, where L = logrLL. r N, N=2 M M is a positive integer, and r is the transform basis of the FFT processor. Based on the number of FFT computation points N and the different transform basis r, different butterfly transform modules are designed according to the actual configured basis r. When using a mixed basis, the butterfly transform modules corresponding to each basis r are sequentially combined to obtain the butterfly transform module. The butterfly transform processing length of each stage of the butterfly transform module in the butterfly transform unit is as follows:

[0015]

[0016] For mixed bases, r is the actual transformation basis of the corresponding level.

[0017] Furthermore, the control signal includes:

[0018] The data memory read / write enable signal is used to control the butterfly conversion unit to read and write the data memory;

[0019] The data is processed by the basic butterfly operator control signal to control the basic butterfly calculator calculation.

[0020] The butterfly converter unit is multiplied by the rotation factor enable signal, and the control data is multiplied by the cascaded rotation factor coefficients.

[0021] The butterfly transformation module includes:

[0022] Data memory: Used to store data input to the butterfly converter module according to the data memory read / write enable signal;

[0023] Basis-r butterfly calculator: Used to perform radix-r butterfly transformation calculations on data after receiving the basic butterfly operator control signal;

[0024] Cascaded rotation factor multiplier: After receiving the rotation factor enable signal from the butterfly transform unit, it performs a complex multiplication of the calculation result of the base-r butterfly calculator with the coefficients of the cascaded rotation factor.

[0025] Status monitor: Used to monitor whether the data processed by the base-r butterfly calculator and the cascaded rotation factor multiplier overflows, and generate an overflow flag.

[0026] Furthermore, the basic butterfly calculator consists of four adders, which are used to perform basic butterfly operations on the data.

[0027] Furthermore, the cascaded rotation factor multiplier includes:

[0028] The complex multiplier is used to perform complex multiplication between the output of the radix-r butterfly transformer and the output data of the rotation factor memory; it is also used to dynamically configure the cascaded rotation factor multiplier according to the configured FFT transform length N.

[0029] Principles and advantages:

[0030] Compared with the prior art, the present invention has the following characteristics:

[0031] 1. Since this invention uses FPGA to implement the FFT processor, it reduces the resource overhead of multipliers and other components for calculating FFT in multi-channel applications, and can be applied to FFT processing in various multi-channel communication systems.

[0032] 2. This invention simplifies the data storage control logic in the pipelined FFT processor, using only sequential storage, reducing memory read and write operations and improving computational efficiency;

[0033] 3. This invention is applicable to FFT calculations of arbitrary lengths and arbitrary combinations of FFT bases. Attached Figure Description

[0034] Figure 1 This is a block diagram of the overall structure of a multi-channel pipelined FFT processor based on FPGA according to an embodiment of the present invention;

[0035] Figure 2 This is a structural block diagram of a base butterfly transform unit according to an embodiment of the present invention;

[0036] Figure 3 This is a structural block diagram of a radix-8 butterfly transformation module according to an embodiment of the present invention;

[0037] Figure 4 This is a structural block diagram of a basic butterfly operator according to an embodiment of the present invention;

[0038] Figure 5 This is a data flow diagram of a radix-8 butterfly transform module according to an embodiment of the present invention;

[0039] Figure 6 This is a data processing diagram according to an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram illustrating parallel-to-serial conversion and the corresponding data address indication according to an embodiment of the present invention;

[0041] Figure 8 This is a schematic diagram of the calculation control signal according to an embodiment of the present invention. Detailed Implementation

[0042] The following detailed description illustrates the specific implementation method:

[0043] Example

[0044] A multi-channel pipelined FFT processor based on FPGA, wherein the FFT processor implements an N-point radix-rFFT processor for parallel input multi-channel parallel data, where N=2. M M is a positive integer, and r is the transform base of the FFT processor. Basically as follows... Figure 1As shown, it includes an input terminal for multi-channel parallel data and configuration parameters and an output terminal for FFT processor calculation, as well as an input data storage module, a calculation control module, a cascaded twitch factor storage module, a butterfly transformation unit and an output data storage module. The butterfly transformation unit includes several serially connected butterfly transformation modules.

[0045] Input data storage module: This module receives input multi-channel parallel data and configuration parameters from the multi-channel parallel data and configuration parameter input terminal, performs parallel-to-serial conversion of the multi-channel parallel data, and transforms the multi-channel parallel data according to the configured extraction method to obtain a new data sequence arranged serially according to channel order. The configuration parameters include the channel number, data address, and data validity flag signal corresponding to the multi-channel parallel data. In this embodiment, the input data storage module converts multi-channel parallel data of length N points into a new data sequence arranged serially according to channel order.

[0046] The decimation methods include time-based decimation (DIT) and frequency-based decimation (DIF). For DIT, the data input to the butterfly transform unit is in reverse order, while the output is in forward order, resulting in a new data sequence. For DIF, the data input to the butterfly transform unit is in forward order, while the output is in reverse order, also resulting in a new data sequence. Both methods have a completely symmetrical butterfly structure, differing only in their input and output order.

[0047] The calculation control module is used to generate the reference data address and control signals required for the butterfly transformation unit to perform butterfly transformation, as well as the read / write signals for the cascaded spin factor memory, based on the configuration parameters and the new data sequence. In this embodiment, the reference data address required for the butterfly transformation unit is recalculated based on the channel number, corresponding data address, and data validity flag signal of the received multi-channel parallel data, and the control signals required for the butterfly transformation unit are generated according to the pipeline butterfly transformation processing flow.

[0048] Cascaded Rotation Factor Storage Module: Used to store the cascaded rotation factor coefficients of each butterfly transformation module for butterfly transformation;

[0049] The butterfly transform unit is used to process new data sequences through butterfly transform modules in stages. Each butterfly transform module is connected in parallel to the calculation control module and performs calculations according to the control signals of the calculation control module. It is also used to read the cascade rotation factor coefficients from the cascade rotation factor storage module according to the cascade rotation factor storage module read / write signals after each butterfly transform module has completed its calculation and before it is transmitted to the next butterfly transform module, and to multiply the calculation result of the current butterfly transform module by the cascade rotation factor coefficients.

[0050] like Figure 2As shown, the butterfly transformation unit contains L-level radix-r butterfly transformation modules, which are sequentially connected, where L = logr r N, N=2 M M is a positive integer, and r is the transform radix of the FFT processor. Different butterfly transform modules can be designed according to the actual number of FFT calculation points N and the different transform radix r. When using a mixed radix, the butterfly transform modules corresponding to each radix r are combined sequentially to obtain the butterfly transform module. For example, for a data sequence of N with 8192 points, using a mixed radix 8 and radix 2, it can be divided into 4 levels of radix 8 butterfly transform modules and 1 level of radix 2 butterfly transform modules to form the butterfly transform unit.

[0051] The butterfly transformation processing length of each stage of the butterfly transformation module in the butterfly transformation unit is as follows:

[0052]

[0053] For mixed bases, r is the actual transformation basis of the corresponding level.

[0054] The control signals include:

[0055] The data memory read / write enable signal is used to control the butterfly conversion unit to read and write the data memory;

[0056] The data is processed by the basic butterfly operator control signal to control the basic butterfly calculator calculation.

[0057] The butterfly converter unit is multiplied by the spin factor enable signal, and the control data is multiplied by the cascaded spin factor coefficient.

[0058] like Figure 3 As shown, the butterfly transformation module includes:

[0059] Data memory: Used to store data input to the butterfly converter module according to the data memory read / write enable signal;

[0060] A radix-r butterfly calculator: This calculator performs radix-r butterfly transformations on data after receiving a basic butterfly operator control signal. The radix-r butterfly calculator varies depending on the radix, and its basic components include multiple adders to complete basic butterfly operations on the data. In this embodiment, four adders are used to perform cross-addition and subtraction calculations on a pair of input complex numbers, such as... Figure 4 The diagram shows a set of basic butterfly operators, consisting of adders, which implement data addition and subtraction functions.

[0061] Cascaded rotation factor multiplier: After receiving the rotation factor enable signal from the butterfly transform unit, it performs a complex multiplication of the calculation result of the radix-r butterfly calculator with the coefficients of the cascaded rotation factor; the cascaded rotation factor multiplier includes: a complex multiplier, used to perform a complex multiplication of the output result of the radix-r butterfly transform with the output data of the rotation factor memory; and also used to dynamically configure the cascaded rotation factor multiplier according to the configured FFT transform length N.

[0062] Status monitor: Used to monitor whether the data processed by the base-r butterfly calculator and the cascaded rotation factor multiplier overflows, and generate an overflow flag.

[0063] Output data storage module: Used to temporarily store the output data processed by the butterfly transformation unit, transform the output data according to the configured extraction method, and perform serial-to-parallel conversion of multi-channel data. It also includes data addresses, benefit flags, etc.

[0064] For ease of explanation: The following example uses the radix-8 DIF FFT algorithm. Assume that there are 4 parallel input channels, and each channel's input data is a complex sequence of length N points, where N = 8. L The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0065] like Figure 5 The diagram shows the structure of the radix-8DIF FFT butterfly transform module. The radix-8DIF FFT butterfly transform module includes three basic butterfly operators connected in sequence. According to the pipelined processing architecture, it requires a total of 12 adders, 2 complex multipliers, and 2 data memories.

[0066] like Figure 6 The diagram shown is a data flow diagram of an embodiment of the present invention. Based on the configured data length N and the transformation basis r, a butterfly transformation unit is composed of several butterfly transformation modules. Each butterfly transformation module performs parallel computation along the pipeline structure. The data processing process will be described in detail below with reference to the data flow diagram.

[0067] Four parallel data streams are written into the input data storage module, which mainly performs two processes: First, it processes the data order according to the configured extraction method. For DIT extraction, the data order is converted to reverse order; in this embodiment, DIF extraction is used, and the data order is forward order. Second, it converts the input four-channel, N-point parallel data into a new data sequence arranged serially according to the channel order, i.e., the length of the new data sequence is 4N. Figure 7 As shown.

[0068] The calculation control module recalculates and generates a new serial data address (0,1,2,...,4N-1) based on the input data channel number (0,1,...,3) and data address (0,1,...N-1). Based on the new serial data address, it generates a read enable signal for the data storage module, reads the memory data, and inputs it into the butterfly transformation unit. Simultaneously, it generates control signals for the butterfly transformation unit, including: a read / write enable signal for the data memory within the butterfly transformation unit, used to control the butterfly transformation unit to read and write the data memory and control basic butterfly operation calculations; a read signal for the cascaded rotation factor register of the butterfly transformation module, used to read the cascaded rotation factor parameters; and a butterfly operator rotation factor multiplication enable signal, controlling the butterfly operator to multiply the calculated data by the cascaded rotation factor coefficient.

[0069] Data is sequentially input into the butterfly transformation unit and processed stage by stage through the butterfly transformation modules. Each stage of the butterfly transformation module performs calculations based on the control parameters of the control unit. For example... Figure 8 The diagram shows the control signals generated by the calculation control module and the calculation process of the radix-8 butterfly transform module. The input sequence length is N(i). The radix-8 butterfly transform module consists of three layers of butterfly operators, and the lengths of the butterfly operation sequences corresponding to each layer are as follows:

[0070]

[0071] Therefore, the data memory depth corresponding to each layer of butterfly operators is...

[0072] like Figure 8 As shown, the data sequence is input into the butterfly transform unit. In the first-level butterfly transform module, according to the first-layer butterfly operator data memory read / write signal indication, when the signal is high, the input data is written to the data memory, and when the signal is low, the data is read from the data memory. That is, for DIF decimation, the first half of the input data sequence is stored in the data memory, then read out of the memory, and butterfly operation is performed with the second half of the data sequence. Further, based on the butterfly operator calculation result, according to the first-layer butterfly operator twitch factor calculation signal indication, a portion of the data is multiplied by a cascaded twitch factor coefficient. Then, for the complex multiplication result, it is input into the second-layer butterfly operator input data memory.

[0073] Furthermore, the processing procedures for the second and third layer butterfly operators are the same as those for the first layer butterfly operator; both are performed by control signals from the calculation control module. The third layer butterfly operator does not include the calculation of the butterfly operator twitch factor. After completing the third layer butterfly operator calculation, the data result is output.

[0074] After the first-level butterfly transformation calculation is completed, the data is multiplied by the cascaded butterfly transformation rotation factor to complete the data calculation of the first-level butterfly transformation module, and then the data is output.

[0075] In each layer of butterfly operator calculation process, a data saturation judgment is designed to determine whether the data will overflow during the calculation process, and the overflow flag is output.

[0076] Furthermore, each butterfly transformation module in the butterfly transformation unit processes the same data, with the corresponding control signal generated by the calculation and control module, and each butterfly transformation module performing parallel calculations.

[0077] In this invention, the FFT butterfly transform and data storage unit adopt a pipelined architecture. Each butterfly transform stage consists of a memory and an independent butterfly transform module, and calculations are performed sequentially stage by stage, with the butterfly transform length decreasing at each stage. The pipelined structure improves the efficiency of FFT computation. Each butterfly transform stage is calculated in parallel, and when the input data rate is matched, the total system computation time is only the time of one pipeline stage. This method offers fast processing speed and moderate hardware resource consumption. For FFT operations with different point counts, different point counts can be achieved simply by adding or removing butterfly transform module stages.

[0078] This invention provides a method for implementing a multi-channel pipelined FFT processor based on FPGA. It can be used in applications such as spectrum analysis in digital signal processing, OFDM signal processing in 4G LTE / 5G NR, and signal processing in monitoring receivers, and has significant implications and applications. This invention solves the problem of high resource overhead when performing FFT processing on multi-channel parallel data sequences. It uses a single-stage pipeline structure to serially process multi-channel parallel data, saving resources such as multipliers while utilizing the same storage resources. Therefore, this invention can be applied to the implementation of multi-channel FFT processors using FPGA.

[0079] The above descriptions are merely embodiments of the present invention. Commonly known structures and characteristics are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, based on the guidance provided in this application, improve and implement this solution in combination with their own capabilities. Some typical well-known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention. These should also be considered within the scope of protection of the present invention, and will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A multi-channel pipelined FFT processor based on FPGA, characterized in that: It includes an input data storage module, a calculation control module, a cascaded rotation factor storage module, a butterfly transformation unit, and an output data storage module. The butterfly transformation unit includes several butterfly transformation modules connected in series. Input data storage module: used to receive input multi-channel parallel data and configuration parameters, perform parallel-to-serial conversion of multi-channel parallel data, and transform the multi-channel parallel data according to the configured extraction method to obtain a new data sequence arranged serially in channel order; The calculation control module is used to generate the reference data address and control signal required for the butterfly transformation unit to perform butterfly transformation, as well as the read and write signals of the cascaded rotation factor memory, based on the configuration parameters and the new data sequence. Cascaded Rotation Factor Storage Module: Used to store the cascaded rotation factor coefficients of each butterfly transformation module for butterfly transformation; The butterfly transform unit is used to process new data sequences through butterfly transform modules one by one. Each butterfly transform module is connected in parallel to the calculation control module and performs calculations according to the control signals of the calculation control module. It is also used to read the cascade rotation factor coefficients from the cascade rotation factor storage module according to the cascade rotation factor storage module read / write signals after each butterfly transform module has completed its calculation and before it is transmitted to the next butterfly transform module, and to multiply the calculation result of the current butterfly transform module by the cascade rotation factor coefficients. Output data storage module: used to temporarily store the output data processed by the butterfly transformation unit, transform the output data according to the configured extraction method, and perform serial-to-parallel conversion of multi-channel data; The butterfly transformation unit contains several butterfly transformation modules, all of which are based on... A multi-stage butterfly transformation module, connected sequentially, wherein... , , It is a positive integer. The transform base of the FFT processor; based on the number of FFT calculation points. and transformation basis The differences depend on the actual configuration. Design different butterfly transform modules; when using a hybrid basis, combine the bases... The corresponding butterfly transformation modules are sequentially combined to obtain a butterfly transformation module; the butterfly transformation processing length of each stage of the butterfly transformation module in the butterfly transformation unit is as follows: For mixed bases, This is the actual transformation basis for the corresponding level.

2. The FPGA-based multi-channel pipelined FFT processor according to claim 1, characterized in that: The FFT processor processes multi-channel parallel data input in parallel to achieve... Point base FFT processor, where , It is a positive integer. The transformation base of the FFT processor is defined by the configuration parameters, which include the channel number, data address, and data validity flag signal corresponding to the multi-channel parallel data. The input data storage module stores data of length [missing information]. N The multi-channel parallel data of points is converted into a new data sequence arranged serially according to the channel order.

3. The FPGA-based multi-channel pipelined FFT processor according to claim 2, characterized in that: The decimation method includes time-decimation method (DIT) and frequency-domain decimation method (DIF). For the time-decimation method (DIT), the data input to the butterfly transform unit is in reverse order, and the output is in forward order, resulting in a new data sequence. For the frequency-domain decimation method (DIF), the data input to the butterfly transform unit is in forward order, and the output is in reverse order, resulting in a new data sequence.

4. The FPGA-based multi-channel pipelined FFT processor according to claim 3, characterized in that: The control signals include: The data memory read / write enable signal is used to control the butterfly conversion unit to read and write the data memory; The data is processed by the basic butterfly operator control signal to control the basic butterfly calculator calculation. The butterfly converter unit is multiplied by the rotation factor enable signal, and the control data is multiplied by the cascaded rotation factor coefficients. The butterfly transformation module includes: Data memory: Used to store data input to the butterfly converter module according to the data memory read / write enable signal; base Butterfly Calculator: Used to perform basic butterfly operator control signals on received data, and then perform basic butterfly operator operations on the data. Calculation of butterfly transformation; Cascaded rotation factor multiplier: Used to multiply the base by the rotation factor after receiving the butterfly transform unit multiplied by the rotation factor enable signal. The calculation result of the butterfly calculator is multiplied by the coefficients of the cascaded rotation factor; Status monitor: used to monitor the base Check if the data processed by the butterfly calculator and cascaded rotation factor multiplier overflows, and generate an overflow flag.

5. A multi-channel pipelined FFT processor based on FPGA according to claim 4, characterized in that: The base A butterfly calculator consists of four adders, which are used to perform basic butterfly operations on data.

6. The FPGA-based multi-channel pipelined FFT processor according to claim 5, characterized in that: The cascaded rotation factor multiplier includes: Complex multipliers are used to perform base multiplication. The complex multiplication of the butterfly transformer output with the rotation factor memory output data; also used for determining the configured FFT transform length. N Dynamically configure the rotating cascaded factor multiplier.

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