Methods and systems of forming integrated circuits and non-transitory computer readable media

Abstract

Embodiments of the invention provide a method of forming an integrated circuit (IC) including generating a netlist of a first circuit, generating a first cell placement of the first circuit, placing the first cell placement in a first region of a layout design by an automatic place and route (APR) tool. The first circuit is configured as a non-functional circuit. The first circuit includes a first pin and a second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes designating the first pin and the second pin as a first set of pins to be connected together. Placing the first cell placement by the APR tool includes connecting the first pin and the second pin in the first set of pins together, thereby changing the first circuit to a second circuit. The second circuit is configured as a functional version of the first circuit. Embodiments of the invention also provide a system for manufacturing an integrated circuit and a non-transitory computer readable medium.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of semiconductors, and more specifically, to methods and systems for forming integrated circuits and non-transitory computer-readable media. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but deliver more functionality at higher speeds. This miniaturization process has also led to more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] One aspect of the present invention provides a method for forming an integrated circuit (IC), the method comprising: generating a netlist of a first circuit by a processor, wherein the first circuit is configured as a non-functional circuit and the first circuit includes a first pin and a second pin electrically disconnected from each other, wherein generating the netlist of the first circuit includes: designating the first pin and the second pin as a first set of pins to be connected together; generating a first cell layout of the first circuit by the processor, wherein the first cell layout includes a first conductive component pattern and a second conductive component pattern extending in a first direction, the first conductive component pattern and the second conductive component pattern being located on a first layout layer and separated from each other in a second direction other than the first direction, wherein the first conductive component pattern and the second conductive component pattern are not connected together, the first conductive component pattern corresponding to the first pin and the second conductive component pattern corresponding to the second pin; placing the first cell layout in a first area of ​​the layout design by an automatic placement and routing (APR) tool, wherein placing the first cell layout by the APR tool includes: connecting the first pin and the second pin in the first set of pins together, thereby transforming the first circuit into a second circuit, the second circuit being configured as a functional version of the first circuit.

[0004] Another aspect of the present invention provides a system for manufacturing an integrated circuit, the system comprising: a non-transitory computer-readable medium configured to store executable instructions; and a processor connected to the non-transitory computer-readable medium, wherein the processor is configured to execute the following instructions: generating a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit and the first circuit includes a first pin, a second pin, and a third pin electrically disconnected from each other, wherein generating the netlist of the first circuit includes: combining the first pin, the second pin, and the third pin into a first set of pins to be connected; generating a first cell layout of the first circuit, wherein the first cell layout includes a first conductive component pattern corresponding to the first pin, a second conductive component pattern corresponding to the second pin, and a third conductive component pattern corresponding to the third pin; placing the first cell layout in a first area of ​​a layout design using an automatic placement and routing (APR) tool, wherein placing the first cell layout using the APR tool includes: connecting the first set of pins to be connected together to transform the first circuit into a second circuit, the second circuit being configured as a functional version of the first circuit.

[0005] Another aspect of the invention provides a non-transitory computer-readable medium configured to store executable instructions, wherein the executable instructions are configured to be executed by a processor connected to the non-transitory computer-readable medium, the non-transitory computer-readable medium causing the processor to execute a method comprising: generating a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit and the first circuit includes a first pin and a second pin electrically disconnected from each other, wherein generating the netlist of the first circuit includes: marking the first pin and the second pin as a first set of pins to be connected; and designating the first set of pins to be connected as a common pin group to be connected together; generating a first cell layout of the first circuit, wherein the first cell layout includes a first conductive component pattern corresponding to the first pin and a second conductive component pattern corresponding to the second pin, and the first conductive component pattern and the second conductive component pattern are in a first layout layer; placing the first cell layout in a first area of ​​the layout design using an automatic placement and routing (APR) tool, wherein placing the first cell layout using the APR tool includes: connecting the first set of pins to be connected in the common pin group together, thereby converting the first circuit into a second circuit, the second circuit being configured as a functional version of the first circuit. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0008] Figure 2 This is a flowchart of a method for changing a first circuit to a second circuit according to some embodiments.

[0009] Figure 3 This is a layout diagram of an integrated circuit according to some embodiments.

[0010] Figure 4 This is a layout diagram of an integrated circuit according to some embodiments.

[0011] Figure 5 This is a flowchart of a method for designating a first pin and a second pin as a first set of pins to be connected together, according to some embodiments.

[0012] Figure 6 This is a flowchart of a method for designating a first pin and a second pin as a first set of pins to be connected together, according to some embodiments.

[0013] Figures 7A-7C These are corresponding diagrams of the layout of integrated circuits according to some embodiments.

[0014] Figure 8 This is a layout diagram of an integrated circuit according to some embodiments.

[0015] Figure 9A These are circuit diagrams of integrated circuits according to some embodiments.

[0016] Figure 9B These are circuit diagrams of integrated circuits according to some embodiments.

[0017] Figure 9C This is a layout diagram of an integrated circuit according to some embodiments.

[0018] Figure 9D This is a layout diagram of an integrated circuit according to some embodiments.

[0019] Figure 9E These are circuit diagrams of integrated circuits according to some embodiments.

[0020] Figure 9F This is a schematic diagram of a Verilog netlist of an integrated circuit according to some embodiments.

[0021] Figure 9G This is a cross-sectional view of an integrated circuit according to some embodiments.

[0022] Figure 10A These are circuit diagrams of integrated circuits according to some embodiments.

[0023] Figure 10B This is a layout diagram of an integrated circuit according to some embodiments.

[0024] Figure 10C This is a layout diagram of an integrated circuit according to some embodiments.

[0025] Figure 10D These are circuit diagrams of integrated circuits according to some embodiments.

[0026] Figure 10E This is a schematic diagram of a Verilog netlist of an integrated circuit according to some embodiments.

[0027] Figure 11A These are circuit diagrams of integrated circuits according to some embodiments.

[0028] Figure 11B This is a layout diagram of an integrated circuit according to some embodiments.

[0029] Figure 11C This is a layout diagram of an integrated circuit according to some embodiments.

[0030] Figure 11D These are circuit diagrams of integrated circuits according to some embodiments.

[0031] Figure 12A These are circuit diagrams of integrated circuits according to some embodiments.

[0032] Figure 12B This is a layout diagram of an integrated circuit according to some embodiments.

[0033] Figure 12C This is a layout diagram of an integrated circuit according to some embodiments.

[0034] Figure 12D These are circuit diagrams of integrated circuits according to some embodiments.

[0035] Figure 13A These are circuit diagrams of integrated circuits according to some embodiments.

[0036] Figure 13B This is a layout diagram of an integrated circuit according to some embodiments.

[0037] Figure 14A These are circuit diagrams of integrated circuits according to some embodiments.

[0038] Figure 14BThis is a layout diagram of an integrated circuit according to some embodiments.

[0039] Figure 15A These are circuit diagrams of integrated circuits according to some embodiments.

[0040] Figure 15B This is a layout diagram of an integrated circuit according to some embodiments.

[0041] Figure 15C This is a layout diagram of an integrated circuit according to some embodiments.

[0042] Figure 15D These are circuit diagrams of integrated circuits according to some embodiments.

[0043] Figure 16 This is a flowchart of a method for arranging and wiring ECO units into a layout according to some embodiments.

[0044] Figure 17 This is a flowchart of a method for generating an integrated circuit layout according to some embodiments.

[0045] Figure 18 This is a functional flowchart of a method for manufacturing an IC device according to some embodiments.

[0046] Figure 19 This is a schematic diagram of a system for designing IC layout and manufacturing IC circuits according to some embodiments.

[0047] Figure 20 This is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to at least one embodiment of the present disclosure. Detailed Implementation

[0048] This invention provides numerous different embodiments or instances for implementing various components of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0049] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0050] According to some embodiments, a method of forming an integrated circuit includes generating a netlist of a first circuit. In some embodiments, the first circuit is configured as a non-functional circuit. In some embodiments, the first circuit includes a first pin and a second pin that are electrically disconnected from each other. In some embodiments, generating a netlist of the first circuit includes designating the first pin and the second pin as a first set of pins to be connected together.

[0051] In some embodiments, the method further includes generating a first cell layout for the first circuit and arranging the first cell layout in a first area of ​​the layout design using an Automatic Place and Routing (APR) tool. In some embodiments, placing the first cell layout using the APR tool includes changing the first circuit into a second circuit. In some embodiments, the second circuit is configured as a functional version of the first circuit. In some embodiments, changing the first circuit into a second circuit includes connecting a first pin and a second pin in a first set of pins together.

[0052] In some embodiments, connecting the first and second pins of the first set of pins together using an APR tool results in a more flexible APR placement scheme and a more flexible layout design compared to other methods.

[0053] Figure 1 This is a flowchart of a method 100 for manufacturing an integrated circuit according to some embodiments. It is understood that, in Figure 1 Additional operations may be performed before, during, and / or after the method 100 described herein, and some other processes may only be briefly described herein.

[0054] In some embodiments, one or more methods 100, 200, 500, 600, 1600, 1700, or 1800 ( Figure 1 , Figure 2 , Figures 5-6 or Figures 16-18Other operations in the sequence of operations are within the scope of this disclosure. One or more methods 100, 200, 500, 600, 1600, 1700, or 1800 include exemplary operations, but these operations do not necessarily have to be performed in the order shown. Operations may be added, substituted, changed in order, and / or omitted as appropriate, according to the spirit and scope of the disclosed embodiments.

[0055] In some embodiments, the method 100 can be used to form an integrated circuit, such as at least an IC device 2060. Figure 20 In some embodiments, the method 100 can be used to form a structure having a similar shape to... Figure 3 Layout 300 or Figure 4 Layout 400 Figure 3 Units 320A1, 320A2, 320B-320E, Figure 4 Units 400A-400B or 440A-440E, Figures 7A-7C Layout 700A-Layout 700C Figure 8 The layout of 800, Figures 9C-9D The layout of 900C-900D, Figures 10B-10C The layout of 1000B-1000C, Figures 11B-11C The layout of 1100B-1100C, Figures 12B-12C The layout of 1200B-1200C, Figure 13B The layout of 1300B, Figure 14B Layout 1400B or Figures 15B-15C The layout of one or more integrated circuits in the 1500B-1500C structural relationship.

[0056] In operation 102 of method 100, a netlist for the first circuit is generated. In some embodiments, the netlist includes a list of components in the first circuit and a list of nodes connected in the first circuit. In some embodiments, the netlist corresponds to a hardware description language, such as Verilog, VHDL, or a similar language.

[0057] In some embodiments, the netlist of method 100 includes at least Figure 19 Netlist 1922. In some embodiments, the netlist of method 100 includes Verilog netlist 900F ( Figure 9F ) or Verilog netlist 1000E ( Figure 10E At least one of them.

[0058] In some embodiments, the netlist is created based on a schematic design of the first circuit. In some embodiments, the netlist is generated by one or more hardware simulators or hardware compilers, such as SPICE (Special Programming Interface). In some embodiments, the netlist of the first circuit is utilized by one or more EDA tools that generate a corresponding circuit schematic of the first circuit based on the netlist. In some embodiments, the circuit schematic of the first circuit is utilized by one or more EDA tools that generate a corresponding netlist of the first circuit. A non-limiting example of a circuit schematic is shown. Figure 9A 900A circuit Figure 9B Circuit 900B Figure 9E Circuit 900E, Figure 10A 1000A circuit Figure 10D Circuit 1000D, Figure 11A 1100A circuit Figure 11D Circuit 1100D, Figure 12A 1200A circuit Figure 12D Circuit 1200D, Figure 13A 1300A circuit Figure 14A 1400A circuit Figure 15A 1500A circuit or Figure 15D At least one of the circuits 1500D.

[0059] In some embodiments, operation 102 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for generating a netlist for a first circuit. Figure 19 )) Execution. In some embodiments, operation 102 is implemented as a software application that is part of an EDA tool.

[0060] In some embodiments, the first circuit is configured as a non-functional circuit. In some embodiments, the non-functional circuit corresponds to a logic circuit that is part of a standard cell. In some embodiments, a non-functional circuit refers to a circuit that includes two or more pins or nodes disconnected from each other, thus making the circuit non-functional, but would be functional if the two or more pins or nodes were connected to each other. For example, according to some embodiments, if the first circuit corresponds to an AND logic gate, one or more internal connections within the AND logic gate are broken, causing the first circuit to not function as an AND logic gate. In some embodiments, once the broken internal connections are reconnected, the first circuit is converted into a second circuit, which is an AND logic gate (e.g., as shown in operation 112). In some embodiments, the first circuit is not limited to logic circuits, but also includes other types of circuits corresponding to standard cells. For example, in some embodiments, the first circuit includes one or more memory cells.

[0061] In some embodiments, the first circuit includes one or more internal pins that are disconnected from each other (e.g., a first pin, a second pin, etc.), thereby making the first circuit a non-functional circuit.

[0062] In some embodiments, each pin is associated with one or more transistor devices or circuit elements. In some embodiments, an internal connection between two or more transistor devices corresponds to a connection between a first pin and a second pin. In some embodiments, an internal connection between at least one transistor device and another circuit element corresponds to a connection between a first pin and a second pin.

[0063] In some embodiments, the first circuit corresponds to a circuit stored in, such as Figure 19 The standard cells are from the standard cell library 1920 in the standard cell library. In some embodiments, the first circuit includes a first pin and a second pin, which are electrically disconnected from each other. In some embodiments, the first pin and the second pin of the first circuit are electrically connected to each other by the APR tool in operation 110 during the APR phase of the design.

[0064] In some embodiments, the first circuit of method 100 includes Figure 9B Circuit 900B Figure 10A 1000A circuit Figure 11A 1100A circuit Figure 12A 1200A circuit or Figure 15A At least one of the circuits 1500A.

[0065] In some embodiments, the first pin of method 100 includes Figure 3 and Figure 8 Pin PIN1 or PIN2, Figures 7A-7C Pin A - Pin D Figures 9B-9E Pins JP1-JP2 Figures 10A-10D Pins JP1-JP2, Figures 11A-11D Pins JP3-JP4, Figures 12A-12D Pins JP5-JP7, Figures 13A-13B The pins +IN, +Internal, and +Z, Figure 14B Pins JP8-JP12 and Figures 15A-15D At least one of pins JP13 to JP17.

[0066] In some embodiments, the second pin of method 100 includes Figure 3 and Figure 8 Pin PIN1 or PIN2, Figures 7A-7C Pin A - Pin D Figures 9B-9E Pins JP1-JP2, Figures 10A-10DPins JP1-JP2, Figures 11A-11D Pins JP3 and JP4, Figures 12A-12D Pins JP5 and JP7, Figures 13A-13B The pins +IN, +Internal, and +Z, Figure 14B Pins JP8-JP12 and Figures 15A-15D At least one of pins JP13-JP17.

[0067] In some embodiments, the first circuit includes a first pin, a second pin, and a third pin that are electrically disconnected from each other. In some embodiments, the first pin, the second pin, and the third pin of the first circuit are electrically connected to each other by an APR tool during operation 110.

[0068] In some embodiments, the first circuit further includes a third pin and a fourth pin that are electrically disconnected from each other. In some embodiments, the third pin and the fourth pin of the first circuit are electrically connected to each other via an APR tool during operation 110.

[0069] In some embodiments, the third pin of method 100 includes Figures 12A-12D Pins JP5-JP7 Figures 13A-13B The pins +IN, +Internal and +Z, Figure 14B and Figures 15A-15D Pins JP8-JP12 and Figures 15A-15D At least one of pins JP13 to JP17.

[0070] In some embodiments, the fourth pin of method 100 includes Figures 12A-12D Pins JP5-JP7 Figures 13A-13B The pins +IN, +Internal and +Z, Figure 14B and Figures 15A-15D Pins JP8-JP12 or Figures 15A-15D At least one of pins JP13 to JP17.

[0071] In some embodiments, operation 102 further includes operation 104.

[0072] In operation 104 of method 100, the first pin and the second pin are designated as a first group of pins to be connected together. In some embodiments, the first group of pins (e.g., the first pin and the second pin) are connected together in operation 110 via an APR tool. In some embodiments, by designating the first pin and the second pin as the first group of pins, the APR tool (e.g., operation 110) knows which pins should be connected together in the APR phase.

[0073] In some embodiments, the first set of pins of method 100 includes Figures 7A-7C At least one of group 702a, 702b, 702c, or 702d. In some embodiments, the first group of method 100 includes Figure 9B and Figure 9E Group G1 Figure 10A and Figure 10D Group G2 Figure 11A and Figure 11D Group G3 Figure 12A and Figure 12D Group G4 or Figure 15A and Figure 15D At least one of group G5 and group G6.

[0074] In some embodiments, operation 104 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for specifying the first pin and the second pin as a first set of pins to be connected together. Figure 19 To proceed.

[0075] In some embodiments, the first circuit includes a first pin, a second pin, and a third pin. In some embodiments, the first pin, the second pin, and the third pin of the first circuit are designated as a first set of pins to be connected together. In some embodiments, operation 104 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for designating the first pin, the second pin, and the third pin as a first set of pins to be connected together. Figure 19 ))implement.

[0076] In some embodiments, the first circuit further includes a third pin and a fourth pin. In some embodiments, the third pin and the fourth pin of the first circuit are designated as a second set of pins to be connected together. In some embodiments, the operation 104 of method 100 is performed by a processing device (e.g., processor 1902). Figure 19 The processor is configured to execute instructions that designate the third and fourth pins as a second set of pins to be connected together.

[0077] In some embodiments, the second set of methods 100 includes Figures 7A-7C At least one of groups 702c and 702d. In some embodiments, the second group of method 100 includes Figure 15A and Figure 15D At least one of group G5 and group G6.

[0078] In operation 106 of method 100, a first layout of the first circuit is generated. In some embodiments, the first layout of method 100 corresponds to the layout design of a standard cell.

[0079] In some embodiments, the standard unit of this disclosure includes logic gate units or memory units. In some embodiments, logic gate units include AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, flip-flops, buffers, latches, delay, or clock units. In some embodiments, memory units include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), or read-only memory (ROM). In some embodiments, at least the standard unit of method 100 includes one or more active or passive elements. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, nanosheet transistors, nanowire transistors, complementary field-effect transistors (CFETs), and planar MOS transistors with convex source / drain terminals. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0080] In some embodiments, operations 106 and 108 are referred to as “cell-level stages” because each operation corresponds to the layout design of a single cell and the internal pattern within the corresponding cell. In some embodiments, the layout design of this application is in Graphical Database System (GDSII) file format.

[0081] In some embodiments, the first layout of this disclosure includes Figure 3 Layout 300A. In some embodiments, the first layout of this disclosure includes one or more patterns or layouts, such as Figure 3 Units 320A1, 320A2, 320B-320E, Figure 4 Units 400A-400B or 440A-440E, Figures 7A-7C Layouts 700A-700C Figure 8 Layout 800 Figures 9C-9D The layout of 900C-900D, Figures 10B-10C The layout of 1000B-1000C, Figures 11B-11C The layout of 1100B-1100C, Figures 12B-12C The layout of 1200B-1200C, Figure 13B The layout of 1300B, Figure 14B Layout 1400B or Figures 15B-15C One or more of the layouts 1500B-1500C.

[0082] In some embodiments, operation 106 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for generating a first layout. Figure 19 ))implement.

[0083] In some embodiments, operation 106 further includes operation 108.

[0084] In operation 108 of method 100, at least a first conductive component pattern and a second conductive component pattern are generated.

[0085] In some embodiments, a first conductive component pattern and a second conductive component pattern extend in a first direction X, are located on a first layout layer, and are separated from each other in a second direction Y, which is different from the first direction. In some embodiments, the first layout layer of method 100 includes metal-O (MO). Other layout layers are also within the scope of this disclosure. In some embodiments, the first conductive component pattern and the second conductive component pattern are not connected together. In some embodiments, the first conductive component pattern corresponds to a first pin, and the second conductive component pattern corresponds to a second pin. In some embodiments, the first conductive component pattern and the second conductive component pattern are part of the first layout.

[0086] In some embodiments, the first conductive component pattern of this disclosure includes at least one of the following: Figure 3 Conductive component patterns 302 or 304, Figure 4 Conductive component pattern 402 or 404, Figures 7A-7C Conductive component patterns 704a-704d, 706a-706d or 708a-708d, Figure 8 The conductive component patterns 802 and 804, Figures 9C-9D Conductive component patterns 920a-920e for 10B-10C, 11B-11C, and 12B-12C. Figures 12B-12C Conductive component patterns 1220a-1220e, Figures 13A-13B The conductive component patterns are 1320a-1320b, 1322a, 1324a, 1330a-1330b, 1332a, 1334a, 1340a-1340b, 1342a, and 1344a. Figure 14B Conductive component pattern 1420a-1420e or Figures 15B-15C The conductive component patterns are 1520a-1520d.

[0087] In some embodiments, the second conductive component pattern of this disclosure includes at least one of the following: Figure 3 Conductive component patterns 302 or 304, Figure 4 Conductive component pattern 402 or 404, Figures 7A-7CThe conductive component patterns are 704a-704d, 706a-706d, or 708a-708d. Figure 8 The conductive component patterns 802 and 804, Figures 9C-9D , Figures 10B-10C , Figures 11B-11C , Figures 12B-12C Conductive component patterns 920a-920e, Figures 12B-12C Conductive component patterns 1220a-1220e, Figures 13A-13B The conductive component patterns are 1320a-1320b, 1322a, 1324a, 1330a-1330b, 1332a, 1334a, 1340a-1340b, 1342a, and 1344a. Figure 14B Conductive component pattern 1420a-1420e or Figures 15B-15C The conductive component patterns are 1520a-1520d.

[0088] In some embodiments, operation 108 further includes generating a third conductive component pattern. In some embodiments, the third conductive component pattern corresponds to a third pin.

[0089] In some embodiments, operation 108 further includes generating a fourth conductive component pattern. In some embodiments, the fourth conductive component pattern corresponds to a fourth pin.

[0090] In some embodiments, at least one of the third conductive component pattern and the fourth conductive component pattern of method 100 includes at least one of the following: Figure 3 Conductive component patterns 302 or 304, Figure 4 Conductive component pattern 402 or 404, Figures 7A-7C Conductive component patterns 704a-704d, 706a-706d or 708a-708d, Figure 8 Conductive component patterns 802 and 804, Figures 9C-9D , Figures 10B-10C , Figures 11B-11C , Figures 12B-12C Conductive component patterns 920a-920e, Figures 12B-12C Conductive component patterns 1220a-1220e, Figures 13A-13B The conductive component patterns are 1320a-1320b, 1322a, 1324a, 1330a-1330b, 1332a, 1334a, 1340a-1340b, 1342a, and 1344a. Figure 14B Conductive component pattern 1420a-1420e or Figures 15B-15C The conductive component patterns are 1520a-1520d.

[0091] In some embodiments, operation 108 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for generating at least one of a first conductive component pattern, a second conductive component pattern, a third conductive component pattern, or a fourth conductive component pattern. Figure 19 ))implement.

[0092] In operation 110 of method 100, the first layout is placed in a first area of ​​the layout design by an APR tool. In some embodiments, the APR tool includes... Figure 19 The system.

[0093] In some embodiments, the layout design of this disclosure includes Figure 3 Layout 300 or Figure 4 The layout is 400.

[0094] In some embodiments, the first region of the layout design of this disclosure includes Figure 3 Area 350 or 352 or Figure 4 At least one of regions 450 or 452.

[0095] In some embodiments, operation 110 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for placing a first layout in a first region of the layout design. Figure 19 ))implement.

[0096] In some embodiments, operation 110 further includes operation 112.

[0097] In operation 112 of method 100, the first circuit is changed to the second circuit.

[0098] In some embodiments, the second circuit is a functional version of the first circuit. In some embodiments, one or more disconnected pins in the first circuit are connected together in the second circuit, thereby changing a non-functional circuit (e.g., the first circuit) into a functional circuit (e.g., the second circuit). For example, if the first circuit is a non-functional AND logic gate, then the second circuit is an AND logic gate.

[0099] In some embodiments, the second circuit of method 100 includes Figure 9E Circuit 900E, Figure 10D Circuit 1000D, Figure 11D Circuit 1100D, Figure 12D Circuit 1200D or Figure 15D At least one of the circuits 1500D.

[0100] In some embodiments, operation 112 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for changing the first circuit to the second circuit. Figure 19 To complete this task.

[0101] In some embodiments, operation 112 further includes operation 114.

[0102] In operation 114 of method 100, the first and second pins of the first group of pins are connected together.

[0103] In some embodiments, the first and second pins of the first set of pins are connected together by at least one or more conductive component patterns located in a second layout layer different from the first layout layer. In some embodiments, the second layout layer of method 100 includes metal-1 (M1). Other layout layers are also within the scope of this disclosure. For example, such as Figure 3 As shown, pin PIN1 and pin PIN2 are connected together via conductive component pattern 322, via pattern 324, and via pattern 326. For example, as Figure 3 As shown, pin PIN1 and pin PIN2 are connected together through conductive component pattern 332, through hole pattern 334 and through hole pattern 336.

[0104] In some embodiments, operation 114 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for connecting the first pin and the second pin together. Figure 19 ))implement.

[0105] In some embodiments, the first circuit includes a first pin, a second pin, and a third pin that are electrically disconnected from each other. In some embodiments, operation 114 includes at least connecting the first pin, the second pin, and the third pin of the first circuit to each other. In some embodiments, operation 104 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for connecting the first pin, the second pin, and the third pin together. Figure 19 ))implement.

[0106] In some embodiments, the first circuit further includes a third pin and a fourth pin, which are electrically disconnected from each other. In some embodiments, operation 114 includes connecting the third pin and the fourth pin of the first circuit to each other. In some embodiments, operation 104 of method 100 is performed by a processing device (e.g., processor 1902) configured to execute instructions for connecting the third pin and the fourth pin together. Figure 19 ))implement.

[0107] In operation 116 of method 100, at least the entire integrated circuit is manufactured based on a layout design. In some embodiments, operation 116 of method 100 includes manufacturing at least one mask based on a layout design, and manufacturing an integrated circuit based on the at least one mask. In some embodiments, operation 116 is method 1800 (… Figure 18 One embodiment of ).

[0108] In some embodiments, the entire integrated circuit of this disclosure includes Figure 20 At least the IC device 2060.

[0109] Although method 100 is described as connecting at least one of the first pin, second pin, third pin, or fourth pin together, other numbers of pins connected together are also within the scope of this disclosure.

[0110] In some embodiments, one or more of operations 102, 104, 106, 108, 110, 112, or 116 are not performed.

[0111] In some embodiments, placing the first layout into the layout design using method 100 is a more flexible APR placement scheme compared to other methods.

[0112] Figure 2 This is a flowchart of a method 200 for changing a first circuit to a second circuit according to some embodiments.

[0113] Understandably, in Figure 2 Additional operations may be performed before, during, and / or after the method 200 depicted herein, and some other processes may only be briefly described herein. In some embodiments, method 200 may be used to generate one or more layouts, such as Figure 8 Layout 800 Figure 9D Layout 900D, Figure 10C Layout 1000C, Figure 11C Layout 1100C, Figure 12C Layout 1200C, Figure 13B Layout 1300B Figure 14B Layout 1400B or Figure 15C The layout is 1500C.

[0114] Method 200 is method 100 ( Figure 1 Examples of operations 112 and 114.

[0115] In operation 202 of method 200, a first routing track is selected from the first group of candidate routing tracks.

[0116] In some embodiments, the first set of candidate wiring tracks is in a second layout layer. Other layout layers are within the scope of this disclosure. In some embodiments, the first set of candidate wiring tracks is not occupied by corresponding conductive component patterns in the second layout layer.

[0117] In some embodiments, the first set of candidate wiring tracks extends in the second direction Y. In some embodiments, each wiring track in the first set of candidate wiring tracks is separated from each other in the first direction X.

[0118] In some embodiments, the first set of candidate wiring tracks disclosed herein includes at least one of the following: Figure 3 , Figures 12B-12C and Figure 14B Wiring tracks T1-T3 in Figure 4 and Figure 8 Wiring tracks T1-T7 in the middle Figures 9C-9D , Figures 10B-10C and Figures 11B-11C Wiring tracks T1-T5 or Figures 15B-15C The wiring tracks T1-T10 in the middle.

[0119] In operation 204 of method 200, the first conductive component pattern and the second conductive component pattern are connected together by at least a third conductive component pattern.

[0120] In some embodiments, operation 204 is an embodiment of operation 114 of method 100.

[0121] In some embodiments, the third conductive component pattern extends in the second direction Y, overlaps with the first conductive component pattern and the second conductive component pattern, and is located on the second layout layer.

[0122] In some embodiments, the third conductive component pattern of method 200 includes at least one of the following: Figure 3 Conductive component pattern 322 or 332, Figure 9E , Figure 10C and Figure 11C Conductive component pattern 930a, Figure 12C Conductive component pattern 1230a, Figure 14B Conductive component patterns 1430a, 1430b and 1430c or Figure 15C The conductive component patterns are 1530a and 1530b.

[0123] In some embodiments, operation 204 includes at least one of operations 206, 208, or 210.

[0124] In operation 206 of method 200, the first through-hole pattern is placed above the first conductive component pattern.

[0125] In some embodiments, the first through-hole pattern of method 200 includes Figure 3 The through-hole pattern is 324 or 334. Figure 9E , 10C The through-hole pattern 932a of 11C, Figure 12C Through-hole pattern 1232c or Figure 15C At least one of the through-hole patterns 1532a and 1532c.

[0126] In operation 208 of method 200, the second through-hole pattern is placed above the second conductive component pattern.

[0127] In some embodiments, the second through-hole pattern of method 200 includes Figure 3 Through-hole pattern 326 or 336, Figure 9E , 10C The through-hole pattern 932b of 11C, Figure 12C Through-hole pattern 1232c or Figure 15C At least one of the through-hole patterns 1532b and 1532d.

[0128] At least one of the first via pattern and the second via pattern in method 200 is positioned in the via-0 (V0) layer. In some embodiments, the V0 layer is located between the first layout layer and the second layout layer. In some embodiments, the V0 layer is located between the M0 layer and the M1 layer.

[0129] In operation 210 of method 200, a third conductive component pattern is placed in a first wiring track of a first set of candidate wiring tracks. In some embodiments, the third conductive component pattern overlaps with the first conductive component pattern and the second conductive component pattern.

[0130] In some embodiments, the first via pattern is located between the first conductive component pattern and the third conductive component pattern. In some embodiments, the first via pattern connects the first conductive component pattern and the third conductive component pattern together.

[0131] In some embodiments, the second via pattern is located between the second conductive component pattern and the third conductive component pattern. In some embodiments, the second via pattern connects the second conductive component pattern and the third conductive component pattern together.

[0132] In some embodiments, the third conductive component pattern is placed in the first wiring track of the first set of candidate wiring tracks. In some embodiments, by placing the third conductive component pattern in the first wiring track, the third conductive component pattern is successfully placed in an unoccupied wiring track in the second layout layer because it is already in the first wiring track and in the second layout layer (in... Figures 3-4(Discussed in more detail below) There is no conflict, thus reducing the need to perform rerouting when placing cells in the layout design.

[0133] In some embodiments, placing the first layout into the layout design using methods 100-200 is a more flexible APR placement scheme compared to other methods.

[0134] In some embodiments, method 200 is repeated to interconnect the third and fourth pins of the first circuit (as discussed above for operation 114).

[0135] While method 200 is described as connecting at least one of a first conductive component pattern (e.g., a first pin) and a second conductive component pattern (e.g., a second pin), connecting other numbers of conductive component patterns (e.g., pins) together is within the scope of this disclosure. For example, in some embodiments, operation 114 includes at least interconnecting a first pin, a second pin, and a third pin of a first circuit. In these embodiments, method 200 also includes placing a third via pattern, such as... Figure 12C The through-hole pattern is 1232c.

[0136] In some embodiments, one or more of operations 202, 204, 206, 208, or 210 are not performed. In some embodiments, the order of other operations of method 200 is within the scope of this disclosure. Method 200 includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be combined, divided, added, replaced, reordered, and / or eliminated as appropriate, according to the spirit and scope of the disclosed embodiments.

[0137] In some embodiments, one or more of operations 202-210 of method 200 are performed by a processing device (e.g., processor 1902) configured to execute instructions for changing the first circuit to the second circuit. Figure 19 ))implement.

[0138] Figure 3 This is a schematic diagram of a corresponding layout 300 of an integrated circuit according to some embodiments.

[0139] In some embodiments, layout 300 is a non-limiting instance of one or more operations of methods 100-200.

[0140] In some embodiments, layout 300 is a non-limiting instance of operations 106 and 110 of method 100. For example, according to some embodiments, layout 300A is placed in region 350 of portion 301A by operation 110 of method 100, and layout 300A is placed in region 352 of portion 301B by operation 110 of method 100.

[0141] In some embodiments, layout 300A corresponds to the first layout after operation 106 of method 100, and each of portions 301A-301B corresponds to the layout design after operation 110 of method 100.

[0142] Layout 300 includes layout 300A, and portions 301A and 301B. Portion 301A includes elements 320A1 and 320B-320E. Portion 301B includes elements 320A2 and 320B-320E.

[0143] Layout 300A includes conductive component patterns 302 and 304 extending in a first direction X and separated from each other in a second direction Y. Conductive component patterns 302 and 304 are located in a first layout layer.

[0144] Conductive component pattern 302 is the first conductive component pattern of methods 100-200, therefore a similar detailed description is omitted. Conductive component pattern 302 corresponds to the first pin of methods 100-200, therefore a similar detailed description is omitted.

[0145] Conductive component pattern 304 is the second conductive component pattern of methods 100-200, therefore a similar detailed description is omitted. Conductive component pattern 304 corresponds to the second pin of methods 100-200, therefore a similar detailed description is omitted.

[0146] Layout 300A also includes a conductive component pattern 306 extending in the second direction Y and overlapping with the conductive component pattern 304. The conductive component layout pattern 306 is on the second layout layer and in the wiring track T3.

[0147] Layout 300A also includes region 308, in which additional conductive component patterns can be placed in wiring tracks T1-T2. In some embodiments, region 308 corresponds to the area where one or more disconnected pins of methods 100-200 will be located. In some embodiments, region 308 is also referred to as the unused M1 region.

[0148] In some embodiments, each of units 320A1, 320A2, and 320B-320E corresponds to a standard unit region of the layout design following operation 110 of method 100. Units 320B-320E are adjacent to units 320A1 and 320A2. Units 320A1 and 320A2 are located in the central region of units 320B-320E. In other words, units 320A1 and 320A2 are surrounded or encapsulated by units 320B-320E.

[0149] Conductive component patterns 322 and 332 are the third conductive component patterns of method 200, and therefore similar detailed descriptions are omitted. Through-hole patterns 324 and 334 are the first through-hole patterns of method 200, and similar detailed descriptions are therefore omitted. Through-hole patterns 326 and 336 are the second through-hole patterns of method 200, and similar detailed descriptions are therefore omitted.

[0150] During the execution of methods 100 and 200, after operation 106 of method 100, layout 300A is generated as a first layout. Then, in operation 110, layout 300A is placed in region 350 of portion 301A by the APR tool, and layout 300A is placed in region 352 of portion 301B by the APR tool.

[0151] Section 301A includes a conductive component pattern 321 extending in the second direction Y and on the second layout layer. The conductive component pattern 321 is similar to conductive component pattern 322, and therefore a similar detailed description is omitted. The conductive component pattern 321 extends through units 320B, 320E, and 320A1. In some embodiments, during placement and routing, the APR tool is configured to automatically place the conductive component pattern 321 in routing track T1 of section 301A. During operation 202, since routing track T2 of section 301A is not occupied by the conductive component pattern, routing track T2 is selected as the first routing track from candidate routing track groups T1-T3. During operation 202, since routing track T1 in section 301A is occupied by the conductive component pattern 321, routing track T1 is not selected as the first routing track from candidate routing track groups T1-T3.

[0152] Subsequently, in operation 206, the through-hole pattern 324 is placed above the conductive component pattern 322. Then, in operation 208, the through-hole pattern 326 is placed above the conductive component pattern 322. Finally, in operation 210, the conductive component pattern 322 is placed in the wiring track T2.

[0153] Part 301B includes a conductive component pattern 331 extending in the second direction Y and on the second layout layer. The conductive component pattern 331 is similar to the conductive component pattern 332, and therefore a similar detailed description is omitted. The conductive component pattern 331 extends through units 320B, 320E, and 320A2. In some embodiments, during placement and routing, the APR tool is configured to automatically place the conductive component pattern 331 in routing track T2 of part 301B. During operation 202, routing track T1 in part 301B is selected as the first routing track from candidate routing track groups T1-T3 because it is not occupied by the conductive component pattern. During operation 202, routing track T2 in part 301B is not selected as the first routing track from candidate routing track groups T1-T3 because it is occupied by the conductive component pattern 331.

[0154] Subsequently, in operation 206, the through-hole pattern 334 is placed above the conductive component pattern 322. Subsequently, in operation 208, the through-hole pattern 336 is placed above the conductive component pattern 322. Subsequently, in operation 210, the conductive component pattern 332 is placed in the wiring track T1.

[0155] In some embodiments, layout 300A increases wiring flexibility and has a more flexible design because, compared to other methods that have a fixed conductive component pattern in the second layout layer and use a different layout design for each different occupied wiring track, the candidate wiring tracks for conductive components 322 or 332 can be adjusted based on available or unoccupied wiring tracks.

[0156] In some embodiments, by disconnecting the first and second pins within the first circuit, the first layout of the first circuit is more flexible because during the APR phase of operation 110, a third conductive pattern that connects the first and second pins together can be placed in some unoccupied wiring tracks. In contrast, in other methods, a conductive pattern that connects the first and second pins together is in a fixed wiring track, which may conflict with another conductive pattern that is already in a fixed wiring track, thus causing rewiring when placing cells in the layout design.

[0157] Other variations in the implementation of methods 100-200 are within the scope of this disclosure.

[0158] In some embodiments, layout 300 achieves one or more of the benefits discussed above.

[0159] The number of elements in other configurations, arrangements, or layouts 300 on other layout layers is within the scope of this disclosure.

[0160] Figure 4 This is a schematic diagram of a corresponding layout 400 of an integrated circuit according to some embodiments.

[0161] In some embodiments, layout 400 is yet another non-limiting instance of one or more operations of methods 100-200.

[0162] In some embodiments, layout 400 is a non-limiting instance of operations 106 and 110 of method 100. For example, according to some embodiments, layout 400A is placed in region 450 of unit 440B by operation 110 of method 100, and layout 400A is placed in region 452 of unit 440D by operation 110 of method 100.

[0163] In some embodiments, layout 400A corresponds to the first layout following operation 106 of method 100. Layout 400B corresponds to a layout not generated by method 100. For example, layout 400B includes a first pin (e.g., conductive component pattern 402a) and a second pin (e.g., conductive component pattern 404b) connected together.

[0164] Layout 400 includes layout 400A, layout 400B and cells 440A-440E.

[0165] Layout 400A includes conductive component pattern 402a and conductive component pattern 404a.

[0166] Layout 400B includes conductive component pattern 402b, conductive component pattern 404b and conductive component pattern 410.

[0167] Conductive component patterns 402a and 402b are similar to conductive component pattern 302, conductive component patterns 404a and 404b are similar to conductive component pattern 304, and conductive component pattern 410 is similar to conductive component pattern 322, therefore similar detailed descriptions are omitted.

[0168] Conductive component pattern 402a is the first conductive component pattern of method 100-200, and conductive component pattern 404a is the second conductive component pattern of method 100-200; therefore, a similar detailed description is omitted. Conductive component pattern 402a corresponds to the first pin of method 100-200, and conductive component pattern 404a corresponds to the second pin of method 100-200; therefore, a similar detailed description is omitted.

[0169] Layout 400A also includes areas where additional conductive component patterns can be placed in wiring tracks T1-T7.

[0170] Layout 400B also includes areas where additional conductive component patterns can be placed in wiring tracks T1-T2 and T4-T7. The conductive component layout pattern 410 is on the second layout layer and in wiring track T3.

[0171] In some embodiments, each of the units 440A-440E corresponds to a standard unit area of ​​the layout design following operation 110 of method 100.

[0172] Unit 440B includes a fixed power rail pattern 420 in track T3. Unit 440D includes a fixed power rail pattern 420 in track T6.

[0173] During the execution of methods 100 and 200, after operation 106 of method 100, layout 400A is generated as the first layout.

[0174] Subsequently, in operation 110, layout 400A is placed in region 450 of cell 440B by the APR tool because the fixed power track pattern 420 in track T3 does not conflict with other conductive component patterns in the second layout layer of layout 400A. In other words, layout 400A does not include conductive component patterns located within wiring tracks T1-T7 in the second layout layer, therefore no conductive component patterns in the second layout layer of layout 400A conflict with the fixed power track pattern 420 in track T3.

[0175] Subsequently, in operation 110, layout 400A is placed in region 452 of cell 440D by the APR tool because the fixed power track pattern 420 in track T6 does not conflict with other conductive component patterns in the second layout layer of layout 400A. In other words, layout 400A does not include conductive component patterns located within wiring tracks T1-T7 in the second layout layer, therefore no conductive component patterns in the second layout layer of layout 400A conflict with the fixed power track pattern 420 in track T6.

[0176] Layout 400B can be placed in region 452 of cell 440B because the fixed power track pattern 420 in track T6 does not conflict with the conductive component pattern 410 of layout 400B. However, layout 400B cannot be placed in region 450 of cell 440B because the fixed power track pattern 420 in track T3 conflicts with the conductive component pattern 410 of layout 400B. In these methods, to overcome the conflict between the wiring track occupied in the second layout layer and the conductive component pattern in layout 400B, electrically equivalent (EEQ) cells are generated to mimic the function of layout 400B, but the conductive component pattern 410 is moved to another wiring track in the first direction X. However, using EEQ cells drastically increases the size of the standard cell library.

[0177] In some embodiments, by using methods 100-200, this disclosure reduces the size of the standard cell library by not generating EEQ cells. In some embodiments, reducing the size of the standard cell library results in the standard cell library occupying less storage compared to other methods (e.g., Figure 19 (Memory 1904). In some embodiments, by occupying less storage, Figure 19 The system exhibits improved performance compared to other methods because... Figure 19 The system has more available storage for other applications. In some embodiments, the time to generate each standard cell in the standard cell library is reduced due to the smaller size of the standard cell library, thus compared to other methods, Figure 19 The performance of System 19 has been improved.

[0178] In some embodiments, layout 400A of layout 400 increases wiring flexibility and has a more flexible design because, compared to layout 400B, which has a fixed conductive component pattern 410 and uses a different layout design / EEQ for each different occupied wiring track, the conductive component pattern connecting conductive component patterns 402a and 404a can be adjusted according to available or unoccupied wiring tracks. In some embodiments, layout 400A can achieve 100% placement flexibility without using additional EEQ units.

[0179] In some embodiments, layout 400A of layout 40 achieves one or more of the advantages discussed above.

[0180] The number of other configurations, arrangements, or elements of layout 400 on other layout layers is within the scope of this disclosure.

[0181] Figure 5 This is a flowchart of a method 500 for designating a first pin and a second pin as a first set of pins to be connected together, according to some embodiments.

[0182] Method 500 is Method 100 ( Figure 1 Example of operation 104.

[0183] Understandably, in Figure 5 Additional operations may be performed before, during, and / or after the method 500 described herein, so only a few other processes will be briefly described here. In some embodiments, method 500 may be used to designate a first pin and a second pin as a first set of pins to be connected together, such as... Figures 7A-7C Groups 702a, 702b, 702c or 702d Figure 9B and 9E Group G1 Figure 10A and Figure 10DGroup G2 Figure 11A and Figure 11D Group G3 Figure 12A and Figure 12D Group G4 or Figure 15A and Figure 15D At least one of groups G5 and G6.

[0184] In operation 502 of method 500, the first pin and the second pin are designated or marked with a common label and are designated as a first group of pins to be connected. In some embodiments, the first pin and the second pin are designated or marked with a common label and are designated as a first group of pins to be connected so that the APR tool in operation 110 knows which pins should be connected together.

[0185] In some embodiments, the common tag of method 500 includes at least one of the following: Figure 7A and Figure 7C Pin label B in Figure 7A and Figure 7C Pin label C in Figures 9B-9E Pin label MJ1 Figures 11A-11D The pin label MJ3 in Figures 12A-12D The pin label MJ4 or Figures 15A-15D The pin label is MJ5 or MJ6.

[0186] In some embodiments, the first set of pins to be connected in method 500 includes at least one of the following: Figure 7A Pins 704a and 706a, Figure 7C Pins 704c and 706c, Figure 7C Pins 704d and 706d, Figures 9B-9E Pins JP1-JP2, Figures 11A-11D Pins JP3-JP4, Figures 12A-12D Pins JP5-JP7, Figures 13A-13B The pins +IN, +Internal, and +Z, or Figures 15A-15D Pins JP13-JP17.

[0187] In operation 504 of method 500, the first group of pins to be connected is designated as the first group of pins to be connected. In some embodiments, the first group of pins to be connected is designated as the first group of pins to be connected together, so that the APR tool in operation 110 knows which pins should be connected together.

[0188] In some embodiments, Figure 7A The layout of 700A and Figure 7C Layout 700C illustrates a non-restrictive instance of method 500.

[0189] Although method 500 is described as designating a first pin and a second pin as a first group of pins to be connected together, other numbers of pins may be designated as a first group of pins to be connected together and are within the scope of this disclosure.

[0190] In some embodiments, method 500 achieves one or more of the benefits discussed within the scope of this disclosure.

[0191] Figure 6 This is a flowchart of a method 600 for designating a first pin and a second pin as a first set of pins to be connected together, according to some embodiments.

[0192] Method 600 is method 100 ( Figure 1 The embodiment of operation 104. It is understood that, in Figure 6 Additional operations may be performed before, during, and / or after the method 600 described herein, so only a few other processes will be briefly described here. In some embodiments, method 600 may be used to designate a first pin and a second pin as a first set of pins to be connected together, such as... Figures 7A-7C Groups 702a, 702b, 702c or 702d Figure 9B and Figure 9E Group G1 Figure 10A and Figure 10D Group G2 Figure 11A and Figure 11D Group G3 Figure 12A and Figure 12D Group G4 or Figure 15A and Figure 15D At least one of groups G5 and G6.

[0193] In operation 602 of method 600, the first pin is designated or marked as the first pin to be connected, and the second pin is designated or marked as the second pin to be connected.

[0194] In some embodiments, a first label is used to designate or mark a first pin, and a second label is used to designate or mark a second pin, so that the APR tool in operation 110 knows the label or name of the pins that should be connected together.

[0195] In some embodiments, the first label of method 500 includes Figure 7B Pin label B in Figures 10A-10E Pin label MJ1 Figure 14B At least one of the pin labels JP8, JP9, JP10, JP11 or JP12.

[0196] In some embodiments, the second label of method 500 includes Figure 7B Pin label C in Figures 10A-10EThe pin label MJ2 or Figure 14B The pin label is at least one of JP8, JP9, JP10, JP11 or JP12.

[0197] In operation 604 of method 600, the first pin to be connected and the second pin to be connected are designed as a first group of pins to be connected. In some embodiments, the first pin to be connected and the second pin to be connected are designed as a first group of pins to be connected so that the APR tool in operation 110 knows which area of ​​the layout includes the pins that should be connected together.

[0198] In some embodiments, the first set of pins to be connected in method 600 includes Figure 7B Pins 704b and 706b Figures 10A-10E Pins JP1-JP2 or Figure 14B At least one of the pins JP8, JP9, JP10, JP11 and JP12.

[0199] In operation 606 of method 600, a first group of pins to be connected is designated as the first group of pins to be connected. In some embodiments, the first group of pins to be connected is designated as the first group of pins to be connected together so that the APR tool in operation 110 knows which pins should be connected together.

[0200] In some embodiments, Figure 7B Layout 700B illustrates a non-restrictive instance of method 600.

[0201] Although method 600 is described as designating a first pin and a second pin as a first group of pins to be connected together, other numbers of pins may be designated as a first group of pins to be connected together, and are within the scope of this disclosure.

[0202] In some embodiments, method 600 achieves one or more of the benefits discussed within the scope of this disclosure.

[0203] Figures 7A-7C These are corresponding schematic diagrams of the layouts 700A-700C of integrated circuits according to some embodiments.

[0204] In some embodiments, layouts 700A-700C are non-limiting instances of one or more operations of methods 500-600.

[0205] In some embodiments, layout 700A is a non-limiting instance of method 500. For example, according to some embodiments, layout 700A corresponds to the layout of the first set of pins to be connected together after operation 504 of method 500.

[0206] In some embodiments, layout 700B is a non-limiting instance of method 600. For example, according to some embodiments, layout 700B corresponds to the layout of the first set of pins to be connected together after operation 506 of method 500.

[0207] In some embodiments, layout 700C is a non-limiting instance of methods 500 and 600. For example, according to some embodiments, layout 700C corresponds to the layout of a first set of pins to be connected together after operation 504 of method 500, and the layout of a second set of pins to be connected together after operation 606 of method 600.

[0208] Layout 700A includes conductive component patterns 704a, 706a, and 708a. In some embodiments, conductive component patterns 704a, 706a, and 708a are similar to conductive component patterns 302 or 304, and therefore such detailed descriptions are omitted.

[0209] Conductive component pattern 704a corresponds to the first pin of methods 100-200 and 500, and conductive component pattern 706a corresponds to the second pin of methods 100-200 and 500; therefore, similar detailed descriptions are omitted. Conductive component pattern 704a is the first conductive component pattern of methods 100-200 and 500, and conductive component pattern 706a is the second conductive component pattern of methods 100-200 and 500; therefore, similar detailed descriptions are omitted.

[0210] During the execution of method 500, in operation 502, conductive component pattern 704a (e.g., first pin) and conductive component pattern 704a (e.g., second pin) are designated or marked with a common label (e.g., "B") as the first group of pins to be connected. Subsequently, in operation 504, the first group of pins to be connected is designated as the first group of pins 702a that will be connected together.

[0211] Layout 700B includes conductive component patterns 704b, 706b, and 708b. In some embodiments, conductive component patterns 704b, 706b, and 708b are similar to conductive component patterns 302 or 304, and therefore such detailed descriptions are omitted.

[0212] Conductive component pattern 704b corresponds to the first pin of methods 100-200 and 600, conductive component pattern 706b corresponds to the second pin of methods 100-200 and 600, and conductive component pattern 708b corresponds to the third pin of methods 100-200 and 600; therefore, similar detailed descriptions are omitted. Conductive component pattern 704b is the first conductive component pattern of methods 100-200 and 600, conductive component pattern 706b is the second conductive component pattern of methods 100-200 and 600, and conductive component pattern 708b is the third conductive component pattern of methods 100-200 and 600; therefore, similar detailed descriptions are omitted.

[0213] During the execution of method 600, in operation 602, conductive component pattern 704b (e.g., a first pin) is designated or marked as a first pin to be connected using a label (e.g., "B"), conductive component pattern 706b (e.g., a second pin) is designated or marked as a second pin to be connected using a label (e.g., "C"), and conductive component pattern 708b (e.g., a third pin) is designated or marked as a third pin to be connected using a label (e.g., "A"). Then, in operation 604 of method 600, the first pin to be connected, the second pin to be connected, and the third pin to be connected are designed as a first group of pins to be connected. Then, in operation 606, the first group of pins to be connected is designated as a first group of pins 702b to be connected together.

[0214] Layout 700C includes conductive component patterns 704c, 706c, and 708c. In some embodiments, conductive component patterns 704c, 706c, and 708c are similar to conductive component patterns 302 or 304, and therefore similar detailed descriptions are omitted.

[0215] Conductive component pattern 704c corresponds to the first pin of methods 100-200 and 500, and conductive component pattern 706c corresponds to the second pin of methods 100-200 and 500; therefore, similar detailed descriptions are omitted. Conductive component pattern 704c is the first conductive component pattern of methods 100-200 and 500, and conductive component pattern 706c is the second conductive component pattern of methods 100-200 and 500; therefore, similar detailed descriptions are omitted.

[0216] During the execution of method 500, in operation 502, conductive component pattern 704c (e.g., first pin) and conductive component pattern 704c (e.g., second pin) are designated or marked with a common label (e.g., "B") as the first group of pins to be connected. Subsequently, in operation 504, the first group of pins to be connected is designated as the first group of pins 702c that will be connected together.

[0217] Layout 700C also includes conductive component patterns 704d, 706d, and 708d. In some embodiments, conductive component patterns 704d, 706d, and 708d are similar to conductive component patterns 302 or 304, and therefore similar detailed descriptions are omitted.

[0218] Conductive component pattern 704d corresponds to the first pin of methods 100-200 and 600, conductive component pattern 706d corresponds to the second pin of methods 100-200 and 600, and conductive component pattern 708d corresponds to the third pin of methods 100-200 and 600; therefore, similar detailed descriptions are omitted. Conductive component pattern 704d is the first conductive component pattern of methods 100-200 and 600, conductive component pattern 706d is the second conductive component pattern of methods 100-200 and 600, and conductive component pattern 708d is the third conductive component pattern of methods 100-200 and 600; therefore, similar detailed descriptions are omitted.

[0219] During the execution of method 600, in operation 602, conductive component pattern 704d (e.g., a first pin) is designated or marked as a first pin to be connected using a label (e.g., "C"), conductive component pattern 706d (e.g., a second pin) is designated or marked as a second pin to be connected using a label (e.g., "D"), and conductive component pattern 708d (e.g., a third pin) is designated or marked as a third pin to be connected using a label (e.g., "C"). Then, in operation 604 of method 600, the first pin to be connected, the second pin to be connected, and the third pin to be connected are designed as a second set of pins to be connected. Then, in operation 606, the second set of pins to be connected is designated as a second set of pins 702d to be connected together.

[0220] Other configurations of layouts 700A-700C are within the scope of this disclosure.

[0221] In some embodiments, layouts 700A-700C implement one or more of the benefits discussed in this disclosure.

[0222] Figure 8 This is a schematic diagram of the layout 800 of an integrated circuit according to some embodiments.

[0223] In some embodiments, layout 800 is yet another non-limiting instance of one or more operations of methods 100-200.

[0224] In some embodiments, layout 800 corresponds to the first layout following operation 106 of method 100.

[0225] In some embodiments, layout 800 is a non-limiting instance of the first routing track in operation 202 of method 200, which selects the first routing track from the first group of candidate routing tracks, and therefore a similar detailed description is omitted. For example, according to some embodiments, layout 800 corresponds to the first layout after operation 106 of method 100, and then the APR tool selects the first routing track from the first group of candidate routing tracks as the selected routing track according to the design criteria in operation 202 of method 200, and then the APR tool places the third conductive component pattern from operation 210 of method 200 into the selected routing track.

[0226] The layout 800 includes conductive component pattern 802, conductive component pattern 804, conductive component pattern 840, conductive component pattern 844, conductive component pattern 846 and conductive component pattern 850.

[0227] Conductive component patterns 802 and 804 and Figure 4 The conductive component patterns 404a and 404b are similar, and the conductive component layout patterns 840, 844, 846, and 850 are similar to... Figure 4 The layout pattern of the conductive components is similar to that of pattern 420, so a similar detailed description is omitted.

[0228] Conductive component pattern 802 is the first conductive component pattern of method 100-200, and conductive component pattern 804 is the second conductive component pattern of method 100-200; therefore, a similar detailed description is omitted. Conductive component pattern 802 corresponds to the first pin of method 100-200, and conductive component pattern 804 corresponds to the second pin of method 100-200; therefore, a similar detailed description is omitted.

[0229] Layout 800 also includes wiring tracks T1-T7. In some embodiments, wiring tracks T2-T3 and T5 correspond to the first set of candidate wiring tracks of method 200, so a similar detailed description is therefore omitted.

[0230] Conductive component layout pattern 850 is on the second layout layer and in wiring track T4. Conductive component layout pattern 840 is on the second layout layer and in wiring track T1. Conductive component layout pattern 844 is on the second layout layer and in wiring track T6. Conductive component layout pattern 846 is on the second layout layer and in wiring track T7.

[0231] Additional conductive component patterns in the second layout layer can be placed in routing tracks T2-T3 and T5 because they are not occupied by conductive component patterns in the second layout layer. However, the first routing track in operation 202 of method 200, which selects the first set of candidate routing tracks, is based on design criteria. In some embodiments, design criteria include an APR tool configured to select performance, power, area (PPA), or routerbility based on cell usage. In other words, according to some embodiments, the APR tool is configured to weigh the PPA and routerbility of the layout.

[0232] For example, if layout 800 includes a low number of occupied M1 routing tracks (LNs), then in operation 202, a larger number of unoccupied M1 routing tracks are available to select the first routing track from the first group of candidate routing tracks. Then, during operation 202, the EDA tool is configured to prioritize PPA over routing availability to optimize PPA. In some embodiments, a low number of occupied M1 routing tracks (LNs) means that less than half the total number of routing tracks are considered as occupied M1 routing tracks.

[0233] In some embodiments, when the EDA tool prioritizes PPA over routing capability, the EDA tool is configured to reduce the wiring tracks of capacitors in the M1 layer by maximizing the distance between the conductive component pattern (e.g., the third conductive component pattern) placed in operation 210 and the existing conductive component pattern (e.g., conductive component pattern 850) in the second layout layer. For example, as Figure 8 As shown, the distance D1 between routing track T2 and occupied routing track T4 is greater than the distance D2 between occupied routing track T4 and routing tracks T3 and T5. Therefore, according to some embodiments, in this non-limiting example, if PPA is prioritized over routing availability by the EDA tool for layout 800, then the EDA tool is configured to select routing track T2 to optimize PPA and reduce the capacitance between conductive component pattern 850 and the conductive component pattern (e.g., a third conductive component pattern) to be placed in routing track T2.

[0234] For example, in some embodiments, when the EDA tool prioritizes PPA over routerability, the EDA tool is configured to select a routing track that is not adjacent to an occupied routing track in the M1 layer (e.g., an existing conductive part pattern (e.g., conductive part pattern 850)).

[0235] For example, if layout 800 includes a high number of occupied M1 routing tracks (HN), a smaller number of unoccupied M1 routing tracks can be used as the first routing track in selecting the first group of candidate routing tracks in operation 202. Then, during operation 202, the EDA tool is configured to prioritize routing availability over PPA to ensure adequate routing of the layout. In some embodiments, occupied M1 routing tracks with a high number of HN are units that include more than half the total number of routing tracks. In some embodiments, the high number of HN occupying M1 routing tracks is greater than the low number of LN occupying M1 routing tracks.

[0236] In some embodiments, when the EDA tool prioritizes wiredability over PPA, the EDA tool is configured to select a wiring track immediately adjacent to an occupied wiring track in the M1 layer (e.g., an existing conductive component pattern (e.g., conductive component pattern 850)). In these embodiments, when the EDA tool prioritizes wiredability over PPA, the wiredability of the conductive component pattern in the M1 layer is prioritized over the capacitance from the M1 layer. For example, according to some embodiments, if for layout 800, when the EDA tool prioritizes wiredability over PPA, then the EDA tool is configured to select wiring track T3 or T5 instead of wiring track T2 to provide more M1 layer wiring options in layout 800, and the conductive component pattern (e.g., a third conductive component pattern) will be placed on wiring track T3 or T5.

[0237] In some embodiments, by utilizing ten components and methods 100-200 of layout 800, this disclosure is able to select PPA or routableness based on cell usage, whereas other methods select M1 placement with optimal PPA at the cell level, making routing at the APR level more difficult than this disclosure.

[0238] Other configurations of layout 800 are within the scope of this disclosure.

[0239] In some embodiments, layout 800 achieves one or more advantages discussed within the scope of this disclosure.

[0240] Figure 9A This is a circuit diagram of an integrated circuit 900A according to some embodiments. Figure 9B This is a circuit diagram of an integrated circuit 900B according to some embodiments. Figure 9C This is a diagram of the layout 900C of an integrated circuit 900B according to some embodiments. Figure 9D This is a diagram of the layout 900D of an integrated circuit 900E according to some embodiments. Figure 9E This is a circuit diagram of an integrated circuit 900E according to some embodiments. Figure 9FThis is a diagram of the Verilog netlist 900F of the integrated circuit 900B according to some embodiments. Figure 9G This is a cross-sectional view of an integrated circuit 900D according to some embodiments.

[0241] Figure 9A This is a circuit diagram of an integrated circuit 900A according to some embodiments.

[0242] In some embodiments, integrated circuit 900A is an AND gate. The AND gate is used for illustration; other types of circuits are within the scope of this disclosure.

[0243] Integrated circuit 900A includes PMOS transistors P1, P2, and P3 connected to NMOS transistors N1, N2, and N3.

[0244] The gate terminal of PMOS transistor P1 is connected to the gate terminal of NMOS transistor N1 and is configured as input node A1. The gate terminal of PMOS transistor P2 is connected to the gate terminal of NMOS transistor N2 and is configured as input node A2.

[0245] The source terminals of PMOS transistors P1 and P2 are connected to the voltage supply VDD. The source terminal of NMOS transistor N2 is connected to the reference voltage supply VSS. The source terminals of NMOS transistor N1 and NMOS transistor N2 are interconnected.

[0246] The drain terminals of PMOS transistor P1, PMOS transistor P2, NMOS transistor N1, PMOS transistor P3, and NMOS transistor N3 are all connected together.

[0247] The drain terminals of PMOS transistor P3 and NMOS transistor N3 are connected together and configured as output node Z. The source terminal of PMOS transistor P3 is connected to the voltage supply VDD. The source terminal of NMOS transistor N3 is connected to the reference voltage supply VSS.

[0248] PMOS transistor P3 and NMOS transistor N3 are connected to the output node Z. PMOS transistor P3 and NMOS transistor N3 are inverters (unlabeled). The gate terminals of PMOS transistor P3 and NMOS transistor N3 are connected together and configured as the input nodes of the inverter.

[0249] In some embodiments, one or more drains or sources can be used interchangeably.

[0250] Figure 9BThis is a circuit diagram of an integrated circuit 900B according to some embodiments.

[0251] Integrated circuit 900B is Figure 9A The NOT function representation of an AND gate. The 900B integrated circuit is... Figures 1-2 An embodiment of the first circuit of method 100-200. In some embodiments, integrated circuit 900B is composed of... Figure 9E Generate the Verilog netlist 900E.

[0252] The integrated circuit 900B includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP1-JP2, group G1 and pin label MJ1.

[0253] Integrated circuit 900B is Figure 9A This is a variant of the 900A integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 9A Compared to the 900A integrated circuit, Figure 9B The drain of NMOS transistor N1 is not connected to the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, or the gate terminal of NMOS transistor N3.

[0254] Integrated circuit 900B corresponds to Figure 1 Method 100 is the first circuit following operation 104, therefore a similar detailed description is omitted. Integrated circuit 900B corresponds to Figure 5 Method 500 is the first circuit after operation 504, therefore a similar detailed description is omitted.

[0255] Pin JP1 corresponds to the first pin of methods 100-200 and 500, and is a pin or node of the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N3.

[0256] Pin JP2 corresponds to the second pin of methods 100-200 and 500, and is the drain pin or node of NMOS transistor N1.

[0257] The pin label MJ1 corresponds to the common label of method 500, so a similar detailed description is omitted.

[0258] Group G1 corresponds to the first group of pins in methods 100 and 500, so a similar detailed description is omitted.

[0259] During the execution of method 500, in operation 502, pins JP1 and JP2 are designated or marked with a common label (e.g., pin label MJ1) and designated as the first group of pins to be connected. Subsequently, in operation 504, the first group of pins to be connected is designated as the first group of pins to be connected together (e.g., group G1).

[0260] Figure 9C This is a schematic diagram of the layout 900C of an integrated circuit 900B according to some embodiments.

[0261] The layout of 900C is Figures 1-2 An embodiment of the first layout of method 100-200. In some embodiments, layout 900C is based on a schematic diagram of integrated circuit 900B or Figure 9E The Verilog netlist 900E is generated. In some embodiments, the layout 900C is stored in... Figure 19 The standard unit library is in 1920.

[0262] Layout 900C corresponds to in Figure 1 The first layout following at least one of operations 106 or 108 in method 100 is therefore omitted in a similar detailed description.

[0263] In some embodiments, layout 900C can be used to manufacture integrated circuits, such as... Figure 9G 900G or integrated circuit Figure 20 IC device 2060.

[0264] Layout 900C includes one or more components such as an oxide diffusion (OD) layer or active layer, a gate (POLY) layer, a metal over diffusion (MD) layer, a metal 0 (MO) layer, a via (VG) above the gate layer, and a via (VD) above the diffusion layer. For clarity, components of other layers are not shown.

[0265] The layout 900C includes one or more active region patterns 902a or 902b extending in the first direction X (collectively referred to as the “active region pattern group 902”).

[0266] The active region patterns 902a and 902b of the active region pattern group 902 are separated from each other in the second direction Y. In some embodiments, the active region pattern group 902 can be used to manufacture a corresponding active region group. The active patterns 902a and 902b can be used to manufacture the corresponding active regions 902a' and 902b' of the integrated circuit 900E.

[0267] In some embodiments, the active region pattern group 902 is referred to as an oxide diffusion (OD) region that defines the source or drain diffusion region of an integrated circuit.

[0268] In some embodiments, the active region pattern 902a of the active region pattern group 902 can be used to manufacture the source and drain regions of the PMOS transistors of integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D, and the active region pattern 902b of the active region pattern group 902 can be used to manufacture the source and drain regions of the NMOS transistors of integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D.

[0269] In some embodiments, the active region pattern 902b of the active region pattern group 902 can be used to manufacture the source and drain regions of the PMOS transistors of integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A or 1500D, and the active region pattern 902a of the active region pattern group 902 can be used to manufacture the source and drain regions of the NMOS transistors of integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A or 1500D.

[0270] In some embodiments, the active area pattern group 902 is located on a third layout layer. In some embodiments, the third layout layer corresponds to an active layer or an OD layer. In some embodiments, the third layout layer is below the first and second layout layers.

[0271] In some embodiments, the active region pattern 902a can be used to fabricate the source and drain regions of one or more p-type finFET transistors, p-type nanosheet transistors, or p-type nanowire transistors, and the active region layout pattern 902b can be used to fabricate the source and drain regions of one or more n-type finFET transistors, n-type nanosheet transistors, or n-type nanowire transistors.

[0272] In some embodiments, the active region pattern 902b can be used to fabricate the source and drain regions of one or more n-type finFET transistors, n-type nanosheet transistors, or n-type nanowire transistors, and the active region layout pattern 902a can be used to fabricate the source and drain regions of one or more p-type finFET transistors, p-type nanosheet transistors, or p-type nanowire transistors.

[0273] Other configurations, arrangements, or number of patterns in other layout layers of the active area pattern group 902 are within the scope of this disclosure.

[0274] The layout 900C also includes one or more gate patterns 904a, 904b, 904c or 904d (collectively referred to as “gate pattern group 904”) extending along the second direction Y. Each gate pattern pattern 904 of the gate group is spaced apart from the adjacent gate pattern of the gate group pattern 904 by a pitch (not marked) in the first direction X.

[0275] Gate pattern group 904 can be used to manufacture corresponding gate groups for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A or 1500D.

[0276] In some embodiments, Figures 9C-9D , Figures 10B-10C , Figures 11B-11C , Figures 12B-12C or Figures 15B-15C The diagram shows each gate pattern in gate pattern group 904, and is labeled "P1 to P3" and "N1 to N3" to identify them. Figures 9A-9B , Figure 9E , Figure 10A , Figure 10D , Figure 11A , Figure 11D , Figure 12A , Figure 12D , Figure 15A or Figure 15D The corresponding transistors manufactured from the corresponding gate patterns in gate pattern group 904 are omitted for the sake of simplicity.

[0277] Gate pattern group 904 is located above active region pattern group 902. Gate pattern group 904 is located on a fourth layout layer, which is different from the first layout layer, the second layout layer, and the third layout layer. In some embodiments, the fourth layout layer corresponds to the POLY layer. In some embodiments, the POLY layer is higher than the OD layer.

[0278] The number of other configurations, arrangements, or patterns on other layout layers of the gate pattern group 904 is within the scope of this disclosure.

[0279] The layout 900C also includes one or more contact patterns 906a, 906b, 906c, 906i (collectively referred to as “contact pattern group 906”) extending in the second direction Y.

[0280] Each contact pattern in the contact pattern group 906 is separated from the adjacent contact pattern in the contact pattern group 906 at least in the first direction X or the second direction Y.

[0281] Contact pattern group 906 can be used to manufacture corresponding contact groups for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D. Contact patterns 906b and 906g can be used to manufacture corresponding contacts 906b' and 906g' for integrated circuit 900E.

[0282] In some embodiments, the contact pattern group 906 is also referred to as a metal over diffuser (MD) pattern group.

[0283] In some embodiments, at least one of the contact patterns 906a, 906b, 906c, ..., 906j of the contact pattern group 906 can be used to manufacture the source or drain terminal of one of the NMOS or PMOS transistors of integrated circuits 100, 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A or 1500D.

[0284] In some embodiments, the contact pattern group 906 overlaps with the active area pattern group 902. The contact pattern group is located on a fifth layout layer. In some embodiments, the fifth layout layer corresponds to a contact layer or an MD layer. In some embodiments, the fifth layout layer is the same as the fourth layout layer. In some embodiments, the fifth layout layer is different from the first, second, and third layout layers. Other configurations, arrangements, or number of patterns on other layout layers of the contact pattern group 906 are within the scope of this disclosure.

[0285] The layout 900C also includes one or more conductive component patterns 920a, 920b, 920c, 920d or 920e (collectively referred to as “conductive component pattern group 920”) extending along the first direction X and located in the first layout layer.

[0286] In some embodiments, conductive component pattern 920a corresponds to the first conductive component pattern of method 100-200, and conductive component pattern 920e corresponds to the second conductive component pattern of method 100-200, therefore a similar detailed description is omitted.

[0287] In some embodiments, the conductive component pattern group 920 corresponds to conductive component patterns 302, 304, 402a, 704a-704d, 706a-706d or 708a-708d, and therefore a similar detailed description is omitted.

[0288] In some embodiments, the conductive component pattern 920a corresponds to Figure 9B and Figure 9E Pin JP1 in the diagram, and the conductive part pattern 920e corresponds to... Figure 9B and Figure 9EPin JP2 in the diagram is omitted, hence a similar detailed description is omitted.

[0289] The conductive component pattern group 920 can be used to manufacture the corresponding conductor group for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D. The conductive component patterns 920a and 920e can be used to manufacture the corresponding conductors 920a' and 920e' for integrated circuit 900E.

[0290] Although each conductive component pattern in the conductive component pattern group 920 is shown as a continuous pattern, in some embodiments, one or more conductive component patterns in the conductive component pattern group 920 are divided into two or more discontinuous patterns.

[0291] The conductive component pattern group 920 overlaps at least with the gate pattern group 904, the active region pattern group 902, and the conductive component pattern group 906. In some embodiments, the conductive component pattern group 920 overlaps with other underlying patterns (not shown for illustration) of other layout layers of layout 900C.

[0292] like Figure 9C As shown, in some embodiments, the conductive component pattern group 920 has corresponding colors MOA or MOB. Color MOA or MOB indicates that conductive component patterns 920 with the same color will be formed on the same mask of multiple mask sets, while conductive component patterns 920 with different colors will be formed on different masks of multiple mask sets. As an example, Figure 9C The diagram depicts two colors, MOA and MOB. In some embodiments, layout 900C may contain more or fewer than two colors.

[0293] In some embodiments, conductive component patterns 920a, 920b, 920c, 920d, or 920e correspond to five M0 wiring tracks in layout 900C. Other numbers of M0 wiring tracks are also within the scope of this disclosure.

[0294] The other widths of the conductive component pattern group 920 are within the scope of this disclosure. The other configurations, arrangements, or number of patterns on other layout layers in the conductive component pattern group 920 are within the scope of this disclosure.

[0295] Layout 900C also includes a set of cabling tracks T1-T5. This set of cabling tracks T1-T5 extends in the second direction Y. This set of cabling tracks T1-T5 includes at least cabling tracks T1, T2, T3, T4, and T5. Each cabling track in this set of cabling tracks T1-T5 is spaced apart from the adjacent cabling track T1-T5 by a pitch (unmarked) in the second direction Y.

[0296] In some embodiments, during operation 110 of method 100, each of the wiring tracks T1-T5 defines a position where the conductive component pattern group 930 can be positioned during operation 100 of method 100. In some embodiments, the wiring tracks T1-T5 are also referred to as the M1 wiring track group.

[0297] Layout 900C also includes one or more through-hole patterns 910a, 910b or 910c (collectively referred to as “through-hole pattern group 910”).

[0298] The through-hole pattern group 910 can be used to manufacture corresponding through-hole groups for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A or 1500D.

[0299] The via pattern group 910 is located on the via (VD) layer above the diffusion region. In some embodiments, the VD layer is above the MD and OD layers. In some embodiments, the VD layer is between the MD layer and the MO layer. In some embodiments, the VD layer is between the fifth layout layer and the first layout layer. Other layout layers are within the scope of this disclosure.

[0300] In some embodiments, the via pattern group 910 is located between the contact pattern group 906 and the conductive component pattern group 920. In some embodiments, the size of one or more via patterns in the via pattern group 910 may be increased, thereby reducing resistance compared to other methods.

[0301] The number of other configurations, arrangements, or patterns on other layout layers in at least the through-hole pattern group 910 is within the scope of this disclosure.

[0302] Layout 900C also includes one or more through-hole patterns 912a, 912b, ... 912d (collectively referred to as "through-hole pattern group 912").

[0303] The via pattern group 912 can be used to manufacture corresponding via groups for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D. The via pattern 910a can be used to manufacture corresponding vias 910a' for integrated circuit 900E.

[0304] In some embodiments, the via pattern group 912 is located between the gate pattern group 904 and the conductive component pattern group 910.

[0305] The via pattern group 912 is located on the gate via (VG) layer. In some embodiments, the VG layer is above the OD layer, MD layer, and POLY layer. In some embodiments, the VG layer is between the POLY layer and the MO layer. In some embodiments, the VG layer is between the fourth layout layer and the first layout layer. Other layout layers are within the scope of this disclosure.

[0306] The number of other configurations, arrangements, or patterns on other layout layers in at least the through-hole pattern group 912 is within the scope of this disclosure.

[0307] Other configurations of the 900C layout are within the scope of this disclosure.

[0308] Figure 9D This is a schematic diagram of the layout 900D of an integrated circuit 900E according to some embodiments.

[0309] Layout 900D is Figures 1-2 Examples of layouts for the second circuit of methods 100-200. In some embodiments, layout 900D is generated based on a schematic diagram of integrated circuit 900E. In some embodiments, layout 900E is stored in... Figure 19 The standard unit library is in 1920.

[0310] Layout 900D is an embodiment of the first layout placed after the first region of the layout design in operation 110 of method 100. Layout 900D corresponds to... Figure 1 The layout of the second circuit following operation 114 of method 100 is omitted, therefore a similar detailed description is omitted. Layout 900D corresponds to the layout of integrated circuit 900E, therefore a similar detailed description is omitted.

[0311] In some embodiments, layout 900D can be used to manufacture integrated circuits, such as... Figure 9E 900E integrated circuit or Figure 20 IC device 2060.

[0312] Layout 900D includes one or more components of an OD layer or active layer, a POLY layer, an MD layer, an M0 layer, a VG layer, a VD layer, a via 0 (V0) layer, or a metal 1 (M1) layer. For ease of illustration, components of other layers are not shown.

[0313] Layout 900D is a variation of layout 900C, therefore a similar detailed description is omitted. Compared to layout 900C, layout 900D also includes conductive component pattern group 930 and via pattern group 932, therefore a similar detailed description is omitted.

[0314] In some embodiments, conductive component pattern 930a corresponds to the third conductive component pattern of method 200, through-hole pattern 932a corresponds to the first through-hole pattern of method 200, and through-hole pattern 932b corresponds to the second through-hole pattern of method 200, therefore detailed description is omitted.

[0315] Layout 900D includes the components of layout 900C. Layout 900D also includes one or more conductive component patterns 930a (collectively referred to as "conductive component pattern group 930") extending in the second direction Y.

[0316] The conductive component pattern group 930 can be used to manufacture the corresponding conductor group for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D. The conductive component pattern 930a can be used to manufacture the corresponding conductor 960 for integrated circuit 900E.

[0317] In some embodiments, the conductive component pattern group 930 overlaps with the conductive component pattern group 920. In some embodiments, the conductive component pattern group 930 is located on a second layout layer. In some embodiments, the second layout layer is different from the first layout layer, the fifth layout layer, the third layout layer, and the fourth layout layer. In some embodiments, the second layout layer corresponds to the M1 layer. In some embodiments, the M1 layer is higher than the M0 layer, the OD layer, the MD layer, and the POLY layer.

[0318] In operation 110 of method 100 or operation 210 of method 200, the conductive component pattern 930a is positioned in wiring track T2. In some embodiments, the conductive component pattern 930a can be positioned in wiring tracks T1, T3, T4, or T5 via operation 110 of method 100 or operation 210 of method 200. In some embodiments, based on at least... Figure 8 The candidate wiring track selection criteria discussed herein position the conductive component pattern 930a in wiring track T2.

[0319] The number of other configurations, arrangements, or patterns on other layout layers of the conductive component pattern group 930 is within the scope of this disclosure.

[0320] Layout 900D also includes one or more through-hole patterns 932a or 932b in the through-hole pattern group (collectively referred to as "through-hole pattern group 932").

[0321] Through-hole pattern group 932 can be used to manufacture corresponding through-hole groups for integrated circuits 900B, 900E, 1000A, 1000D, 1100A, 1100D, 1200A, 1200D, 1500A, or 1500D. Through-hole patterns 932a and 932b can be used to manufacture corresponding through-holes 932a' and 932b' for integrated circuit 900E.

[0322] The via pattern group 932 is located at the via layer on M0 (V0). In some embodiments, the V0 layer is above the OD layer, MD layer, POLY layer, and M0 layer. In some embodiments, the V0 layer is below the M1 layer. In some embodiments, the V0 layer is between the first layout layer and the second layout layer. Other layout layers are within the scope of this disclosure.

[0323] Conductive component pattern 930a, through-hole pattern 932a and through-hole pattern 932b connect conductive component pattern 920a and conductive component pattern 920e together.

[0324] The number of other configurations, arrangements, or patterns on other layout layers of at least the via pattern group located on the V0 layer is within the scope of this disclosure.

[0325] In some embodiments, layout 900D achieves one or more of the benefits discussed in this disclosure.

[0326] Other configurations of the 900D layout are within the scope of this disclosure.

[0327] Figure 9E This is a circuit diagram of an integrated circuit 900E according to some embodiments.

[0328] Integrated circuit 900E is an AND gate. In some embodiments, integrated circuit 900E is configured to function as integrated circuit 900A.

[0329] Integrated circuit 900E is Figures 1-2 An embodiment of the second circuit of method 100-200.

[0330] The integrated circuit 900E includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP1-JP2, group G1, pin label MJ1 and conductor 960.

[0331] Integrated circuit 900E is Figure 9B This is a variant of the 900B integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 9B Compared to the 900B integrated circuit, Figure 9E The drain of NMOS transistor N1 is connected to the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N3 via conductor 960.

[0332] Integrated circuit 900E corresponds to Figure 1 Method 100 is the second circuit following operation 114, therefore a similar detailed description is omitted.

[0333] In some embodiments, the integrated circuit 900E achieves one or more of the benefits discussed in this disclosure.

[0334] Figure 9F This is a schematic diagram of the Verilog netlist 900F of an integrated circuit 900B according to some embodiments.

[0335] Verilog netlist 900F is a netlist for integrated circuit 900B. In some embodiments, Verilog netlist 900F corresponds to the netlist of the first circuit generated by method 100 after operation 102, and therefore a similar detailed description is omitted. In some embodiments, method 100 may use Verilog netlist 900F to generate a schematic diagram of integrated circuit 900B.

[0336] Figure 9G This is a cross-sectional view of an integrated circuit 900G according to some embodiments. Figure 9G It is a cross-sectional view of an integrated circuit 900G corresponding to layout 900D intersecting with plane A-A' according to some embodiments.

[0337] Integrated circuit 900G includes each component of layout 900D, but some components are not shown for ease of illustration.

[0338] Conductor 960 connects conductors 920a' and 920e'. For example, conductor 960 is connected to conductor 920a' through through hole 932a', and conductor 960 is connected to conductor 920e' through through hole 932b'.

[0339] Other configurations of the 900G integrated circuit are within the scope of this disclosure.

[0340] Figure 10A This is a circuit diagram of integrated circuit 1000A according to some embodiments. Figure 10B This is a schematic diagram of the layout 1000B of an integrated circuit 1000A according to some embodiments. Figure 10C This is a schematic diagram of the layout 1000C of an integrated circuit 1000D according to some embodiments. Figure 10D This is a circuit diagram of an integrated circuit 1000D according to some embodiments. Figure 10E This is a schematic diagram of the Verilog netlist 1000E of an integrated circuit 1000A according to some embodiments.

[0341] Figure 10A This is a circuit diagram of integrated circuit 1000A according to some embodiments.

[0342] Integrated circuit 1000A is Figure 9A The non-functional representation of an AND gate. Integrated circuit 1000A is... Figures 1-2An embodiment of the first circuit of method 100-200. In some embodiments, integrated circuit 1000A is composed of... Figure 10E Generate the Verilog netlist 1000E.

[0343] Integrated circuit 1000A includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP1-JP2, group G2 and pin labels MJ1 and MJ2.

[0344] Integrated circuit 1000A is Figure 9A This is a variant of the 900A integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 9A Compared to the 900A integrated circuit, Figure 10A The drain of NMOS transistor N1 is not connected to the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, or the gate terminal of NMOS transistor N3.

[0345] Integrated circuit 1000A corresponds to Figure 1 Method 100 is the first circuit following operation 104, therefore a similar detailed description is omitted. Integrated circuit 1000A corresponds to Figure 6 Method 600 is the first circuit after operation 606, therefore a similar detailed description is omitted.

[0346] Pin JP1 corresponds to the first pin of methods 100-200 and 600, and is a pin or node of the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N3.

[0347] Pin JP2 corresponds to the second pin of methods 100-200 and 600, and is the drain pin or node of NMOS transistor N1.

[0348] Pin label MJ1 corresponds to the first label of method 600, and pin label MJ2 corresponds to the second label of method 600, therefore a similar detailed description is omitted.

[0349] Group G2 corresponds to the first group of pins in methods 100 and 600, so a similar detailed description is omitted.

[0350] During the execution of method 600, in operation 602, pin JP1 is designated or marked as the first pin to be connected using a first pin label (e.g., pin label MJ1), and pin JP2 is designated or marked using a second pin label (e.g., pin label MJ2). Then, in operation 604 of method 600, the first and second pins to be connected are designed as a first group of pins to be connected. Then, in operation 606, the first group of pins to be connected is designated as a first group of pins to be connected together (e.g., group G2).

[0351] Figure 10B This is a schematic diagram of the layout 1000B of an integrated circuit 1000A according to some embodiments.

[0352] Layout 1000B is Figures 1-2 An embodiment of the first layout of method 100-200. In some embodiments, layout 1000B is based on a schematic diagram of integrated circuit 1000A or Figure 10E The Verilog netlist 1000E is generated. In some embodiments, layout 1000B is stored in... Figure 19 The standard unit library is in 1920.

[0353] Layout 1000B corresponds to Figure 1 Method 100 is the first layout following at least one of operations 106 and 108, therefore a similar detailed description is omitted.

[0354] In some embodiments, layout 1000B can be used to manufacture integrated circuits, such as integrated circuit 1000A or... Figure 9G 900G or integrated circuit Figure 20 IC device 2060.

[0355] Layout 1000B is a variation of Layout 900C, therefore a detailed description similar to this is omitted. Figure 9C Compared to layout 900C, conductive component pattern 920a is labeled with pin label MJ1, while conductive component pattern 920e is labeled with pin label MJ2, therefore similar detailed descriptions are omitted.

[0356] Layout 1000B also includes area 1002. Area 1002 corresponds to the area of ​​layout 900C or layout 1000B that includes wiring tracks T1-T3.

[0357] Other configurations of layout 1000B are within the scope of this disclosure.

[0358] Figure 10C This is a schematic diagram of the layout 1000C of an integrated circuit 1000D according to some embodiments.

[0359] Layout 1000C is Figures 1-2 Examples of layouts for the second circuit of methods 100-200. In some embodiments, layout 1000C is generated based on a schematic diagram of integrated circuit 1000D. In some embodiments, layout 1000C is stored in... Figure 19 The standard unit library is in 1920.

[0360] Layout 1000C is an embodiment following the placement of the first layout in the first region of the layout design in operation 110 of method 100. Layout 1000C corresponds to... Figure 1 The layout of the second circuit following operation 114 in method 100 is omitted, and therefore a similar detailed description is omitted. Layout 1000C corresponds to the layout of integrated circuit 1000D, and therefore a similar detailed description is omitted.

[0361] In some embodiments, layout 1000C can be used to manufacture integrated circuits, such as integrated circuit 1000D or... Figure 9G 900G or integrated circuit Figure 20 IC device 2060.

[0362] Layout 1000C is a variation of layout 900D, therefore a similar detailed description is omitted. (And...) Figure 9D Compared to layout 900D, conductive component pattern 920a is labeled with pin label MJ1, while conductive component pattern 920e is labeled with pin label MJ2, therefore similar detailed descriptions are omitted.

[0363] In some embodiments, layout 1000C achieves one or more of the benefits discussed in this disclosure.

[0364] Other configurations of the Layout 1000C are within the scope of this disclosure.

[0365] Figure 10D This is a circuit diagram of an integrated circuit 1000D according to some embodiments.

[0366] Integrated circuit 1000D is an AND gate. In some embodiments, integrated circuit 1000D is configured to function as integrated circuit 900A.

[0367] Integrated circuit 1000D is Figures 1-2 An embodiment of the second circuit of method 100-200.

[0368] Integrated circuit 1000D includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP1-JP2, group G2, pin labels MJ1 and MJ2, and conductor 960.

[0369] Integrated circuit 1000D is Figure 10AThis is a variant of the 1000A integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 10A Compared to the 1000A integrated circuit, Figure 10D The drain of NMOS transistor N1 is connected to the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N3 via conductor 960.

[0370] Integrated circuit 1000D corresponds to Figure 1 Method 100 is the second circuit following operation 114, therefore a similar detailed description is omitted.

[0371] In some embodiments, the integrated circuit 1000D achieves one or more of the benefits discussed in this disclosure.

[0372] Figure 10E This is a schematic diagram of the Verilog netlist 1000E of an integrated circuit 1000A according to some embodiments.

[0373] Verilog netlist 1000E is a netlist of integrated circuit 1000A. In some embodiments, Verilog netlist 1000E corresponds to the netlist of the first circuit generated by method 100 after operation 102, and therefore a similar detailed description is omitted. In some embodiments, method 100 may use Verilog netlist 1000E to generate a schematic diagram of integrated circuit 1000A.

[0374] Figure 11A This is a circuit diagram of integrated circuit 1100A according to some embodiments. Figure 11B This is a schematic diagram of the layout 1100B of an integrated circuit 1100A according to some embodiments. Figure 11C This is a schematic diagram of the layout 1100C of an integrated circuit 1100D according to some embodiments. Figure 11D This is a circuit diagram of integrated circuit 1100D according to some embodiments.

[0375] Figure 11A This is a circuit diagram of integrated circuit 1100A according to some embodiments.

[0376] Integrated circuit 1100A is Figure 9A The non-functional representation of the AND gate. The 1100A integrator circuit is... Figures 1-2 Examples of the first circuit of methods 100-200. In some embodiments, integrated circuit 1100A is generated from a Verilog netlist (not shown).

[0377] The integrated circuit 1100A includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP3-JP4, group G3 and pin label MJ3.

[0378] Integrated circuit 1100A is Figure 9A This is a variant of the 900A integrated circuit, therefore a similar detailed description is omitted. Figure 9A Compared to the 900A integrated circuit, Figure 11A The drain terminals of PMOS transistor P1, PMOS transistor P2, and PMOS transistor P3 are not connected to the drain terminals of NMOS transistor N1 and the gate terminals of NMOS transistor N3.

[0379] Integrated circuit 1100A corresponds to Figure 1 Method 100 is the first circuit following operation 104, therefore a similar detailed description is omitted. Integrated circuit 1100A corresponds to Figure 5 Method 500 is the first circuit after operation 504, therefore a similar detailed description is omitted.

[0380] Pin JP3 corresponds to the first pin of methods 100-200 and 500, and is a pin or node of the drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, and the gate terminal of PMOS transistor P3.

[0381] Pin JP4 corresponds to the second pin of methods 100-200 and 500, and is a pin or node of the drain terminal of NMOS transistor N1 and the gate terminal of NMOS transistor N3.

[0382] The pin label MJ3 corresponds to the common label of method 500, so a similar detailed description is omitted.

[0383] Group G3 corresponds to the first group of pins in methods 100 and 500, so a similar detailed description is omitted.

[0384] During the execution of method 500, in operation 502, pins JP3 and JP4 are designated or marked with a common label (e.g., pin label MJ3) and designated as the first group of pins to be connected. Subsequently, in operation 504, the first group of pins to be connected is designated as the first group of pins to be connected together (e.g., group G3).

[0385] Figure 11B This is a schematic diagram of the layout 1100B of an integrated circuit 1100A according to some embodiments.

[0386] Layout 1100B is Figures 1-2This describes an embodiment of the first layout of method 100-200. In some embodiments, layout 1100B is generated based on a schematic diagram of integrated circuit 1100A or a Verilog netlist (not shown). In some embodiments, layout 1100B is stored in... Figure 19 The standard unit library is in 1920.

[0387] Layout 1100B corresponds to Figure 1 Method 100 is the first layout following at least one of operations 106 and 108, therefore a similar detailed description is omitted.

[0388] In some embodiments, layout 1100B can be used to manufacture integrated circuits, such as integrated circuit 1100A or... Figure 9G 900G or integrated circuit Figure 20 IC device 2060.

[0389] Layout 1100B is a variation of Layout 900C, therefore a detailed description similar to that is omitted. Figure 9C Compared to layout 900C, conductive component patterns 920a and 920e are marked with pin label MJ3, therefore a similar detailed description is omitted.

[0390] and Figure 9C Compared to layout 900C, layout 1100B further includes a diced part pattern 1130. The diced part pattern 1130 extends in a first direction X. The diced part pattern 1130 overlaps with gate patterns 904c and 904d. In some embodiments, the diced part pattern 1130 overlaps with gate patterns 904c and 904d in the middle portion of layout 1100B.

[0391] The gate pattern 904c is divided into gate patterns 1104c1 and 1104c2.

[0392] The gate pattern 904d is divided into gate patterns 1104d1 and 1104d2.

[0393] In some embodiments, the cut part pattern 1130 can be used to identify the corresponding position of the removed portion of the corresponding gate structure that is removed during the POLY dicing process.

[0394] In some embodiments, the cutting pattern 1130 can be used to identify the corresponding position of the removed portion of the corresponding gate structure.

[0395] In some embodiments, the cut component pattern 1130 is located on a fourth layout layer or POLY layer. Other configurations or number of patterns of the cut component pattern 1130 are within the scope of this disclosure.

[0396] Other configurations of layout 1100B are within the scope of this disclosure.

[0397] Figure 11C This is a schematic diagram of the layout 1100C of an integrated circuit 1100D according to some embodiments.

[0398] Layout 1100C is Figures 1-2 Examples of layouts for the second circuit of methods 100-200. In some embodiments, layout 1100C is generated based on a schematic diagram of integrated circuit 1100D. In some embodiments, layout 1100C is stored in... Figure 19 The standard unit library is in 1920.

[0399] Layout 1100C is an embodiment of the first layout placed after the first region of the layout design in operation 110 of method 100. Layout 1100C corresponds to Figure 1 The layout of the second circuit following operation 114 in method 100 is omitted, and therefore a similar detailed description is omitted. Layout 1100C corresponds to the layout of integrated circuit 1100D, and therefore a similar detailed description is omitted.

[0400] In some embodiments, layout 1100C can be used to manufacture integrated circuits, such as integrated circuit 1100D or... Figure 9G 900G or integrated circuit Figure 20 IC device 2060.

[0401] Layout 1100C is a variant of layout 900D, therefore a similar detailed description is omitted. (And...) Figure 9D Compared to layout 900D, conductive component patterns 920a and 920e are marked with pin label MJ3, so similar detailed descriptions are omitted.

[0402] and Figure 9D Compared to layout 900D, layout 1100C also includes Figure 9C The cutting component pattern 1130 discussed herein is omitted, therefore a similar detailed description is omitted.

[0403] In some embodiments, layout 1100C achieves one or more of the benefits discussed in this disclosure.

[0404] Other configurations of the Layout 1100C are within the scope of this disclosure.

[0405] Figure 11D This is a circuit diagram of integrated circuit 1100D according to some embodiments.

[0406] Integrated circuit 1100D is an AND gate. In some embodiments, integrated circuit 1100D is configured to function as integrated circuit 900A.

[0407] Integrated circuit 1100D is Figures 1-2 An embodiment of the second circuit of method 100-200.

[0408] Integrated circuit 1100D includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP3-JP4, group G3, pin label MJ3 and conductor 1160.

[0409] In some embodiments, conductor 1160 is similar to conductor 960, so a similar detailed description is omitted.

[0410] Integrated circuit 1100D is Figure 11A This is a variant of the 1100A integrated circuit, therefore a similar detailed description is omitted. Figure 11A Compared to the 1100A integrated circuit, Figure 11A The drain terminal of PMOS transistor P1, the drain terminal of PMOS transistor P2, and the gate terminal of PMOS transistor P3 are connected to the drain terminal and gate terminal of NMOS transistor N1 and NMOS transistor N3 through conductor 1160.

[0411] Integrated circuit 1100D corresponds to Figure 1 Method 100 is the second circuit following operation 114, therefore a similar detailed description is omitted.

[0412] In some embodiments, the integrated circuit 1100D realizes one or more of the benefits discussed in this disclosure.

[0413] Figure 12A This is a circuit diagram of integrated circuit 1200A according to some embodiments. Figure 12B This is a schematic diagram of the layout 1200B of an integrated circuit 1200A according to some embodiments. Figure 12C This is a schematic diagram of the layout 1200C of an integrated circuit 1200D according to some embodiments. Figure 12D This is a circuit diagram of an integrated circuit 1200D according to some embodiments.

[0414] Figure 12A This is a circuit diagram of integrated circuit 1200A according to some embodiments.

[0415] Integrated circuit 1200A is Figure 9A The NOT function representation of an AND gate. Integrated circuit 1200A is... Figures 1-2 Examples of the first circuit of methods 100-200. In some embodiments, the integrated circuit 1200A is generated from a Verilog netlist (not shown).

[0416] The integrated circuit 1200A includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP5-JP7, group G4 and pin label MJ4.

[0417] Integrated circuit 1200A is Figure 9A This is a variant of the 900A integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 9A Compared to the integrated circuit 900A, the drain terminals of PMOS transistor P1 and PMOS transistor P2, the gate terminals of PMOS transistor P3 and NMOS transistor N3, and the drain terminal of NMOS transistor N1 are... Figure 12A Not connected.

[0418] Integrated circuit 1200A corresponds to Figure 1 Method 100 is the first circuit following operation 104, therefore a similar detailed description is omitted. Integrated circuit 1200A corresponds to Figure 5 Method 500 is the first circuit after operation 504, therefore a similar detailed description is omitted.

[0419] Pin JP5 corresponds to the first pin of methods 100-200 and 500, and is a pin or node of the drain terminal of PMOS transistor P1 and the drain terminal of PMOS transistor P2.

[0420] Pin JP6 corresponds to the second pin of methods 100-200 and 500, and is the pin or node of the drain terminal of NMOS transistor N1.

[0421] Pin JP7 corresponds to the third pin in methods 100-200 and 500, and is a pin or node of the gate terminal of PMOS transistor P3 and the gate terminal of NMOS transistor N3.

[0422] The pin label MJ4 corresponds to the common label of method 500, therefore a similar detailed description is omitted.

[0423] Group G4 corresponds to the first group of pins in methods 100 and 500, so a similar detailed description is omitted.

[0424] During the execution of method 500, in operation 502, pins JP5, JP6, and JP7 are designated or marked with a common label (e.g., pin label MJ4) and designated as the first group of pins to be connected. Subsequently, in operation 504, the first group of pins to be connected is designated as the first group of pins to be connected together (e.g., group G4).

[0425] Figure 12B This is a schematic diagram of the layout 1200B of an integrated circuit 1200A according to some embodiments.

[0426] Layout 1200B is Figures 1-2 An embodiment of the first layout of method 100-200. In some embodiments, layout 1200B is generated based on a schematic diagram of integrated circuit 1200A or a Verilog netlist (not shown). In some embodiments, layout 1200B is stored in... Figure 19 The standard unit library is in 1920.

[0427] Layout 1200B corresponds to Figure 1 Method 100 is the first layout following at least one of operations 106 and 108, therefore a similar detailed description is omitted.

[0428] In some embodiments, layout 1200B can be used to manufacture integrated circuits, such as integrated circuit 1200A or... Figure 20 IC device 2060.

[0429] Layout 1200B is a double-height unit. Layout 1200B is a variation of Layout 900C, therefore a similar detailed description is omitted. Figure 9C Compared to layout 900C, layout 1200B includes region 1002, therefore a similar detailed description is omitted.

[0430] and Figure 9C Compared to layout 900C, conductive component patterns 920a and 920e are marked with pin label MJ4, so a similar detailed description is omitted.

[0431] and Figure 9C Compared to layout 900C, layout 1200B also includes active region patterns 1202a and 1202b. In some embodiments, active region patterns 1202a and 1202b are similar to active region patterns 902a and 902b, therefore a similar detailed description is omitted.

[0432] and Figure 9C Compared to layout 900C, layout 1200B also includes conductive component patterns 1220a, 1220b, 1220c, 1220d, or 1220e. In some embodiments, conductive component patterns 1220a, 1220b, 1220c, 1220d, or 1220e are similar to the corresponding conductive component patterns 920a, 920b, 920c, 920d, or 920e, therefore such detailed descriptions are omitted.

[0433] In some embodiments, the conductive component pattern 920a corresponds to Figures 12B-12C Pin JP5, conductive component pattern 920e corresponds to Figures 12B-12C Pin JP6 in the diagram, and conductive part pattern 1220a corresponds to Figures 12B-12CPin JP7 in the diagram is used, therefore a similar detailed description is omitted.

[0434] and Figure 9C Compared to layout 900C, layout 1200B also includes a via pattern 1210c. In some embodiments, via pattern 1210c is similar to one or more of via patterns 910a, 910b, or 910c, so a similar detailed description is omitted.

[0435] and Figure 9C Compared to layout 900C, layout 1200B also includes via patterns 1212c and 1212d. In some embodiments, via patterns 1212c and 1212d are similar to one or more of via patterns 912a, 912b, 912c or 912d, and therefore such detailed descriptions are omitted.

[0436] and Figure 9C Compared to layout 900C, contact pattern 1206a replaces contact pattern 906a, and contact pattern 1206c replaces contact pattern 906c, therefore similar detailed descriptions are omitted.

[0437] and Figure 9C Compared to layout 900C, layout 1200B also includes contact patterns 1206b and 1206d. In some embodiments, contact patterns 1206b and 1206d are similar to the corresponding contact patterns 906a, 906b, ..., 906h, therefore such detailed descriptions are omitted.

[0438] and Figure 9C Compared to layout 900C, layout 1200B includes wiring tracks T1-T3, therefore a similar detailed description is omitted.

[0439] Other configurations of layout 1200B are within the scope of this disclosure.

[0440] Figure 12C This is a schematic diagram of the layout 1200C of an integrated circuit 1200D according to some embodiments.

[0441] Layout 1200C is Figures 1-2 An embodiment of the layout of the second circuit of method 100-200. In some embodiments, layout 1200C is generated based on a schematic diagram of integrated circuit 1200D. In some embodiments, layout 1200C is stored in... Figure 19 The standard unit library is in 1920.

[0442] Layout 1200C is an embodiment following the placement of the first layout in the first region of the layout design in operation 110 of method 100. Layout 1200C corresponds to Figure 1The layout of the second circuit following operation 114 in method 100 is omitted, therefore a similar detailed description is omitted. Layout 1200C corresponds to the layout of integrated circuit 1200D, therefore a similar detailed description is omitted.

[0443] In some embodiments, layout 1200C can be used to manufacture integrated circuits, such as integrated circuit 1200D or... Figure 9G 900G or integrated circuit Figure 20 IC device 2060.

[0444] Layout 1200C is a variant of Layout 1200B, therefore a similar detailed description is omitted. (And...) Figure 12B Compared to layout 1200B, conductive component pattern 1230a replaces conductive component pattern 930a, therefore a similar detailed description is omitted.

[0445] and Figure 12B Compared to layout 1200B, layout 1200C also includes a via pattern 1232c, therefore a similar detailed description is omitted. In some embodiments, via pattern 1232c is similar to via patterns 932a or 932b, therefore a similar detailed description is omitted.

[0446] In some embodiments, through-hole pattern 932a corresponds to the first through-hole pattern of method 200, through-hole pattern 932b corresponds to the second through-hole pattern of method 200, and through-hole pattern 932c corresponds to the third through-hole pattern of method 200; therefore, similar detailed descriptions are omitted.

[0447] Conductive component pattern 1230a, through hole pattern 932a, through hole pattern 932b and through hole pattern 1232c connect conductive component pattern 920a, conductive component pattern 920e and conductive component pattern 1220a together.

[0448] In some embodiments, layout 1200C achieves one or more of the benefits discussed in this disclosure.

[0449] Other configurations of the layout 1200C are within the scope of this disclosure.

[0450] Figure 12D This is a circuit diagram of an integrated circuit 1200D according to some embodiments.

[0451] Integrated circuit 1200D is an AND gate. In some embodiments, integrated circuit 1200D is configured to function as integrated circuit 900A.

[0452] Integrated circuit 1200D is Figures 1-2 An embodiment of the second circuit of method 100-200.

[0453] Integrated circuit 1200D includes PMOS transistors P1, P2 and P3, NMOS transistors N1, N2 and N3, pins JP5-JP7, group G4, pin label MJ4 and conductor 1260.

[0454] In some embodiments, conductor 1260 is similar to conductor 960, so a similar detailed description is omitted.

[0455] Integrated circuit 1200D is Figure 12A This is a variant of the 1200A integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 12A Compared to the integrated circuit 1200A, the drain terminals of PMOS transistor P1 and PMOS transistor P2 are connected to the gate terminals of PMOS transistor P3 and NMOS transistor N3, and the drain terminal of NMOS transistor N1, via conductor 1260.

[0456] Integrated circuit 1200D corresponds to Figure 1 Method 100 is the second circuit following operation 114, therefore a similar detailed description is omitted.

[0457] In some embodiments, the integrated circuit 1200D achieves one or more of the benefits discussed in this disclosure.

[0458] Figure 13A This is a circuit diagram of integrated circuit 1300A according to some embodiments.

[0459] Integrated circuit 1300A is a buffer circuit. Integrated circuit 1300A includes region group 1302. Region group 1302 includes regions 1302a, 1302b, and 1302c. Each region 1302a, 1302b, or 1302c in region group 1302 is a buffer circuit. Each region 1302a, 1302b, or 1302c in region group 1302 includes two stages of inverters (e.g., a first inverter stage and a second inverter stage). An internal pin (e.g., internal) is located between the first inverter stage and the second inverter stage.

[0460] The inputs of regions 1302a, 1302b and 1302c are connected together via the input pin IN.

[0461] The outputs of regions 1302a, 1302b and 1302c are connected together via output pin Z.

[0462] The inputs of each inverter in the first inverter stage are connected together via the input pin IN.

[0463] In some embodiments, such as Figures 13A-13BAs shown, at least one or more components of methods 100-200 can be applied to the input pins (e.g., IN), output pins (e.g., Z), and internal pins (e.g., Internal) of integrated circuit 1300B, therefore a similar detailed description is omitted. For example, two or more internal pins (e.g., Internal) of integrated circuit 1300B can be disconnected in method 100 and then reconnected by method after operation 114, therefore a similar detailed description is omitted. In yet another example, two or more input pins (e.g., IN) of integrated circuit 1300B can be disconnected in method 100 and then reconnected by method after operation 114, therefore a similar detailed description is omitted. In yet another example, two or more output pins (e.g., Z) of integrated circuit 1300B can be disconnected in method 100 and then reconnected by method after operation 114, therefore a similar detailed description is omitted.

[0464] Other configurations of the integrated circuit 1300A are within the scope of this disclosure.

[0465] In some embodiments, the integrated circuit 1300A achieves one or more of the benefits discussed in this disclosure.

[0466] Figure 13B This is a schematic diagram of the layout 1300B of an integrated circuit 1300A according to some embodiments.

[0467] Layout 1300B is Figures 1-2 This describes an embodiment of the first layout of method 100-200. In some embodiments, layout 1300B is generated based on a schematic diagram of integrated circuit 1300A or a Verilog netlist (not shown). In some embodiments, layout 1300B is stored in... Figure 19 The standard unit library is in 1920.

[0468] Layout 1300B corresponds to Figure 1 Method 100 is the first layout following at least one of operations 106 and / or 108, therefore a similar detailed description is omitted.

[0469] In some embodiments, layout 1300B can be used to manufacture integrated circuits, such as integrated circuit 1300A or... Figure 20 IC device 2060.

[0470] Layout 1300B is a triple-height cell. Other cell heights are within the scope of this disclosure. Layout 1300B includes rows (e.g., rows 1, 2, and 3) of cells 1310a, 1310b, and 1310c. Cell 1310a corresponds to region 1302a, cell 1310b corresponds to region 1302b, and cell 1310c corresponds to region 1302c.

[0471] Each of the cells in units 1310a, 1310b, and 1310c is a variation of layout 900C, therefore a similar detailed description is omitted. Figure 9C Compared to layout 900C, for ease of explanation, layout 1500B does not show other components from layout 900C, but layout 1500B still includes... Figure 15B Other elements not shown in the diagram.

[0472] Unit 1310a includes conductive component patterns 1320a, 1320b, 1322a, and 1324a. In some embodiments, conductive component patterns 1320a, 1320b, 1322a, and 1324a are similar to corresponding conductive component patterns 920a, 920b, 920c, 920d, or 920e, and therefore such detailed descriptions are omitted.

[0473] Unit 1310b includes conductive component patterns 1330a, 1330b, 1332a, and 1334a. In some embodiments, conductive component patterns 1330a, 1330b, 1332a, and 1334a are similar to corresponding conductive component patterns 920a, 920b, 920c, 920d, or 920e, and therefore such detailed descriptions are omitted.

[0474] Unit 1310c includes conductive component patterns 1340a, 1340b, 1342a, and 1344a. In some embodiments, conductive component patterns 1340a, 1340b, 1342a, and 1344a are similar to corresponding conductive component patterns 920a, 920b, 920c, 920d, or 920e, and therefore such detailed descriptions are omitted.

[0475] Conductive component patterns 1320a, 1320b, 1330a, 1330b, 1340a, and 1340b correspond to internal pins (e.g., Internal) of integrated circuit 1300B. Conductive component patterns 1322a, 1332a, and 1342b correspond to input pins (e.g., IN) of integrated circuit 1300B. Conductive component patterns 1324a, 1334a, and 1344b correspond to output pins (e.g., Z) of integrated circuit 1300B.

[0476] In some embodiments, layout 1300B achieves one or more of the benefits discussed in this disclosure.

[0477] Other configurations of the Layout 1300B are within the scope of this disclosure.

[0478] Figure 14A This is a circuit diagram of integrated circuit 1400A according to some embodiments.

[0479] Integrated circuit 1400A is a multi-bit flip-flop circuit. Integrated circuit 1400A includes a group of flip-flops 1402. This group of flip-flops 1402 includes flip-flops 1402a, 1402b, 1402c, and 1402d. Each flip-flop 1402a, 1402b, 1402c, and 1402d in the group of flip-flops 1402 corresponds to a single bit. Other numbers of flip-flops in the group of flip-flops 1402 are within the scope of this disclosure.

[0480] Each flip-flop 1402a, 1402b, 1402c, and 1402d in flip-flop group 1402 includes a clock pin group 1404 (e.g., clkb). In some embodiments, the clock pin group 1404 (e.g., clkb) is connected together.

[0481] In some embodiments, such as Figures 14A-14B As shown, at least one or more components of methods 100-200 can be applied to the clock pin group 1404 (e.g., clkb) of integrated circuit 1400B, therefore a similar detailed description is omitted. For example, two or more clock pins in the clock pin group 1404 (e.g., clkb) of integrated circuit 1400B can be disconnected in method 100 and then reconnected by method after operation 114, therefore a similar detailed description is omitted.

[0482] Other configurations of the integrated circuit 1400A are within the scope of this disclosure.

[0483] In some embodiments, the integrated circuit 1400A achieves one or more of the benefits discussed in this disclosure.

[0484] Figure 14B This is a schematic diagram of the layout 1400B of an integrated circuit 1400A according to some embodiments.

[0485] Layout 1400B is Figures 1-2 This describes an embodiment of the first layout of method 100-200. In some embodiments, layout 1400B is generated based on a schematic diagram of integrated circuit 1400A or a Verilog netlist (not shown). In some embodiments, layout 1400B is stored in... Figure 19 The standard unit library is in 1920.

[0486] Layout 1400B corresponds to Figure 1 Method 100 is the first layout following at least one of operations 106 and 108, therefore a similar detailed description is omitted.

[0487] In some embodiments, layout 1400B can be used to manufacture integrated circuits, such as integrated circuit 1400A or... Figure 20 IC device 2060.

[0488] Layout 1400B corresponds to the layout of at least one of the triggers 1402a, 1402b, 1402c or 1402d in the trigger group 1402.

[0489] Layout 1400B is a variation of layout 900C, therefore a detailed description similar to this is omitted. Figure 9C Compared to layout 900C, layout 1400B does not show other components found in layout 900C for ease of explanation, but layout 1400B still includes... Figure 14B Other components not shown in the image.

[0490] Layout 1400B includes conductive component patterns 1420a, 1420b, 1420c, 1420d, and 1420e. In some embodiments, conductive component patterns 1420a, 1420b, 1420c, 1420d, and 1420e are similar to corresponding conductive component patterns 920a, 920b, 920c, 920d, or 920e, therefore such detailed descriptions are omitted.

[0491] Pin JP8 corresponds to conductive component pattern 1420a. Pin JP9 corresponds to conductive component pattern 1420b. Pin JP10 corresponds to conductive component pattern 1420c. Pin JP11 corresponds to conductive component pattern 1420d. Pin JP12 corresponds to conductive component pattern 1420e.

[0492] The conductive component patterns 1420a, 1420b, 1420c, 1420d and 1420e correspond to the clock pin group 1404 (e.g., clkb) of integrated circuit 1400B.

[0493] Layout 1400B also includes regions 1430a, 1430b, and 1430c, wherein, in operation 110 of method 100, the conductive component pattern in layer M1 can be placed in the corresponding wiring tracks T1-T3.

[0494] In some embodiments, the clock pin group 1404 (e.g., clkb) in the integrated circuit 1400A and layout 1400B allows for flexible placement of the M1 conductive part pattern during the APR phase, thereby reducing connections without requiring the M1 conductive part pattern to block the clock pins.

[0495] In some embodiments, layout 1400B achieves one or more of the benefits discussed in this disclosure.

[0496] Other configurations of layout 1400B are within the scope of this disclosure.

[0497] Figure 15A This is a circuit diagram of integrated circuit 1500A according to some embodiments. Figure 15B This is a schematic diagram of the layout 1500B of an integrated circuit 1500A according to some embodiments. Figure 15C This is a schematic diagram of the layout 1500C of an integrated circuit 1500D according to some embodiments. Figure 15D This is a circuit diagram of an integrated circuit 1500D according to some embodiments.

[0498] Figure 15A This is a circuit diagram of integrated circuit 1500A according to some embodiments.

[0499] Integrated circuit 1500A is Figure 9A The NOT function representation of an AND gate. Integrated circuit 1500A is... Figures 1-2 Examples of the first circuit of methods 100-200. In some embodiments, the integrated circuit 1500A is generated from a Verilog netlist (not shown).

[0500] In some embodiments, integrated circuit 1500A is... Figure 16 A schematic diagram of the Engineering Change Order (ECO) unit placed in operation 1606 or 1608 is provided, therefore a similar detailed description is omitted. In some embodiments, at least one or more components of methods 100-200, 500, and 600 can be applied to Figures 15A-15D And method 1600, therefore a similar detailed description is omitted. For example, two or more pins in integrated circuit 1500A can be disconnected in method 100 and then reconnected via method after operation 114, therefore a similar detailed description is omitted.

[0501] The integrated circuit 1500A includes PMOS transistors P1, P2, P3 and P4, NMOS transistors N1, N2, N3, N4, N5 and N6, pins JP13-JP17, group G5 and group G6, and pin labels MJ5 and MJ6.

[0502] Integrated circuit 1500A is Figure 9A This is a variant of the 900A integrated circuit, therefore a similar detailed description is omitted.

[0503] and Figure 9ACompared to the 900A integrated circuit, the integrated circuit also includes PMOS transistor P4 and NMOS transistors N4, N5 and N6.

[0504] and Figure 9A Compared to the integrated circuit 900A, the drain terminals of PMOS transistor P1 and PMOS transistor P2 are connected to the gate terminals of PMOS transistor P3, NMOS transistor N3, and NMOS transistor N1 respectively. Figure 15A There is no connection in the middle.

[0505] and Figure 9A Compared to the 900A integrated circuit, the drain terminals of PMOS transistor P3 and NMOS transistor N3, as well as the output node Z, are... Figure 15A There is no connection in the middle.

[0506] NMOS transistor N4 is configured as capacitor C1, so the source terminal and the drain terminal of NMOS transistor N4 are connected together.

[0507] The gate terminal of NMOS transistor N4 is connected to the voltage source VDD. The source terminal of NMOS transistor N4, the drain terminal of NMOS transistor N4, the drain terminal of NMOS transistor N2, and the source terminal of NMOS transistor N1 are connected to each other.

[0508] NMOS transistor N5 is configured as capacitor C2, so the source terminal and the drain terminal of NMOS transistor N5 are connected together.

[0509] The gate terminal of NMOS transistor N5 is connected to the voltage source VDD. The source terminal of NMOS transistor N5, the drain terminal of NMOS transistor N5, the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P3, and the gate terminal of NMOS transistor N3 are all connected together.

[0510] PMOS transistor P4 is configured as capacitor C3, so the source terminal and the drain terminal of PMOS transistor P4 are connected together.

[0511] NMOS transistor N6 is configured as capacitor C4, so the source terminal and the drain terminal of NMOS transistor N6 are connected together.

[0512] The gate terminal of PMOS transistor P4 is connected to the voltage source VDD. The gate terminal of NMOS transistor N5 is connected to the voltage source VDD.

[0513] Each of the source terminal of NMOS transistor N6, the drain terminal of NMOS transistor N6, the drain terminal of PMOS transistor P4, the source terminal of PMOS transistor P4, and the output node Z is connected together.

[0514] In some embodiments, at least one of capacitors C1, C2, C3, and C4 is in Figure 16 During operation 1602 of method 1600, the following was performed: Figure 19 The system was inserted in 1900, therefore a similar detailed description is omitted.

[0515] Integrated circuit 1500A corresponds to Figure 1 Method 100 is the first circuit following operation 104, therefore a similar detailed description is omitted. Integrated circuit 1500A corresponds to Figure 5 Method 500 is the first circuit after operation 504, therefore a similar detailed description is omitted.

[0516] In some embodiments, pin JP13 corresponds to the first pin of methods 100-200 and 500, and is a pin or node of the drain terminal of PMOS transistor P1 and the drain terminal of PMOS transistor P2.

[0517] In some embodiments, pin JP14 corresponds to the second pin of methods 100-200 and 500, and is a pin or node of the drain terminal of NMOS transistor N1.

[0518] In some embodiments, pin JP15 corresponds to the first pin of methods 100-200 and 500, and is a pin or node of the drain terminal of PMOS transistor P3.

[0519] In some embodiments, pin JP16 corresponds to the second pin of methods 100-200 and 500, and is a pin or node of the drain terminal of NMOS transistor N3.

[0520] In some embodiments, pin JP17 corresponds to the third pin of methods 100-200 and 500, and is a pin or node of output node Z, the drain and source terminals of PMOS transistor P4, and the drain and source terminals of NMOS transistor N6.

[0521] In some embodiments, pin label MJ5 corresponds to the common label of method 500, therefore a similar detailed description is omitted.

[0522] In some embodiments, pin label MJ6 corresponds to the common label of method 500, therefore a similar detailed description is omitted.

[0523] In some embodiments, group G5 corresponds to the first group of pins in methods 100 and 500, so a similar detailed description is omitted.

[0524] In some embodiments, group G6 corresponds to the second group of pins in methods 100 and 500, therefore a similar detailed description is omitted.

[0525] During the execution of method 500, in operation 502, pins JP13 and JP14 are designated or marked with a common label (e.g., pin label MJ4) as the first group of pins to be connected, and pins JP15, JP16, and JP17 are designated or marked with a common label (e.g., pin label MJ5) as the second group of pins to be connected. Then, in operation 504, the first group of pins to be connected is designated as the first group of pins to be connected together (e.g., group G5), and the second group of pins to be connected is designated as the second group of pins to be connected together (e.g., group G6).

[0526] Figure 15B This is a schematic diagram of the layout 1500B of an integrated circuit 1500A according to some embodiments.

[0527] Layout 1500B is Figures 1-2 An embodiment of the first layout of method 100-200. In some embodiments, layout 1500B is generated based on a schematic diagram of integrated circuit 1500A or a Verilog netlist (not shown). In some embodiments, layout 1500B is stored in... Figure 19 The standard unit library is in 1920.

[0528] Layout 1500B corresponds to in Figure 1 The first layout following at least one of operations 106 and 108 in method 100 is therefore omitted in a similar detailed description.

[0529] In some embodiments, layout 1500B is... Figure 16 The layout of the ECO cells placed in operation 1606 or 1608 is described, so a similar detailed description is omitted.

[0530] In some embodiments, layout 1500B can be used to manufacture integrated circuits, such as integrated circuit 1500A or... Figure 20 IC device 2060.

[0531] Layout 1500B is a variation of layout 900C, therefore a similar detailed description is omitted. (And...) Figure 9C Compared to layout 900C, for ease of explanation, layout 1500B does not show other components from layout 900C, but layout 1500B still includes... Figure 15B Other elements not shown in the diagram.

[0532] and Figure 9C Compared to layout 900C, conductive component patterns 1520a and 1520b replace conductive component pattern 920a, conductive component pattern 1520c replaces conductive component pattern 920d, and conductive component pattern 1520d replaces conductive component pattern 920e; therefore, similar detailed descriptions are omitted.

[0533] Conductive component patterns 1520a and 1520c are marked with pin label MJ5, and conductive component patterns 1520b and 1520d are marked with pin label MJ6.

[0534] In some embodiments, the conductive component pattern 1520a corresponds to Figures 15B-15C Pin JP13, conductive part pattern 1520c corresponds to Figures 15B-15C Pin JP14, conductive part pattern 1520b corresponds to Figures 15B-15C At least one of pins JP15 and JP17, the conductive part pattern 1520d corresponds to Figures 15B-15C At least one of pins JP16 and JP17 in the circuit, therefore a similar detailed description is omitted.

[0535] and Figure 9C Compared to layout 900C, layout 1500B also includes via patterns 1512a, 1512b, 1512c, and 1512d. In some embodiments, via patterns 1512a, 1512b, 1512c, and 1512d are similar to one or more of via patterns 912a, 912b, 912c, or 912d, and therefore such detailed descriptions are omitted.

[0536] and Figure 9C Compared to layout 900C, layout 1500B includes two sets of wiring tracks (e.g., T1a-T3a and T1b-T7b) instead of one set of wiring tracks T1-T5, so a similar detailed description is omitted.

[0537] In some embodiments, each wiring track in the wiring track group T1a-T3a defines an area where the conductive component pattern 1530a can be positioned in operation 110 of method 100.

[0538] In some embodiments, each wiring track in the wiring track group T1b-T7b defines an area where the conductive component pattern 1530b can be positioned in operation 110 of method 100.

[0539] Other configurations of layout 1500B are within the scope of this disclosure.

[0540] Figure 15CThis is a schematic diagram of the layout 1500C of an integrated circuit 1500D according to some embodiments.

[0541] Layout 1500C is Figures 1-2 Examples of layouts for the second circuit of methods 100-200. In some embodiments, layout 1500C is generated based on a schematic diagram of integrated circuit 1500D. In some embodiments, layout 1500C is stored in... Figure 19 The standard unit library is in 1920.

[0542] Layout 1500C is an embodiment following the placement of the first layout in the first region of the layout design in operation 110 of method 100. Layout 1500C corresponds to Figure 1 Method 100 is the layout diagram of the second circuit after operation 114, therefore a similar detailed description is omitted. Routing 1500C corresponds to the layout of integrated circuit 1500D, therefore a similar detailed description is omitted.

[0543] In some embodiments, layout 1500C is Figure 16 The layout of the ECO cell after operation 1618 is omitted, so a similar detailed description is omitted.

[0544] In some embodiments, layout 1500C can be used to manufacture integrated circuits, such as... Figure 20 The integrated circuit 1500D or IC device 2060.

[0545] Layout 1500C is a variant of Layout 1500B, therefore a similar detailed description is omitted. (And...) Figure 15B Compared to layout 1500B, layout 1500C also includes conductive component patterns 1530a and 1530b, as well as through-hole patterns 1532a, 1532b, 1532c and 1532d, therefore similar detailed descriptions are omitted.

[0546] In some embodiments, conductive component patterns 1530a and 1530b are similar to conductive component pattern 930a, therefore a similar detailed description is omitted.

[0547] In some embodiments, through-hole patterns 1532a, 1532b, 1532c, and 1532d are similar to through-hole patterns 932a or 932b, and therefore similar detailed descriptions are omitted.

[0548] In some embodiments, through-hole pattern 1532a corresponds to the first through-hole pattern of method 200, and through-hole pattern 1532b corresponds to the second through-hole pattern of method 200, so similar detailed descriptions are omitted.

[0549] In some embodiments, through-hole pattern 1532c corresponds to the first through-hole pattern of method 200, and through-hole pattern 1532d corresponds to the second through-hole pattern of method 200, so similar detailed descriptions are omitted.

[0550] Conductive component pattern 1530a, through hole pattern 1532a and through hole pattern 1532b connect conductive component pattern 1520a and conductive component pattern 1520c together.

[0551] Conductive component pattern 1530b, through-hole pattern 1532c, and through-hole pattern 1532d connect conductive component pattern 1520b and conductive component pattern 1520d together.

[0552] In some embodiments, layout 1500C achieves one or more of the benefits discussed in this disclosure.

[0553] Other configurations of the Layout 1500C are within the scope of this disclosure.

[0554] Figure 15D This is a circuit diagram of an integrated circuit 1500D according to some embodiments.

[0555] Integrated circuit 1500D is an AND gate. In some embodiments, integrated circuit 1500D is configured to function as integrated circuit 900A.

[0556] Integrated circuit 1500D is Figures 1-2 An embodiment of the second circuit of method 100-200.

[0557] In some embodiments, integrated circuit 1500D is Figure 16 The diagram shows the ECO unit after operation 1618, so a similar detailed description is omitted.

[0558] Integrated circuit 1500D includes PMOS transistors P1, P2, P3 and P4, NMOS transistors N1, N2, N3, N4, N5 and N6, pins JP13-JP17, group G5 and group G6, and pin labels MJ5 and MJ6, as well as conductors 1560 and 1260.

[0559] In some embodiments, conductor 1560 is similar to conductor 960, so a similar detailed description is omitted.

[0560] Integrated circuit 1500D is Figure 15A This is a variant of the 1500A integrated circuit, therefore a similar detailed description is omitted. (And...) Figure 15ACompared to the integrated circuit 1500A, the drain terminals of PMOS transistor P1 and PMOS transistor P2, the gate terminal of PMOS transistor P3, the gate terminal of NMOS transistor N3, and the drain terminal of NMOS transistor N1 are connected via conductor 1560.

[0561] and Figure 15A Compared to the integrated circuit 1500A, the drain terminals of PMOS transistor P3 and NMOS transistor N3, output node Z, and capacitors C3 and C4 are connected via conductor 1260.

[0562] Integrated circuit 1500D corresponds to Figure 1 Method 100 is the second circuit following operation 114, therefore a similar detailed description is omitted.

[0563] In some embodiments, the integrated circuit 1500D achieves one or more of the benefits discussed in this disclosure.

[0564] Figure 16 This is a flowchart of a method 1600 for placing and wiring ECO units into a layout according to some embodiments.

[0565] It should be understood that it is possible Figure 16 Additional operations are performed before, during, and / or after the method described in the document 1600, so only a few other processes will be briefly described herein.

[0566] In some embodiments, method 1600 includes applying Figures 15A-15D Methods 100-200, 500, and 600 have at least one or more features, therefore a similar detailed description is omitted.

[0567] In some embodiments, method 1600 applies methods 100-200, 500, and 600 to an ECO unit, and therefore similar detailed descriptions are omitted. For example, in some embodiments, method 1600 applies methods 100-200, 500, and 600 to an ECO unit, wherein one or more pins in the corresponding ECO unit are connected in a manner similar to methods 100-200, 500, and 600, and therefore similar detailed descriptions are omitted.

[0568] In some embodiments, method 1600 can be used to connect a first pin and a second pin in an ECO replacement unit. In some embodiments, the ECO unit is a spare unit inserted into a layout. In some embodiments, the layout of method 1600 includes at least one of the following: Figure 3 Layout 300 or Figure 4 Layout 400 Figure 3Units 320A1, 320A2, 320B-320E, Figure 4 Units 400A-400B or 440A-440E, Figures 7A-7C Layout 700A-Layout 700C Figure 8 Layout 800 Figures 9C-9D The layout of 900C-900D, Figures 10B-10C Layout 1000B-1000C, Figures 11B-11C Layout 1100B-1100C, Figures 12B-12C Layout 1200B-1200C, Figure 13B Layout 1300B Figure 14B The layout of 1400B and Figures 15B-15C The layout is 1500B-1500C.

[0569] In operation 1602 of method 1600, one or more fill cells or decoupling capacitor (DCAP) cells are placed in the layout.

[0570] In some embodiments, operation 1602 includes filling existing cells with padding cells and then placing the padding cells into the layout. In some embodiments, operation 1602 includes filling existing cells within the layout with padding cells. In some embodiments, padding cells are cells that do not have logical functions and are used to fill blank spaces in standard cell rows.

[0571] In some embodiments, operation 1602 includes filling existing cells with DCAPS and then placing the DCAP cells in the layout. In some embodiments, operation 1602 includes filling existing cells within the layout with DCAPS. In some embodiments, the DCAP cells improve the timing performance of the layout by reducing noise. In some embodiments, DCAP cells are added near one or more paths in a layout that does not meet timing requirements.

[0572] In some embodiments, the DCAPS of method 1600 includes Figures 15A-15D The capacitor is at least one of C1, C2, C3 or C4.

[0573] In some embodiments, the operation unit 1602 corresponds to the ECO unit.

[0574] In operation 1604 of method 1600, one or more cells are placed in a layout and routed. In some embodiments, operation 1604 includes actually placing the cells in the layout. In some embodiments, operation 1604 includes placing one or more standard cells in the layout. In some embodiments, operation 1604 of method 1600 includes one or more of operations 102, 104, 106, 108, 110, 112, or 114, and therefore a similar detailed description is omitted.

[0575] In some embodiments, one or more units of operation 1604 include at least one of the following layouts: Figures 9C-9D The layout of 900C-900D, Figure 10B-10C Layout 1000B-1000C, Figures 11B-11C Layout 1100B-1100C, Figures 12B-12C Layout 1200B-1200C, Figure 13B Layout 1300B Figure 14B Layout 1400B or Figure 15B-Figure 1 The layout of 5 is 1500B-1500C.

[0576] In operation 1606 of method 1600, one or more padding cells of operation 1602 are replaced by corresponding ECO replacement cells. In some embodiments, operation 1606 includes replacing one or more padding cells with corresponding ECO cells to improve layout performance (e.g., timing).

[0577] In some embodiments, the ECO replacement unit is a functional version of the filling unit.

[0578] In some embodiments, a fill cell can be "programmed" (converted) into an ECO replacement cell, which is configured to operate and provide one of the same, common, low-level functions provided by a corresponding standard functional unit. In some embodiments, the ECO replacement cell is configured to operate and provide one of the following logic functions: inverter, NAND, NOR, XOR, D latch, decoupling capacitor (DeCap), AND-OR-NOT (AOI), OR-NAND (OAI), multiplexer, flip-flop, etc. In some embodiments, a fill cell is programmed (converted) into an ECO replacement cell by changing one or more connections within at least one fill cell (connections within the fill cell), such as metal-to-silicon contacts and metal-to-polysilicon contacts, or by changing other metal layers using corresponding vias or contacts.

[0579] In operation 1608 of method 1600, an ECO connection is established on the pins within each ECO replacement unit. In some embodiments, operation 1608 of method 1600 includes reconnecting the first and second pins within each ECO replacement unit using an APR tool, similar to methods 100-200, and therefore a similar detailed description is omitted.

[0580] In some embodiments, operation 1608 of method 1600 includes applying one or more of operations 102, 104, 106, 108, 110, 112, or 114 to each ECO replacement unit, and therefore a similar detailed description is omitted.

[0581] In operation 1610 of method 1600, by Figure 19 System 1900 determines whether one or more connection pins within each ECO replacement unit cause a conflict with existing APR wiring. In some embodiments, operation 1610 of method 1600 includes applying one or more of operations 110, 112, or 114 to each ECO replacement unit, and therefore a similar detailed description is omitted.

[0582] If one or more connection pins within each ECO replacement unit cause a conflict with existing APR wiring, method 1600 proceeds to operation 1612. In some embodiments, the conflict process of operation 1610 is similar to... Figure 4 Due to the conflict, a similar detailed description is omitted.

[0583] If one or more connection pins within each ECO replacement unit do not cause a conflict with existing APR wiring, then method 1600 proceeds to operation 1618.

[0584] In operation 1612 of method 1600, overlapping wiring shapes are removed from the layout. In some embodiments, the overlapping wiring shapes removed from the layout are those that conflict with operation 1610 or Figure 4 The conflicting wiring patterns are therefore omitted in a detailed description. In some embodiments, operation 1612 includes disconnecting pins previously connected in at least operation 1608.

[0585] In operation 1614 of method 1600, other networks and cabling are frozen. In some embodiments, the frozen other networks and cabling cannot be used for cabling by APR tools.

[0586] In some embodiments, other network and cabling are frozen until a conflict occurs in Operation 1610 or... Figure 4 The conflict was resolved.

[0587] In operation 1616 of method 1600, incremental routing is applied to the layout. In some embodiments, incremental routing is applied to the layout to resolve conflicts in operation 1610 or Figure 4 Conflict.

[0588] In operation 1618 of method 1600, the placement of patterns and cells in the layout is completed.

[0589] In operation 1620 of method 1600, at least one of the ECO input routing and output routing of the layout is performed.

[0590] Although method 1600 is described as connecting the first pin and the second pin together, other numbers of pins may be connected together and are within the scope of this disclosure.

[0591] In some embodiments, by using method 1600, the number of conflicts with pre-existing APR wiring during ECO placement is reduced compared to other methods.

[0592] In some embodiments, by using method 1600, rerouting during ECO layout is reduced compared to other methods, and the timing and power of the layout are ensured to meet design parameters.

[0593] In some embodiments, method 1600 achieves one or more of the benefits discussed in this disclosure.

[0594] Figure 17 This is a flowchart of a method 1700 for generating an integrated circuit layout according to some embodiments. It can be understood that... Figure 17 Additional operations are performed before, during, and / or after the method described in the document 1700, so some other processes may only be briefly described herein.

[0595] In some embodiments, method 1700 is an embodiment of at least one of operations 106 and 108 of method 100. In some embodiments, method 1700 can be used to generate one or more layout patterns of at least layout designs 500A-500D, 700A-700B, 800A-800B, 900A-900B, 1000A-1000B, or 1100A-1100B, or at least one or more components similar to integrated circuit 600.

[0596] In some embodiments, method 1700 can be used to generate one or more layout patterns or one or more components similar to at least an integrated circuit 900G having structural relationships, the structural relationships including alignment, length and width, and at least the following configurations and layers: Figure 3 Layout 300A, Figure 3Units 320A1, 320A2, 320B-320E, Figure 4 Units 400A-400B or 440A-440E, Figures 7A-7C Layout 700A-Layout 700C Figure 8 Layout 800 Figures 9C-9D The layout of 900C-900D, Figures 10B-10C Layout 1000B-1000C, Figures 11B-11C Layout 1100B-1100C, Figures 12B-12C Layout 1200B-1200C, Figure 13B Layout 1300B Figure 14B Layout 1400B or Figures 15B-15C The layout is 1500B-1500C, therefore for the sake of brevity, similar detailed descriptions will not be repeated. Figure 17 As described in the text.

[0597] In operation 1702 of method 1700, an active area pattern group is generated or placed on a layout design. In some embodiments, the active area pattern group of method 1700 includes at least a portion of one or more patterns of the active area pattern group 902 or 1202. In some embodiments, the active area pattern group of method 1700 includes one or more regions resembling active areas 902a' or 902b'. In some embodiments, the active area pattern group of method 1700 includes one or more active area patterns in an OD layer.

[0598] In operation 1704 of method 1700, a group of contact patterns is generated or placed on a layout design. In some embodiments, the group of contact patterns in method 1700 includes at least a portion of one or more patterns of at least contact pattern group 906 or 1206. In some embodiments, a first group of contact patterns in method 1700 includes one or more contact patterns that are at least similar to contact 906b' or 906g'. In some embodiments, the group of contact patterns in method 1700 includes one or more contact patterns in an MD layer.

[0599] In operation 1706 of method 1700, a group of gate patterns is generated or placed on a layout design. In some embodiments, the group of gate patterns in method 1700 includes at least a portion of one or more gate patterns of gate pattern group 904 or 1204. In some embodiments, the group of gate patterns in method 1700 includes one or more gate patterns in a POLY layer.

[0600] In operation 1708 of method 1700, a first set of cutting patterns is generated or placed on a layout design. In some embodiments, the first set of cutting patterns in method 1700 includes at least a portion of one or more cutting patterns of the cutting component pattern 1130.

[0601] In operation 1710 of method 1700, a first conductive component pattern set is generated or placed on a layout design. In some embodiments, the first conductive component pattern set of method 1700 includes at least a portion of one or more patterns of at least conductive component pattern sets 920, 1220, or 1520.

[0602] In some embodiments, the first conductive component pattern set of method 1700 includes at least portions of at least one or more of the following patterns: Figure 3 Conductive component patterns 302 or 304, Figure 4 Conductive component pattern 402 or 404, Figures 7A-7C Conductive component patterns 704a-704d, 706a-706d or 708a-708d, Figure 8 The conductive component patterns 802 and 804, Figures 9C-9D , Figures 10B-10C , Figures 11B-11C , Figures 12B-12C Conductive component patterns 920a-920e Figures 12B-12C Conductive component patterns 1220a-1220e, Figures 13A-13B The conductive component patterns are 1320a-1320b, 1322a, 1324a, 1330a-1330b, 1332a, 1334a, 1340a-1340b, 13342a, 1344a. Figure 14B Conductive component pattern 1420a-1420e or Figures 15B-15C The conductive component patterns are 1520a-1520d.

[0603] In some embodiments, the first conductive component pattern set of method 1700 includes one or more conductive component patterns that are at least similar to conductors 920a' or 920e'. In some embodiments, the conductive component pattern set of method 1700 includes one or more conductive component patterns in the MO layer.

[0604] In operation 1712 of method 1700, a first through-hole pattern group and a second through-hole pattern group are generated or placed in the layout design.

[0605] In some embodiments, the first via pattern group of method 1700 includes at least a portion of one or more via patterns of via pattern group 910 or 1210. In some embodiments, the first via pattern group of method 1700 includes one or more via patterns at least similar to via 910a'. In some embodiments, the first via pattern group of method 1700 includes one or more vias at least similar to vias in the VD layer.

[0606] In some embodiments, the second set of via patterns in method 1700 includes at least a portion of one or more via patterns in via pattern groups 912, 1212, or 1512. In some embodiments, the second set of via patterns in method 1700 includes one or more vias that are at least similar to vias in a VG layer.

[0607] In operation 1714 of method 1700, a second set of conductive component patterns is generated or placed on a layout design. In some embodiments, the second set of conductive component patterns in method 1700 includes at least a portion of one or more conductive component patterns from at least conductive component pattern sets 930, 1230, or 1530.

[0608] In some embodiments, the second conductive component pattern set of method 1700 includes at least a portion of one or more of the following conductive component patterns: Figure 3 Conductive component pattern 322 or 332, Figure 9E , Figure 10C , Figure 11C Conductive component pattern 930a, Figure 12C The conductive component pattern 1230a, Figure 14B Conductive component patterns 1430a, 1430b and 1430c or Figure 15C The conductive component patterns are 1530a and 1530b.

[0609] In some embodiments, the second conductive component pattern set of method 1700 includes one or more conductive component patterns that are at least similar to conductors 960, 1160, 1260, or 1560. In some embodiments, the second conductive component pattern set 1700 of the method includes one or more conductors that are at least similar to conductors in the MO layer.

[0610] In operation 1716 of method 1700, a third through-hole pattern group is generated or placed in the layout design.

[0611] In some embodiments, the third via pattern group of method 1700 includes at least a portion of one or more via patterns of via pattern groups 932, 1232 or 1532.

[0612] In some embodiments, the third via pattern group of method 1700 includes at least a portion of one or more of the following via patterns: Figure 3 Through-hole pattern 324 or 334, Figure 9E , Figure 10C and Figure 11C Through-hole pattern 932a, Figure 12C Through-hole pattern 1232c or Figure 15CThe through-hole patterns are 1532a and 1532c. In some embodiments, the third group of through-hole patterns in method 1700 includes at least a portion of one or more of the following through-hole patterns: Figure 3 Through-hole pattern 326 or 336, Figure 9E , Figure 10C and Figure 11C Through-hole pattern 932b Figure 12C Through-hole pattern 1232c or Figure 15C The through-hole patterns are 1532b and 1532d.

[0613] In some embodiments, the third via pattern set of method 1700 includes one or more via patterns that are at least similar to vias 932a' or 932b'. In some embodiments, the third via pattern set of method 1700 includes one or more vias that are at least similar to vias in the VO layer.

[0614] Figure 18 This is a corresponding functional flowchart of a method 1800 for manufacturing an IC device according to some embodiments. It should be understood that... Figure 18 Additional operations are performed before, during, and / or after at least one of the methods 1800 described herein, so only a few other processes may be briefly described herein.

[0615] In some embodiments, the order of other operations of method 1800 is within the scope of this disclosure. Method 1800 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately combined, divided, added, substituted, rearranged, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more operations of methods 100, 200, 500, 600, 1600, 1700, or 1800 are not performed.

[0616] In some embodiments, method 1800 is an embodiment of operation 116 of method 100. In some embodiments, method 1800 can be used to manufacture or produce at least integrated circuits 900E, 900G, 1000D, 1100D, 1200D, 1300A, 1400A, or 1500D, or integrated circuits having at least the following similar components: Figure 3 Layout 300A, Figure 3 Units 320A1, 320A2, 320B-320E, Figure 4 Units 400A-400B or 440A-440E, Figures 7A-7C Layout 700A-Layout 700C Figure 8 Layout 800 Figures 9C-9D The layout of 900C-900D, Figures 10B-10C Layout 1000B-1000C, Figures 11B-11C Layout 1100B-1100C, Figures 12B-12C Layout 1200B-1200C, Figure 13B Layout 1300B Figure 14B Layout 1400B or Figures 15B-15C The layout is 1500B-1500C.

[0617] In operation 1802 of method 1800, a set of active regions of a set of transistors is formed in the front side of substrate 990. In some embodiments, at least the set of transistors of method 1800 includes one or more transistors in active regions 902a' or 902b'. In some embodiments, at least the group of transistors of method 1800 includes one or more transistors as described herein. In some embodiments, the group of active regions includes one or more active regions similar to active region pattern groups 902 or 1202.

[0618] In some embodiments, operation 1802 further includes at least operation 1802a. In some embodiments, operation 1802a (not shown) includes fabricating source and drain regions of the set of transistors in a first well. In some embodiments, the first well includes a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown over a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after its formation. In some embodiments, the first well is formed by doping a substrate. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a range from 1 × 10⁻⁶. 12 atoms / cm 3 Up to 1×10 14 atoms / cm 3 The dopant concentration is specified. Other dopant concentrations are within the scope of this disclosure.

[0619] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the concentration of the n-type dopant ranges from about 1 × 10⁻⁶. 12 atoms / cm 3 To approximately 1×10 14 atoms / cm 3 Other dopant concentrations are within the range specified in this disclosure.

[0620] In some embodiments, the formation of the source / drain components includes removing a portion of the substrate to form a groove at the edge of the spacer, and then performing a filling process by filling the groove in the substrate. In some embodiments, the groove is etched by means of wet etching or dry etching after the removal of the pad oxide layer or sacrificial oxide layer. In some embodiments, an etching process is performed to remove a portion of the top surface of the active region adjacent to the isolation region (e.g., the STI region). In some embodiments, the filling process is performed by epitaxy or epitaxial (epi) processes. In some embodiments, the groove is filled using a growth process concurrent with the etching process, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of growth and etching processes is used to fill the groove. For example, a material layer is grown in the groove, and then the grown material is etched to remove a portion of the material. A subsequent growth process is then performed on the etched material until the desired thickness of the material in the groove is reached. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by isotropic or anisotropic etching processes. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, semiconductor material is deposited in a trench to form source / drain components. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the trench. In some embodiments, the epitaxial process includes selective epitaxial growth (SEG), CVD, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that interact with the composition of the substrate. In some embodiments, the source / drain components include epitaxially grown silicon (epiSi), silicon carbide, or silicon-germanium. In some cases, the source / drain components of the IC device associated with the gate structure are either in-situ doped or undoped during the epitaxial process. When the source / drain components are undoped during the epitaxial process, they are sometimes doped during subsequent processes. Subsequent doping processes are achieved through ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain components are also exposed to an annealing process after the source / drain components are formed and / or after a subsequent doping process.

[0621] In operation 1804 of method 1800, a first conductive material is deposited on the source / drain regions of the transistor group on the first layer, thereby forming a set of contacts for the transistor group. In some embodiments, at least the first layer of method 1800 includes an MD layer or a POLY layer.

[0622] In some embodiments, the source / drain regions of the transistor group of at least method 1800 include the source / drain regions of one or more transistors in the active region group. In some embodiments, the contact group of at least method 1800 includes at least contact 906b' or 906g'. In some embodiments, the contact group includes one or more contacts similar to contact pattern group 906 or 1206. In some embodiments, the contact group of at least method 1800 includes components of the MD layer.

[0623] In operation 1806 of method 1800, a gate group of the transistors is formed on a second layer. In some embodiments, at least the gate group of method 1800 includes a gate region similar to gate group pattern 904 or 1204. In some embodiments, at least the second layer of method 1800 includes a POLY layer.

[0624] In some embodiments, the gate region is located between the drain region and the source region. In some embodiments, the gate region is located above the first well and the substrate. In some embodiments, the operation 1806 of fabricating the gate region includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition processes include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable processes for depositing one or more material layers. In some embodiments, fabricating the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, the gate region includes a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0625] In operation 1808 of method 1800, a dicing process is performed to remove a portion of the gate assembly. In some embodiments, the removed portion of the gate assembly in method 1800 includes components similar to at least the diced component pattern 1130. In some embodiments, the removed portion of the gate assembly in method 1800 includes components in the POLY layer.

[0626] In some embodiments, operation 1808 is performed by one or more removal processes. In some embodiments, the one or more removal processes include one or more etching processes suitable for removing portions of the gate structure. In some embodiments, the etching process of operation 1808 includes identifying the portions of the gate structure to be removed and etching the portions of the gate structure to be removed. In some embodiments, a mask is used to define the portions of the gate structure to be cut or removed.

[0627] In some embodiments, the mask is a hard mask. In some embodiments, the mask is a soft mask. In some embodiments, etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable processes, any combination thereof, etc.

[0628] In operation 1810 of method 1800, a first set of through holes and a second set of through holes are formed.

[0629] In some embodiments, at least the first set of vias of method 1800 is in the VD layer. In some embodiments, at least the first set of vias of method 1800 includes at least via 910a'. In some embodiments, the first set of vias includes one or more vias similar to via pattern group 910 or 1210.

[0630] In some embodiments, at least the second set of vias in method 1800 is located in the VG layer. In some embodiments, the second set of vias includes one or more vias similar to via pattern groups 912, 1212, or 1512.

[0631] In some embodiments, a first set of vias is formed above a first set of contacts. In some embodiments, a second set of vias is formed above a gate group.

[0632] In some embodiments, operation 1810 includes forming a first set and a second set of self-aligned contacts (SACs) in an insulating layer above the front side of the wafer. In some embodiments, the first set and the second set of vias are electrically connected to at least the set of transistors.

[0633] In operation 1812 of method 1800, a second conductive material is deposited on the third layer to form a second set of conductive lines. In some embodiments, at least the third layer of method 1800 includes an MO layer. In some embodiments, operation 1814 includes depositing a first set of conductive regions at least over the front side of the integrated circuit.

[0634] In some embodiments, at least the first set of wires in method 1800 includes one or more portions of at least conductor 920a' or 920e'. In some embodiments, the first set of wires includes one or more wires similar to conductive component pattern group 920 or 1220.

[0635] In some embodiments, the first set of wires includes one or more wires similar to at least one of the following: Figure 3 Conductive component patterns 302 or 304, Figure 4 Conductive component pattern 402 or 404, Figure 4 The conductive component pattern is 402 or 404. Figures 7A-7C The conductive component patterns are 704a-704d, 706a-706d, or 708a-708d. Figure 8 The conductive component patterns 802 and 804, Figures 9C-9D , Figures 10B-10C , Figures 11B-11C , Figures 12B-12C Conductive component patterns 920a-920e Figures 12B-12C Conductive component patterns 1220a-1220e, Figures 13A-13B The conductive component patterns are 1320a-1320b, 1322a, 1324a, 1330a-1330b, 1332a, 1334a, 1340a-1340b, 1342a, and 1344a. Figure 14B Conductive component pattern 1420a-1420e or Figures 15B-15C The conductive component patterns are 1520a-1520d.

[0636] In operation 1814 of method 1800, a third set of vias is formed. In some embodiments, at least the third set of vias of method 1800 is located in layer V0. In some embodiments, at least the third set of vias of method 1800 includes at least vias 932a' or 932b'. In some embodiments, the third set of vias includes one or more vias similar to via pattern groups 932, 1232, or 1532.

[0637] In some embodiments, the third set of vias includes one or more vias, similar to at least one or more of the following via patterns: Figure 3 Through-hole pattern 324 or 334, Figure 9E , Figure 10C and Figure 11C Through-hole pattern 932a, Figure 12C Through-hole pattern 1232c or Figure 15C The through-hole patterns 1532a and 1532c. In some embodiments, the third set of through holes includes those... Figure 3 Through-hole pattern 326 or 336, Figure 9E , Figure 10C and Figure 11C Through-hole pattern 932b Figure 12C Through-hole pattern 1232c or Figure 15C One or more through holes with at least one or more through hole patterns similar to those of 1532b and 1532d.

[0638] In operation 1816 of method 1800, a third conductive material is deposited on the fourth layer to form a first set of conductors. In some embodiments, at least the fourth layer of method 1800 includes an M1 layer. In some embodiments, at least the first set of conductors of method 1800 includes one or more portions of at least conductors 960, 1160, 1260, or 1560.

[0639] In some embodiments, the first set of conductors includes one or more wires similar to conductive component pattern groups 930, 1230, or 1530. In some embodiments, the first set of conductors includes similar to Figure 3 At least the conductive component pattern 322 or 332, Figure 9E , Figure 10C and Figure 11C Conductive component pattern 930a, Figure 12C Conductive component pattern 1230a, Figure 14B Conductive component patterns 1430a, 1430b and 1430c or Figure 15C One or more conductors of the conductive component patterns 1530a and 1530b.

[0640] In some embodiments, at least the first set of conductors in method 1800 includes one or more conductors that are at least similar to the conductors in layer M1.

[0641] Figure 19 This is a schematic diagram of a system 1900 for designing IC layout and manufacturing IC circuits according to some embodiments.

[0642] In some embodiments, system 1900 generates or places one or more IC layout designs as described herein. System 1900 includes a hardware processor 1902 and a non-transitory computer-readable storage medium 1904 (e.g., memory 1904) encoded with (i.e., stored) computer program code 1906, i.e., a set of executable instructions 1906. Computer-readable storage medium 1904 is configured to interface with manufacturing machines used to produce integrated circuits. Processor 1902 is electrically connected to computer-readable storage medium 1904 via bus 1908. Processor 1902 is also electrically connected to I / O interface 1910 via bus 1908. Network interface 1912 is also electrically connected to processor 1902 via bus 1908. Network interface 1912 is connected to network 1914, enabling processor 1902 and computer-readable storage medium 1904 to be connected to external components via network 1914. Processor 1902 is configured to execute computer program code 1906 encoded in computer-readable storage medium 1904 so that system 1900 can be used to perform some or all of the operations described in methods 100-200, 500-600 and 1600-1700.

[0643] In some embodiments, the processor 1902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0644] In some embodiments, the computer-readable storage medium 1904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1904 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 1904 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0645] In some embodiments, storage medium 1904 stores computer program code 1906 configured to cause system 1900 to perform methods 100-200, 500-600, and 1600-1700. In some embodiments, storage medium 1904 also stores information required to perform methods 100-200, 500-600, and 1600-1700, as well as information generated during the execution of methods 100-200, 500-600, and 1600-1700, such as layout design 1916, user interface 1918, standard cell library 1920, netlist 1922, and manufacturing tool 1930, and / or a set of executable instructions to perform the operations of methods 100-200, 500-600, and 1600-1700. In some embodiments, layout design 1916 includes one or more of layout patterns of at least layout designs 500A-500D, 700A-700B, 800A-800B, 900A-900B, 1000A-1000B or 1100A-1100B, or components similar to at least integrated circuit 600.

[0646] In some embodiments, storage medium 1904 stores instructions (e.g., computer program code 1906) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1906) enable processor 1902 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement methods 100-200, 500-600, and 1600-1700 in a manufacturing process.

[0647] System 1900 includes an I / O interface 1910. The I / O interface 1910 is connected to external circuitry. In some embodiments, the I / O interface 1910 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor arrow keys for transmitting information and commands to processor 1902.

[0648] System 1900 also includes a network interface 1912 connected to processor 1902. Network interface 1912 allows system 1900 to communicate with a network 1914 to which one or more other computer systems are connected. Network interface 1912 includes a wireless network interface such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-2094. In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented in two or more systems 1900, and information such as layout design and user interface is exchanged between different systems 1900 via network 1914.

[0649] System 1900 is configured to receive layout design-related information via I / O interface 1910 or network interface 1912. The information is transmitted via bus 1908 to processor 1902 to determine a layout design for producing at least integrated circuit 600. The layout design is then stored as layout design 1916 in computer-readable medium 1904. System 1900 is configured to receive user interface-related information via I / O interface 1910 or network interface 1912. This information is stored as user interface 1918 in computer-readable medium 1904. System 1900 is configured to receive standard cell library-related information via I / O interface 1910 or network interface 1912. This information is stored as standard cell library 1920 in computer-readable medium 1904. System 1900 is configured to receive netlist-related information via I / O interface 1910 or network interface 1912. This information is stored as netlist 1922 in computer-readable medium 1904. System 1900 is configured to receive information related to manufacturing tool 1930 via I / O interface 1910 or network interface 1912. The information is stored as manufacturing tool 1930 in computer-readable medium 1904. In some embodiments, manufacturing tool 1930 includes manufacturing information used by system 1900. In an embodiment, manufacturing tool 1930 corresponds to... Figure 20 Mask manufacturing 2034.

[0650] In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented as standalone software applications executed by a processor. In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented as software applications that are part of an additional software application. In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented as plug-ins to a software application. In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented as software applications that are part of an EDA tool. In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented as software applications used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, a layout is generated using tools such as those available from CADENCE DESIGN SYSTEMS, Inc., or other suitable layout generation tools. In some embodiments, the layout is generated based on a netlist created based on a schematic design. In some embodiments, methods 100-200, 500-600, and 1600-1700 are implemented by a manufacturing device to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs generated by system 1900. In some embodiments, system 1900 is a manufacturing device configured to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs of this disclosure. In some embodiments, Figure 19 The System 1900 generates layout designs for integrated circuits that are smaller than those using other methods. In some embodiments, Figure 19 The System 1900 generates layout designs for integrated circuit structures that occupy less area and provide better wiring resources than other methods.

[0651] Figure 20 This is a block diagram of an integrated circuit (IC) manufacturing system 2000 and its associated IC manufacturing process according to at least one embodiment of the present disclosure. In some embodiments, based on the layout diagram, the manufacturing system 2000 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0652] exist Figure 20In this context, the IC manufacturing system 2000 (hereinafter referred to as "System 2000") includes entities such as a design room 2020, a mask room 2030, and an IC manufacturer / foundry ("fab") 2040, which interact in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 2060. The entities in System 2000 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of the design room 2020, mask room 2030, and IC fab 2040 are owned by a single, larger company. In some embodiments, one or more of the design room 2020, mask room 2030, and IC fab 2040 coexist in a common entity and use common resources.

[0653] Design studio (or design team) 2020 generates IC design layout 2022. IC design layout 2022 includes various geometric patterns designed for IC device 2060. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 2060 to be manufactured. The layers are combined to form various IC components. For example, portions of IC design layout 2022 include various IC components such as active regions, gate electrodes, source electrodes and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads to form on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 2020 implements appropriate design procedures to form IC design layout 2022. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 2022 is presented in one or more data files containing geometric pattern information. For example, IC design layout 2022 may be represented in GDSII file format or DFII file format.

[0654] Mask chamber 2030 includes data preparation 2032 and mask fabrication 2034. Mask chamber 2030 uses IC design layout 2022 to fabricate one or more masks 2045 for fabricating various layers of IC device 2060 according to IC design layout 2022. Mask chamber 2030 performs mask data preparation 2032, where IC design layout 2022 is converted into a representative data file (RDF). Mask data preparation 2032 provides the RDF to mask fabrication 2034. Mask fabrication 2034 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 2045 or a semiconductor wafer 2042. Design layout 2022 is manipulated by mask data preparation 2032 to conform to the characteristics of the mask writer and / or the requirements of IC fab 2040. Figure 20 In this embodiment, mask data preparation 2032 and mask manufacturing 2034 are shown as separate elements. In some embodiments, mask data preparation 2032 and mask manufacturing 2034 may be collectively referred to as mask data preparation.

[0655] In some embodiments, mask data preparation 2032 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 2022. In some embodiments, mask data preparation 2032 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution aids, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, treating OPC as an inverse imaging problem.

[0656] In some embodiments, mask data preparation 2032 includes a mask rule checker (MRC) that checks the IC design layout already processed in the OPC using a set of mask creation rules. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 2034, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0657] In some embodiments, mask data preparation 2032 includes lithography process inspection (LPC), an LPC simulation performed by IC foundry 2040 to manufacture IC device 2060. The LPC simulates this process based on IC design layout 2022 to create a simulated manufactured device, such as IC device 2060. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC inspection takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), and other suitable factors, or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 2022.

[0658] It should be understood that, for clarity, the above description of mask data preparation 2032 has been simplified. In some embodiments, data preparation 2032 includes additional components such as logic operations (LOPs) to modify the IC design layout 2022 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 2022 during data preparation 2032 can be performed in various different sequences.

[0659] After mask data preparation 2032 and during mask fabrication 2034, a mask 2045 or mask set 2045 is fabricated based on a modified IC design layout 2022. In some embodiments, mask fabrication 2034 performs one or more photolithographic exposures based on the IC design layout 2022. In some embodiments, a mechanism of electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or intermediate mask) 2045 according to the modified IC design layout 2022. The mask 2045 can be formed using various techniques. In some embodiments, the mask 2045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and pass through the transparent regions. In one example, the binary form of the mask 2045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 2045. In the phase-shifting mask (PSM) version of mask 2045, various components in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 2034 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0660] IC Fab 2040 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Fab 2040 is a semiconductor foundry. For example, there may be manufacturing devices for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing device can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing device may provide additional services for casting operations.

[0661] IC wafer fab 2040 includes wafer fabrication tools 2052 (hereinafter referred to as "fabrication tools 2052") configured to perform various fabrication operations on semiconductor wafers 2042 to fabricate IC devices 2060 according to a mask (e.g., mask 2045). In various embodiments, fabrication tools 2052 include one or more of the following: wafer stepper, ion implanter, coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication devices as discussed herein capable of performing one or more suitable fabrication processes.

[0662] IC foundry 2040 uses mask 2045, manufactured by mask chamber 2030, to fabricate IC device 2060. Therefore, IC foundry 2040 at least indirectly uses IC design layout 2022 to fabricate IC device 2060. In some embodiments, IC foundry 2040 uses mask 2045 to fabricate semiconductor wafer 2042 to form IC device 2060. In some embodiments, IC fabrication includes at least indirectly performing one or more photolithographic exposures based on IC design 2022. Semiconductor wafer 2042 includes a silicon substrate or other suitable substrate having multiple material layers formed thereon. Semiconductor wafer 2042 also includes one or more of various doped regions, dielectric components, and multilayer interconnects (formed in subsequent fabrication steps).

[0663] System 2000 is shown as having a design room 2020, a mask room 2030, or an IC foundry 2040 as separate components or entities. However, it should be understood that one or more of the design room 2020, mask room 2030, or IC foundry 2040 are part of the same component or entity.

[0664] One aspect of this specification relates to a method of forming an integrated circuit (IC), the method including generating a netlist of a first circuit by a processor, wherein the first circuit is configured as a non-functional circuit, the first circuit including a first pin and a second pin electrically disconnected from each other. In some embodiments, generating the netlist of the first circuit includes designating the first pin and the second pin as a first set of pins to be connected together. In some embodiments, the method further includes generating a first cell layout of the first circuit by a processor, wherein the first cell layout includes a first conductive component pattern and a second conductive component pattern extending in a first direction, the first conductive component pattern and the second conductive component pattern being located in a first layout layer and separated from each other in a second direction other than the first direction, wherein the first conductive component pattern and the second conductive component pattern are not connected together, the first conductive component pattern corresponding to a first pin, and the second conductive component pattern corresponding to a second pin. In some embodiments, the method further includes placing the first cell layout in a first area of ​​the layout design using an Automatic Place and Route (APR) tool. In some embodiments, placing the first cell layout using an APR tool includes connecting the first pin and the second pin in a first set of pins together, thereby changing the first circuit into a second circuit, the second circuit being configured as the first circuit.

[0665] In some embodiments, designating the first pin and the second pin as the first group of pins to be connected together includes: marking the first pin and the second pin with a common label and designating them as the first group of pins to be connected; and designating the first group of pins to be connected as the first group of pins to be connected together.

[0666] In some embodiments, designating the first pin and the second pin as the first group of pins to be connected together includes: labeling the first pin as a first pin to be connected with a first label and labeling the second pin as a second pin to be connected with a second label; designating the first pin to be connected and the second pin to be connected as a first group of pins to be connected; and designating the first group of pins to be connected as a first group of pins to be connected together.

[0667] In some embodiments, connecting the first pin and the second pin in the first group of pins together includes connecting the first conductive component pattern and the second conductive component pattern by at least a third conductive component pattern extending in the second direction, overlapping the first conductive component pattern and the second conductive component pattern, and located on a second layout layer above the first layout layer.

[0668] In some embodiments, placing the first unit layout in the first region of the layout design includes: selecting a first wiring track from a first group of candidate wiring tracks, wherein the first group of candidate wiring tracks is not occupied by the corresponding conductive component pattern in the second layout layer, the first group of candidate wiring tracks extends in the second direction, and each wiring track in the first group of candidate wiring tracks is separated from each other in the first direction; and placing the third conductive component pattern in the first wiring track.

[0669] In some embodiments, connecting the first conductive component pattern and the second conductive component pattern via at least the third conductive component pattern includes: placing the third conductive component pattern to overlap with the first conductive component pattern and the second conductive component pattern, and in a first wiring track of a first set of wiring tracks extending in a second direction, and each wiring track of the first set of wiring tracks being separated from each other in the first direction; placing the first via pattern above the first conductive component pattern, the first via pattern being located between the first conductive component pattern and the third conductive component pattern and connecting the first conductive component pattern and the conductive third conductive component pattern together; and placing the second via pattern above the second conductive component pattern, the second via pattern being located between the second conductive component pattern and the third conductive component pattern and connecting the second conductive component pattern and the third conductive component pattern together.

[0670] In some embodiments, the first circuit further includes a third pin and a fourth pin that are electrically disconnected from each other; the netlist that generates the first circuit further includes designating the third pin and the fourth pin as a second set of pins to be connected together; the first cell layout further includes a fourth conductive component pattern and a fifth conductive component pattern extending in a first direction, the fourth conductive component pattern and the fifth conductive component pattern being on the first layout layer and separated from each other in the second direction, wherein the fourth conductive component pattern and the fifth conductive component pattern are not connected together, the fourth conductive component pattern corresponding to the third pin, and the fifth conductive component pattern corresponding to the fourth pin.

[0671] In some embodiments, placing the first cell layout using the APR tool further includes connecting the third and fourth pins in the second group of pins together, thereby transforming the first circuit into the second circuit.

[0672] In some embodiments, connecting the third and fourth pins in the second set of pins together includes connecting the fourth conductive component pattern and the fifth conductive component pattern through at least a sixth conductive component pattern, the sixth conductive component pattern extending in the second direction, overlapping the fourth and fifth conductive component patterns, and located on the second layout layer.

[0673] In some embodiments, connecting the fourth conductive component pattern and the fifth conductive component pattern via at least the sixth conductive component pattern includes: placing the sixth conductive component pattern to overlap with the fourth and fifth conductive component patterns and located in a second wiring track of a second set of wiring tracks extending in a second direction, and each wiring track of the second set of wiring tracks being separated from each other in the first direction; placing a third via pattern above the fourth conductive component pattern, the third via pattern being located between the fourth and sixth conductive component patterns and connecting the fourth and sixth conductive component patterns together; and placing a fourth via pattern above the fifth conductive component pattern, the fourth via pattern being located between the fifth and sixth conductive component patterns and connecting the fifth and sixth conductive component patterns together.

[0674] Another aspect of this specification relates to a system for manufacturing an integrated circuit, the system including a non-transitory computer-readable medium configured to store executable instructions, and a processor connected to the non-transitory computer-readable medium, wherein the processor is configured to execute instructions for generating a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit, and the first circuit includes a first pin, a second pin, and a third pin electrically disconnected from each other. In some embodiments, the netlist for generating the first circuit, including the integrated circuit, further includes combining the first pin, the second pin, and the third pin into a first set of pins to be connected. In some embodiments, the processor is configured to execute instructions for generating a first cell layout of the first circuit, wherein the first cell layout includes a first conductive component pattern corresponding to the first pin, a second conductive component pattern corresponding to the second pin, and a third conductive component pattern corresponding to the third pin. In some embodiments, the processor is configured to execute instructions for placing the first cell layout in a first region of a layout design using an automatic placement and routing (APR) tool, wherein placing the first cell layout using the APR tool includes connecting the first set of pins to be connected together, thereby transforming the first circuit into a second circuit, the second circuit being configured as a functional version of the first circuit.

[0675] In some embodiments, the processor is configured to execute the instructions to connect the first set of pins to be connected together, thereby changing the first circuit to the second circuit by connecting the first pin, the second pin, and the third pin together.

[0676] In some embodiments, the processor is configured to execute instructions to connect the first pin, the second pin, and the third pin together, including: connecting the first conductive component pattern, the second conductive component pattern, and the third conductive component pattern through at least a fourth conductive component pattern, wherein the first conductive component pattern, the second conductive component pattern, and the third conductive component pattern extend in a first direction, are located on a first layout layer, and are separated from each other in a second direction different from the first direction, and the fourth conductive component pattern extends along the second direction, overlaps with the first conductive component pattern, the second conductive component pattern, and the third conductive component pattern, and is located on a second layout layer above the first layout layer.

[0677] In some embodiments, the processor is configured to execute the instructions to connect the first conductive component pattern, the second conductive component pattern, and the third conductive component pattern via at least the fourth conductive component pattern, comprising: placing the fourth conductive component pattern to overlap with the first conductive component pattern, the second conductive component pattern, and the third conductive component pattern, and located in a first wiring track of a first set of wiring tracks extending in a second direction, and each wiring track of the first set of wiring tracks being spaced apart from each other in the first direction; placing a first via pattern above the first conductive component pattern, the first via pattern being located between the first conductive component pattern and the fourth conductive component pattern, and connecting the first conductive component pattern and the fourth conductive component pattern together; placing a second via pattern above the second conductive component pattern, the second via pattern being located between the second conductive component pattern and the fourth conductive component pattern, and connecting the second conductive component pattern and the fourth conductive component pattern together; and placing a third via pattern above the third conductive component pattern, the third via pattern being located between the third conductive component pattern and the fourth conductive component pattern, and connecting the third conductive component pattern and the fourth conductive component pattern together.

[0678] In some embodiments, the first circuit includes: a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor, wherein the first conductive component is patterned connected to the gate of the first transistor and the gate of the second transistor; the second conductive component is patterned connected to the drain of the third transistor and the drain of the fourth transistor; and the third conductive component is patterned connected to the drain of the fifth transistor.

[0679] Another aspect of this specification relates to a non-transitory computer-readable medium configured to store executable instructions. In some embodiments, the executable instructions are configured to be executed by a processor connected to the non-transitory computer-readable medium, the non-transitory computer-readable medium causing the processor to perform a method including generating a netlist of a first circuit, wherein the first circuit is configured as a non-functional circuit and includes a first pin and a second pin electrically disconnected from each other. In some embodiments, generating the netlist of the first circuit includes marking the first pin and the second pin as a first set of pins to be connected, and designating the first set of pins to be connected as a common set of pins to be connected. In some embodiments, the method further includes generating a first cell layout of the first circuit, wherein the first cell layout includes a first conductive component pattern corresponding to the first pin and a second conductive component pattern corresponding to the second pin, and is located on a first layout layer. In some embodiments, the method further includes placing the first cell layout in a first area of ​​the layout design using an Automatic Place and Route (APR) tool. In some embodiments, placing the first cell layout using an APR tool includes connecting the first set of pins to be connected in the common set of pins together, thereby changing the first circuit into a second circuit, the second circuit being configured as a functional version of the first circuit.

[0680] In some embodiments, connecting the first group of pins to be connected in the common pin group together to change the first circuit to the second circuit includes connecting the first pin and the second pin together.

[0681] In some embodiments, connecting the first pin and the second pin together includes: placing a third conductive component pattern in a first wiring track of a first set of candidate wiring tracks, the third conductive component pattern extending in a first direction and overlapping the first conductive component pattern and the second conductive component pattern, and on a second layout layer above the first layout layer, the first set of candidate wiring tracks is not occupied by a corresponding conductive component pattern in the second layout layer, the first set of candidate wiring tracks extending in the first direction, and each wiring track of the first set of candidate wiring tracks being separated from each other in a second direction different from the first direction; and connecting the first conductive component pattern and the second conductive component pattern by at least the third conductive component pattern.

[0682] In some embodiments, the first circuit includes: a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor, wherein the first conductive component is patterned connected to the gate of the first transistor, the gate of the second transistor, the drain of the third transistor, and the drain of the fourth transistor; and the second conductive component is patterned connected to the drain of the fifth transistor.

[0683] In some embodiments, the first circuit includes: a first transistor; a second transistor; a third transistor; a fourth transistor; and a fifth transistor, wherein the first conductive component is patterned connected to the gate of the first transistor, the drain of the third transistor, and the drain of the fourth transistor; and the second conductive component is patterned connected to the drain of the fifth transistor and the gate of the first transistor.

[0684] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an integrated circuit (IC), the method comprising: A processor generates a netlist for a first circuit, wherein the first circuit is configured as a non-functional circuit and includes a first pin and a second pin electrically disconnected from each other, wherein generating the netlist by the first circuit includes: Designate the first pin and the second pin as the first set of pins to be connected together; The processor generates a first cell layout for the first circuit, wherein the first cell layout includes a first conductive component pattern and a second conductive component pattern extending in a first direction, the first conductive component pattern and the second conductive component pattern being located on a first layout layer and separated from each other in a second direction different from the first direction, wherein the first conductive component pattern and the second conductive component pattern are not connected together, the first conductive component pattern corresponding to the first pin, and the second conductive component pattern corresponding to the second pin; The first cell layout is placed in the first area of ​​the layout design using an Automatic Placement and Routing (APR) tool, wherein placing the first cell layout using the APR tool includes: Connect the first pin and the second pin in the first group of pins together to transform the first circuit into a second circuit, which is configured as a functional version of the first circuit.

2. The method according to claim 1, wherein, The first group of pins designated as to be connected together includes: The first and second pins are labeled with a common tag and designated as the first group of pins to be connected; and Specify the first group of pins to be connected as the first group of pins to be connected together.

3. The method according to claim 1, wherein, The first group of pins designated as to be connected together includes: The first pin is marked as the first pin to be connected using a first label, and the second pin is marked as the second pin to be connected using a second label; The first pin to be connected and the second pin to be connected are designated as the first group of pins to be connected; and Specify the first group of pins to be connected as the first group of pins to be connected together.

4. The method according to claim 1, wherein, Connecting the first pin and the second pin in the first group of pins together includes: The first conductive component pattern and the second conductive component pattern are connected by at least a third conductive component pattern, the third conductive component pattern extending in the second direction, overlapping with the first conductive component pattern and the second conductive component pattern, and located on a second layout layer above the first layout layer.

5. The method according to claim 4, wherein, Placing the first unit layout in the first region of the layout design includes: A first routing track is selected from a first group of candidate routing tracks, wherein the first group of candidate routing tracks is not occupied by the corresponding conductive component pattern in the second layout layer, the first group of candidate routing tracks extends in the second direction, and each routing track in the first group of candidate routing tracks is separated from each other in the first direction; and The pattern of the third conductive component is placed in the first wiring track.

6. The method according to claim 4, wherein, Connecting the first conductive component pattern and the second conductive component pattern through at least the third conductive component pattern includes: The third conductive component pattern is placed to overlap with the first conductive component pattern and the second conductive component pattern, and in the first wiring track of the first group of wiring tracks, the first group of wiring tracks extends in the second direction, and each wiring track of the first group of wiring tracks is separated from each other in the first direction; A first through-hole pattern is placed above the first conductive component pattern, the first through-hole pattern being located between the first conductive component pattern and the third conductive component pattern, and the first conductive component pattern and the conductive third conductive component pattern being connected together; and The second through-hole pattern is placed above the second conductive component pattern, the second through-hole pattern is located between the second conductive component pattern and the third conductive component pattern, and the second conductive component pattern and the third conductive component pattern are connected together.

7. The method of claim 6, wherein The first circuit also includes a third pin and a fourth pin that are electrically disconnected from each other; The netlist for generating the first circuit further includes: Designate the third pin and the fourth pin as the second set of pins to be connected together; The first unit layout further includes a fourth conductive component pattern and a fifth conductive component pattern extending in the first direction. The fourth conductive component pattern and the fifth conductive component pattern are on the first layout layer and separated from each other in the second direction. The fourth conductive component pattern and the fifth conductive component pattern are not connected together. The fourth conductive component pattern corresponds to the third pin, and the fifth conductive component pattern corresponds to the fourth pin.

8. The method according to claim 7, wherein, Placing the first unit layout using the automatic layout and wiring tool also includes: Connect the third and fourth pins in the second group of pins together to transform the first circuit into the second circuit.

9. The method according to claim 8, wherein, Connecting the third and fourth pins in the second group of pins together includes: The fourth conductive component pattern and the fifth conductive component pattern are connected by at least a sixth conductive component pattern, the sixth conductive component pattern extending in the second direction, overlapping with the fourth conductive component pattern and the fifth conductive component pattern, and located on the second layout layer.

10. The method according to claim 9, wherein, Connecting the fourth conductive component pattern and the fifth conductive component pattern through at least the sixth conductive component pattern includes: The sixth conductive component pattern is placed to overlap with the fourth and fifth conductive component patterns and is located in the second wiring track of the second set of wiring tracks, which extends in the second direction and each wiring track of the second set of wiring tracks is separated from each other in the first direction. The third through-hole pattern is placed above the fourth conductive component pattern, the third through-hole pattern being located between the fourth conductive component pattern and the sixth conductive component pattern and connecting the fourth conductive component pattern and the sixth conductive component pattern together; and The fourth through-hole pattern is placed above the fifth conductive component pattern, the fourth through-hole pattern is located between the fifth conductive component pattern and the sixth conductive component pattern, and the fifth conductive component pattern and the sixth conductive component pattern are connected together.

11. A system for manufacturing integrated circuits, the system comprising: A non-transitory computer-readable medium configured to store executable instructions; as well as A processor, connected to the non-transitory computer-readable medium, wherein the processor is configured to execute the following instructions: Generating a netlist for a first circuit, wherein the first circuit is configured as a non-functional circuit and includes a first pin, a second pin, and a third pin electrically disconnected from each other, wherein generating the netlist for the first circuit includes: The first pin, the second pin, and the third pin are combined into a first group of pins to be connected; A first cell layout for the first circuit is generated, wherein the first cell layout includes a first conductive component pattern corresponding to the first pin, a second conductive component pattern corresponding to the second pin, and a third conductive component pattern corresponding to the third pin. The first cell layout is placed in the first area of ​​the layout design using an Automatic Placement and Routing (APR) tool, wherein placing the first cell layout using the APR tool includes: The first group of pins to be connected are connected together, thereby turning the first circuit into a second circuit, which is configured as a functional version of the first circuit.

12. The system according to claim 11, wherein, The processor is configured to execute the instructions to connect the first group of pins to be connected together, thereby changing the first circuit to the second circuit, including: Connect the first pin, the second pin, and the third pin together.

13. The system according to claim 12, wherein, The processor is configured to execute instructions that connect the first pin, the second pin, and the third pin together, including: The first conductive component pattern, the second conductive component pattern, and the third conductive component pattern are connected by at least a fourth conductive component pattern. The first conductive component pattern, the second conductive component pattern, and the third conductive component pattern extend in a first direction and are located on a first layout layer, and are separated from each other in a second direction different from the first direction. The fourth conductive component pattern extends along the second direction, overlaps with the first conductive component pattern, the second conductive component pattern and the third conductive component pattern, and is located on a second layout layer above the first layout layer.

14. The system according to claim 13, wherein, The processor is configured to execute the instructions that connect the first conductive component pattern, the second conductive component pattern, and the third conductive component pattern through at least the fourth conductive component pattern, including: The fourth conductive component pattern is placed to overlap with the first conductive component pattern, the second conductive component pattern and the third conductive component pattern, and is located in the first wiring track of the first group of wiring tracks, the first group of wiring tracks extending in the second direction, and each wiring track of the first group of wiring tracks being separated from each other in the first direction; The first through-hole pattern is placed above the first conductive component pattern, the first through-hole pattern is located between the first conductive component pattern and the fourth conductive component pattern, and the first conductive component pattern and the fourth conductive component pattern are connected together. A second through-hole pattern is placed above the second conductive component pattern, the second through-hole pattern being located between the second conductive component pattern and the fourth conductive component pattern, and connecting the second conductive component pattern and the fourth conductive component pattern together; and The third through-hole pattern is placed above the third conductive component pattern, and the third through-hole pattern is located between the third conductive component pattern and the fourth conductive component pattern, connecting the third conductive component pattern and the fourth conductive component pattern together.

15. The system according to claim 11, wherein, The first circuit includes: First transistor; Second transistor; Third transistor; Fourth transistor; The fifth transistor, Wherein, the first conductive component is patterned and connected to the gate of the first transistor and the gate of the second transistor; The second conductive component pattern is connected to the drain of the third transistor and the drain of the fourth transistor; and The third conductive component pattern is connected to the drain of the fifth transistor.

16. A non-transitory computer-readable medium configured to store executable instructions, wherein, The executable instructions are configured to be executed by a processor connected to the non-transitory computer-readable medium, the non-transitory computer-readable medium causing the processor to perform a method comprising: Generating a netlist for a first circuit, wherein the first circuit is configured as a non-functional circuit and includes a first pin and a second pin electrically disconnected from each other, wherein generating the netlist for the first circuit includes: The first pin and the second pin are labeled as the first group of pins to be connected; and Designate the first group of pins to be connected as the common pin group to be connected together; A first cell layout of the first circuit is generated, wherein the first cell layout includes a first conductive component pattern corresponding to the first pin and a second conductive component pattern corresponding to the second pin, and the first conductive component pattern and the second conductive component pattern are in a first layout layer; The first cell layout is placed in the first area of ​​the layout design using an Automatic Placement and Routing (APR) tool, wherein placing the first cell layout using the APR tool includes: The first group of pins to be connected in the common pin group are connected together, thereby changing the first circuit into a second circuit, which is configured as a functional version of the first circuit.

17. The non-transitory computer-readable medium according to claim 16, wherein, Connecting the first group of pins to be connected in the common pin group together, thereby changing the first circuit into the second circuit, includes: Connect the first pin and the second pin together.

18. The non-transitory computer-readable medium according to claim 16, wherein, Connecting the first pin and the second pin together includes: A third conductive component pattern is placed in the first wiring track of the first group of candidate wiring tracks. The third conductive component pattern extends in a first direction, overlaps with the first conductive component pattern and the second conductive component pattern, and on a second layout layer above the first layout layer, the first group of candidate wiring tracks is not occupied by the corresponding conductive component pattern in the second layout layer. The first group of candidate wiring tracks extends in the first direction, and each wiring track of the first group of candidate wiring tracks is separated from each other in a second direction different from the first direction; and The first conductive component pattern and the second conductive component pattern are connected by at least the third conductive component pattern.

19. The non-transitory computer-readable medium according to claim 16, wherein, The first circuit includes: First transistor; Second transistor; Third transistor; Fourth transistor; The fifth transistor, Wherein, the first conductive component is patterned and connected to the gate of the first transistor, the gate of the second transistor, the drain of the third transistor, and the drain of the fourth transistor; and The second conductive component pattern is connected to the drain of the fifth transistor.

20. The non-transitory computer-readable medium of claim 16, wherein, The first circuit includes: First transistor; Second transistor; Third transistor; Fourth transistor; The fifth transistor, Wherein, the first conductive component is patterned and connected to the gate of the first transistor, the drain of the third transistor, and the drain of the fourth transistor; and The second conductive component is patterned to the drain of the fifth transistor and the gate of the first transistor.

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