Simulation method, device and equipment of quantum chip layout and storage medium

Abstract

The present disclosure provides a quantum chip layout simulation method, device, equipment and storage medium, relates to the field of computers, in particular to the field of quantum computing and quantum simulation. The specific implementation scheme is: simulating a quantum chip layout to obtain a plurality of eigenmode information; based on the plurality of eigenmode information, obtaining an electrical energy proportion of a quantum device under different eigenmodes; wherein the eigenmode information in the plurality of eigenmode information corresponds to an eigenmode; the quantum device is one of a plurality of quantum devices included in the quantum chip layout; based on the electrical energy proportion of the quantum device under different eigenmodes, eigenmode information of the quantum device is identified from the plurality of eigenmode information.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computing and quantum simulation technology. Background Technology

[0002] Similar to the development path of classical chips, expanding the number of qubits in superconducting quantum chips not only places higher demands on micro- and nano-fabrication processes, but also makes the simulation of superconducting quantum chips increasingly indispensable before formal fabrication. It should be noted that the simulation of superconducting quantum chips aims to characterize the chip's features as realistically as possible, enabling researchers to better predict chip performance during the design phase and reduce the material, human, and time costs of repeated experiments. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for simulating quantum chip layouts.

[0004] According to one aspect of this disclosure, a simulation method for quantum chip layout is provided, comprising:

[0005] Pattern recognition steps for quantum devices: wherein the pattern recognition steps include:

[0006] The quantum chip layout was subjected to a first simulation process to obtain information on multiple intrinsic modes.

[0007] Based on the multiple intrinsic mode information, the inductance energy ratio of the quantum device under different intrinsic modes is obtained; wherein, the intrinsic mode information in the multiple intrinsic mode information corresponds to an intrinsic mode; the quantum device is one of the multiple quantum devices included in the quantum chip layout;

[0008] Based on the inductance energy ratio of the quantum device under different intrinsic modes, the intrinsic mode information of the quantum device is identified from the multiple intrinsic mode information.

[0009] According to another aspect of this disclosure, a simulation apparatus for a quantum chip layout is provided, comprising:

[0010] A simulation unit is used to execute a pattern recognition step for a quantum device. The pattern recognition step includes: performing a first simulation process on a quantum chip layout to obtain multiple intrinsic mode information; obtaining the inductance energy percentage of the quantum device under different intrinsic modes based on the multiple intrinsic mode information; wherein each intrinsic mode information corresponds to an intrinsic mode; the quantum device is one of multiple quantum devices included in the quantum chip layout; and identifying the intrinsic mode information of the quantum device from the multiple intrinsic mode information based on the inductance energy percentage of the quantum device under different intrinsic modes.

[0011] The output unit is used to output the intrinsic mode information of the quantum device.

[0012] According to another aspect of this disclosure, a computing device is provided, comprising:

[0013] At least one quantum processing unit (QPU);

[0014] A memory, coupled to the at least one QPU and used to store executable instructions,

[0015] The instruction is executed by the at least one QPU to enable the at least one QPU to perform the method described above;

[0016] Or, including:

[0017] At least one processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above.

[0020] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above.

[0021] Alternatively, the computer instructions may be used to cause the computer to perform the methods described above.

[0022] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by at least one quantum processing unit, implements the methods described above.

[0023] Alternatively, the computer program may implement the above-described method when executed by a processor.

[0024] In this way, the present invention utilizes multiple intrinsic mode information obtained from simulation to obtain the inductance energy ratio of the quantum device under different intrinsic modes, and then identifies the intrinsic mode information of the quantum device from the multiple intrinsic mode information; thus, the matching of the quantum device with the mode is completed automatically, and the process is accurate and efficient, laying the foundation for the efficient execution of other simulation tasks in the future; in addition, the present invention is simple and easy to implement, has a low threshold for use, and is practical.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0026] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0027] Figure 1 This is a schematic diagram of the implementation flow of the simulation method for quantum chip layout according to embodiments of this disclosure. Figure 1 ;

[0028] Figure 2 This is a schematic diagram of the implementation flow of the simulation method for quantum chip layout according to embodiments of this disclosure. Figure 2 ;

[0029] Figure 3 This is a schematic diagram of the implementation flow of the simulation method for quantum chip layout according to embodiments of this disclosure. Figure 3 ;

[0030] Figure 4 This is a schematic diagram of the quantum chip layout according to an embodiment of the present disclosure;

[0031] Figure 5 This is a schematic diagram illustrating the implementation flow of a simulation method for a quantum chip layout according to an embodiment of the present disclosure in a specific example;

[0032] Figure 6 This is a schematic diagram of the layout of a quantum chip in a specific application scenario according to an embodiment of this disclosure;

[0033] Figure 7 This is a schematic diagram illustrating the implementation flow of a simulation method for a quantum chip layout according to an embodiment of the present disclosure in another specific example;

[0034] Figure 8 This is a schematic diagram of the quantum chip layout in another specific application scenario according to an embodiment of this disclosure;

[0035] Figures 9(a) to 9(e) This is a schematic diagram illustrating the performance analysis results in a specific application scenario according to an embodiment of this disclosure;

[0036] Figure 10 This is a schematic diagram of the structure of a simulation device used to implement the quantum chip layout of the embodiments of this disclosure;

[0037] Figure 11 This is a block diagram of a computing device used to implement a simulation method for a quantum chip layout according to embodiments of the present disclosure. Detailed Implementation

[0038] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0039] In this document, the term "and / or" merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The term "at least one" in this document indicates any combination of at least two of a plurality of elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. The terms "first" and "second" in this document refer to and distinguish between multiple similar technical terms, not to restrict the order or to limit there to only two. For example, "first feature" and "second feature" refer to two categories / two features; the first feature can be one or more, and the second feature can also be one or more.

[0040] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can still be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0041] As a logical inevitable breakthrough in chip size beyond the limits of classical physics and a landmark technology of the post-Moore's Law era, quantum computing has garnered significant attention. Currently, quantum computing is developing rapidly at the application, algorithm, and hardware levels. It is worth noting that the realization of quantum algorithms and applications is highly dependent on the development and progress of quantum hardware. Several different technological solutions exist for quantum hardware implementation, such as superconducting circuits, ion traps, and optical quantum systems. Benefiting from its excellent scalability and mature semiconductor manufacturing processes, superconducting quantum circuits are considered one of the most promising technological routes. Furthermore, in recent years, with the development of superconducting quantum computing technologies and micro / nano fabrication processes, the number of qubits integrated on superconducting quantum chips is increasing, leading to richer and more comprehensive chip structures.

[0042] Similar to the development path of classical chips, expanding the number of qubits in superconducting quantum chips not only places higher demands on micro- and nano-fabrication processes, but also makes the simulation of superconducting quantum chips increasingly indispensable before formal fabrication. It should be noted that the simulation of superconducting quantum chips aims to characterize the chip's features as realistically as possible, enabling researchers to better predict chip performance during the design phase and reduce the material, human, and time costs of repeated experiments.

[0043] In the design and simulation of superconducting quantum chip layouts, the output simulation results typically include eigenmode information from the quantum chip layout. This eigenmode information mainly includes the eigenfrequency and electromagnetic field distribution information corresponding to the eigenmode. Researchers usually need to map the eigenmode information one by one to the quantum device to determine the matching relationship between the quantum device and the eigenmode information. Currently, researchers mainly determine the correspondence between eigenmode information and quantum devices based on the electromagnetic field distribution information in each eigenmode information in the simulation results (through manual interaction with electromagnetic field simulation software), according to the distribution of the electric field under different eigenmodes. For example, if the electromagnetic field of a certain eigenmode information is concentrated in a specific quantum device, it can be determined that the eigenmode information belongs to that quantum device. However, with the increase in the scale of qubits in quantum chip layouts, the number of quantum devices whose eigenmode information needs to be determined is also increasing. Relying solely on manual matching of quantum devices with eigenmode information based on electromagnetic field distribution would become extremely labor-intensive and inefficient; moreover, manual operation has a high degree of uncertainty, leading to a certain error rate, which would reduce the accuracy of the simulation results.

[0044] Furthermore, the design and simulation of superconducting quantum chip layouts require various simulation tasks to verify the chip's performance. These tasks are diverse, demanding different simulation parameters and requiring different post-processing methods. Current methods often involve manually obtaining simulation parameters and then manually analyzing the results to arrive at performance analysis. However, with the increasing number of qubits in superconducting quantum chips, traditional manual methods significantly reduce simulation efficiency, severely impacting the iteration speed of quantum chip layout development. Therefore, an accurate, efficient, and automated simulation scheme for quantum chip layouts is urgently needed.

[0045] Based on this, the disclosed solution provides an automated simulation method. On the one hand, it can automatically identify the correspondence between quantum devices and intrinsic mode information, thus effectively improving processing efficiency while reducing the error rate. On the other hand, it can also automatically generate performance analysis results, thereby supporting the iterative development of quantum chip layouts.

[0046] Specifically, Figure 1 This is a schematic diagram of the implementation flow of the simulation method for quantum chip layout according to embodiments of this disclosure. Figure 1 This method can be optionally applied to quantum computing devices that also have classical computing capabilities, or it can be applied to classical computing devices that also have quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any restrictions on this method.

[0047] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 1 As shown, it includes: a pattern recognition step for quantum devices: wherein the pattern recognition step includes:

[0048] Step S101: Perform the first simulation processing on the quantum chip layout to obtain multiple intrinsic mode information.

[0049] Step S102: Based on the multiple intrinsic mode information, obtain the inductance energy ratio of the quantum device in different intrinsic modes.

[0050] Here, the intrinsic mode information in the plurality of intrinsic mode information corresponds to an intrinsic mode; for example, there is a one-to-one correspondence between intrinsic mode information and intrinsic modes. Furthermore, the quantum device is one of the plurality of quantum devices included in the quantum chip layout.

[0051] Step S103: Based on the inductance energy ratio of the quantum device in different intrinsic modes, identify the intrinsic mode information of the quantum device from the multiple intrinsic mode information.

[0052] In this way, the present invention utilizes multiple intrinsic mode information obtained from simulation to obtain the inductance energy ratio of the quantum device under different intrinsic modes, and then identifies the intrinsic mode information of the quantum device from the multiple intrinsic mode information; thus, the matching of the quantum device with the mode is completed automatically, and the process is accurate and efficient, laying the foundation for the efficient execution of other simulation tasks in the future; in addition, the present invention is simple and easy to implement, has a low threshold for use, and is practical.

[0053] It should be noted that the intrinsic modes described in this disclosure are the inherent oscillation modes of the quantum chip (or quantum chip layout) itself, and these oscillation modes are caused by the quantum devices in the quantum chip layout. In practical applications, when the quantum chip layout contains multiple quantum devices, there will be multiple oscillation modes (i.e., intrinsic modes). In this case, this disclosure can be used to automatically determine the quantum device to which the oscillation mode belongs. This provides data support for subsequent simulation tasks and lays the foundation for improving simulation efficiency.

[0054] In one specific example, the quantum chip layout includes, but is not limited to, quantum bits, couplers, readout cavities, etc.

[0055] In a specific example, the intrinsic mode information includes: the intrinsic frequency corresponding to the intrinsic mode, and the electric field intensity distribution information of the intrinsic mode in space.

[0056] Furthermore, in a specific example, the quantum chip layout can also be a chip layout of a superconducting quantum chip. Here, the superconducting quantum chip refers to a quantum chip made of superconducting materials. For example, all components in the superconducting quantum chip (such as qubits, coupling devices, etc.) are made of superconducting materials. This allows the disclosed solution to be applied to superconducting quantum chips, enriching the application scenarios of the disclosed solution.

[0057] Furthermore, when this disclosed solution is applied to a superconducting quantum chip layout, it can also be applied to superconducting quantum chip layouts of any size, and it remains applicable as the number of quantum devices increases.

[0058] In a specific example of the disclosed scheme, the eigenfrequency of the quantum device can be obtained in the following manner; specifically, the pattern recognition step of the quantum device further includes: obtaining the eigenfrequency of the quantum device based on the eigenmode information of the quantum device. This lays the foundation for the efficient execution of other simulation tasks subsequently.

[0059] In a specific example of the scheme disclosed herein, Figure 2 This is a schematic diagram of the implementation flow of the simulation method for quantum chip layout according to embodiments of this disclosure. Figure 2 This method can be optionally applied to quantum computing devices that also possess classical computing capabilities, or it can be applied to classical computing devices that also possess quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any limitations on these applications. It is understood that the above... Figure 1 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0060] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 2 As shown, the simulation method includes a pattern recognition step for quantum devices; wherein, the pattern recognition step specifically includes:

[0061] Step S201: Perform the first simulation processing on the quantum chip layout to obtain multiple intrinsic mode information.

[0062] Step S202: Based on the multiple intrinsic mode information, obtain the inductance energy ratio of the quantum device in different intrinsic modes.

[0063] Here, the intrinsic mode information in the multiple intrinsic mode information corresponds to an intrinsic mode; the quantum device is one of the multiple quantum devices included in the quantum chip layout.

[0064] Step S203: Based on the inductance energy ratio of the quantum device in different intrinsic modes, identify the intrinsic mode information of the quantum device from the multiple intrinsic mode information.

[0065] Step S204: Based on the eigenmode information of the quantum device, obtain the eigenfrequency of the quantum device.

[0066] In a specific example, each eigenmode information corresponds to an eigenmode. In this case, the eigenmode information of the quantum device can specifically include the eigenfrequency of the quantum device within its eigenmode. Thus, based on the eigenmode information of the quantum device, the eigenfrequency of the quantum device can be obtained.

[0067] Step S205: Based on the intrinsic frequencies of each quantum device, obtain the target mapping relationship corresponding to the quantum chip layout.

[0068] Here, the target mapping relationship characterizes the correspondence between quantum devices and intrinsic frequencies in the quantum chip layout.

[0069] Thus, this disclosure provides a feasible solution for obtaining the target mapping relationship corresponding to the quantum chip layout, and the process is automated. Compared with the existing method of manually matching quantum devices with intrinsic frequencies, this disclosure greatly shortens the matching time and improves efficiency, thereby improving the ease of execution and simulation efficiency of subsequent simulation tasks.

[0070] In a specific example of the disclosed solution, the intrinsic mode information of the quantum device can be identified from the plurality of intrinsic mode information in the following manner; specifically, the above-mentioned identification of the intrinsic mode information of the quantum device from the plurality of intrinsic mode information based on the inductance energy ratio of the quantum device in different intrinsic modes (i.e., the above-mentioned step S103 or step S203) specifically includes:

[0071] Step S103-1: Determine the target inductance energy ratio of the quantum device from the inductance energy ratio of the quantum device in different intrinsic modes.

[0072] Step S103-2: Based on the multiple intrinsic mode information, determine the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device;

[0073] Step S103-3: Based on the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device, obtain the intrinsic mode information of the quantum device.

[0074] In other words, from the calculated inductance energy percentages of the quantum device under different intrinsic modes, the inductance energy percentage that meets the requirements is selected as the target inductance energy percentage of the quantum device; then the intrinsic mode information corresponding to the target inductance energy percentage of the quantum device is used as the intrinsic mode information of the quantum device, thus realizing the automated matching process between the quantum device and the intrinsic mode information.

[0075] Thus, this disclosure provides a specific scheme for obtaining the intrinsic mode information of a quantum device. This scheme is simple, easy to implement, and highly practical.

[0076] In a specific example of the disclosed solution, the target inductance energy ratio of the quantum device can be obtained in the following manner; specifically, the determination of the target inductance energy ratio of the quantum device from the inductance energy ratios of the quantum device in different intrinsic modes (i.e., step S103-1 as described above) specifically includes:

[0077] The maximum proportion is selected from the proportions of inductance energy corresponding to different intrinsic modes of the quantum device, wherein the target inductance energy proportion is the maximum proportion.

[0078] In other words, among the calculated inductance energy percentages of the quantum device under different intrinsic modes, the inductance energy percentage with the largest value is selected as the target inductance energy percentage of the quantum device, so as to determine the intrinsic mode information of the quantum device.

[0079] Thus, this disclosure provides a specific scheme for obtaining the target inductance energy ratio of a quantum device. Moreover, the scheme is simple and easy to implement, has strong practicality, and is highly interpretable.

[0080] In a specific example of the disclosed solution, the inductance energy ratio of the quantum device under different intrinsic modes can be obtained in the following manner; specifically, the above-described method of obtaining the inductance energy ratio of the quantum device under different intrinsic modes based on the multiple intrinsic mode information (i.e., the above-described steps S102 or S202) specifically includes:

[0081] The inductance energy percentage p of quantum device n in intrinsic mode m among the plurality of quantum devices is obtained as follows: mn :

[0082] Based on information from multiple intrinsic modes, the inductance energy of intrinsic mode m stored in quantum device n is obtained. And obtain the total inductance energy stored in the intrinsic mode m. Wherein, the intrinsic mode information corresponding to intrinsic mode m is one of the plurality of intrinsic mode information;

[0083] The inductor energy stored in quantum device n based on the intrinsic mode m and the total inductance energy stored in the intrinsic mode m The inductance energy percentage p of quantum device n in intrinsic mode m is obtained. mn .

[0084] In other words, in this example, the inductance energy of eigenmode m stored in quantum device n is first obtained based on information from multiple eigenmodes. And obtain the total inductance energy stored in the intrinsic mode m. The inductor energy stored in quantum device n based on the intrinsic mode m and the total inductance energy stored in the intrinsic mode m For example, based on the ratio of the two, the inductance energy percentage p of quantum device n in eigenmode m can be obtained. mn In this way, the inductance energy ratio of quantum devices in different intrinsic modes can be obtained.

[0085] For example, the inductance energy percentage of quantum device n in its intrinsic mode m can be obtained by the following specific expression: p mn :

[0086]

[0087] Furthermore, based on the above formula, the inductor energy percentage of the quantum device in multiple eigenmodes can be obtained. For example, if simulation of the quantum chip layout yields M (positive integers greater than or equal to 2) eigenmodes, and each eigenmode corresponds to a single eigenmode, then the inductor energy percentage of the quantum device in the M eigenmodes can be obtained, which can be denoted as p. 1n ,p 2n ,…,p mn ,…,p Mn Thus, based on the energy percentage of the M inductors, the eigenmode information of quantum device n can be obtained, and consequently, the eigenfrequency of quantum device n can be obtained.

[0088] Thus, this disclosure provides a specific method for obtaining the inductance energy ratio of a quantum device under different intrinsic modes. This provides quantifiable data support for the subsequent automated and rapid acquisition of intrinsic mode information of quantum devices. Moreover, the method is simple to implement, highly interpretable, and has strong practicality.

[0089] In a specific example of the scheme disclosed herein, the inductor energy described above can be obtained in the following manner. That is, based on the information from multiple intrinsic modes described above, the inductance energy of intrinsic mode m stored in quantum device n is obtained. Specifically, it includes:

[0090] Based on information from multiple intrinsic modes, the inductance value L of quantum device n is calculated. n And the voltage (i.e. peak voltage) V of the eigenmode m along the voltage integral line of the quantum device n in space is calculated. mn ;

[0091] Based on the inductance value L of quantum device n n The intrinsic mode m represents the voltage V along the voltage integral line of the quantum device n in space. mn and the intrinsic frequency ω' corresponding to the intrinsic mode m m The inductance energy of the intrinsic mode m stored in the quantum device n is obtained.

[0092] It should be noted that the eigenmode information obtained from finite element electromagnetic simulation (e.g., high-frequency electromagnetic field simulation) of the quantum chip layout includes the eigenfrequency corresponding to the eigenmode. Furthermore, the eigenmode information corresponding to eigenmode m in the plurality of eigenmode information includes the eigenfrequency ω' corresponding to eigenmode m. m .

[0093] For example, in a specific instance, the intrinsic mode m is stored in the inductance energy of the quantum device n. It can be obtained through the following formula:

[0094]

[0095] in, This represents the magnetic flux of quantum device n in its eigenmode m.

[0096] Thus, this disclosure provides a method for obtaining the inductor energy of the intrinsic mode m stored in the quantum device n. This specific scheme provides quantifiable data support for the subsequent automated and rapid acquisition of intrinsic mode information of quantum devices. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0097] In a specific example of the scheme disclosed herein, the inductance value L of the quantum device n can be obtained in the following manner. n Specifically, based on multiple intrinsic mode information, the inductance value L of the quantum device n is calculated as described above. n Specifically, it includes:

[0098] The correlation between the inductance energy ratio of quantum device n in different intrinsic modes was obtained;

[0099] Based on the correlation between the inductance energy ratio of quantum device n in different eigenmodes, the inductance value L of quantum device n is obtained. n .

[0100] For example, based on the normalization relation, the correlation between the inductance energy percentage of quantum device n in different eigenmodes can be specifically as follows:

[0101]

[0102] Here, for the M eigenmodes, m takes values ​​from 1 to M.

[0103] Furthermore, based on the above correlation, the inductance value L of the quantum device n can be obtained. n The specific expression is:

[0104]

[0105] Thus, this disclosed method provides a way to obtain the inductance value L of the quantum device n. n This specific scheme provides quantifiable data support for the subsequent automated and rapid acquisition of intrinsic mode information of quantum devices. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0106] Furthermore, in a specific example of the scheme disclosed herein, the voltage V of the eigenmode m along the voltage integral line of the quantum device n in space can be obtained in the following manner. mn Specifically, based on information from multiple intrinsic modes, the voltage V of intrinsic mode m along the voltage integral line of quantum device n in space is calculated. mn Specifically, it includes:

[0107] Based on the electric field intensity distribution information of intrinsic mode m in space, the voltage V of quantum device n along the voltage integral line in space is calculated. mn Here, the eigenmode information corresponding to eigenmode m includes the electric field intensity distribution information of eigenmode m in space.

[0108] It should be noted that the eigenmode information obtained from finite element electromagnetic simulation (e.g., high-frequency electromagnetic field simulation) of the quantum chip layout may also include the electric field intensity distribution information of the eigenmode in space. Furthermore, the eigenmode information corresponding to eigenmode m among the multiple eigenmode information includes the electric field intensity distribution information of eigenmode m in space, such as the peak electric field intensity distribution.

[0109] For example, based on the peak electric field distribution of eigenmode m in space The voltage (i.e., peak voltage) V of the eigenmode m along the voltage integral line of the quantum device n in space can be obtained using the following formula. mn :

[0110]

[0111] here, This represents the voltage integral line vector of quantum device n in the quantum chip layout. For known terms, The length can be determined by the voltage integration line added during preprocessing, the voltage integration line vector. The direction can be determined based on the default positive direction of the coordinate system in which the quantum chip layout is located. The location vector represents the peak distribution of the electric field intensity.

[0112] Thus, this disclosure provides a method for obtaining the voltage V of the eigenmode m along the voltage integral line of the quantum device n in space. mn This specific scheme provides quantifiable data support for the subsequent automated and rapid acquisition of intrinsic mode information of quantum devices. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0113] In a specific example of the scheme disclosed herein, the total inductance energy stored in the eigenmode m can be obtained in the following manner. Specifically, the total inductance energy stored in the intrinsic mode m as described above is obtained. Specifically, it includes:

[0114] Based on the electric field intensity distribution information of eigenmode m in space, the average electric field energy stored in space by eigenmode m is obtained. Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space;

[0115] The average electric field energy stored in space for the eigenmode m The total inductance energy stored in the intrinsic mode m

[0116] For example, the average electric field energy stored in space by the eigenmode m It can be obtained through the following formula:

[0117]

[0118] here, The dielectric tensor, v, represents the dielectric tensor at different locations in space. fullThe volume of the space is represented by the above quantities, all of which are known quantities.

[0119] Furthermore, the average electric field energy stored in space for the eigenmode m The total inductance energy stored in the intrinsic mode m That is to say

[0120] Thus, the present disclosure provides a method for obtaining the total inductance energy stored in the eigenmode m. This specific scheme provides quantifiable data support for the subsequent automated and rapid acquisition of intrinsic mode information of quantum devices. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0121] In a specific example, such as Figure 3 As shown, to obtain the inductance energy percentage p of quantum device n in eigenmode m, mn The flowchart is as follows:

[0122] Step S301: Based on the electric field intensity distribution information of the intrinsic mode m in space, obtain the average electric field energy stored in space by the intrinsic mode m.

[0123] Step S302: Store the average electric field energy of the intrinsic mode m in space. The total inductance energy stored in the intrinsic mode m

[0124] Step S303: Based on the electric field intensity distribution information of intrinsic mode m in space, calculate the voltage V of quantum device n along the voltage integral line in space for intrinsic mode m. mn .

[0125] Step S304: Obtain the correlation between the inductance energy ratio of quantum device n in different intrinsic modes.

[0126] Step S305: Based on the correlation between the inductance energy ratio of quantum device n in different eigenmodes, obtain the inductance value L of quantum device n. n .

[0127] Step S306: Based on the inductance value L of quantum device n n The intrinsic mode m represents the voltage V along the voltage integral line of the quantum device n in space. mn and the intrinsic frequency ω' corresponding to the intrinsic mode m m The inductance energy of the intrinsic mode m stored in the quantum device n is obtained.

[0128] Step S307: Inductance stored in quantum device n based on intrinsic mode m and the total inductance energy stored in the intrinsic mode m The inductance energy percentage p of quantum device n in intrinsic mode m is obtained. mn .

[0129] In a specific example of the disclosed solution, after identifying the intrinsic mode information of the quantum device, the obtained intrinsic mode information of the quantum device can also be applied to the following scenarios, specifically including:

[0130] Scenario 1: After identifying the intrinsic mode information of the quantum device, the coupling strength between quantum devices in the quantum chip layout is obtained based on the intrinsic mode information of the quantum device.

[0131] or,

[0132] Scenario 2: After identifying the intrinsic mode information of the quantum device, the quality factor corresponding to the quantum device in the quantum chip layout is obtained based on the intrinsic mode information and the preset mapping relationship between the intrinsic mode information and the quality factor. For example, in one example, the intrinsic frequency and the quality factor are in one-to-one correspondence. Therefore, in the process of simulating the quality factor of the quantum device, the intrinsic frequency of the quantum device can be obtained using the pattern recognition step of the quantum device, and then the quality factor of the quantum device can be obtained based on the correspondence between the intrinsic frequency and the quality factor.

[0133] Thus, this disclosed solution provides specific application scenarios, further enriching the application scenarios of this disclosed solution and laying the foundation for subsequent automated and rapid completion of simulation tasks.

[0134] In a specific example of the scheme disclosed herein, this disclosure provides a simulation method for pattern recognition steps based on quantum devices. Specifically, the simulation method includes:

[0135] The quantum chip layout is pre-simulated to obtain pre-simulation results;

[0136] Based on the pre-simulation results and the task information of the quantum task, a second simulation process is performed on the quantum chip layout to obtain the simulation results.

[0137] Based on the simulation results, a target report (i.e., performance analysis results) for the simulation task is generated;

[0138] The pre-simulation process includes a pattern recognition step for the quantum device, and the pre-simulation result is obtained based on the identified intrinsic mode information of the quantum device.

[0139] And / or, the second simulation processing steps include a pattern recognition step for the quantum device, and the simulation result is obtained based on the identified intrinsic mode information of the quantum device.

[0140] In other words, this disclosure provides a simulation method based on the pattern recognition steps of quantum devices. For example, in the pre-simulation process, the pattern recognition steps of quantum devices are used to identify the intrinsic mode information of quantum devices, thereby obtaining the pre-simulation results. Alternatively, in the simulation process for the simulation task (i.e., the second simulation process mentioned above), the pattern recognition steps of quantum devices are used to identify the intrinsic mode information of quantum devices, thereby obtaining the simulation results. This enriches the application scenarios of this disclosure and automates and rapidly realizes the simulation task.

[0141] Furthermore, the disclosed solution can automatically output a performance analysis result that characterizes the quantum chip layout, which can greatly improve the efficiency and accuracy of simulation, and at the same time promote the research and development and iteration efficiency of quantum chip layout.

[0142] Furthermore, in a specific example, in the pre-simulation processing flow, a pattern recognition step for quantum devices is used to identify the intrinsic mode information of the quantum devices, and then the pre-simulation results are obtained based on the identified intrinsic mode information of the quantum devices. That is, the pre-simulation processing of the quantum chip layout described above to obtain the pre-simulation results specifically includes:

[0143] At the first simulation accuracy, a pattern recognition step is performed on the quantum device to obtain the intrinsic mode information of the quantum device at the first simulation accuracy.

[0144] Based on the task information of the simulation task and the intrinsic mode information of the quantum device under the first simulation accuracy, the pre-simulation results are obtained; wherein, the pre-simulation results include the simulation parameters required by the simulation task.

[0145] In a specific example, the simulation parameters required for the simulation task include a target simulation start frequency and a number of target frequencies. Here, the target minimum eigenfrequency is the minimum value among the eigenfrequencys of each of the at least two target quantum devices to be simulated in the simulation task. The number of target frequencies is used to determine a plurality of target simulation frequencies starting from the target simulation start frequency, and the plurality of target simulation frequencies include the eigenfrequencys of the target quantum devices to be simulated in the simulation task.

[0146] In this way, the pattern recognition step of quantum devices is used in the pre-simulation process to identify the intrinsic mode information of quantum devices. Then, based on the identified intrinsic mode information of quantum devices, the pre-simulation results are automatically obtained, which provides support for subsequent simulations and greatly improves the efficiency and accuracy of simulation. At the same time, it effectively promotes the research and development and iteration efficiency of quantum chip layout.

[0147] Furthermore, in another example, a pattern recognition step for quantum devices is used in the simulation process for the simulation task (i.e., the second simulation processing described above) to identify the intrinsic mode information of the quantum devices, thereby obtaining the simulation results. That is, based on the pre-simulation results and the task information of the quantum task, the second simulation processing is performed on the quantum chip layout to obtain the simulation results, specifically including:

[0148] Based on the pre-simulation results and the task information of the quantum task, a pattern recognition step is performed on the quantum device under the target simulation accuracy to obtain the intrinsic mode information of the quantum device under the target simulation accuracy.

[0149] Based on the intrinsic mode information of the quantum device at the target simulation accuracy, the simulation results at the target simulation accuracy are obtained.

[0150] It should be noted that the target simulation accuracy is greater than the first simulation accuracy. For example, the first simulation accuracy is in the range of 1%-5%, while the target simulation accuracy is in the range of 0.1%-0.3%. In other words, the accuracy of the eigenfrequency of the quantum device obtained under the target simulation accuracy is higher than the eigenfrequency of the quantum device obtained from the above pre-simulation.

[0151] In this way, the simulation process for the simulation task adopts the pattern recognition step of quantum devices to identify the intrinsic mode information of quantum devices, and automatically obtains the simulation results based on the identified intrinsic mode information of quantum devices. This greatly improves the efficiency and accuracy of simulation, and also enhances the intelligence of the simulation process, thereby effectively promoting the research and development and iteration efficiency of quantum chip layout.

[0152] The following provides a more detailed explanation of this disclosed solution with specific examples;

[0153] First, this disclosure proposes a specific scheme for automatically identifying the correspondence between quantum devices and intrinsic frequencies in a quantum chip layout, based on the inductance energy participation ratio (iEPR). This allows for the automatic matching of the correspondence between quantum devices and intrinsic frequencies by inputting the quantum chip layout to be simulated. Furthermore, experimental verification shows that this scheme significantly improves the simulation efficiency of quantum chip layouts, providing important guidance for the automated design of quantum chips (such as superconducting quantum chips). Second, this disclosure also proposes a method for automatically generating performance analysis results. Using this scheme, only the quantum chip layout to be simulated (including or excluding couplers) and the task information of the simulation task need to be input; a performance analysis result characterizing the quantum chip layout can be automatically output. This greatly improves the efficiency and accuracy of simulation, while simultaneously promoting the research and iteration efficiency of quantum chip layouts.

[0154] The following section uses a superconducting quantum chip as an example and elaborates on the proposed solution from several aspects.

[0155] Part 1: Quantum Chip Landscape

[0156] As the core carrier of superconducting circuit technology, the development of superconducting quantum chips is crucial. Similar to classical chips, a complete quantum chip layout needs to be designed before formal production and processing. This layout includes all the core quantum devices, control lines, readout lines, etc., of the superconducting quantum chip. In practical applications, one of the most important quantum devices in superconducting quantum chips is the qubit. A qubit is typically composed of a coplanar capacitor and a Josephson junction. In practice, a substrate (usually silicon or sapphire) is selected, an aluminum film is deposited on the substrate, and different shapes are etched into the aluminum film to form the capacitance of the qubit. Finally, nonlinear devices, such as Josephson junctions, are placed between the two substrates and the aluminum film.

[0157] For example, in one example, such as Figure 4 The diagram shown is a schematic representation of a quantum chip layout comprising a qubit-coupler-qubit configuration. Specifically, the quantum chip layout includes:

[0158] A qubit (Qubit) 401, for example, has a cross-shaped structure;

[0159] Coupler 402, for example, is a rectangular structure;

[0160] Reading cavity 403, for example, is a triangular or serpentine structure;

[0161] The qubits 401 are connected to each other via couplers 402, and each qubit 401 is also connected to a corresponding readout cavity 403. The readout cavity 403 is connected to a readout port, which is then connected to a readout line 404 to facilitate the reading of quantum correlation data of the qubits 401 through the readout cavity 403.

[0162] Furthermore, in a specific example, such as Figure 4 As shown, both the quantum bit 401 and the coupler 402 are equipped with Josephson junctions 405. For example, a Josephson junction 405 can be placed below a cross-shaped structure or below a rectangular structure. Here, in actual electromagnetic simulation, the Josephson junction can be represented by its equivalent inductance.

[0163] Similar to classical chips, quantum chip layouts require simulation verification before formal tape-out to ensure they meet design requirements and reduce the manpower and material costs of repeated experiments. Finite element method (FEM) electromagnetic field simulation software is commonly used for quantum chip layout simulation. However, during simulation, the quantum chip layout is treated as a whole, without distinguishing individual quantum devices. Therefore, only the overall eigenmode information is obtained, not the eigenmode information of each individual quantum device within the layout. For example, the eigenmode information corresponding to qubits, couplers, or readout cavities cannot be determined, making it impossible to further calculate parameters crucial to the performance of superconducting quantum chips, such as the coupling strength between quantum devices.

[0164] Based on this, the present invention provides a highly accurate and fast pattern recognition method that can efficiently determine the correspondence between each quantum device and intrinsic mode information in the quantum chip layout, laying the foundation for further characterization of superconducting quantum chips.

[0165] Part Two: iEPR-based pattern recognition method (i.e., the pattern recognition steps for quantum devices described above).

[0166] The input to this scheme is the quantum chip layout of the superconducting quantum chip; the output is the target mapping relationship corresponding to the quantum chip layout, which characterizes the correspondence between quantum devices and intrinsic frequencies in the quantum chip layout.

[0167] like Figure 5 As shown, the specific steps include:

[0168] Step S501: Input the quantum chip layout.

[0169] Step S502: Perform finite element electromagnetic simulation (e.g., high-frequency electromagnetic field simulation) to obtain multiple eigenmode information; wherein, the eigenmode information includes the eigenfrequency corresponding to the eigenmode and the electric field intensity distribution information corresponding to the eigenmode; for example, the obtained eigenmode information includes:

[0170] (1) The eigenfrequency ω' corresponding to the eigenmode m m ;

[0171] (2) Information on the electric field intensity distribution of the intrinsic mode m in space, such as the peak electric field intensity distribution.

[0172] Step S503: Calculate the iEPR of the quantum devices in different intrinsic modes among multiple quantum devices.

[0173] Specifically, the iEPR of quantum device n under different eigenmodes m in a series of quantum devices will be explained in detail. Here, iEPR can characterize the proportion of the inductance energy distributed on the quantum device under different eigenmodes to the total inductance energy of that eigenmode in a capacitively coupled quantum system. For example, the iEPR of quantum device n under eigenmode m can be denoted as p. mn At this time, p mn It can be defined as:

[0174]

[0175] Furthermore, p can be calculated based on the following steps. mn Specifically, it includes:

[0176] Step S5031: Calculate the voltage (i.e., peak voltage) V across the voltage integral line of quantum device n in eigenmode m. mn The specific expression is as follows:

[0177]

[0178] in, This represents the voltage integral line vector of quantum device n in the quantum chip layout. For known terms, The length can be determined by the voltage integration line added during preprocessing, the voltage integration line vector. The direction can be determined based on the default positive direction of the coordinate system in which the quantum chip layout is located.

[0179] Step S5032: Calculate the average inductance energy of eigenmode m on quantum device n in space, and use it as the inductance energy of eigenmode m on quantum device n in space. The specific expression is as follows:

[0180]

[0181] in, L n Let be the inductance value of quantum device n, and be an unknown term.

[0182] Step S5033: Calculate the average electric field energy stored in space for the eigenmode m (which can be denoted as...). The total inductance energy stored in the intrinsic mode m is expressed as follows:

[0183]

[0184] in, This represents the electric field energy of the eigenmode m in space. The dielectric tensor, v, represents the dielectric tensor at different locations in space. full The volume of the space is represented by the above quantities, all of which are known quantities.

[0185] Step S5034: Based on the normalization relation, the following formula exists:

[0186]

[0187] Step S5035: Obtain the inductance value L of quantum device n n ,Right now:

[0188]

[0189] Step S5036: Obtain p mn This leads to the iEPR of quantum device n under different eigenmodes. Here, p mn This can be specifically expressed as:

[0190]

[0191] In this way, the iEPR of quantum device n in different eigenmodes can be obtained.

[0192] Step S504: Based on the iEPR of the quantum device in different intrinsic modes, obtain the target iEPR of the quantum device, for example, obtain the maximum iEPR of the quantum device.

[0193] For example, let p be the maximum iEPR of quantum device n. sn ,but:

[0194]

[0195] Understandably, according to iEPR theory, in a superconducting quantum chip containing multiple quantum devices, for quantum device n, the following relationship exists:

[0196] p nn >p mn

[0197] That is, the proportion of inductance energy of quantum device n in its own eigenmode n is greater than the proportion of inductance energy of quantum device n in eigenmode m. Therefore, the proportion of inductance energy of quantum device n in different eigenmodes m can be calculated, and then the eigenfrequency of quantum device n can be obtained based on the eigenmode corresponding to the maximum value of the inductance energy proportion. For example, the eigenfrequency of the eigenmode corresponding to the maximum value can be directly used as the eigenfrequency of quantum device n to complete the identification and matching between quantum device and eigenmode.

[0198] Step S505: Based on the maximum iEPR of the quantum device, obtain the eigenmode information of the quantum device, and then obtain the eigenfrequency of the qubit; based on the eigenfrequency of each quantum device, obtain the target mapping relationship.

[0199] Step S506: Output the target mapping relationship.

[0200] Based on this, the present disclosure provides a simple and efficient process for quantitatively matching quantum devices with intrinsic mode information and then automatically matching quantum devices with intrinsic frequencies.

[0201] Part Three: Application Scenarios

[0202] Based on the pattern recognition method described above, the solution disclosed herein can be applied to the following scenarios:

[0203] Scenario 1: Determining the mode affiliation of a quantum device in pre-simulation. Here, pre-simulation refers to performing a rough simulation of the quantum chip layout before the actual simulation task, obtaining pre-simulation results that can be used as input for the simulation task. This process requires establishing a mapping relationship between the quantum device and its eigenmode information, or between the quantum device and its eigenfrequency. This mapping is then combined with the simulation task to obtain the simulation parameters required for the simulation task, which serve as the input. In Scenario 1, the eigenmode information of the quantum device can be efficiently identified using the scheme disclosed herein, thus improving the processing efficiency of pre-simulation and laying the foundation for improving overall simulation efficiency.

[0204] Scenario 2: Simulating the eigenfrequency of quantum devices. In the simulation of quantum chip layouts, it is necessary to simulate the eigenfrequency of some quantum devices. Since the eigenfrequency of quantum devices with the same structure is very close, it is difficult to obtain the eigenfrequency of only one quantum device in a single simulation with current precision. Therefore, the simulation results will contain the eigenfrequency of multiple quantum devices. However, existing simulation software cannot directly obtain the correspondence between quantum devices and their eigenfrequency. In this case, the eigenfrequency of the quantum device can be automatically identified using the scheme disclosed in this paper. This process is fast and highly accurate.

[0205] Scenario 3: Simulating the quality factor of a quantum device. Since there is a one-to-one correspondence between the eigenfrequency and the quality factor, the eigenfrequency of the quantum device can be obtained using the scheme disclosed in this disclosure during the simulation of the quality factor. Then, based on the correspondence between the eigenfrequency and the quality factor, the quality factor of the quantum device can be obtained.

[0206] Scenario 4: Simulating the coupling strength between quantum devices. Coupling strength refers to the degree of interaction between two quantum devices. In the simulation of a quantum chip layout, it is necessary to calculate the coupling strength between two devices, which requires first determining the eigenfrequency of the quantum device. At this point, the scheme disclosed herein can be used to efficiently and accurately obtain the correspondence between quantum devices and their eigenfrequency, thus laying the foundation for efficiently obtaining the coupling strength between quantum devices.

[0207] Part Four: Application Demonstration

[0208] This section uses the quality factor of quantum devices in a simulated quantum chip layout as an example to illustrate the feasibility and correctness of the pattern recognition steps in this disclosure. Figure 6 The diagram shows the structural layout of the quantum chip to be simulated. The cross-shaped structure represents a qubit; there are four qubits in this layout: Q1, Q2, Q3, and Q4. The rectangular structure represents a coupler; there are three couplers in this layout: C12, C23, and C34. Coupler C12 connects qubits Q1 and Q2, coupler C23 connects qubits Q2 and Q3, and coupler C34 connects qubits Q3 and Q4. Long straight wires represent readout cavities, located on each qubit: readout cavity 1 for qubit Q1, readout cavity 2 for qubit Q2, readout cavity 3 for qubit Q3, and readout cavity 4 for qubit Q4.

[0209] Furthermore, the simulation task of this application is to determine the quality factor of the four readout cavities. Electromagnetic simulation of the quantum chip layout described in this application yielded the following results (i.e., Table 1):

[0210] Table 1

[0211] serial number Intrinsic frequency (GHz) quality factor Mode 1 5.114 8204.26 Mode 2 5.16 6596.43 Mode 3 5.254 5871.42 Mode 4 5.35 4926.85

[0212] The above provides the correspondence between intrinsic frequencies and quality factors; however, it does not determine which specific readout cavity the quality factor belongs to. Therefore, the scheme disclosed herein can be used to further distinguish the correspondence between intrinsic frequencies and readout cavities. Specifically, the following results (Table 2) are obtained after simulating the above quantum chip layout using the scheme disclosed herein:

[0213] Table 2

[0214] serial number iEPR of reading cavity 1 iEPR of reading cavity 2 iEPR of reading cavity 3 iEPR of reading cavity 4 Mode 1 9.99939643e-01 6.21061238e-05 1.10484040e-06 5.83105774e-08 Mode 2 5.93881792e-05 9.99862319e-01 7.44001811e-05 1.96632331e-06 Mode 3 9.30815019e-07 7.41663195e-05 9.99412240e-01 5.14037050e-04 Mode 4 3.81925321e-08 1.40870687e-06 5.12255318e-04 9.99483938e-01

[0215] Based on the iEPR in Table 2, the intrinsic frequency corresponding to the read cavity is obtained, and then the quality factor of the read cavity is obtained, i.e.:

[0216] Reading cavity 1 corresponds to Mode 1, its intrinsic mode is 5.114, and its quality factor is 8204.26 accordingly;

[0217] Reading cavity 2 corresponds to Mode 2, its intrinsic mode is 5.16, and its quality is 6596.43 accordingly;

[0218] Reading cavity 3 corresponds to Mode 3, its intrinsic mode is 5.254, and its quality factor is 5871.42 accordingly;

[0219] Reading cavity 4 corresponds to Mode 4, its intrinsic mode is 5.35, and its quality factor is 4926.85.

[0220] Thus, the application verifies the effectiveness of the disclosed solution.

[0221] In summary, the specific advantages of the present invention are listed below:

[0222] First, it significantly speeds up the process. Compared with manual pattern recognition methods, the proposed solution can quantitatively and automatically perform pattern recognition and quickly identify the intrinsic mode information of quantum devices. On the one hand, this facilitates subsequent simulation verification; on the other hand, it greatly reduces the time spent on manual operations during simulation, laying the foundation for improving the iterative efficiency of quantum chip layout.

[0223] Second, it has high accuracy. This disclosed solution can perform quantitative calculations to achieve pattern matching, and has a rigorous result judgment mechanism, resulting in higher accuracy.

[0224] Third, it is easy to operate. As the layout of a quantum chip increases, the information on quantum devices and intrinsic modes within the quantum chip layout also increases. Therefore, compared to existing manual pattern recognition methods, the proposed solution is convenient and quick to operate.

[0225] Fourth, it has a wide range of applications. This disclosed solution can be applied to pre-simulation, quality factor assignment, and simulation of coupling strength between quantum devices, etc., and has a very broad range of applications, which can comprehensively improve simulation efficiency in a variety of scenarios.

[0226] Part 5: Methods for Automating the Generation of Performance Analysis Results

[0227] The inputs for this section are: the quantum chip layout to be simulated, and the task information of the simulation task; the output is: the performance analysis results of the quantum chip layout.

[0228] like Figure 7 As shown, the core steps of this disclosed solution specifically include:

[0229] Step S701: Input the quantum chip layout containing N quantum devices to be simulated, as well as the task information of each simulation task in multiple simulation tasks.

[0230] In a specific example, you can input a quantum chip layout, the identification information of quantum devices in the quantum chip layout, and task information from multiple simulation tasks.

[0231] Here, the simulation task can be specifically defined as follows:

[0232] Simulation Task 1: Simulate the eigenmodes of each qubit in the quantum chip layout, that is, simulate the eigenfrequency of the qubit; the eigenmodes are electromagnetic properties of the qubit itself.

[0233] Accordingly, the task information for simulation task one can be specifically as follows: the intrinsic frequencies of each qubit in the quantum chip layout are obtained through simulation, and the identification information of the target quantum device to be simulated in simulation task one, such as the numbering information of each qubit.

[0234] Simulation Task 2: Simulate and obtain the dispersion ratio of the quantum system formed by "qubit-coupler-qubit". This dispersion ratio is used to measure whether dispersion coupling between qubits in the quantum system formed by the qubit-coupler is realized. This dispersion ratio is denoted as β and satisfies the following relationship:

[0235]

[0236] Here, g qc ω represents the coupling strength between the qubit and the coupler in the "qubit-coupler-qubit" model;c ω represents the eigenfrequency of the coupler. q This represents the eigenfrequency of the qubit. In a specific simulation, the dispersion ratio can be calculated by obtaining the coupling strength between the qubit and the coupler at the opening point (such as the critical point when the coupling strength between the qubit and the coupler is greater than a preset threshold), as well as the eigenfrequency of the qubit and the eigenfrequency of the coupler.

[0237] For example, for "qubit Q1-coupler-qubit Q2", the dispersion ratio of "qubit-coupler-qubit" can be specifically defined as follows:

[0238]

[0239] Here, g q1c This represents the coupling strength between qubit Q1 and the coupler. Furthermore, in a specific simulation process, the dispersion ratio can be calculated by simulating the coupling strength between qubit Q1 and the coupler at the opening point (e.g., the critical point where the coupling strength between qubit Q1 and the coupler is greater than a preset threshold), as well as the eigenfrequency of qubit Q1 and the eigenfrequency of the coupler.

[0240] It should be noted that in simulation task 4, the two qubits in the "qubit-coupler-qubit" are adjacent, and the two adjacent qubits are connected by a coupler.

[0241] Accordingly, the task information for simulation task two may specifically include: the dispersion ratio of the quantum system formed by the "qubit-coupler-qubit" obtained by simulation, and the identification information of the target quantum device to be simulated in simulation task two, such as the numbering information of each quantum device in the "qubit-coupler-qubit".

[0242] Simulation Task 3: Simulate the coupling strength of the "qubit-reading cavity (QR)" to ensure that the reading cavity can accurately read the quantum data information of the qubit. There is usually a certain coupling strength between two quantum devices. For the qubit-reading cavity, under the combined effect of other quantum devices on the qubit and the coupler in the qubit-reading cavity, the coupling strength between the qubit and the reading cavity (such as the equivalent coupling strength) determines the reading rate of the reading cavity and the fidelity of the qubit. Therefore, the coupling strength between the qubit and the reading cavity needs to be within a suitable range, which is the significance of simulating the coupling strength between the qubit and the reading cavity.

[0243] It should be noted that in simulation task three, "qubit-reading cavity (QR)" refers to the qubit and its corresponding reading cavity. Based on this, simulation task three refers to simulating the coupling strength between the qubit and its corresponding reading cavity.

[0244] It should be noted that the target quantum device to be simulated in this simulation task three is the quantum bit whose coupling strength is to be solved (which can be called the target quantum bit), as well as all the readout cavities in the quantum chip layout. In the actual scenario, the frequency of the readout cavities cannot be adjusted, so if you want to simulate the coupling strength between the quantum bit and the readout cavity, the simulation needs to include all the readout cavities in the quantum chip layout.

[0245] Accordingly, the simulation information for simulation task three may specifically include: the coupling strength of the “qubit-reading cavity (QR)” obtained from the simulation, and the identification information of the target quantum device to be simulated in simulation task three, such as the numbering information of the quantum device to be simulated, and the numbering information of each reading cavity in all reading cavities.

[0246] Simulation Task 4: Simulate the cut-off point between qubits in the "qubit-coupler-qubit" system, or the coupling strength between qubits in the "qubit-coupler-qubit" system. Here, for the "qubit-coupler-qubit" system, when the coupling strength (e.g., equivalent coupling strength) between two qubits is 0, the inductance or frequency value of the coupler at this time can be used as the cut-off point between qubits in the "qubit-coupler-qubit" system.

[0247] It should be noted that in simulation task four, the two qubits in the "qubit-coupler-qubit" are adjacent, and the two adjacent qubits are connected by a coupler.

[0248] Accordingly, the simulation information for simulation task four may specifically include: the shutdown point between qubits in the "qubit-coupler-qubit" obtained by simulation, and the identification information of the target quantum device to be simulated in simulation task four, such as the numbering information of each target qubit in two adjacent target qubits to be simulated, and the numbering information of the target coupler connecting the two target qubits.

[0249] Step S702: For the current simulation task, under the first simulation accuracy, perform a pre-simulation of the quantum chip layout to be simulated based on the task information of the current simulation task to obtain the simulation parameters required for the current simulation task.

[0250] It should be noted that before proceeding with the specific steps of automated performance analysis, a pre-simulation is required, which involves performing a rough simulation of the quantum chip layout. This allows for the automated acquisition of simulation parameters required for subsequent simulation tasks by analyzing the intrinsic mode information of the quantum device and the task information of the simulation task to be performed.

[0251] In a specific example, the simulation parameters required for the simulation task include the target simulation start frequency and the number of target frequencies. Here, the target minimum eigenfrequency is the minimum value among the eigenfrequencys of each of the at least two target quantum devices to be simulated in the simulation task. The number of target frequencies is used to determine a plurality of target simulation frequencies starting from the target simulation start frequency, and the plurality of target simulation frequencies include the eigenfrequencys of the target quantum devices to be simulated in the simulation task.

[0252] Here, the first simulation accuracy is an empirical value, such as within the range of 1%-5%. It is understood that in practical applications, the first simulation accuracy should not be too high, as this will result in excessively long simulation time. Moreover, in the pre-simulation process, a very high simulation accuracy is not required. At the same time, the first simulation accuracy should not be too low either, as this may result in incorrect pre-simulation results or pre-simulation results that are too far from the actual results.

[0253] Furthermore, the pre-simulation method can be specifically a pre-simulation method based on iEPR (i.e., pattern recognition steps based on quantum devices), or it can be other pre-simulation methods, as long as the pre-simulation results that meet the requirements of the first simulation accuracy can be obtained. This disclosure does not limit this.

[0254] For example, the pre-simulation process is illustrated using a pattern recognition step (i.e., iEPR) pre-simulation method. In one example, initialization is performed first, for instance, by setting the initial simulation start frequency to a preset minimum value, i.e., the preset lowest frequency, and the number of initial frequencies for pre-simulation to a preset number, such as a preset maximum value (e.g., 20). After initialization, finite element electromagnetic simulation is performed using the pattern recognition step described above at a preset first simulation accuracy to obtain multiple intrinsic mode information, thereby obtaining the target mapping relationship.

[0255] Furthermore, based on the target mapping relationship and the task information of the current simulation task, the simulation parameters of the simulation task are obtained. For example, based on the correspondence between quantum devices and intrinsic frequencies, the frequency distribution of the intrinsic frequencies of the target quantum devices to be simulated in the simulation task is determined. Then, based on the frequency distribution, the target simulation start frequency required by the simulation task and the number of target frequencies to be simulated in the simulation task can be determined.

[0256] It is understandable that, since different simulation tasks target different quantum devices, the frequency distribution of the intrinsic frequencies corresponding to different simulation tasks will also be different, and consequently the simulation parameters of different simulation tasks will also be different. This disclosure does not impose any restrictions on this.

[0257] Step S703: For the current simulation task, under the target simulation accuracy, based on the task information of the current simulation task and the simulation parameters obtained in step S702, the quantum chip layout is simulated to obtain the simulation results.

[0258] Step S703-1: Based on the task information of the current simulation task, obtain the identification information of the target quantum device to be simulated in the current simulation task, adjust the inductance value of the target quantum device to be simulated (equivalent to changing the frequency of the target quantum device), and adjust the inductance value of the quantum devices other than the target quantum device (hereinafter referred to as non-target quantum devices) in the quantum chip layout.

[0259] Specifically, based on the task information of the current simulation task, the target quantum device to be simulated can be obtained; the inductance values ​​of all target quantum devices are adjusted to preset inductance values ​​(for example, the preset inductance value is the design value of the target quantum device), and the inductance values ​​of non-target quantum devices in the quantum chip layout are increased or decreased. In this way, in subsequent simulations, the intrinsic mode information of the target quantum device basically does not contain the intrinsic mode information of non-target quantum devices in the quantum chip layout, further improving the simulation efficiency.

[0260] Step S703-2: Input the simulation parameters of the current simulation task, the simulation information of the current simulation task, and the quantum chip layout into the electromagnetic simulation software to obtain the simulation results.

[0261] Step S703-2-1: Under the pre-set target simulation accuracy, the pattern recognition steps described above are used to obtain the intrinsic frequency of the target quantum device under the target simulation accuracy.

[0262] It should be noted that the target simulation accuracy is an empirical value greater than the first simulation accuracy, for example, within the range of 0.1%-0.3%. In other words, the accuracy of the intrinsic frequency of the target quantum device obtained in this step S703-2-1 is higher than the intrinsic frequency of the quantum device obtained from the above pre-simulation.

[0263] It should be noted that, in one example, step S703-2-1 can also utilize the pattern recognition step described above to obtain the intrinsic frequencies of each quantum device in the quantum chip layout under the target simulation accuracy.

[0264] Step S703-2-2: Based on the eigenfrequency of the target quantum device under the target simulation accuracy, obtain the simulation results of the current simulation task under the target simulation accuracy.

[0265] Step S703-3: Based on the post-processing method of the current simulation task, further process the obtained simulation results to obtain the performance analysis results of the quantum chip layout under the current simulation task.

[0266] It should be noted that the performance analysis results include task information of the simulation task, performance parameters (such as eigenfrequency) of the target quantum device to be simulated, or the eigenfrequency of each quantum device in the quantum chip layout. Furthermore, the post-processing method may include preset functions for further processing of the obtained simulation results; in this case, the performance analysis results may also include the preset functions used. This disclosure does not limit the specific content of the performance analysis results or the format in which that content is presented.

[0267] Step S704: Determine if there are any unfinished simulation tasks. If so, return to step S703 to continue with the next simulation task; otherwise, proceed to step S705.

[0268] It should be noted that multiple simulation tasks can be completed independently and in parallel. For example, multiple electromagnetic simulation software programs can be used to process multiple simulation tasks in parallel to further improve efficiency.

[0269] Step S705: Output the performance analysis results of each simulation task in multiple simulation tasks.

[0270] Here, the performance analysis results may include...

[0271] The following explains the specific adjustment methods for the inductance value of the quantum device in step S703-1, tailored to different simulation tasks:

[0272] Simulation Task 1, namely, simulating the eigenfrequency of each qubit.

[0273] The target quantum device to be simulated in this simulation task is all the qubits in the quantum chip layout. If all the qubits in the quantum chip layout have the same inductance value, their eigenfrequency will be very similar. Therefore, to save simulation time, the inductance value of all qubits can be adjusted to a preset inductance value. For example, the qubits in the quantum chip layout can be iterated through, and the inductance value of each qubit can be set to the preset inductance value through the simulation software's control interface; then, the simulation process can be performed to obtain the simulation results at the target simulation accuracy.

[0274] Simulation Task 2, namely, simulating the dispersion ratio in the quantum system formed by "qubit-coupler-qubit".

[0275] The target quantum device to be simulated in the second simulation task is two adjacent qubits (which can be called target qubits) and a coupler used to connect the two adjacent qubits (which can be called target couplers).

[0276] Here, to obtain more accurate simulation results and save simulation time, it is also necessary to adjust the inductance values ​​of other non-target qubits and non-target couplers so that their eigenfrequencys are far from the eigenfrequencys of the target quantum devices (i.e., the target qubit and the target coupler). For example, the numbering information of all quantum devices is traversed; when the target qubit is encountered, its inductance value is adjusted to a preset inductance value, or when the target coupler is encountered, its inductance value is adjusted to the inductance value at the open point; conversely, when a non-target qubit is encountered, its inductance value is adjusted to any value greater than the preset inductance value, such as 100nH, or when a non-target coupler is encountered, its inductance value is adjusted to the inductance value at the close point; then, simulation processing is performed to obtain simulation results at the target simulation accuracy.

[0277] Simulation Task 3, namely, simulating the coupling strength between the "qubit-read cavity".

[0278] The target quantum device to be simulated in the third simulation task is the quantum bit whose coupling strength needs to be solved (which can be called the target quantum bit), as well as all the readout cavities in the quantum chip layout.

[0279] Here, to ensure simulation speed, a similar approach to simulation task two is needed to adjust the inductance values ​​of the target quantum device and the non-target quantum device before performing simulation processing to obtain simulation results at the target simulation accuracy.

[0280] Simulation Task 4: Simulate the cutoff point between qubits in the "qubit-coupler-qubit" system, that is, simulate the cutoff point between two adjacent qubits.

[0281] The target quantum device to be simulated in simulation task four is the qubit whose turn-off point needs to be determined (i.e., the target qubit) and the coupler used to connect the target qubit (i.e., the target coupler). Here, a similar approach to simulation task two can be adopted, adjusting the inductance values ​​of the target qubit and the target coupler, and sampling the inductance values ​​of non-target qubits and non-target couplers, and then performing simulation processing to obtain simulation results at the target simulation accuracy.

[0282] In practical applications, an iterative approach can be used to obtain the inductance values ​​of multiple target couplers and the coupling strength between two adjacent qubits. This leads to the relationship between the inductance values ​​of the target couplers and the coupling strength between two adjacent qubits, resulting in a qubit coupling performance curve. Based on this curve, the turn-off point between two adjacent qubits can then be determined.

[0283] Part Six: Application Demonstration

[0284] by Figure 8 The effectiveness of the disclosed scheme is illustrated using the quantum chip layout of the qubit-coupler-qubit shown as an example.

[0285] (I) Quantum Chip Layout

[0286] like Figure 8 The quantum chip layout shown includes:

[0287] Two qubits, namely qubit Q1 (the leftmost cross-shaped structure) and qubit Q2 (the rightmost cross-shaped structure);

[0288] A coupler C (the cross-shaped structure in the middle) is used to connect qubit Q1 and qubit Q2;

[0289] There are two readout cavities: readout cavity 1, corresponding to qubit Q1, and readout cavity 2, corresponding to qubit Q2.

[0290] Three Josephson junction inductors, for example, represented by a small square structure below a cross-shaped structure; and,

[0291] One read line.

[0292] It should be noted that the quantum chip layout described above is only an illustrative example. In practical applications, the quantum chip layout can take other specific structures, and this disclosure does not limit this. For example, for the four simulation tasks mentioned above, this disclosure is suitable for the automated simulation of all quantum chip layouts containing couplers.

[0293] (II) Verification Process

[0294] The first step is to input the layout of the quantum chip to be simulated, as well as the task information for each simulation task.

[0295] The simulation task to be performed in this example can be specifically as follows:

[0296] Simulation Task 1: Simulate and obtain the eigenfrequency of qubit Q1 in the quantum chip layout;

[0297] Simulation Task 2: Simulate and obtain the dispersion ratio of the quantum system formed by "Q1-C-Q2";

[0298] Simulation Task 3: Simulate and obtain the coupling strength between qubit Q1 and readout cavity 1;

[0299] Simulation Task 4: Simulate and obtain the cutoff point between qubit Q1 and qubit Q2 in “Q1-C-Q2”.

[0300] The second step is to perform a pre-simulation of the quantum chip layout at the first simulation accuracy based on the task information of the current simulation task, and obtain the simulation parameters of the current simulation task. For example, the simulation parameters of each simulation task are shown in Table 3.

[0301] Table 3

[0302] Simulation Task Name Target simulation start frequency Number of target frequencies Simulation Task 1 6.5GHz 1 Simulation Task 2 6.5GHz 6 Simulation Task 3 4GHz 3 Simulation Task 4 6.5GHz 2

[0303] The third step involves adjusting the inductance value of the quantum device based on the methods described above, and running a simulation to obtain the performance analysis results of the quantum chip layout.

[0304] Specifically, for simulation task one, the target quantum device to be simulated in simulation task one is quantum bit Q1. At this time, the inductance value of quantum bit Q1 in the quantum chip layout is set to 8.1nH, and the inductance value of other quantum bits is set to 6nH. Then, based on the simulation parameters in Table 3, the simulation is performed using the scheme disclosed in this paper to obtain the eigenfrequency of quantum bit Q1 and generate the performance analysis results shown in Figure 9(a).

[0305] For simulation task two, the target quantum devices to be simulated are qubits Q1 and Q2, and coupler C. The inductance values ​​of qubits Q1 and Q2 are adjusted to 8.1 nH; the inductance value of coupler C is adjusted to the inductance value at the open point, such as 6.5 nH; and the inductance values ​​of the other qubits are adjusted to 100 nH, and the inductance values ​​of the other couplers are adjusted to the inductance values ​​at the close point, such as 2.3 nH. Based on the simulation parameters in Table 3 and using the scheme disclosed herein, the coupling strength between any two target quantum devices and the eigenfrequency of each target quantum device are obtained. The dispersion ratio of the quantum system formed by Q1-C-Q2 is then obtained, and the performance analysis results shown in Figure 9(b) are generated.

[0306] For simulation task three, the target quantum device to be simulated is qubit Q1, and all readout cavities in the quantum chip layout. This example can use a similar approach to simulation task one to adjust the inductance value; then, based on the simulation parameters in Table 3 and using the scheme disclosed herein, the intrinsic frequency of readout cavity 1, the coupling strength between qubit Q1 and readout cavity 1, and the performance analysis results shown in Figure 9(c) are obtained.

[0307] For simulation task four, the target quantum devices to be simulated are qubits Q1 and Q2, and coupler C. The inductance value can be adjusted in a similar manner to simulation task two; then, based on the simulation parameters in Table 3, simulations are performed using the scheme disclosed herein, and the performance analysis results shown in Figure 9(d) are generated.

[0308] In summary, the overall performance analysis results of the four simulation tasks can be obtained, as shown in Figure 9(e). For example, the overall results include: a first part containing basic information, such as the simulation start time, the number of qubits in the quantum chip layout, and the number of couplers; a second part showing the simulation results of simulation task one; a third part showing the results of simulation task two; a fourth part showing the results of simulation task three; and a fifth part showing the results of simulation task four. In this way, an overall performance analysis result containing simulation results from multiple simulation tasks is automatically generated.

[0309] In summary, the disclosed solution has the following advantages:

[0310] First, it significantly speeds up the process. This disclosed solution can quickly obtain performance analysis results for quantum chip layouts, laying the foundation for improving the iterative efficiency of quantum chip layouts.

[0311] Second, it boasts a high degree of automation. From inputting the layout and basic information to outputting performance analysis results, no human intervention is required, thus greatly enhancing the automation level of simulation verification.

[0312] Third, it is easy to operate. Researchers do not need to manually set relevant parameters, which greatly reduces the complexity of operation when the workload of simulation tasks increases. Moreover, it is not only researchers who can use this invention for simulation verification; even personnel lacking simulation knowledge can quickly perform simulation tasks. Therefore, the usage threshold of this disclosed solution is low, facilitating its engineering application.

[0313] Fourth, it improves the utilization rate of the electromagnetic simulation workstation. Manual simulation methods require a lot of human intervention, resulting in gaps between electromagnetic simulation tasks and potentially wasting time due to a lack of task input. In contrast, the automatic simulation program of this disclosed solution can work continuously with almost no gap between two simulation tasks, thereby greatly improving the time utilization rate of the electromagnetic simulation workstation.

[0314] This disclosure also provides a simulation device for quantum chip layout, such as... Figure 10 As shown, it includes:

[0315] Simulation unit 1001 is used to execute a pattern recognition step for a quantum device; wherein the pattern recognition step includes: performing a first simulation process on a quantum chip layout to obtain multiple intrinsic mode information; based on the multiple intrinsic mode information, obtaining the inductance energy ratio of the quantum device in different intrinsic modes; wherein, the intrinsic mode information in the multiple intrinsic mode information corresponds to an intrinsic mode; the quantum device is one of multiple quantum devices included in the quantum chip layout; based on the inductance energy ratio of the quantum device in different intrinsic modes, identifying the intrinsic mode information of the quantum device from the multiple intrinsic mode information;

[0316] Output unit 1002 is used to output the intrinsic mode information of quantum devices.

[0317] In a specific example of the scheme disclosed herein, the simulation unit is further configured to:

[0318] Based on the eigenmode information of the quantum device, the first eigenfrequency of the quantum device is obtained.

[0319] In a specific example of the scheme disclosed herein, the simulation unit is further configured to:

[0320] Based on the intrinsic frequencies of each quantum device, the target mapping relationship corresponding to the quantum chip layout is obtained, wherein the target mapping relationship characterizes the correspondence between quantum devices and intrinsic frequencies in the quantum chip layout.

[0321] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0322] The target inductance energy percentage of the quantum device is determined from the inductance energy percentage of the quantum device in different intrinsic modes;

[0323] Based on the multiple intrinsic mode information, the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device is determined;

[0324] The intrinsic mode information of the quantum device is obtained based on the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device.

[0325] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0326] The maximum proportion is selected from the proportions of inductance energy corresponding to different intrinsic modes of the quantum device, wherein the target inductance energy proportion is the maximum proportion.

[0327] In a specific example of the scheme disclosed herein, the simulation unit is specifically used to obtain the inductance energy percentage p of quantum device n in intrinsic mode m among the plurality of quantum devices in the following manner. mn :

[0328] Based on information from multiple intrinsic modes, the inductance energy of intrinsic mode m stored in quantum device n is obtained. And obtain the total inductance energy stored in the intrinsic mode m. Wherein, the intrinsic mode information corresponding to intrinsic mode m is one of the plurality of intrinsic mode information;

[0329] The inductor energy stored in quantum device n based on the intrinsic mode m and the total inductance energy stored in the intrinsic mode m The inductance energy percentage p of quantum device n in intrinsic mode m is obtained. mn .

[0330] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0331] Based on information from multiple intrinsic modes, the inductance value L of quantum device n is calculated. n And the voltage V of the intrinsic mode m along the voltage integral line of the quantum device n in space is calculated. mn ;

[0332] Based on the inductance value L of quantum device n n The intrinsic mode m represents the voltage V along the voltage integral line of the quantum device n in space. mn and the intrinsic frequency ω' corresponding to the intrinsic mode m m The inductance energy of the intrinsic mode m stored in the quantum device n is obtained.

[0333] Among them, the eigenmode information corresponding to eigenmode m includes the eigenfrequency ω' corresponding to eigenmode m. m .

[0334] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0335] The correlation between the inductance energy ratio of quantum device n in different intrinsic modes was obtained;

[0336] Based on the correlation between the inductance energy ratio of quantum device n in different eigenmodes, the inductance value L of quantum device n is obtained. n .

[0337] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0338] Based on the electric field intensity distribution information of intrinsic mode m in space, the voltage V of quantum device n along the voltage integral line in space is calculated. mn ;

[0339] Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space.

[0340] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0341] Based on the electric field intensity distribution information of eigenmode m in space, the average electric field energy stored in space by eigenmode m is obtained. Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space;

[0342] The average electric field energy stored in space for the eigenmode m The total inductance energy stored in the intrinsic mode m

[0343] In a specific example of the scheme disclosed herein, the simulation unit is further configured to:

[0344] Based on the eigenmode information of quantum devices, the coupling strength between quantum devices in the quantum chip layout can be obtained; or,

[0345] Based on the intrinsic mode information of quantum devices and the preset mapping relationship between intrinsic mode information and quality factor, the quality factor corresponding to the quantum device in the quantum chip layout is obtained.

[0346] In a specific example of the scheme disclosed herein, the simulation unit is further configured to:

[0347] A pre-simulation process is performed on the quantum chip layout to obtain pre-simulation results; based on the pre-simulation results and the task information of the quantum task, a second simulation process is performed on the quantum chip layout to obtain simulation results; a target report for the simulation task is generated based on the simulation results.

[0348] The pre-simulation processing steps include a pattern recognition step for the quantum device, and the pre-simulation result is obtained based on the identified intrinsic mode information of the quantum device; and / or, the second simulation processing steps include a pattern recognition step for the quantum device, and the simulation result is obtained based on the identified intrinsic mode information of the quantum device.

[0349] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0350] At the first simulation accuracy, a pattern recognition step is performed on the quantum device to obtain the intrinsic mode information of the quantum device at the first simulation accuracy.

[0351] Based on the intrinsic mode information of the quantum device at the first simulation accuracy, the pre-simulation results are obtained.

[0352] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0353] Based on the pre-simulation results and the task information of the quantum task, a pattern recognition step is performed on the quantum device under the target simulation accuracy to obtain the intrinsic mode information of the quantum device under the target simulation accuracy.

[0354] Based on the intrinsic mode information of the quantum device at the target simulation accuracy, the simulation results at the target simulation accuracy are obtained.

[0355] In a specific example of the scheme disclosed herein, the quantum chip layout is a chip layout of a superconducting quantum chip.

[0356] For a description of the specific functions and examples of each unit of the apparatus in this disclosure embodiment, please refer to the relevant descriptions of the corresponding steps in the above method embodiments, which will not be repeated here.

[0357] This disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above using a quantum computing device.

[0358] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described above for use in classical computing devices.

[0359] Alternatively, the computer program, when executed by at least one quantum processing unit, implements the method applied to a quantum computing device.

[0360] This disclosure also provides a quantum computing device, the quantum computing device comprising:

[0361] At least one quantum processing unit;

[0362] A memory, coupled to the at least one QPU and used to store executable instructions,

[0363] The instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method applied to the quantum computing device.

[0364] It is understood that the quantum processing unit (QPU) used in the present disclosure may also be referred to as a quantum processor or quantum chip, and may involve a physical chip comprising multiple qubits interconnected in a specific manner.

[0365] Furthermore, it is understood that the qubit described in this disclosure can refer to the basic information unit of a quantum computing device. The qubit is contained within the QPU and extends the concept of the classical digital bit.

[0366] According to embodiments of this disclosure, this disclosure also provides a computing device, a readable storage medium, and a computer program product.

[0367] Figure 11 A schematic block diagram of an example computing device 1100 that can be used to implement embodiments of the present disclosure is shown. The computing device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The computing device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0368] like Figure 11 As shown, device 1100 includes a computing unit 1101, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1102 or a computer program loaded from storage unit 1108 into random access memory (RAM) 1103. The RAM 1103 may also store various programs and data required for the operation of device 1100. The computing unit 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0369] Multiple components in device 1100 are connected to I / O interface 1105, including: input unit 1106, such as keyboard, mouse, etc.; output unit 1107, such as various types of monitors, speakers, etc.; storage unit 1108, such as disk, optical disk, etc.; and communication unit 1109, such as network card, modem, wireless transceiver, etc. Communication unit 1109 allows device 1100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0370] The computing unit 1101 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1101 performs the various methods and processes described above, such as the quantum chip layout simulation method. For example, in some embodiments, the quantum chip layout simulation method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1108. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1100 via ROM 1102 and / or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by the computing unit 1101, one or more steps of the quantum chip layout simulation method described above can be performed. Alternatively, in other embodiments, computing unit 1101 may be configured to perform a simulation method of quantum chip layout by any other suitable means (e.g., by means of firmware).

[0371] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0372] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0373] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0374] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0375] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0376] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0377] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0378] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A simulation method for quantum chip layout, comprising: Pattern recognition steps for quantum devices: wherein the pattern recognition steps include: The quantum chip layout was subjected to a first simulation process to obtain information on multiple intrinsic modes. Based on the multiple intrinsic mode information, the inductance energy ratio of the quantum device under different intrinsic modes is obtained; wherein, the intrinsic mode information in the multiple intrinsic mode information corresponds to an intrinsic mode; the quantum device is one of the multiple quantum devices included in the quantum chip layout; Based on the proportion of inductor energy in different intrinsic modes of the quantum device, the intrinsic mode information of the quantum device is identified from the multiple intrinsic mode information. The process of identifying the intrinsic mode information of a quantum device from the multiple intrinsic mode information based on the proportion of inductor energy in different intrinsic modes includes: The target inductance energy percentage of the quantum device is determined from the inductance energy percentage of the quantum device in different intrinsic modes; Based on the multiple intrinsic mode information, the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device is determined; The intrinsic mode information of the quantum device is obtained based on the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device.

2. The method according to claim 1, wherein, The pattern recognition step of the quantum device further includes: The intrinsic frequencies of quantum devices are obtained based on the intrinsic mode information of the quantum devices.

3. The method according to claim 2, wherein, The pattern recognition step of the quantum device further includes: Based on the intrinsic frequencies of each quantum device, the target mapping relationship corresponding to the quantum chip layout is obtained, wherein the target mapping relationship characterizes the correspondence between quantum devices and intrinsic frequencies in the quantum chip layout.

4. The method according to claim 1, wherein, Determining the target inductance energy percentage of the quantum device from the inductance energy percentages in different intrinsic modes includes: The maximum proportion is selected from the proportions of inductance energy corresponding to different intrinsic modes of the quantum device, wherein the target inductance energy proportion is the maximum proportion.

5. The method according to any one of claims 1-4, wherein, The process of obtaining the inductance energy percentage of the quantum device under different intrinsic modes based on the multiple intrinsic mode information includes: The inductance energy percentage of quantum device n in intrinsic mode m among the multiple quantum devices is obtained as follows: : Based on information from multiple intrinsic modes, the inductance energy of intrinsic mode m stored in quantum device n is obtained. And obtain the total inductance energy stored in the intrinsic mode m. Wherein, the intrinsic mode information corresponding to intrinsic mode m is one of the plurality of intrinsic mode information; The inductor energy stored in quantum device n based on the intrinsic mode m And the total inductance energy stored in the intrinsic mode m The inductance energy ratio of quantum device n in intrinsic mode m was obtained. .

6. The method according to claim 5, wherein, The inductance energy of intrinsic mode m stored in quantum device n is obtained based on information from multiple intrinsic modes. ,include: Based on information from multiple intrinsic modes, the inductance value of quantum device n is calculated. And the voltage of the intrinsic mode m along the voltage integral line of the quantum device n in space is calculated. ; Inductance value based on quantum device n The voltage of intrinsic mode m along the voltage integral line of quantum device n in space. and the intrinsic frequencies corresponding to the intrinsic mode m The inductance energy of the intrinsic mode m stored in the quantum device n is obtained. ; Among them, the eigenmode information corresponding to eigenmode m includes the eigenfrequency corresponding to eigenmode m. .

7. The method according to claim 6, wherein, The inductance value of quantum device n is calculated based on multiple intrinsic mode information. ,include: The correlation between the inductance energy ratio of quantum device n in different intrinsic modes was obtained; Based on the correlation between the inductance energy ratio of quantum device n in different eigenmodes, the inductance value of quantum device n is obtained. .

8. The method according to claim 6, wherein, Based on information from multiple intrinsic modes, the voltage of intrinsic mode m along the voltage integral line of quantum device n in space is calculated. ,include: Based on the electric field intensity distribution information of intrinsic mode m in space, the voltage of quantum device n along the voltage integration line in space is calculated. ; Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space.

9. The method according to claim 5, wherein, The total inductance energy stored in the intrinsic mode m is obtained. ,include: Based on the electric field intensity distribution information of eigenmode m in space, the average electric field energy stored in space by eigenmode m is obtained. Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space; The average electric field energy stored in space for the eigenmode m The total inductance energy stored in the intrinsic mode m .

10. The method according to any one of claims 1-4, wherein, The simulation method further includes: Based on the eigenmode information of quantum devices, the coupling strength between quantum devices in the quantum chip layout can be obtained; or, Based on the intrinsic mode information of quantum devices and the preset mapping relationship between intrinsic mode information and quality factor, the quality factor corresponding to the quantum device in the quantum chip layout is obtained.

11. The method according to claim 3 or 4, wherein, The simulation method further includes: The quantum chip layout is pre-simulated to obtain pre-simulation results; Based on the pre-simulation results and the task information of the simulation task, the quantum chip layout is subjected to a second simulation process to obtain the simulation results. Generate a target report for the simulation task based on the simulation results; The pre-simulation processing steps include a pattern recognition step for the quantum device, and the pre-simulation result is obtained based on the identified intrinsic mode information of the quantum device; and / or, the second simulation processing steps include a pattern recognition step for the quantum device, and the simulation result is obtained based on the identified intrinsic mode information of the quantum device.

12. The method according to claim 11, wherein, The pre-simulation processing of the quantum chip layout to obtain pre-simulation results includes: At the first simulation accuracy, a pattern recognition step is performed on the quantum device to obtain the intrinsic mode information of the quantum device at the first simulation accuracy. Based on the task information of the simulation task and the intrinsic mode information of the quantum device under the first simulation accuracy, the pre-simulation results are obtained; wherein, the pre-simulation results include the simulation parameters required by the simulation task.

13. The method according to claim 11, wherein, Based on the pre-simulation results and the task information of the quantum task, a second simulation process is performed on the quantum chip layout to obtain simulation results, including: Based on the pre-simulation results and the task information of the quantum task, a pattern recognition step is performed on the quantum device under the target simulation accuracy to obtain the intrinsic mode information of the quantum device under the target simulation accuracy. Based on the intrinsic mode information of the quantum device at the target simulation accuracy, the simulation results at the target simulation accuracy are obtained.

14. The method according to any one of claims 1-4, wherein, The quantum chip layout is a chip layout of a superconducting quantum chip.

15. A simulation device for quantum chip layout, comprising: A simulation unit is used to execute a pattern recognition step for a quantum device. The pattern recognition step includes: performing a first simulation process on a quantum chip layout to obtain multiple intrinsic mode information; obtaining the inductance energy percentage of the quantum device under different intrinsic modes based on the multiple intrinsic mode information; wherein each intrinsic mode information corresponds to an intrinsic mode; the quantum device is one of multiple quantum devices included in the quantum chip layout; and identifying the intrinsic mode information of the quantum device from the multiple intrinsic mode information based on the inductance energy percentage of the quantum device under different intrinsic modes. Output unit, used to output the intrinsic mode information of quantum devices; Specifically, the simulation unit is used for: The target inductance energy percentage of the quantum device is determined from the inductance energy percentage of the quantum device in different intrinsic modes; Based on the multiple intrinsic mode information, the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device is determined; The intrinsic mode information of the quantum device is obtained based on the intrinsic mode information corresponding to the target inductance energy ratio of the quantum device.

16. The apparatus according to claim 15, wherein, The simulation unit is also used for: Based on the eigenmode information of the quantum device, the first eigenfrequency of the quantum device is obtained.

17. The apparatus according to claim 16, wherein, The simulation unit is also used for: Based on the intrinsic frequencies of each quantum device, the target mapping relationship corresponding to the quantum chip layout is obtained, wherein the target mapping relationship characterizes the correspondence between quantum devices and intrinsic frequencies in the quantum chip layout.

18. The apparatus according to claim 15, wherein, The simulation unit is specifically used for: The maximum proportion is selected from the proportions of inductance energy corresponding to different intrinsic modes of the quantum device, wherein the target inductance energy proportion is the maximum proportion.

19. The apparatus according to any one of claims 15-18, wherein, The simulation unit is specifically used to obtain the inductance energy percentage of quantum device n in intrinsic mode m among the plurality of quantum devices in the following manner. : Based on information from multiple intrinsic modes, the inductance energy of intrinsic mode m stored in quantum device n is obtained. And obtain the total inductance energy stored in the intrinsic mode m. Wherein, the intrinsic mode information corresponding to intrinsic mode m is one of the plurality of intrinsic mode information; The inductor energy stored in quantum device n based on the intrinsic mode m And the total inductance energy stored in the intrinsic mode m The inductance energy ratio of quantum device n in intrinsic mode m was obtained. .

20. The apparatus according to claim 19, wherein, The simulation unit is specifically used for: Based on information from multiple intrinsic modes, the inductance value of quantum device n is calculated. And the voltage of the intrinsic mode m along the voltage integral line of the quantum device n in space is calculated. ; Inductance value based on quantum device n The voltage of intrinsic mode m along the voltage integral line of quantum device n in space. and the intrinsic frequencies corresponding to the intrinsic mode m The inductance energy of the intrinsic mode m stored in the quantum device n is obtained. ; Among them, the eigenmode information corresponding to eigenmode m includes the eigenfrequency corresponding to eigenmode m. .

21. The apparatus according to claim 20, wherein, The simulation unit is specifically used for: The correlation between the inductance energy ratio of quantum device n in different intrinsic modes was obtained; Based on the correlation between the inductance energy ratio of quantum device n in different eigenmodes, the inductance value of quantum device n is obtained. .

22. The apparatus according to claim 20, wherein, The simulation unit is specifically used for: Based on the electric field intensity distribution information of intrinsic mode m in space, the voltage of quantum device n along the voltage integration line in space is calculated. ; Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space.

23. The apparatus according to claim 19, wherein, The simulation unit is specifically used for: Based on the electric field intensity distribution information of eigenmode m in space, the average electric field energy stored in space by eigenmode m is obtained. Among them, the intrinsic mode information corresponding to intrinsic mode m includes the electric field intensity distribution information of intrinsic mode m in space; The average electric field energy stored in space for the eigenmode m The total inductance energy stored in the intrinsic mode m .

24. The apparatus according to any one of claims 15-18, wherein, The simulation unit is also used for: Based on the eigenmode information of quantum devices, the coupling strength between quantum devices in the quantum chip layout can be obtained; or, Based on the intrinsic mode information of quantum devices and the preset mapping relationship between intrinsic mode information and quality factor, the quality factor corresponding to the quantum device in the quantum chip layout is obtained.

25. The apparatus according to claim 17 or 18, wherein, The simulation unit is also used for: The quantum chip layout is pre-simulated to obtain pre-simulation results; Based on the pre-simulation results and the task information of the simulation task, the quantum chip layout is subjected to a second simulation process to obtain the simulation results. Generate a target report for the simulation task based on the simulation results; The pre-simulation processing steps include a pattern recognition step for the quantum device, and the pre-simulation result is obtained based on the identified intrinsic mode information of the quantum device; and / or, the second simulation processing steps include a pattern recognition step for the quantum device, and the simulation result is obtained based on the identified intrinsic mode information of the quantum device.

26. The apparatus according to claim 25, wherein, The simulation unit is specifically used for: At the first simulation accuracy, a pattern recognition step is performed on the quantum device to obtain the intrinsic mode information of the quantum device at the first simulation accuracy. Based on the intrinsic mode information of the quantum device at the first simulation accuracy, the pre-simulation results are obtained.

27. The apparatus according to claim 25, wherein, The simulation unit is specifically used for: Based on the pre-simulation results and the task information of the quantum task, a pattern recognition step is performed on the quantum device under the target simulation accuracy to obtain the intrinsic mode information of the quantum device under the target simulation accuracy. Based on the intrinsic mode information of the quantum device at the target simulation accuracy, the simulation results at the target simulation accuracy are obtained.

28. The apparatus according to any one of claims 15-18, wherein, The quantum chip layout is a chip layout of a superconducting quantum chip.

29. A computing device, comprising: At least one quantum processing unit (QPU); A memory, coupled to the at least one QPU and used to store executable instructions, The instruction is executed by the at least one QPU to enable the at least one QPU to perform the method of any one of claims 1-14; Or, including: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method of any one of claims 1-14.

30. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, When at least one quantum processing unit is executed, the computer instructions cause the at least one quantum processing unit to perform the method according to any one of claims 1-14; Alternatively, the computer instructions are used to cause the computer to perform the method according to any one of claims 1-14.

31. A computer program product comprising a computer program that, when executed by at least one quantum processing unit, implements the method according to any one of claims 1-14; Alternatively, the computer program, when executed by a processor, implements the method according to any one of claims 1-14.

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