Method for routing very large scale integrated circuits based on integer linear programming

Abstract

The application discloses a super large scale integrated circuit wiring method based on integer linear programming, comprising the following steps: initializing basic data according to obstacle information in a wiring area, to-be-wired net information, design rule information and wiring track information; generating a line net queue according to the basic data, and searching for a candidate path of each to-be-wired net in the line net queue by using an A* search algorithm; checking violation conditions between different candidate paths based on the design rule information, and saving first violation information; constructing a value function and a constraint condition according to the first violation information, and solving an optimal path; and outputting a wiring result based on the optimal path. The application solves the problems that a traditional wiring scheme is not easy to wire and cannot maximize the use of intermediate results. Moreover, the checking mode of the design rule is optimized, a plurality of to-be-wired nets and a plurality of candidate paths can be checked at the same time, and a new idea is provided for the checking mode of the design rule in a wiring tool.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit layout design technology, specifically relating to a routing method for very large-scale integrated circuits based on integer linear programming. Background Technology

[0002] Digital circuit design tools are complete systems that can automate the process from high-level logic synthesis to low-level layout and routing. Routing, the process of connecting pins with the same potential using wires, is a crucial step in digital circuit design and generally involves two stages: global routing and detailed routing. Global routing typically occurs within a coarse-grained grid. It should be understood that routing regions are usually represented by many coarse-grained routing grids, with the grid size indicating the amount of routing resources. The result of global routing is the generation of a net topology, which specifies the grids the net must traverse to reach its final pin. Detailed routing, built upon the results of global routing, is a fine-grained process of assigning nets to specific tracks.

[0003] As integrated circuits become larger and more integrated, and transistor feature sizes approach physical limits, the power consumption and signal delay caused by interconnects have become significant factors affecting circuit performance. Furthermore, high integration levels prevent some nets from being fully routed, leading to unavoidable design rule violations. Common routing algorithms include maze routing and pattern routing, but both have drawbacks. For example, while maze routing has strong routing capabilities, it is easily affected by the net routing order, resulting in a generally larger net length and number of vias. Pattern routing is often used in the global routing stage, employing simple topologies, but it is prone to design rule violations and congestion during the transition from 2D to 3D topologies. Summary of the Invention

[0004] To address the aforementioned problems in the existing technology, this invention provides a very large-scale integrated circuit routing method based on integer linear programming. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a very large-scale integrated circuit routing method based on integer linear programming, comprising:

[0006] Based on the obstacle information, the network to be wired information, the design rule information, and the wiring track information within the wiring area, perform basic data initialization;

[0007] A net queue is generated based on the basic data, and the candidate path for each net to be wired in the net queue is searched using the A* search algorithm.

[0008] Based on the design rule information, violations among different candidate paths are checked, and the first violation information is saved;

[0009] Based on the first violation information, construct a value function and constraints, and solve for the optimal path;

[0010] Output the wiring results based on the optimal path.

[0011] In one embodiment of the present invention, the obstacle information includes metal layers and obstacle areas that need to be avoided during wiring, the network information to be wired includes the constituent pins of the network to be wired, the coordinates of the pins and the metal layer in which they are located, the design rule information includes the minimum line width, the minimum line spacing and the minimum via spacing, and the wiring track information includes the number of tracks and the track spacing for each metal layer.

[0012] In one embodiment of the present invention, the step of initializing and generating a net queue based on the basic data includes:

[0013] Determine whether the wiring area is being wired for the first time; if so, add all the nets in the wiring area as nets to be wired to the net queue.

[0014] Conversely, nets with violations from the previous wiring process are added to the net queue as nets to be wired.

[0015] In one embodiment of the present invention, the step of searching for candidate paths for each net to be routed in the net queue using the A* search algorithm includes:

[0016] Let k = 1, l = 1;

[0017] For the k-th net to be wired in the net queue, the l-th candidate path is searched using the A* search algorithm;

[0018] Increase the weight of the first grid point traversed by the l-th candidate path, as well as the weight of the adjacent grid points of the first grid point; the adjacent grid points are other grid points within the preset neighborhood of the first grid point;

[0019] Count the number of vias and the wire length of the l-th candidate path;

[0020] Determine if l is less than the preset value L; if not, let l = l + 1, and return to the step of searching for the l-th candidate path of the k-th net to be wired in the net queue using the A* search algorithm; otherwise, obtain the L candidate routes of the k-th net to be wired, and further determine if k is less than the number K of nets to be wired in the net queue.

[0021] If k < K, then set k = k + 1, and return the step of using the A* search algorithm to search for the l-th candidate path for the k-th to-be-routed net in the net queue; otherwise, obtain the candidate routes for all to-be-routed nets.

[0022] In an embodiment of the present invention, after the step of using the A* search algorithm to search for the l-th candidate path, the following is further included:

[0023] Store the l-th candidate route of the k-th to-be-routed net in the two-dimensional array netARRAY of the basic data;

[0024] After the step of obtaining the L candidate routes of the k-th to-be-routed net, the following is further included:

[0025] For the k-th to-be-routed net, zero out the weights of the first grid points passed by its L candidate routes and the weights of the adjacent grid points of each first grid point.

[0026] In an embodiment of the present invention, the step of checking the violation situations between different candidate paths based on the design rule information and saving the first violation information includes:

[0027] Based on the design rule information, check the violation situations between each candidate route in each to-be-routed net and each candidate route in other to-be-routed nets, and save the first violation information in the violation array of the basic data.

[0028] In an embodiment of the present invention, the step of constructing a value function and constraint conditions according to the first violation information and solving for the optimal path includes:

[0029] Construct a value function according to the first violation information:

[0030]

[0031] In the formula, violation[c] represents the c-th first violation information stored in the violation array, c = 1, 2, ..., netsize, violation[c] = netARRAY[A][m] * netARRAY[B][n], netARRAY[A][m] and netARRAY[B][n] are two candidate paths that cause the c-th first violation information, netARRAY[A][m] represents the m-th candidate path of the A-th net to be wired stored in the two-dimensional array netARRAY, netARRAY... Y[B][n] represents the nth candidate path of the Bth net to be routed stored in the two-dimensional array netARRAY, netARRAY[i][j] represents the jth candidate path of the ith net to be routed stored in the two-dimensional array netARRAY, i = 1, 2, ..., K, j = 1, 2, ..., L, wirelength[i][j] represents the metal trace length of netARRAY[i][j], viacout[i][j] represents the number of vias contained in netARRAY[i][j], and w1, w2, and w3 are all preset weights;

[0032] For each network to be wired, construct the following constraints:

[0033] netARRAY[i][1]+netARRAY[i][2]+...+netARRAY[i][maxnum]=1;

[0034] Under the given constraints, the optimal path for each of the networks to be wired is calculated by minimizing the value function.

[0035] In one embodiment of the present invention, netARRAY[i][j] = 1 indicates that the j-th candidate path of the i-th network to be wired is selected as the optimal path, and netARRAY[i][j] = 0 indicates that the j-th candidate path of the i-th network to be wired is not selected as the optimal path.

[0036] In one embodiment of the present invention, the step of outputting the routing result based on the optimal path includes:

[0037] Delete the interconnection information of each net to be wired in the basic data in the net queue, the interconnection information including the optimal path of each net to be wired in the last wiring;

[0038] Write the optimal path for each network to be wired into the interconnection information in the basic data;

[0039] Clear the violation array in the underlying data;

[0040] Based on the design rule information and the current interconnection information, violations between different optimal paths are checked, and the second violation information is saved in the violation array of the basic data.

[0041] Determine if the violation array is empty; if not, take the area where the network to be wired with the violation is located as the wiring area and return to the step of determining if the wiring area is the first wiring; if so, output the wiring result according to the current interconnection information.

[0042] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0043] This invention provides a routing method for very large-scale integrated circuits based on integer linear programming. This method collects candidate paths generated during the search process for each net to be routed and selects the optimal path from these candidate paths, which greatly solves the problems of traditional routing schemes that are not easy to route and cannot make the maximum use of intermediate results. Furthermore, this invention optimizes the method of checking design rules, which can check multiple nets to be routed and multiple candidate paths at the same time, providing a new approach to the method of checking design rules in routing tools.

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0045] Figure 1 This is a flowchart of a very large-scale integrated circuit routing method based on integer linear programming provided in an embodiment of the present invention;

[0046] Figure 2 This is a flowchart of searching for candidate paths in a network to be wired, provided in an embodiment of the present invention.

[0047] Figure 3 This is a flowchart of a design rule check provided in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the optimal path for the cabling network provided in an embodiment of the present invention. Detailed Implementation

[0049] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0050] Figure 1 This is a flowchart of a very large-scale integrated circuit routing method based on integer linear programming provided in an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a very large-scale integrated circuit routing method based on integer linear programming, including:

[0051] S11. Initialize basic data based on obstacle information, network information to be wired, design rule information, and wiring track information within the wiring area;

[0052] S12. Generate a net queue based on the basic data, and use the A* search algorithm to search for candidate paths for each net to be wired in the net queue.

[0053] S13. Based on the design rule information, check for violations among different candidate paths and save the first violation information;

[0054] S14. Construct a value function and constraints based on the information of the first violation, and solve for the optimal path;

[0055] S15. Output routing results based on the optimal path.

[0056] In this embodiment, the first step is to read in the obstacle information, net information to be routed, design rule information, and routing track information within the routing area, and assign values ​​to the basic data based on the above information to complete the initialization. For example, the obstacle information includes the metal layers and obstacle areas that need to be avoided during routing, and the shape is a set of polygons. The net information to be routed includes the constituent pins of the net to be routed, the coordinates of the pins, and the metal layer in which they are located. The design rule information includes the minimum line width, minimum line spacing, and minimum via spacing. The routing track information indicates the amount of available routing resources, which includes the number of tracks and the track spacing for each metal layer.

[0057] Optionally, step S12, the step of initializing and generating the net queue based on the basic data, includes:

[0058] Determine if the routing area is being routed for the first time; if so, add all nets in the routing area as nets to be routed to the net queue.

[0059] Conversely, nets with violations from the previous wiring process are added to the net queue as nets to be wired.

[0060] It should be understood that if the routing area has not undergone a routing process before, then all nets in the routing area have not been pin interconnected and need to be treated as nets to be routed; if the routing area is not undergoing a routing process for the first time, then nets that had design rule violations during the previous routing are obtained and added to the net queue as nets to be routed this time.

[0061] Figure 2 This is a flowchart illustrating a method for searching candidate paths in a network to be wired, as provided in an embodiment of the present invention. Further, as... Figure 2 As shown, the steps for searching candidate paths for each net to be routed in the net queue using the A* search algorithm include:

[0062] S21. Let k = 1, l = 1;

[0063] S22. For the k-th to-be-routed net in the net queue, use the A* search algorithm to search for its l-th candidate path;

[0064] S23. Increase the weight of the first grid point passed by the l-th candidate path, as well as the weights of the adjacent grid points of the first grid point; the adjacent grid points are other grid points within the preset neighborhood of the first grid point;

[0065] S24. Count the number of vias and the net length of the l-th candidate path;

[0066] S25. Determine whether l is less than the preset value L; if not, set l = l + 1, and return to the step of using the A* search algorithm to search for the l-th candidate path for the k-th to-be-routed net in the net queue; otherwise, obtain the L candidate routes for the k-th to-be-routed net, and further determine whether k is less than the number K of to-be-routed nets in the net queue;

[0067] S26. If k < K, set k = k + 1, and return to the step of using the A* search algorithm to search for the l-th candidate path for the k-th to-be-routed net in the net queue; otherwise, obtain the candidate routes for all to-be-routed nets.

[0068] Among them, after the step of using the A* search algorithm to search for the l-th candidate path, it further includes:

[0069] Store the l-th candidate route of the k-th to-be-routed net in the two-dimensional array netARRAY of the basic data;

[0070] After the step of obtaining the L candidate routes for the k-th to-be-routed net, it further includes:

[0071] For the k-th to-be-routed net, zero the weights of the first grid points passed by its L candidate routes respectively, as well as the weights of the adjacent grid points of each first grid point.

[0072] In this embodiment, path search is carried out for each to-be-routed net in the net queue, and the candidate paths generated during the search process are recorded. Specifically, as Figure 2 shown, for each to-be-routed net, use the A* search method to generate candidate paths. After each candidate path is searched, immediately save this candidate path to the two-dimensional array netARRAY of the basic data; then increase the weights of the first grid point passed by the candidate path and its surrounding grid points, and count the net length (unit: micrometer) and the number of vias (unit: piece) of each candidate path. It should be understood that by increasing the weights of the first grid point passed by the candidate path and its adjacent grid points, the chance that the subsequent searched candidate path passes through this first grid point again will be reduced, so as to ensure the difference between candidate paths during the search process for each to-be-routed net.

[0073] Determine whether the number of candidate paths generated by the network to be wired after this search has reached the preset value L. If not, repeat the A* search to generate another candidate path. Otherwise, if the number of candidate paths of the network to be wired has reached the preset value L, stop searching for new candidate paths for the network to be wired and reset the weights of the first grid point and its adjacent grid points through which the L candidate paths of the network to be wired are 0, thereby ensuring the degree of freedom of other networks to be wired in the path search process.

[0074] Furthermore, a candidate path search is performed on the next net to be wired in the net queue. The above steps are repeated until all nets to be wired have been searched, and then the candidate paths for all nets to be wired can be obtained.

[0075] Optionally, step S13 above, which involves checking for violations among different candidate paths based on design rule information and saving the first violation information, includes:

[0076] Based on the design rule information, the violations between each candidate route in each network to be wired and each candidate route in other networks to be wired are checked, and the first violation information is saved in the violation array of the basic data.

[0077] The design rule check involves trimming and dividing the candidate paths of the network to be wired into multiple rectangles. By comparing the relative positions of the rectangles, it is determined whether there are any violations among the candidate paths. For example, this embodiment uses the Boost library to store the rectangle information of the candidate paths. The Boost library provides a lookup index function.

[0078] It should be noted that when checking the candidate routes of the k-th cabling frame, it is only necessary to check whether there are violations between it and the candidate routes of other cabling frames, and it is not necessary to check whether there are violations between the candidate routes of the k-th cabling frame. In addition, if the l1-th candidate path of the A-th cabling network and the l2-th and l3-th candidate paths of the B-th cabling network both have violations, then both violations are recorded, and two first violation messages are generated accordingly.

[0079] The following section uses short circuit, insufficient contact, and line spacing checks as examples to further explain the inspection of violations.

[0080] Figure 3 This is a flowchart illustrating a design rule check provided in an embodiment of the present invention. Please refer to [link / reference]. Figure 3The rectangle 'a' being inspected is the subject, and the other indexed rectangles 'b' constitute set B. Rectangles 'b' are called objects. To avoid misidentification and violations between different candidate paths of the same net, before the design rule check, rectangles 'b' in set B that belong to the same net but are different candidate paths from rectangle 'a' are filtered out. For the remaining rectangles 'b' in set B, if they intersect with rectangle 'a', short-circuit checks and insufficient contact checks are performed; if they do not intersect with rectangle 'a', line spacing checks are performed.

[0081] Optionally, step S14, which involves constructing a value function and constraints based on the first violation information and solving for the optimal path, includes:

[0082] Construct a value function based on the first violation information:

[0083]

[0084] In the formula, violation[c] represents the c-th first violation information stored in the violation array, c = 1, 2, ..., netsize, violation[c] = netARRAY[A][m] * netARRAY[B][n], netARRAY[A][m] and netARRAY[B][n] are two candidate paths that cause the c-th first violation information, and netARRAY[A][m] represents the m-th candidate path of the A-th net to be wired stored in the two-dimensional array netARRAY, netARRAY [B][n] represents the nth candidate path of the Bth net to be wired stored in the two-dimensional array netARRAY, netARRAY[i][j] represents the jth candidate path of the ith net to be wired stored in the two-dimensional array netARRAY, i = 1, 2, ..., K, j = 1, 2, ..., L, wirelength[i][j] represents the metal trace length of netARRAY[i][j], viacout[i][j] represents the number of vias contained in netARRAY[i][j], and w1, w2, and w3 are all preset weights;

[0085] For each network to be wired, construct the following constraints:

[0086] netARRAY[i][1]+netARRAY[i][2]+...+netARRAY[i][maxnum]=1;

[0087] Under constraints, the optimal path for each network to be wired is calculated by minimizing the value function.

[0088] Specifically, the violation array is obtained from the basic data. The violation array stores multiple first violation information. When constructing the value function, it is necessary to find two candidate paths corresponding to each first violation information. For example, if the indexed first violation information is generated by the m-th candidate path of the A-th network to be wired and the n-th candidate path of the B-th network to be wired, then it is necessary to find the variables netARRAY[A][m] and netARRAY[B][n] corresponding to the m-th candidate path and the n-th candidate path in the array netARRAY.

[0089] Iterate through the VioSize entries of the first violation in the violation array and construct the value function according to the following formula:

[0090]

[0091] Among them, w1 = 500, w2 = 0.5, and w3 = 2.

[0092] Next, constraints are constructed based on the number of one-dimensional variables in netARRAY. Each one-dimensional variable netARRAY[i] in netARRAY has the following constraints:

[0093] netARRAY[i][1]+netARRAY[i][2]+...+netARRAY[i][maxnum]==1.

[0094] Then, the CPLEX solver is used to solve for the value function under constraints, that is, to minimize the value function while satisfying the constraints. After the solution is completed, if netARRAY[i][j] = 1, it means that the j-th candidate path of the i-th network to be wired is selected as the optimal path; if netARRAY[i][j] = 0, it means that the j-th candidate path of the i-th network to be wired is not selected as the optimal path.

[0095] Figure 4 This is a schematic diagram of the optimal path for the cabling network provided in an embodiment of the present invention. For example... Figure 4 As shown, A, B, and C are three nets to be routed. The rectangles represent the pins of the three nets to be routed, and a1, a2, b1, b2, c1, and c2 represent candidate paths. It can be seen that the first violation information is v[a1,b1], v[a1,b2], v[a1,c1], v[a1,c2], v[b1,c1], v[b2,c2]. To minimize the value function, the solution is that net A selects candidate path a2 as the optimal path, net B selects candidate path b1 as the optimal path, and net C selects candidate path c2.

[0096] In step S15 above, the step of outputting the routing result based on the optimal path includes:

[0097] Delete the interconnection information of each net to be wired in the basic data of the net queue. The interconnection information includes the optimal path of each net to be wired during the last wiring.

[0098] Write the optimal path for each network to be wired into the interconnection information in the basic data;

[0099] Clear the violation array in the underlying data;

[0100] Based on the design rule information and the current interconnection information, the violation situation between different optimal paths is checked, and the second violation information is saved in the violation array of the basic data;

[0101] Check if the violation array is empty; if not, take the area containing the network to be wired with the violation as the wiring area and return to the step of checking if the wiring area is the first wiring; if so, output the wiring result according to the current interconnection information.

[0102] For the updated basic data, a design rule check is performed. First, the violation array containing the first violation information in the current basic data is cleared. Then, the second violation information obtained from this design rule check is rewritten into the violation array. Further, it is determined whether the violation array is empty. If it is empty, the routing result is output based on the updated basic data. If it is not empty, the nets with violations need to be rerouted. At this point, the process returns to step S12 to generate a new net queue.

[0103] It should be noted that the output routing results can be saved as a text file, which includes the metal layers through which the net passes and the types of vias used. The shape within the metal layers can be represented by the vertex coordinates of multiple rectangles.

[0104] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0105] This invention provides a routing method for very large-scale integrated circuits based on integer linear programming. This method collects candidate paths generated during the search process for each net to be routed and selects the optimal path from these candidate paths, which greatly solves the problems of traditional routing schemes that are not easy to route and cannot make the maximum use of intermediate results. Furthermore, this invention optimizes the method of checking design rules, which can check multiple nets to be routed and multiple candidate paths at the same time, providing a new approach to the method of checking design rules in routing tools.

[0106] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0107] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0108] Although this application has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in carrying out the claimed application by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0109] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A routing method for very large-scale integrated circuits based on integer linear programming, characterized in that, include: Based on the obstacle information, the network to be wired information, the design rule information, and the wiring track information within the wiring area, perform basic data initialization; A net queue is generated based on the aforementioned basic data, and the A* search algorithm is used to search for candidate paths for each net to be routed in the net queue, including: make k =1, l =1; For the first in the net queue k For a network to be wired, use the A* search algorithm to search for its i-th... l The candidate path will be the first one. k The first network to be wired l The candidate routes are stored in a two-dimensional array of the underlying data. middle; Add the first l The weight of the first grid point traversed by the candidate path, and the weights of the adjacent grid points of the first grid point; the adjacent grid points are other grid points within the preset neighborhood of the first grid point. The statistics of the first l The number of vias and the wire length of each candidate path; judge l Is it less than the preset value? L If not, then let l = l +1, and return the value for the first net in the net queue. k For a network to be wired, use the A* search algorithm to search for its i-th... l The steps for the first candidate path; otherwise, the steps for the second candidate path are obtained. k A network to be wired L The candidate route, for the first k A network to be wired, its L The weights of the first grid points traversed by each candidate route, as well as the weights of the adjacent grid points of each first grid point, are set to zero, and further judgment is made. k Is it less than the number of nets to be wired in the net queue? K ; like k < K Then let k = k +1, and return the value for the first net in the net queue. k For a network to be wired, use the A* search algorithm to search for its i-th... l The steps for selecting candidate paths; conversely, obtaining candidate routes for all networks to be wired. Based on the design rule information, violations among different candidate paths are checked, and the first violation information is saved; A value function is constructed based on the first violation information; constraints are constructed for each network to be wired; under the constraints, the value function is minimized, and the optimal path for each network to be wired is calculated. Output the cabling results based on the optimal path for each of the nets to be cabled.

2. The VLSI routing method based on integer linear programming according to claim 1, characterized in that, The obstacle information includes metal layers and obstacle areas that need to be avoided during routing; the network information to be routed includes the constituent pins of the network to be routed, the coordinates of the pins, and the metal layer in which they are located; the design rule information includes the minimum line width, minimum line spacing, and minimum via spacing; and the routing track information includes the number of tracks and track spacing for each metal layer.

3. The VLSI routing method based on integer linear programming according to claim 2, characterized in that, The steps for initializing and generating a net queue based on the aforementioned basic data include: Determine whether the wiring area is being wired for the first time; if so, add all the nets in the wiring area as nets to be wired to the net queue. Conversely, nets with violations from the previous wiring process are added to the net queue as nets to be wired.

4. The VLSI routing method based on integer linear programming according to claim 3, characterized in that, The step of checking for violations among different candidate paths based on the design rule information and saving the first violation information includes: Based on the design rule information, the violations between each candidate route in each network to be wired and each candidate route in other networks to be wired are checked, and the first violation information is saved in the violation array of the basic data.

5. The VLSI routing method based on integer linear programming according to claim 4, characterized in that, The steps for constructing a value function and constraints based on the first violation information, and solving for the optimal path, include: Construct a value function based on the first violation information: In the formula, This indicates the number of violations stored in the violation array. The first violation information, , , , To cause the aforementioned first Two candidate paths for the first violation information. Representing a two-dimensional array The first stored in the middle The first network to be wired Candidate paths, Representing a two-dimensional array The first stored in the middle The first network to be wired Candidate paths, Representing a two-dimensional array The first stored in the middle The first network to be wired Candidate paths, , , express The length of the metal trace, express Number of through holes included. , , All are preset weights; For each network to be wired, construct the following constraints: ； Under the given constraints, the optimal path for each of the networks to be wired is calculated by minimizing the value function.

6. The VLSI routing method based on integer linear programming according to claim 5, characterized in that, Indicates the first The first network to be wired The candidate path was selected as the optimal path. Indicates the first The first network to be wired The candidate paths were not selected as the optimal paths.

7. The VLSI routing method based on integer linear programming according to claim 6, characterized in that, The steps for outputting routing results based on the optimal path include: Delete the interconnection information of each net to be wired in the basic data in the net queue, the interconnection information including the optimal path of each net to be wired in the last wiring; Write the optimal path for each network to be wired into the interconnection information in the basic data; Clear the violation array in the underlying data; Based on the design rule information and the current interconnection information, violations between different optimal paths are checked, and the second violation information is saved in the violation array of the basic data. Determine if the violation array is empty; if not, take the area where the network to be wired with the violation is located as the wiring area and return to the step of determining if the wiring area is the first wiring; if so, output the wiring result according to the current interconnection information.

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