A method for optimizing via pad impedance matching tear drop based on TDR simulation

Abstract

The application belongs to the field of electromagnetic compatibility and electronic packaging design, and particularly relates to an optimization method for via pad impedance matching tear drop based on TDR simulation. The application proposes a targeted b and theta parameter control for the linear tear drop pad to be optimized through modeling, simplifies the linear tear drop pad into a Boolean union of a circle and a rectangle, and takes the pad center as the coordinate system origin, with the trace in the negative direction of the y axis. A point (0, -b) on the trace center line and a point (rcos theta, rsin theta) on the circle are taken to construct the relevant model of the linear tear drop pad, and then the impedance matching capability is analyzed. The application can more accurately and efficiently reduce the via breakage while considering the signal integrity problem, improve the design margin of other impedance compensation structures, and thus improve the overall design margin of the PCB.

Description

Technical Field

[0001] This invention belongs to the fields of electromagnetic compatibility and electronic packaging design; specifically, it is an optimization method for via pad impedance matching teardrops based on TDR simulation. Background Technology

[0002] Teardrops are a crucial and common feature in PCB design. Their primary application is in the final stages of PCB design, where they reduce via breakage and improve manufacturing yield; prevent acid traps and enhance reliability; reduce mechanical and thermal stress at the connection points between traces and pads, thus minimizing fine-line cracks in the traces; increase pad tolerances for PCB manufacturers, making circuit board production easier and reducing scrap and cracking risk; improve resistance to thermal shock, primarily affecting rework and wave soldering during production; and, if discovered in emergency environments, enhance the product's thermal shock resistance.

[0003] From a stress perspective, changing the teardrop shape can eliminate stress concentration at the base teardrop between the pad and via, reducing the probability of cracking on the substrate and PCB. However, this approach does not consider the impact of changing the teardrop shape on signal integrity. From a signal integrity perspective, surface mount devices, pads, vias, and other structures can cause impedance discontinuities in transmission lines, leading to a decrease in signal integrity. Existing technologies mention using ground gaps to compensate for excess parasitic capacitance and use TDR simulations to illustrate the impedance discontinuity problem in signal interconnects. Summary of the Invention

[0004] To address the aforementioned problems or shortcomings and to solve the technical issues, this invention proposes an optimization method for via pad impedance matching teardrops based on TDR simulation, in order to find the optimal design for linear teardrops to compensate for impedance changes in the via pad structure.

[0005] An optimization method for via pad impedance matching teardrops based on TDR simulation is described below:

[0006] Step 1: Create a 3D model of the target PCB stack-up structure, traces, vias, and pads in HFSS.

[0007] Step 2: Under the conditions of the 3D model established in Step 1, establish a coordinate system for the linear teardrop pad to be optimized:

[0008] The linear teardrop pad is simplified into a Boolean union of a circle and a rectangle, wherein the pad corresponds to the circle and the trace corresponds to the rectangle; taking the center of the pad as the coordinate origin, the direction from the trace toward the pad is defined as the positive direction of the y-axis, and the trace is located in the negative direction of the y-axis; for a point (rcosθ,rsinθ) on the circle and a point (0,-b) on the center line of the trace, r is the radius of the circle, θ is the included angle formed by the straight line from the point (rcosθ,rsinθ) to the origin and the positive direction of the x-axis; the connecting line segment between the two points is a solid line, where k is the slope of the solid line, corresponding to the solid

[0009]

[0010] Step 3: In the three-dimensional model constructed in step 1, perform TDR impedance simulation by scanning the two parameters b and θ set in step 2 through HFSS, find the curve with the smoothest impedance change, and the corresponding structure is the linear teardrop structure with optimal impedance matching optimization corresponding to the pre-optimized linear teardrop pad.

[0011] Further, the value range of k in said step 2 satisfies tanθ1≤k<tanθ2, so as to achieve higher parameter scanning effectiveness;

[0012] Two rays starting from the point (0,-b) on the center line of the conductor: one is tangent to the circle in the first quadrant or the fourth quadrant, and the tangent point is (x1,y1), the other passes through the corner point and intersects the circular edge at another point (x2,y2), wherein the corner point is the intersection of the outer edge of the wide side of the trace and the circle, w is the width of the trace, and a is represented as

[0013]

[0014]

[0015] θ1 is the included angle between the straight line from the point (x1,y1) to the origin and the positive direction of the x-axis, and θ2 is the included angle between the straight line from the point (x2,y2) to the origin and the positive direction of the x-axis; the value range of k is between the slopes of the two rays, that is, tanθ1≤k<tanθ2; through the intersection points of three lines starting from (0,-b) and the circle, the value range of k can be converted into the value range of the angle θ.

[0016] In conclusion, the present invention proposes a targeted control of two parameters b and θ for the linear teardrop pad to be optimized through modeling, and then analyzes the impedance matching capability, which can more accurately and efficiently reduce through hole cracking while taking into account the signal integrity problem, increase the design margin of other impedance compensation structures, thereby improving the overall design margin of a PCB. Description of Drawings

[0017] Figure 1 These are the PCB board stack-up parameters used in the simulation of the example;

[0018] Figure 2 This is a simplified original view of a pair of differential trace vias and pads in the embodiment.

[0019] Figure 3 This is a top view of a pair of differential trace vias and pads after the simplification of the embodiment;

[0020] Figure 4 This is a simplified front view of a pair of differential trace vias and pads in the embodiment.

[0021] Figure 5 This is a simplified side view of a pair of differential trace vias and pads in the embodiment.

[0022] Figure 6 This is a top view of the teardrop pads obtained by substituting the default design parameters in Altium Designer.

[0023] Figure 7 This is the mathematical model for pre-optimizing linear teardrop pads in this invention;

[0024] Figure 8 This is a comparison between the best TDR impedance curve of the embodiment and the default teardrop pad design and the teardrop pad design;

[0025] Figure 9 This is a top view of the teardrop pad with the best impedance matching effect obtained from the embodiment. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0027] The PCB stack-up parameters used in this embodiment are as follows: Figure 1 As shown. Its corresponding via pad model is a differential via pad, such as... Figures 2-5 As shown. Figure 6 The teardrop pad is obtained by substituting the default design parameters of the PCB design software (Altium Designer). The default design is that the teardrop width is 30% of the pad diameter and the length is 70% of the pad diameter.

[0028] The stack-up structure in this embodiment is a common four-layer board stack-up structure, which is controlled by material properties and the thickness of each metal layer and dielectric layer; the traces are controlled by thickness, spacing and line width; and the vias and pads are controlled by radius and spacing.

[0029] In order to find the optimal impedance matching capability of the linear teardrop via pad in this embodiment, the following design was performed: Figure 6 Mathematical modeling of the model, such as Figure 7As shown. The linear teardrop pad is simplified as a Boolean union of a circle and a rectangle, wherein the pad corresponds to the circle and the trace corresponds to the rectangle; with the center of the pad as the coordinate origin, the direction from the trace to the pad is taken as the positive direction of the y-axis, and the trace is located in the negative direction of the y-axis; for a point (rcosθ, rsinθ) on the circle and a point (0,-b) on the center line of the trace, r is the radius of the circle, and θ is the included angle formed by the straight line from the point (rcosθ, rsinθ) to the origin and the positive direction of the x-axis; the connecting line segment between the two points is a solid line, wherein k is the slope of the solid line, and the corresponding solid line is expressed by the formula as y+b=kx, the slope

[0030] To eliminate some meaningless cases and improve the effectiveness of parameter scanning, it is necessary to set the value range of k, and the value range of k is tanθ1≤k<tanθ2.

[0031] Two rays starting from the point (0,-b) on the center line of the trace: one ray is tangent to the circle in the first quadrant or the fourth quadrant, and the tangent point is (x1,y1), the other ray passes through the corner point and intersects the circular edge at another point (x2,y2), wherein the corner point is the intersection of the outer edge of the wide side of the trace and the circle, w is the width of the trace, and a is expressed as

[0032]

[0033]

[0034] θ1 is the included angle between the straight line from the point (x1,y1) to the origin and the positive direction of the x-axis, and θ2 is the included angle between the straight line from the point (x2,y2) to the origin and the positive direction of the x-axis; the value range of k is between the slopes of the two rays, that is, tanθ1≤k<tanθ2; through the intersection points of three lines starting from (0,-b) and the circle, the value range of k can be converted into the value range of the angle θ.

[0035] In the present invention, all linear teardrop via pads are represented by two parameters b and θ, therefore, by adding the two-parameter scanning of b and θ in the TDR simulation of HFSS, in the simulation results, the TDR impedance curve with the gentlest change corresponds to the optimal design in the present experiment.

[0036] Figure 8 it is the TDR impedance presented by one port in the 4-port differential line of the present embodiment, and the change trends of the other three ports are consistent with that of this port. In Figure 8As we can see, without adding teardrops to the via pads, the signal line impedance drops significantly around 100ps due to the presence of vias and residual stubs. The optimal point of this embodiment occurs at b = 15mil, θ = 15deg, and its shape is as follows. Figure 9 As shown. And in Figure 8 As we can see, compared to the default design, the structure obtained by this invention has a significantly improved impedance smoothing capability. Using 50 ohms as the standard impedance, the maximum impedance deviation of the teardrop-less pad is approximately 6 ohms. The maximum impedance deviation of the default straight teardrop structure is approximately 5.6 ohms, an optimization of approximately 6.7%. The maximum impedance deviation of the straight teardrop structure obtained by the optimization method of this invention is approximately 3.8 ohms, an optimization of approximately 36.7%.

[0037] As can be seen from the above embodiments, the modeling method of the present invention for linear via teardrop pads matches the actual scenario well, and provides a good optimization effect for the impedance matching-based design of linear via teardrop pads, which has important engineering value.

Claims

1. An optimization method for impedance matching teardrops of via pads based on TDR simulation, characterized in that, The specific steps are as follows: Step 1: Perform three-dimensional modeling on the target PCB stack structure, traces, vias and pads in HFSS; Step 2: Under the condition of the three-dimensional model established in Step 1, establish a coordinate system for the linear teardrop pad to be optimized; The linear teardrop pad is simplified to a Boolean union of a circle and a rectangle, with the pad corresponding to the circle and the trace to the rectangle. The origin of the coordinate system is the center of the pad, the direction of the trace towards the pad is the positive y-axis, and the trace is in the negative y-axis direction. For a point (rcosθ, rsinθ) on the circle and a point (0, -b) on the center line of the trace, r is the radius of the circle, and θ is the angle between the line from (rcosθ, rsinθ) to the origin and the positive x-axis. The line segment connecting the two points is a solid line, where k is the slope of this solid line, expressed by the formula y + b = kx, where the slope is... Step 3: In the three-dimensional model constructed in Step 1, scan the two parameters b and θ set in Step 2 through HFSS, perform TDR impedance simulation, and find the curve with the smoothest impedance change. The corresponding structure is the linear teardrop structure obtained by the optimal impedance matching optimization corresponding to the linear teardrop pad to be pre-optimized.

2. The optimization method for via pad impedance matching teardrops based on TDR simulation as described in claim 1, characterized in that: The value range of k in Step 2 is tanθ1≤k<tanθ2; Two rays originating from the midline of the conductor at point (0, -b): one is tangent to the circle in the first or fourth quadrant, with the point of tangency at (x1, y1). Another corner point The circle intersects at another point (x2, y2), where the corner point is the intersection of the outer edge of the trace width and the circle, w is the trace width, and a represents... θ1 is the included angle between the straight line from the point (x1,y1) to the origin and the positive direction of the x-axis, and θ2 is the included angle between the straight line from the point (x2,y2) to the origin and the positive direction of the x-axis; the value range of k is between the slopes of the two rays, that is, tanθ1≤k<tanθ2; through the intersection points of three lines starting from (0,-b) and the circle, the value range of k can be converted into the value range of the angle θ.

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