Memory and sensing amplifier device therefor

Abstract

A memory and a sensing amplifier device thereof are provided. The sensing amplifier device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first pre-charge circuit is coupled to the first input terminal. The first pre-charge circuit performs a pre-charge operation on the first input terminal based on a power supply voltage, a pre-charge enable signal, and a control voltage. The control voltage generator generates the control voltage based on the power supply voltage, wherein the control voltage is positively related to the power supply voltage.

Description

Technical Field

[0001] This invention relates to a memory and a sensing amplification device thereof. Background Technology

[0002] In the field of memory technology, a pre-charge circuit is often provided at the input terminal of the sensing amplification device to pre-charge the input terminal of the sensing amplification device before performing a reading operation of the memory cell, which can accelerate the sensing operation of the data signal of the subsequent memory cell.

[0003] In known technologies, pre-charge circuits typically have a fixed pre-charge time. However, when the power supply voltage received by the sensing amplifier changes, the pre-charge circuit may raise the voltage at the input of the sensing amplifier to varying degrees within this fixed pre-charge time. For example, when the power supply voltage increases, the input voltage of the sensing amplifier may be pre-charged to a relatively high value; conversely, when the power supply voltage decreases, the input voltage may be pre-charged to a relatively low value. This instability in the pre-charge operation can cause sensing data errors when the memory is used with different power supply voltages, or cause read speeds to vary with the power supply voltage. Summary of the Invention

[0004] According to an embodiment of the present invention, the sensing amplification device includes a differential amplifier, a first precharge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first precharge circuit is coupled to the first input terminal. The first precharge circuit performs a precharge operation on the first input terminal based on a power supply voltage, a precharge start signal, and a control voltage. The control voltage generator generates a control voltage based on the power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

[0005] According to an embodiment of the present invention, the memory includes at least one memory cell and a sensing amplification device. The sensing amplification device is coupled to the memory cell. The sensing amplification device includes a differential amplifier, a first precharge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first precharge circuit is coupled to the first input terminal. The first precharge circuit performs a precharge operation on the first input terminal based on a power supply voltage, a precharge start signal, and a control voltage. The control voltage generator generates a control voltage based on the power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

[0006] Based on the above, the sensing amplification device of the present invention performs a pre-charge operation at the input terminal of the differential amplifier by controlling the voltage. Since the control voltage is positively correlated with the power supply voltage, changes in the power supply voltage can be compensated for during the pre-charge operation of the first pre-charge circuit, and the pre-charge operation is unaffected by changes in the power supply voltage. Therefore, the overall operation of the memory can be independent of changes in the power supply voltage. Attached Figure Description

[0007] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0008] Figure 1 This is a schematic diagram of a sensing amplification device according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of an embodiment of the pre-charging circuit in the sensing amplification device of the present invention;

[0010] Figure 3 For the present invention Figure 2 In the embodiment, a waveform diagram of an embodiment of the control voltage generator 200 is shown;

[0011] Figure 4 This is a schematic diagram of an embodiment of the pre-charging circuit of the sensing amplification device according to an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram of a memory according to an embodiment of the present invention;

[0013] Figure 6 This is a schematic diagram of a memory according to another embodiment of the present invention.

[0014] Explanation of icon numbers

[0015] 100: Sensing amplification device;

[0016] 110, 511, 611: Differential amplifiers;

[0017] 120, 400, 512, 6121, 6122: Pre-charging circuit;

[0018] 130, 200: Control voltage generator;

[0019] 210: Constant current source;

[0020] 310: Curve;

[0021] 410, 420: Pre-charge sub-circuit;

[0022] 500, 600: Memory;

[0023] 513, 613: Data latches;

[0024] BL, RBL: Bit lines;

[0025] CELL, CELLR: Storage unit;

[0026] DisC: Discharge control signal;

[0027] DL, RBL: Data cables;

[0028] DO: Sensor data;

[0029] IN1, IN2: Input terminals;

[0030] MPP0, MNN0, MP0~MP5, MP01, MP11, MN2~MN6, MND, MND1, MND2, MPR2~MPR6, MNR0~MNR3: transistors;

[0031] PC: Precharge start signal;

[0032] PCSb, PCWb: Precharge starter signals;

[0033] Sout: Output signal;

[0034] VCC: Power supply voltage;

[0035] Vpgp: Control voltage;

[0036] Vra: Reference signal;

[0037] VREF, VSS: Reference voltages;

[0038] Vsa: Data signal;

[0039] Vthp: On-state voltage;

[0040] Y, Vsen, SET, SETN: Signals. Detailed Implementation

[0041] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0042] Please refer to Figure 1 , Figure 1This is a schematic diagram of a sensing amplification device according to an embodiment of the present invention. The sensing amplification device 100 includes a differential amplifier 110, a pre-charge circuit 120, and a control voltage generator 130. The differential amplifier 110 has input terminals IN1 and IN2. Input terminal IN1 of the differential amplifier 110 is coupled to the pre-charge circuit 120 and receives a data signal. Input terminal IN2 of the differential amplifier 110 receives a reference signal Vra. In this embodiment, input terminal IN1 of the differential amplifier 110 can be coupled to a selected memory cell, wherein the selected memory cell is selected to perform a read operation. The selected memory cell can be used to provide a data signal Vsa to input terminal IN1 of the differential amplifier 110. During the read operation, the pre-charge circuit 120 performs a pre-charge operation on input terminal IN1 of the differential amplifier 110 before the data signal Vsa is provided to input terminal IN1 of the differential amplifier 110.

[0043] The differential amplifier 110 is used to compare the magnitudes of the data signal Vsa on the input terminal IN1 and the reference signal Vra on the input terminal IN2, and generates the output signal Sout by amplifying the difference between the data signal Vsa and the reference signal Vra.

[0044] In this embodiment, the pre-charge circuit 120 can perform a pre-charge operation on the input terminal IN1 based on the power supply voltage VCC, the pre-charge start signal PC, and the control voltage Vpgp. The control voltage Vpgp is provided by the control voltage generator 130. The control voltage generator 130 generates the control voltage Vpgp based on the power supply voltage VCC. In one embodiment, the control voltage Vpgp is positively correlated with the power supply voltage VCC.

[0045] To further explain, the control voltage generator 130 can adjust the control voltage Vpgp based on the magnitude of the power supply voltage VCC. When the power supply voltage VCC is less than or equal to a reference value, the control voltage Vpgp can be maintained at a low voltage close to 0 volts. When the power supply voltage VCC is greater than the aforementioned reference value, the control voltage Vpgp can increase linearly proportional to the power supply voltage VCC. In this embodiment, when the power supply voltage VCC is greater than the aforementioned reference value, the change in control voltage Vpgp can be equal to the change in power supply voltage VCC.

[0046] As explained above, when the power supply voltage VCC changes, the pre-charge circuit 120 can maintain the pre-charge capability of the input terminal IN1 by dynamically changing the control voltage Vpgp according to the change in power supply voltage VCC. In this way, regardless of the change in power supply voltage VCC, the pre-charge operation at the input terminal IN1 of the differential amplifier 110 remains constant. The voltage at the input terminal IN1 of the differential amplifier 110 will not experience insufficient or excessive pre-charge due to changes in power supply voltage VCC, reducing the possibility of the differential amplifier 110 generating an erroneous output signal Sout, and effectively maintaining the data sensing rate of the sensing amplification device 100.

[0047] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of an embodiment of the control voltage generator in the sensing amplification device of the present invention. The control voltage generator 200 includes a transistor MPP0 and a constant current source 210. A first terminal of the transistor MPP0 receives a power supply voltage VCC; a control terminal of the transistor MPP0 receives a reference voltage VSS; and a second terminal of the transistor MPP0 is coupled to the constant current source 210 and generates a control voltage Vpgp. The constant current source 210 is coupled between the second terminal of the transistor MPP0 and a reference ground terminal, wherein the reference ground terminal is used to receive the reference voltage VSS. In this embodiment, the reference voltage VSS can be a 0-volt ground voltage.

[0048] In this embodiment, the constant current source 210 is constructed by transistor MNN0. The first terminal of transistor MNN0 is coupled to the second terminal of transistor MPP0; the control terminal of transistor MNN0 receives a reference voltage VREF; and the second terminal of transistor MNN0 receives a reference voltage VSS. The reference voltage VREF can be greater than the reference voltage VSS. In this embodiment, the reference voltage VREF can be, for example, 1.1 volts to 1.2 volts.

[0049] A constant current source 210 draws a fixed current from the second terminal of transistor MPP0 to the second terminal of transistor MNN0. When the supply voltage VCC is not greater than the turn-on voltage of transistor MPP0 (equivalent to a reference value), transistor MPP0 is not turned on, and the control voltage Vpgp at the second terminal of transistor MPP0 can be pulled low by the constant current source 210 to a very low voltage (e.g., 0 volts). When the supply voltage VCC is greater than the turn-on voltage of transistor MPP0, transistor MPP0 can be turned on. At this time, a fixed difference can be maintained between the control voltage Vpgp at the second terminal of transistor MPP0 and the supply voltage VCC.

[0050] You can refer to this simultaneously. Figure 2 as well as Figure 3 ,in Figure 3 For the present invention Figure 2 In this embodiment, a waveform diagram of the control voltage generator 200 is shown. When the power supply voltage VCC is not greater than the turn-on voltage Vthp of transistor MPP0, the control voltage Vpgp is essentially equal to 0 volts. When the power supply voltage VCC is greater than the turn-on voltage Vthp of transistor MPP0, the control voltage Vpgp increases linearly with the increase of the power supply voltage VCC. The slope of the curve 310 showing the relationship between the control voltage Vpgp and the power supply voltage VCC can be equal to 1.

[0051] Next, please refer to Figure 4 , Figure 4 This is a schematic diagram of an embodiment of the pre-charge circuit of the sensing amplification device according to an embodiment of the present invention. The pre-charge circuit 400 includes pre-charge sub-circuits 410 and 420. Pre-charge sub-circuit 410 includes transistors MP0 and MP01. Pre-charge sub-circuit 420 includes transistors MP1 and MP11. In this embodiment, the first terminal of transistor MP0 receives the power supply voltage VCC; the second terminal of transistor MP0 is coupled to the first terminal of transistor MP01; the control terminal of transistor MP0 receives the pre-charge starter signal PCSb. The control terminal of transistor MP01 receives the control voltage Vpgp; the second terminal of transistor MP01 is coupled to the input terminal IN1 of the differential amplifier.

[0052] The first terminal of transistor MP1 receives the power supply voltage VCC; the second terminal of transistor MP1 is coupled to the first terminal of transistor MP11; the control terminal of transistor MP1 receives the pre-charge starter signal PCWb. The control terminal of transistor MP11 receives the control voltage Vpgp; the second terminal of transistor MP11 is coupled to the input terminal IN1 of the differential amplifier.

[0053] In this embodiment, the pre-charge sub-circuit 410 and the pre-charge sub-circuit 420 can each provide different driving capabilities to pull the input terminal IN1 to the power supply voltage VCC to perform the pre-charge operation. Specifically, the driving capability provided by the pre-charge sub-circuit 410 can be greater than that provided by the pre-charge sub-circuit 420.

[0054] When the precharge sub-circuit 410 performs the precharge operation, transistor MP0 can be turned on according to the precharge initiator signal PCSb. Regardless of changes in the power supply voltage VCC, when the power supply voltage VCC is greater than the reference value, the difference between the power supply voltage VCC and the control voltage Vpgp can remain constant because the control voltage Vpgp changes with the power supply voltage VCC. Therefore, the driving capability provided by the precharge sub-circuit 410 is fixed.

[0055] Similarly, when the precharge sub-circuit 420 performs the precharge operation, transistor MP1 can be turned on according to the precharge initiator signal PCWb. Regardless of changes in the power supply voltage VCC, when the power supply voltage VCC is greater than the reference value, the difference between the power supply voltage VCC and the control voltage Vpgp can remain constant because the control voltage Vpgp changes with the power supply voltage VCC. Therefore, the driving capability provided by the precharge sub-circuit 420 is also fixed.

[0056] Incidentally, in this embodiment, the pre-charge sub-circuits 410 and 420 can perform pre-charge operations simultaneously or in a time-sharing manner, without any fixed limitation. Furthermore, when the power supply voltage VCC is lower than the aforementioned reference value, the sensing amplification device of this embodiment will not operate.

[0057] Please refer to the following: Figure 5 , Figure 5 This is a schematic diagram of a memory according to an embodiment of the present invention. The memory 500 includes one or more memory cells CELL and a sensing amplification device 510. The sensing amplification device 510 includes a differential amplifier 511, a precharge circuit 512, and a data latch 513. The memory cell CELL can be a selected memory cell, whose bit line BL is coupled to the data line DL through a switch constructed by transistor MN2, and then coupled to the input terminal IN1 of the differential amplifier 511 through a switch constructed by transistor MN3. When transistors MN2 and MN3 are turned on according to signals Y and Vsen, respectively, the memory cell CELL provides a data signal Vsa to the input terminal IN1 of the differential amplifier 511 through the bit line BL and the data line DL. The memory cell CELL is controlled by the character line signal WL.

[0058] Furthermore, the pre-charge circuit 512 includes transistors MP0, MP1, MP01, and MP11. Transistors MP0 and MP01 constitute a pre-charge sub-circuit, and transistors MP1 and MP11 constitute another pre-charge sub-circuit. Transistors MP0 and MP01 are controlled by the pre-charge initiator signal PCSb and the control voltage Vpgp, respectively, while transistors MP1 and MP11 are controlled by the pre-charge initiator signal PCWb and the control voltage Vpgp, respectively, and perform a pre-charge operation on the input terminal IN1 based on the power supply voltage VCC.

[0059] Regarding the operational details of the pre-charging circuit 512, and Figure 4 The pre-charge circuit 400 in this embodiment is the same and will not be described in detail here. Similar to pre-charge circuit 400, pre-charge circuit 512 can perform a pre-charge operation on input terminal IN1 independently of changes in the power supply voltage VCC, based on a fixed drive capability. In this way, the voltage boosted on input terminal IN1 during the pre-charge operation can be maintained.

[0060] Furthermore, one end of transistor MND is coupled to input terminal IN1, and the other end of transistor MND is coupled to receive reference voltage VSS. Transistor MND is turned on according to the discharge control signal DisC to cause input terminal IN1 to discharge.

[0061] The differential amplifier 511 includes transistors MP3, MP2, MN4, MPR2, and MNR3. Transistors MN4 and MNR3 form a differential input pair, while transistors MP2 and MPR2 are coupled to form an active load, and transistor MP3 can form a current source.

[0062] Another input terminal IN2 of the differential amplifier 511 receives the reference signal Vra. The differential amplifier 511 is used to amplify the difference between the reference signal Vra and the data signal Vsa to generate the output signal Sout.

[0063] In this embodiment, the sensing amplification device 510 further includes a data latch 513. The data latch 513 includes transistors MP4, MP5, MN5, and MN6, and inverters IV1 and IV2. Transistors MP4, MP5, MN5, and MN6 are connected in series between the power supply voltage VCC and the reference voltage VSS. Transistor MP4 is controlled by the signal SETN, transistors MP5 and MN5 are jointly controlled by the input signal Sout, and transistor MN6 is controlled by the signal SET. The signals SET and SETN are inverted.

[0064] When transistors MP4 and MN6 are turned on, data latch 513 can transmit the output signal Sout to the latch composed of inverters IV1 and IV2 through transistors MP5 and MN5, and obtain sensing data DO.

[0065] Because the precharge circuit 512 can provide a fixed precharge drive capability to perform precharge operation on the input terminal IN1 of the differential amplifier independently of the power supply voltage VCC variation, the memory cell CELL can provide the correct data signal Vsa to the input terminal IN1. Even under conditions of power supply voltage VCC variation, the memory 500 can provide the correct sense data DO and effectively maintain the data sensing rate of the sense amplifier 510.

[0066] It is worth mentioning that the circuit architectures of the differential amplifier 511 and the data latch 513 in this embodiment are merely illustrative examples. In other embodiments of the present invention, differential amplifier circuits and data latch circuits well known to those skilled in the art can be applied to the present invention without specific limitations.

[0067] Furthermore, the storage unit CELL in this embodiment of the invention can be a flash memory unit or other storage units of any form, without any fixed limitations.

[0068] Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram of a memory according to another embodiment of the present invention. The memory 600 includes one or more memory cells CELL, a sense amplification device 610, and a reference memory cell CELLR. The sense amplification device 610 includes a differential amplifier 611, a precharge circuit 6121, a data latch 613, and a precharge circuit 6122. The bit line BL of the memory cell CELL is coupled to the data line DL through a switch constructed by transistor MN2, and then coupled to the input terminal IN1 of the differential amplifier 611 through a switch constructed by transistor MN3. When transistors MN2 and MN3 are turned on according to signals Y and Vsen respectively, the memory cell CELL provides a data signal Vsa to the input terminal IN1 of the differential amplifier 611 through the bit line BL and the data line DL.

[0069] The bit line RBL of the reference memory cell CELLR is coupled to the reference data line RDL through a switch constructed by transistor MNR0, and then coupled to the input terminal IN2 of the differential amplifier 611 through a switch constructed by transistor MNR1. When transistors MNR0 and MNR1 are turned on according to the power supply voltage VCC and the signal Vsen respectively, the reference memory cell CELLR provides the reference signal Vra to the input terminal IN2 of the differential amplifier 611 through the bit line RBL and the reference data line RDL.

[0070] In this embodiment, the differential amplifier 611, pre-charge circuit 6121, and data latch 613 in the sensing amplification device 610 are... Figure 5 The differential amplifier 511, precharge circuit 512, and data latch 513 in the embodiment have the same circuit architecture and the same circuit operation, which will not be described in detail here. Unlike the previous embodiment, the sensing amplification device 610 further includes a precharge circuit 6122 coupled to the input terminal IN2 of the differential amplifier 611. The precharge circuit 6122 includes transistors MPR3, MPR4, MPR5, and MPR6. Transistors MPR3 and MPR4 constitute a precharge sub-circuit, and transistors MPR5 and MPR6 constitute another precharge sub-circuit. Transistors MPR3 and MPR4 are controlled by the precharge initiator signal PCWb and the control voltage Vpgp, respectively, while transistors MPR5 and MPR6 are controlled by the precharge initiator signal PCSb and the control voltage Vpgp, respectively, and perform a precharge operation on the input terminal IN2 based on the power supply voltage VCC.

[0071] When performing a data read operation on the storage cell CELL, the pre-charge circuit 6122 can first perform a pre-charge operation on the input terminal IN2. Details regarding the operation of the pre-charge circuit 6122 are available in [contact information]. Figure 4 The pre-charge circuit 400 in this embodiment is the same and will not be described in detail here. Similar to pre-charge circuit 400, pre-charge circuit 6122 can perform a pre-charge operation on input terminal IN2 independently of changes in the power supply voltage VCC, based on a fixed drive capability. In this way, the voltage boosted on input terminal IN2 during the pre-charge operation can be maintained.

[0072] As explained above, in this embodiment, when the memory 600 performs a read operation on the memory cell CELL, the voltages on the two input terminals IN1 and IN2 of the differential amplifier 611 can be pre-charged to a fixed voltage value through the pre-charge circuits 6121 and 6122 during the pre-charge operation, independent of the change in the power supply voltage VCC. In this way, after the pre-charge operation, the memory cell CELL can provide a correct data signal Vsa to input terminal IN1, and the reference memory cell CELLR can also provide a correct reference signal Vra to input terminal IN2. Accordingly, the sensing amplification device 610 can sense the recorded data of the memory cell CELL in real time and accurately, obtaining correct sensing data DO.

[0073] Incidentally, transistors MND1 and MND2 are coupled to the input terminals IN1 and IN2 and the reference voltage VSS, respectively, and are used to turn on according to the discharge control signal DisC to enable the input terminals IN1 and IN2 to discharge.

[0074] As described above, the control voltage generator in the sensing amplification device of the present invention provides a control voltage that is positively correlated with changes in the power supply voltage, and enables the pre-charge circuit to perform an independent pre-charge operation on the input terminal of the differential amplifier based on a fixed difference between the power supply voltage and the control voltage. In this way, when the power supply voltage changes, the pre-charge circuit can maintain the voltage value at the input terminal of the differential amplifier that was increased during the pre-charge operation. Consequently, the selected storage unit can accurately provide data signals to the input terminal of the differential amplifier, enabling the sensing amplification device to obtain sensing data accurately and in real time.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A sensing amplification device, characterized in that, include: A differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively; A first pre-charging circuit is coupled to the first input terminal and performs a pre-charging action on the first input terminal based on the power supply voltage, according to the pre-charging start signal and the control voltage. as well as A control voltage generator generates the control voltage based on the power supply voltage, wherein the control voltage is positively correlated with the power supply voltage. The control voltage generator includes: A first transistor has a first terminal that receives the power supply voltage, a second terminal that generates the control voltage, a control terminal that receives a first reference voltage, and a turn-on voltage value equal to the reference value. as well as A constant current source is coupled between a second terminal of the first transistor and a reference ground terminal, wherein the reference ground terminal receives the first reference voltage.

2. The sensing amplification device according to claim 1, characterized in that, When the power supply voltage is greater than the reference value, the control voltage generator makes the control voltage proportional to the power supply voltage.

3. The sensing amplification device according to claim 1, characterized in that, The constant current source is a second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is coupled to the reference ground terminal, and a control terminal of the second transistor receives a second reference voltage. The second reference voltage is greater than the first reference voltage.

4. The sensing amplification device according to claim 1, characterized in that, The first pre-charging circuit includes: A first pre-charge sub-circuit, coupled to the first input terminal, pulls the first input terminal up to the power supply voltage based on a first drive capability, according to a first pre-charge initiation sub-signal and the control voltage; and The second pre-charge sub-circuit, coupled to the first input terminal, pulls the first input terminal up to the power supply voltage based on the second driving capability, according to the second pre-charge initiation sub-signal and the control voltage. The first driving capability is greater than the second driving capability.

5. The sensing amplification device according to claim 4, characterized in that, The first pre-charge sub-circuit includes: A second transistor has a first terminal for receiving the power supply voltage, and a control terminal for receiving the first precharge initiator signal; and A third transistor has a first terminal coupled to a second terminal of the second transistor, a control terminal of the third transistor receiving the control voltage, and a second terminal of the third transistor coupled to the first input terminal. The voltage difference between the first terminal and the control terminal of the third transistor is independent of the power supply voltage.

6. The sensing amplification device according to claim 5, characterized in that, The second pre-charge sub-circuit includes: A fourth transistor has a first terminal for receiving the power supply voltage, and a control terminal for receiving the second precharge initiator signal; and A fifth transistor has a first terminal coupled to a second terminal of the fourth transistor, a control terminal of the fifth transistor receiving the control voltage, and a second terminal of the fifth transistor coupled to the first input terminal. The voltage difference between the first terminal and the control terminal of the fifth transistor is independent of the power supply voltage.

7. The sensing amplification device according to claim 1, characterized in that, Including: A second pre-charging circuit, coupled to the second input terminal, performs a pre-charging operation on the second input terminal based on the power supply voltage, the pre-charging start signal, and the control voltage. The second input terminal is used to couple to a reference storage unit, which provides the reference signal.

8. The sensing amplification device according to claim 1, characterized in that, The first input terminal is used to couple to the selected memory cell, and the bit line of the selected memory cell provides the data signal.

9. The sensing amplification device according to claim 1, characterized in that, Including: A data latch, coupled to the output of the differential amplifier, latches the output signal at the output of the differential amplifier to generate sensing data.

10. A memory, characterized in that, include: At least one storage unit; as well as A sensing amplification device, coupled to the at least one memory cell, the sensing amplification device comprising: A differential amplifier has a first input terminal and a second input terminal, wherein the first input terminal is coupled to the at least one memory cell to receive a data signal, and the second input terminal receives a reference signal; A first pre-charging circuit, coupled to the first input terminal, performs a pre-charging operation on the first input terminal based on the power supply voltage, a pre-charging start signal, and a control voltage; and A control voltage generator generates the control voltage based on the power supply voltage, wherein the control voltage is positively correlated with the power supply voltage. The control voltage generator includes: A first transistor has a first terminal receiving the power supply voltage, a second terminal generating the control voltage, a control terminal receiving a first reference voltage, and a turn-on voltage value equal to the reference value; and A constant current source is coupled between a second terminal of the first transistor and a reference ground terminal, wherein the reference ground terminal receives the first reference voltage.

11. The memory according to claim 10, characterized in that, When the power supply voltage is greater than the reference value, the control voltage generator makes the control voltage proportional to the power supply voltage.

12. The memory according to claim 10, characterized in that, The constant current source is a second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is coupled to the reference ground terminal, and a control terminal of the second transistor receives a second reference voltage. The second reference voltage is greater than the first reference voltage.

13. The memory according to claim 10, characterized in that, The first pre-charging circuit includes: A first pre-charge sub-circuit, coupled to the first input terminal, pulls the first input terminal up to the power supply voltage based on a first drive capability, according to a first pre-charge initiation sub-signal and the control voltage; and The second pre-charge sub-circuit, coupled to the first input terminal, pulls the first input terminal up to the power supply voltage based on the second driving capability, according to the second pre-charge initiation sub-signal and the control voltage. The first driving capability is greater than the second driving capability.

14. The memory according to claim 13, characterized in that, The first pre-charge sub-circuit includes: A second transistor has a first terminal for receiving the power supply voltage, and a control terminal for receiving the first precharge initiator signal; and A third transistor has a first terminal coupled to a second terminal of the second transistor, a control terminal of the third transistor receiving the control voltage, and a second terminal of the third transistor coupled to the first input terminal. The voltage difference between the first terminal and the control terminal of the third transistor is independent of the power supply voltage.

15. The memory according to claim 14, characterized in that, The second pre-charge sub-circuit includes: A fourth transistor has a first terminal for receiving the power supply voltage, and a control terminal for receiving the second precharge initiator signal; and A fifth transistor has a first terminal coupled to a second terminal of the fourth transistor, a control terminal of the fifth transistor receiving the control voltage, and a second terminal of the fifth transistor coupled to the first input terminal. The voltage difference between the first terminal and the control terminal of the fifth transistor is independent of the power supply voltage.

16. The memory according to claim 10, characterized in that, Including: A reference storage unit, coupled to the second input terminal, is used to provide the reference signal. The sensing amplification device further includes The second pre-charging circuit is coupled to the second input terminal and performs a pre-charging action on the second input terminal based on the power supply voltage, the pre-charging start signal, and the control voltage.

17. The memory according to claim 10, characterized in that, The sensing amplification device further includes: A data latch, coupled to the output of the differential amplifier, latches the output signal at the output of the differential amplifier to generate sensing data.

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