storage device

Abstract

Embodiments provide a storage device capable of reducing misreads. The storage device of the embodiments includes a first storage unit, a second storage unit, a first circuit that supplies a write current to the first storage unit and the second storage unit, a first wiring connected to the first circuit, a first plug that electrically connects the first storage unit and the first wiring, and a second plug that electrically connects the second storage unit and the first wiring. The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug. The resistance value of the first plug is higher than the resistance value of the second plug.

Description

[0001] This application enjoys priority to Japanese Patent Application No. 2022-044000 (filed March 18, 2022) and U.S. Patent Application No. 17 / 843084 (filed June 17, 2022). This application incorporates the entire contents of the basic applications by reference. Technical Field

[0002] Embodiments of the present invention relate to storage devices. Background Technology

[0003] Storage devices that use variable resistance elements as storage elements are known. For example, magnetic storage devices (MRAM: Magnetoresistive Random Access Memory) that use magnetoresistive elements as variable resistance elements are known. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a storage device that can reduce false reads.

[0005] The storage device according to the embodiment includes: a first storage cell; a second storage cell; a first circuit that supplies write current to the first storage cell and the second storage cell; a first wiring connected to the first circuit; a first plug that electrically connects the first storage cell and the first wiring; and a second plug that electrically connects the second storage cell and the first wiring. The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug. The resistance value of the first plug is higher than the resistance value of the second plug. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating the configuration of the storage device according to the first embodiment.

[0007] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the memory device according to the first embodiment.

[0008] Figure 3 This is a plan view showing an example of the planar structure of the memory cell array included in the memory device according to the first embodiment.

[0009] Figure 4 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the first embodiment.

[0010] Figure 5This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the first embodiment.

[0011] Figure 6 This is a perspective view of a portion of the memory cell array included in the memory device according to the first embodiment.

[0012] Figure 7 This is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive element included in the storage device according to the first embodiment.

[0013] Figure 8 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the first embodiment.

[0014] Figure 9 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the first embodiment.

[0015] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the first embodiment.

[0016] Figure 11 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the first embodiment.

[0017] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the first embodiment.

[0018] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the first embodiment.

[0019] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the first embodiment.

[0020] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the first variation of the first embodiment.

[0021] Figure 16 This is a flowchart illustrating an example of a method for manufacturing a storage device according to a second variation of the first embodiment.

[0022] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the second variation of the first embodiment.

[0023] Figure 18This is a cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the storage device according to the second variation of the first embodiment.

[0024] Figure 19 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the third variation of the first embodiment.

[0025] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fourth variation of the first embodiment.

[0026] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the second embodiment.

[0027] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to a variation of the second embodiment.

[0028] Figure 23 This is a plan view showing an example of the planar structure of the memory cell array included in the memory device according to the third embodiment.

[0029] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the third embodiment.

[0030] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the third embodiment.

[0031] Figure 26 This is a perspective view of a portion of the memory cell array included in the memory device according to the third embodiment.

[0032] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fourth embodiment.

[0033] Figure 28 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fifth embodiment.

[0034] Figure 29 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fifth embodiment.

[0035] Figure 30This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the sixth embodiment.

[0036] Figure 31 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the sixth embodiment.

[0037] Label Explanation

[0038] 1. Storage device; 10. Storage cell array; 11. Input / output circuit; 12. Control circuit; 13. Decoding circuit; 14. Row selection circuit; 15. Column selection circuit; 16. Voltage generation circuit; 17. Write circuit; 18. Read circuit; 19. Write driver; 30. Semiconductor substrate; 31. Insulating layer; 32, 33a, 33b, 33b1-33b4 conductors; 34, 35. Components; 36, 37a, 37b, 38. Conductors; 39. Ferromagnetic material; 40. Nonmagnetic material; 41. Ferromagnetic material; 42. Insulating layer; 43, 44. Resist mask; CP1, CP2 contact plugs. Detailed Implementation

[0039] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having substantially the same function and structure are labeled with the same reference numeral. When elements having the same structure are specifically distinguished from each other, sometimes different letters or numbers are appended to the end of the same reference numeral.

[0040] 1. First Implementation Method

[0041] The storage device according to the first embodiment will be described. The storage device according to the first embodiment is, for example, a magnetic storage device that uses an element with a magnetoresistance effect (also called an MTJ element or magnetoresistance effect element) as a variable resistance element through a magnetic tunnel junction (MTJ). In this embodiment and the embodiments and modifications described later, the case in which an MTJ element is used as a variable resistance element will be described, and it will be described as a magnetoresistance effect element MTJ in the description.

[0042] 1.1 Composition

[0043] 1.1.1 Composition of storage devices

[0044] use Figure 1 The configuration of the storage device according to the first embodiment will be described. Figure 1This is a block diagram showing the configuration of a storage device. The storage device 1 includes a storage cell array 10, an input / output circuit 11, a control circuit 12, a decoding circuit 13, a row selection circuit 14, a column selection circuit 15, a voltage generation circuit 16, a write circuit 17, and a read circuit 18.

[0045] The cell array 10 is a non-volatile memory. The cell array 10 includes multiple cell MCs, each associated with a group of rows and columns. The cell MCs store data in a non-volatile manner. For example, cell MCs in the same row are connected to the same word line WL. Cell MCs in the same column are connected to the same bit line BL.

[0046] Input / output circuit 11 is a circuit for transmitting and receiving data. Input / output circuit 11 receives control signals CNT, commands CMD, address ADD, and data (write data) DAT from the external storage device 1. Input / output circuit 11 sends control signals CNT and commands CMD to control circuit 12. Input / output circuit 11 sends address ADD to decoding circuit 13. Input / output circuit 11 sends data (write data) DAT to write circuit 17. Input / output circuit 11 receives data (read data) DAT from read circuit 18. Input / output circuit 11 sends data (read data) DAT to the external storage device 1.

[0047] The control circuit 12 is a circuit that controls the operation of the storage device 1 as a whole. Based on the control signal CNT and the command CMD, the control circuit 12 controls the operation of the input / output circuit 11, the decoding circuit 13, the row selection circuit 14, the column selection circuit 15, the voltage generation circuit 16, the write circuit 17, and the read circuit 18.

[0048] Decoding circuit 13 is a circuit that decodes address ADD. Decoding circuit 13 receives address ADD from input / output circuit 11. Decoding circuit 13 decodes address ADD. Decoding circuit 13 sends the decoding result of address ADD to row selection circuit 14 and column selection circuit 15. Address ADD includes row address and column address.

[0049] Row selection circuit 14 is a circuit that selects the word line WL corresponding to the row of memory cell array 10. Row selection circuit 14 is connected to memory cell array 10 via word line WL. Row selection circuit 14 receives the decoding result (row address) of address ADD from decoding circuit 13. Based on the decoding result of address ADD, row selection circuit 14 selects the word line WL corresponding to the row.

[0050] Column selection circuit 15 is a circuit that selects the bit line BL corresponding to the column of memory cell array 10. Column selection circuit 15 is connected to memory cell array 10 via bit line BL. Column selection circuit 15 receives the decoding result (column address) of address ADD from decoding circuit 13. Based on the decoding result of address ADD, column selection circuit 15 selects the bit line BL corresponding to the column.

[0051] The voltage generation circuit 16 is a circuit that uses a power supply voltage applied from outside the storage device 1 to generate voltages for various operations of the storage cell array 10. For example, the voltage generation circuit 16 generates a voltage used in the write operation (hereinafter also referred to as "write voltage"). The voltage generation circuit 16 supplies the write voltage to the write circuit 17. In addition, the voltage generation circuit 16 generates a voltage used in the read operation (hereinafter also referred to as "read voltage"). The voltage generation circuit 16 supplies the read voltage to the read circuit 18.

[0052] The write circuit 17 is a circuit that writes data to the memory cell MC. The write circuit 17 includes a write driver 19. The write circuit 17 receives write data DAT from the input / output circuit 11. A write voltage is applied to the write circuit 17 from the voltage generation circuit 16. The write driver 19 is, for example, a constant current driver circuit. The write driver 19 supplies current based on the write voltage (the current used in the write operation; hereinafter also referred to as "write current") to the row selection circuit 14 and the column selection circuit 15. The row selection circuit 14 and the column selection circuit 15 supply write current to the memory cell array 10 via the selected word line WL and bit line BL.

[0053] The readout circuit 18 is a circuit that reads data from the memory cell MC. The readout circuit 18 includes a sense amplifier (not shown). A readout voltage is applied to the readout circuit 18 from the voltage generation circuit 16. The readout circuit 18 supplies the readout voltage to the column selection circuit 15. The column selection circuit 15 supplies the readout voltage to the memory cell array 10 via a selected bit line BL. The readout circuit 18 receives the voltage of the bit line BL from the column selection circuit 15. Based on the voltage of the bit line BL, the sense amplifier infers the data stored in the memory cell MC. The readout circuit 18 sends the inferred data as readout data DAT to the input / output circuit 11.

[0054] 1.1.2 Circuit configuration of memory cell array

[0055] use Figure 2 The circuit configuration of the memory cell array 10 will be described. Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10. Figure 2 In this context, the memory cell MC, word line WL, and bit line BL are represented by labels that include indexes ("<>").

[0056] like Figure 2 As shown, the memory cells MC are configured in a matrix within the memory cell array 10, and are associated with one of the multiple word lines WL (WL<0>, WL<1>, ..., WL<M>) and one of the multiple bit lines BL (BL<0>, BL<1>, ..., BL<N>) (M and N are arbitrary integers). That is, the memory cells MC<i,j> (0≤i≤M, 0≤j≤N) are connected between the word line WL and the bit line BL<j>. The memory cells MC<i,j> include a switching element SEL<i,j> and a magnetoresistive element MTJ<i,j> connected in series.

[0057] The switching element SEL functions as a selector, which controls the current supply to the corresponding magnetoresistive element MTJ during data writing and reading.

[0058] The switching element SEL in this embodiment will be described with two terminals. When the voltage applied between the two terminals is less than a first threshold, the switching element SEL is in a high-resistance state, for example, an electrically non-conducting state (off state). When the voltage applied between the two terminals rises to above the first threshold, the switching element SEL becomes a low-resistance state, for example, an electrically conducting state (on state). When the voltage applied between the two terminals of the low-resistance switching element SEL decreases to below a second threshold, the switching element SEL becomes a high-resistance state. The switching element SEL also has the same function as the switching function between high-resistance and low-resistance states based on the magnitude of the voltage applied in the first direction in the second direction opposite to the first direction. That is, the switching element SEL is a bidirectional switching element. By turning the switching element SEL on or off, the presence or absence of current supply to the MTJ element MTJ connected to the switching element SEL can be controlled, i.e., the selection or non-selection of the MTJ element MTJ.

[0059] In this embodiment, a switching element with the following characteristics can be used: at a certain voltage, the resistance value decreases sharply, and with this, the applied voltage decreases sharply and the current increases (snapback).

[0060] Alternatively, a switching element formed substantially of a composition containing silicon (Si), oxygen (O) and predetermined elements selected from arsenic (As), phosphorus (P), antimony (Sb), sulfur (S), selenium (Se) and tellurium (Te) (e.g., silicon oxide (SiOx) containing the aforementioned predetermined elements) can also be used.

[0061] Furthermore, descriptions containing the word "substantial" (e.g., substantially formed) and similar descriptions imply that substantially formed materials (compositions) may contain undesirable impurities.

[0062] The magnetoresistive element (MTJ) can switch between low and high resistance states by controlling the supplied current through a switching element (SEL). The MTJ functions as a storage element, capable of writing data through changes in its resistance state, and can store and retrieve the written data in a non-volatile manner.

[0063] 1.1.3 Construction of Storage Cell Array

[0064] An example of the construction of the memory cell array 10 will be described. Furthermore, in the figures referred to below, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate used in the formation of the memory device 1.

[0065] (Plane Construction)

[0066] use Figure 3 The planar structure of the storage cell array 10 will be described. Figure 3 This is a plan view showing an example of the planar structure of the memory cell array 10. Figure 3 The word lines WL between multiple memory cells MC and row select circuit 14, and the bit lines BL between multiple memory cells MC and column select circuit 15 are shown within the memory cell array 10. Furthermore, in Figure 3 The word lines WL<5> to WL<M>, bit lines BL<5> to BL<N>, and the multiple memory cells MC corresponding to these lines are omitted.

[0067] Furthermore, the planar structure referred to here is the following structure (single-layer structure), which is as follows: Figure 6 As in the previous construction, in the Z direction, for a memory cell MC, a memory cell MC can be selected by a combination of a word line WL and a bit line BL. Subsequent descriptions of planar constructions will also use the same meaning.

[0068] like Figure 3 As shown, in the memory cell array 10, for example, the memory cell MC is positioned above the word line WL. The bit line BL is positioned above the memory cell MC.

[0069] Each word line WL is connected to the row selection circuit 14 and a plurality of memory cells MC arranged in the X direction. The row selection circuit 14 supplies write current to the memory cells MC via the word lines WL. Hereinafter, the regions containing the plurality of memory cells MC connected to the word lines WL<0> to WL<4> are respectively referred to as regions R0w to R4w. Region R0w contains memory cells MC<0,0> to MC<0,N>. Region R1w contains memory cells MC<1,0> to MC<1,N>. Region R2w contains memory cells MC<2,0> to MC<2,N>. Region R3w contains memory cells MC<3,0> to MC<3,N>. Region R4w contains memory cells MC<4,0> to MC<4,N>.

[0070] Regions R0w to R4w are arranged in the order of region R4w, region R3w, region R2w, region R1w, and region R0w, starting from the column select circuit 15 side. The closer a memory cell MC is to the column select circuit 15 (e.g., region R4w, also referred to as "the cell closest to the column select circuit 15"), the shorter the bit line BL between the memory cell MC and the column select circuit 15. In other words, the farther a memory cell MC is from the column select circuit 15 (e.g., region R0w, also referred to as "the cell farthest from the column select circuit 15"), the longer the bit line BL between the memory cell MC and the column select circuit 15. Therefore, the closer a cell is to the column select circuit 15, the lower the resistance value of the bit line BL between the memory cell MC and the column select circuit 15.

[0071] Each bit line BL is connected to the column select circuit 15 and a plurality of memory cells MC arranged in the Y direction. The column select circuit 15 supplies write current to the memory cells MC via the bit lines BL. Hereinafter, the regions containing the plurality of memory cells MC connected to the bit lines BL<0> to BL<4> are respectively referred to as regions R0b to R4b. Region R0b contains memory cells MC<0,0> to MC<M,0>. Region R1b contains memory cells MC<0,1> to MC<M,1>. Region R2b contains memory cells MC<0,2> to MC<M,2>. Region R3b contains memory cells MC<0,3> to MC<M,3>. Region R4b contains memory cells MC<0,4> to MC<M,4>.

[0072] Regions R0b to R4b are arranged in the order of region R0b, region R1b, region R2b, region R3b, and region R4b, starting from the row selection circuit 14 side. The closer a memory cell MC is to the row selection circuit 14 (e.g., region R0b, also referred to as "the cell closest to the row selection circuit 14"), the shorter the word line WL between the memory cell MC and the row selection circuit 14. In other words, the farther a memory cell MC is from the row selection circuit 14 (e.g., region R4b, also referred to as "the cell farther from the row selection circuit 14"), the longer the word line WL between the memory cell MC and the row selection circuit 14. Therefore, the closer a cell is to the row selection circuit 14, the lower the resistance value of the word line WL between the memory cell MC and the row selection circuit 14.

[0073] (Cross-section construction)

[0074] use Figures 4-6 The cross-sectional structure of the memory cell array 10 will be described. Figure 4 It is along Figure 3 A sectional view along line II. Figure 5 It is along Figure 3 A sectional view along line II-II. Figure 6 This is a three-dimensional view of a portion of the storage cell array 10. Furthermore, in Figures 4-6 The insulating layer is omitted in the example shown.

[0075] like Figures 4-6 As shown, the memory cell array 10 is disposed above the semiconductor substrate 30.

[0076] Above the semiconductor substrate 30, for example, separated by an insulating layer 31, a plurality of conductors 32 are disposed. The plurality of conductors 32 are made of a conductive material and function as word lines WL. The plurality of conductors 32 are arranged, for example, in the Y direction and extend in the X direction. Furthermore, in Figure 6 The semiconductor substrate 30 and the insulating layer 31 are omitted.

[0077] Multiple contact plugs CP1 (hereinafter also referred to as "first electrode" or "upper electrode") are disposed on the upper surface of a conductor 32. The contact plugs CP1 electrically connect the storage cell MC and the conductor 32. The multiple contact plugs CP1 disposed on the upper surface of the conductor 32 are arranged, for example, in the X direction.

[0078] Contact plug CP1 in region R0b includes conductor 33a. Contact plug CP1 in regions R1b to R4b each includes conductors 33a and 33b. Conductors 33a and 33b are made of conductive materials. Conductor 33b contains a material with a lower resistivity than conductor 33a. Conductors 33a and 33b may, for example, contain carbon, boron nitride (BN), metal oxides, metal nitrides, polysilicon (poly-Si), tungsten, titanium, aluminum, copper, etc. For example, two materials may be selected from these materials, wherein conductor 33a contains a material with a relatively high resistivity (hereinafter also referred to as "high-resistivity material"), and conductor 33b contains a material with a relatively low resistivity (hereinafter also referred to as "low-resistivity material"). Furthermore, conductors 33a and 33b are not limited to these materials as long as the resistivity of conductor 33a is higher than that of conductor 33b.

[0079] The high-resistance material used in conductor 33a and the low-resistance material used in conductor 33b can be selected, for example, as follows: If at least one of copper and aluminum is selected as the low-resistance material, at least one of tungsten, tungsten nitride (WN), titanium, titanium nitride (TiN), carbon, and polycrystalline silicon can be selected as the high-resistance material. If at least one of tungsten, tungsten nitride, titanium, and titanium nitride is selected as the low-resistance material, at least one of carbon and polycrystalline silicon can be selected as the high-resistance material. If carbon is selected as the low-resistance material, polycrystalline silicon can be selected as the high-resistance material.

[0080] The diameters of the contact plugs CP1 in regions R0b to R4b are approximately the same. Furthermore, the shape of the cross-section (XY section) of the contact plug CP1 is not limited to a circle. For example, the cross-section of the contact plug CP1 can be either elliptical or rectangular. Regardless of the shape of the cross-section of the contact plug CP1, the contact area (contact area) between the contact plug CP1 and the word line WL in regions R0b to R4b is approximately the same.

[0081] The closer the contact plug CP1 is to the horizontal selection circuit 14, the lower the ratio of conductors 33b included in each of the contact plugs CP1 in regions R1b to R4b. The closer the contact plug CP1 is to the horizontal selection circuit 14, the lower the height of the conductors 33b included in each of the contact plugs CP1 in regions R1b to R4b. Therefore, the closer the contact plug CP1 is to the horizontal selection circuit 14, the higher its resistance value.

[0082] The length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R0b is shorter than the length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R1b. The length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R1b is shorter than the length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R2b. The same applies to the following.

[0083] Conductor 33b is disposed on conductor 33a. Alternatively, conductor 33a may also be disposed on conductor 33b. Furthermore, the contact plugs CP1 of each region R1b to R4b may also be composed of three or more conductors with different resistivities.

[0084] Conductors 33a and 33b may also contain two or more materials. For example, if conductors 33a and 33b each contain two materials A and B with different resistance values, the ratio of material A to material B in conductor 33a and the ratio of material A to material B in conductor 33b may also be different. Consequently, the resistivity of conductor 33a and the resistivity of conductor 33b may also be different.

[0085] A component 34, which functions as a switching element SEL, is provided on the upper surface of the contact plug CP1.

[0086] A component 35, which functions as a magnetoresistive element MTJ, is disposed on the upper surface of component 34. The details of the configuration of component 35 will be described later.

[0087] A conductor 36 is disposed on the upper surface of the component 35. The conductor 36 is made of a conductive material and functions as a hard mask when processing the component 35.

[0088] A contact plug CP2 (hereinafter also referred to as the "second electrode" or "lower electrode") is disposed on the upper surface of the conductor 36. The contact plug CP2 electrically connects the memory cell MC and the conductor 38 described later via the conductor 36. The contact plug CP2 includes a conductor 37a. The conductor 37a is made of a conductive material.

[0089] Conductors 38 are provided on the upper surface of the contact plug CP2. Multiple conductors 38 are made of conductive material and function as bit lines BL. The multiple conductors 38 are arranged, for example, in the X direction and each extends in the Y direction. For example, multiple contact plugs CP2 arranged in the Y direction are connected to one conductor 38.

[0090] like Figure 6 As shown, a storage unit MC is provided at the intersection of conductor 32 and conductor 38.

[0091] Furthermore, components 34 and 35 may not be connected to each other. For example, components 34 and 35 may be electrically connected via a conductor (not shown). Additionally, using... Figures 4-6 The case where element 35 and conductor 36 are disposed on element 34 has been described, but it is not a limitation. For example, element 34 may also be disposed on element 35 and conductor 36.

[0092] As described above, the memory cell array 10 has a structure in which memory cells MC are disposed between the corresponding word line WL and bit line BL.

[0093] use Figures 3-6 The text describes a configuration where a memory cell MC can be selected using a combination of a word line WL and a bit line BL (referred to as a single-layer configuration), but is not limited to this. For example, any array configuration, such as an array configuration having multiple such configurations stacked in the Z direction, can be applied.

[0094] exist Figure 6 In the example described below, the configuration in which the diameters of CP1 and CP2 are smaller than the diameter of MC is illustrated, but this configuration is not the only one that can be described. The same effect can be achieved even when the diameters of CP1 and CP2 are approximately the same as the diameter of MC.

[0095] 1.1.4 Construction of Magnetoresistive Elements

[0096] use Figure 7 The construction of the magnetoresistive element MTJ is explained. Figure 7 This is a cross-sectional view showing an example of the cross-sectional structure of a magnetoresistive element MTJ.

[0097] like Figure 7 As shown, element 35 (magnetoresistive element MTJ) includes a ferromagnetic material 39 that functions as a reference layer RL, a nonmagnetic material 40 that functions as a tunnel barrier layer TB, and a ferromagnetic material 41 that functions as a storage layer SL.

[0098] For example, a magnetoresistive element (MTJ) consists of multiple materials stacked in the order of ferromagnetic material 39, non-magnetic material 40, and ferromagnetic material 41, from the word line WL side towards the bit line BL side (in the Z-axis direction). The MTJ functions as a perpendicularly magnetized type, where the magnetization directions of the magnetic materials constituting the MTJ are perpendicular to the film surface.

[0099] The ferromagnetic material 39 is ferromagnetic and has an easy magnetization axis direction perpendicular to the film surface. The ferromagnetic material 39 has a magnetization direction toward either the bit line BL side or the word line WL side. The ferromagnetic material 39 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB). The magnetization direction of the ferromagnetic material 39 is fixed. Figure 7 In the example, the orientation is opposite to the surface where the non-magnetic body 40 is located. Furthermore, "the magnetization direction is fixed" means that the magnetization direction will not change according to the magnitude of the current (spin torque) that can reverse the magnetization direction of the ferromagnetic body 41.

[0100] The non-magnetic material 40 is a non-magnetic insulating film, such as containing magnesium oxide (MgO). The non-magnetic material 40 is disposed between the ferromagnetic material 39 and the ferromagnetic material 41. Thus, the ferromagnetic material 39, the non-magnetic material 40, and the ferromagnetic material 41 constitute a magnetic tunnel junction.

[0101] Ferromagnetic material 41 is ferromagnetic and has an easy axis of magnetization in a direction perpendicular to the film surface. Ferromagnetic material 41 has a magnetization direction toward either the bit line BL side or the word line WL side. Ferromagnetic material 41 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB) and may have a body-centered cubic (bcc) crystal structure.

[0102] Storage device 1, for example, directly injects a write current into a magnetoresistive element MTJ configured as described above. This write current injects spin torque into the storage layer SL and the reference layer RL, thereby controlling the magnetization directions of the storage layer SL and the reference layer RL. This writing method is also known as spin injection writing. The magnetoresistive element MTJ can achieve either a low-resistance state or a high-resistance state by determining whether the relative magnetization directions of the storage layer SL and the reference layer RL are parallel or antiparallel.

[0103] When along the magnetoresistive element MTJ Figure 7 When a write current Iw0 flows in the direction of arrow A1 (i.e., from the storage layer SL towards the reference layer RL), the magnetization directions of the storage layer SL and the reference layer RL become parallel. In this parallel state, the resistance of the magnetoresistive element MTJ is at its lowest, and the magnetoresistive element MTJ is set to a low-resistance state. This low-resistance state is called the "P (Parallel) state," and is, for example, defined as the state of data "0".

[0104] Additionally, when along the magnetoresistive effect element MTJ Figure 7 When a write current Iw1, greater than the write current Iw0, flows in the direction of arrow A2 (i.e., from the reference layer RL towards the storage layer SL), the relative magnetization directions of the storage layer SL and the reference layer RL become antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ reaches its maximum, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state," and is, for example, defined as the state of data "1".

[0105] Furthermore, the way data "1" and data "0" are specified is not limited to the examples above. For example, the P state can also be specified as data "1" and the AP state as data "0".

[0106] 1.2 Manufacturing method of storage device

[0107] use Figures 8 to 14 The manufacturing method of the storage device 1 according to the first embodiment will be described. Figure 8 This is a flowchart illustrating an example of a method for manufacturing the contact plug CP1 in the storage device 1. Figures 9-14 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of storage device 1. In the following, to form... Figure 4 The following explanation will be based on the case of contact plug CP1 in regions R0b to R2b. Figures 9-14 The middle shows Figure 4 The contact plug CP1 in regions R0b to R2b. Furthermore, in... Figures 9-14 In the original text, semiconductor substrate 30, insulating layer 31, element 34, element 35, conductor 36, contact plug CP2, and conductor 38 are omitted.

[0108] like Figure 8 As shown, in the manufacturing process of the contact plug CP1, processes S100 to S105 are performed sequentially. The following will refer to... Figure 8 An example of the manufacturing process of the contact plug CP1 will be described.

[0109] First, such as Figure 9 As shown, a conductor 33a is formed that penetrates the insulating layer 42 and whose bottom surface reaches the conductor 32 (S100). More specifically, firstly, a hole is formed that penetrates the insulating layer 42 and whose bottom surface reaches the conductor 32. The hole corresponds to the contact plug CP1. Next, the conductor 33a is formed into a film by filling the hole. Then, the conductor 33a on the insulating layer 42 is removed by CMP (Chemical Mechanical Polishing) or the like.

[0110] Next, as Figure 10 As shown, a photoresist mask 43 for processing the conductor 33a in region R2b is formed on the conductor 33a and the insulating layer 42 by photolithography (S101). An opening of the photoresist mask 43 is provided in region R2b. Therefore, the upper surface of the conductor 33a in region R2b is exposed (not covered by the photoresist mask 43). The upper surfaces of the conductors 33a in regions R0b and R1b are covered by the photoresist mask 43.

[0111] Next, as Figure 11 As shown, the conductor 33a is processed, for example, by RIE (reactive ion etching) (S102). In S102, the upper part of the conductor 33a in region R2b is removed. The upper surface of the conductor 33a in region R2b is located lower than the upper surface of the insulating layer 42. Alternatively, the conductor 33a can also be processed by wet etching. After processing the conductor 33a, the resist mask 43 is peeled off.

[0112] Next, as Figure 12 As shown, a photoresist mask 44 for processing the conductor 33a in region R2b and the conductor 33a in region R1b is formed on the conductor 33a and the insulating layer 42 by photolithography (S103). Openings of the photoresist mask 44 are provided in regions R1b and R2b. Therefore, the upper surfaces of the conductors 33a in regions R1b and R2b are exposed (not covered by the photoresist mask 44). The upper surface of the conductor 33a in region R0b is covered by the photoresist mask 44.

[0113] Next, as Figure 13 As shown, conductor 33a is processed, for example, by RIE (S104). In S104, the upper portions of conductor 33a in region R2b and conductor 33a in region R1b are removed. The upper surface of conductor 33a in region R1b is located lower than the upper surface of insulating layer 42. The upper surface of conductor 33a in region R2b is located lower than the upper surface of conductor 33a in region R1b. That is, through S102 and S104, conductor 33a in region R2b is removed more deeply than conductor 33a in region R1b. Alternatively, conductor 33a can also be processed by wet etching. After processing conductor 33a, resist mask 44 is peeled off.

[0114] Next, as Figure 14As shown, conductors 33b are formed on conductors 33a in region R2b and conductors 33a in region R1b (S105). More specifically, conductors 33b are formed into a film by filling the region where conductors 33a were removed in S102 and S104. Then, conductors 33b on insulating layer 42 are removed by CMP or the like.

[0115] Furthermore, generally speaking, materials with higher resistivity tend to have better affinity for RIE than materials with lower resistivity. Therefore, it is preferable that conductor 33a is disposed below conductor 33b.

[0116] With k bit lines BL (k being an integer greater than or equal to 1), photolithography and RIE are performed (k-1) times to change the ratio of the conductor 33b.

[0117] The contact plug CP1 is formed through the manufacturing processes described above. Furthermore, the manufacturing processes described above are merely an example and are not limited to this. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or combined. Additionally, the manufacturing processes may be interchanged to the extent possible.

[0118] 1.3 Effects of this implementation method

[0119] According to the first embodiment, misreading can be reduced. This effect will be explained below.

[0120] As described above, the closer a cell is to the row selection circuit 14, the lower the resistance value of the word line WL between the memory cell MC and the row selection circuit 14. Assume that the resistance values ​​of the multiple contact plugs CP1 connected to the word line WL are the same. In this case, the resistance value of the wiring path (hereinafter also referred to as "row selection circuit-cell wiring path") formed by the word line WL from the row selection circuit 14 to the contact plugs CP1 varies depending on the length of the word line WL from the row selection circuit 14 to the contact plugs CP1. Depending on the resistance value of the row selection circuit-cell wiring path, the time from the start of the write driver 19's operation to the time when element 34 (switching element SEL) of the memory cell MC becomes on varies. Therefore, the length of the time (hereinafter also referred to as "current supply time") during which the write driver 19 supplies write current to the memory cell MC varies depending on the length of the word line WL.

[0121] Cells closer to the row selection circuit 14 have a longer current supply time, while cells farther away from the row selection circuit 14 have a shorter current supply time. In memory cells MC with shorter current supply times, i.e., cells farther from the row selection circuit 14, write failures may sometimes occur due to insufficient current supply time. On the other hand, in memory cells MC with longer current supply times, i.e., cells closer to the row selection circuit 14, damage to the magnetoresistive element MTJ may sometimes occur due to excessive current supply time.

[0122] Therefore, in this embodiment, the resistance value of the contact plug CP1 is changed according to the length of the word line WL from the row selection circuit 14 to the contact plug CP1. In other words, the resistance value of the contact plug CP1 varies depending on the configuration of the row selection circuit 14 and the memory cell MC.

[0123] More specifically, the contact plug CP1 in region R0b includes a conductor 33a. The contact plug CP1 in regions R1b to R4b each includes a conductor 33a and a conductor 33b with a lower resistivity than the conductor 33a. The closer the contact plug CP1 is to the row selection circuit 14, the lower the ratio of conductors 33b included in the contact plug CP1. Therefore, the closer the contact plug CP1 is to the row selection circuit 14, the higher its resistance value. Thus, in regions closer to the row selection circuit 14, compared to more distant regions, the resistance value of the word line WL is lower, and the resistance value of the contact plug CP1 is higher. Conversely, in regions farther from the row selection circuit 14, compared to more nearby regions, the resistance value of the word line WL is higher, and the resistance value of the contact plug CP1 is lower. In this way, by combining the resistance values ​​of the word line WL and the contact plug CP1, the variation in the resistance value of the row selection circuit-cell wiring path caused by the length of the word line WL can be suppressed. This reduces the likelihood of data misreading.

[0124] 1.4 Example of the first variation

[0125] The storage device according to the first variation of the first embodiment will be described. In the storage device 1 according to the first variation of the first embodiment, the method of distributing the ratio of the conductors 33b included in the contact plug CP1 is different from that in the first embodiment. In the following description, the configuration that is the same as that in the first embodiment will be omitted, and the configuration that is different from that in the first embodiment will be described mainly.

[0126] 1.4.1 Construction of Storage Cell Array

[0127] The construction of the storage cell array 10 is the same as that in the first embodiment.

[0128] use Figure 15The cross-sectional structure of the memory cell array 10 will be described. Figure 15 It is along Figure 3 A sectional view along line II. Furthermore, in Figure 15 The insulating layer is omitted in the example shown.

[0129] like Figure 15 As shown, the diameters of the contact plugs CP1 in regions R0b to R4b are approximately the same. Furthermore, the cross-sectional shape of the contact plugs CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plugs CP1, the contact area between the contact plugs CP1 in regions R0b to R4b and the word line WL is approximately the same.

[0130] Regions R1b to R4b are divided into group G0, which includes two adjacent regions R1b and R2b, and group G1, which includes two adjacent regions R3b and R4b. The ratio of conductors 33b included in the contact plugs CP1 of regions R1b and R2b is the same. The ratio of conductors 33b included in the contact plugs CP1 of regions R3b and R4b is the same. The ratio of conductors 33b included in the contact plugs CP1 of regions R1b and R2b is lower than that of the contact plugs CP1 of regions R3b and R4b. Thus, the closer the contact plugs CP1 of a group are to the row selection circuit 14, the lower the ratio of conductors 33b included in the contact plugs CP1 of groups G0 and G1. The closer the contact plugs CP1 of a group are to the row selection circuit 14, the lower the height of the conductors 33b included in the contact plugs CP1 of groups G0 and G1. Therefore, the closer the contact plug CP1 is to the group of rows selected by the row selection circuit 14, the higher its resistance value. Furthermore, using... Figure 15 The text describes the scenario where each group comprises two adjacent regions, but is not limited to this. For example, each group may also comprise three or more adjacent regions. Furthermore, the number of regions included in each group may vary.

[0131] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

[0132] 1.4.2 Effects of this variation

[0133] According to this modified example, the same effect as the first embodiment is achieved.

[0134] Furthermore, according to this modified example, the ratio of the conductors 33b included in the contact plug CP1 varies depending on the group. Therefore, the ratio of the conductors 33b included in the contact plug CP1 can be changed without altering the ratios of the conductors 33b in each region R1b to R4b. Consequently, compared to the case where the ratio of the conductors 33b included in the contact plug CP1 is changed individually, the number of contact plugs CP1 with different conductor 33b ratios is reduced. Therefore, the number of photolithography and RIE repetitions for changing the conductor 33b ratio can be reduced. As a result, process costs can be reduced.

[0135] 1.5 Second Variation

[0136] The storage device according to the second variation of the first embodiment will be described. In the storage device 1 according to the second variation of the first embodiment, the materials of the conductors 33a and 33b included in the contact plug CP1 are different from those in the first embodiment. In the following description, the configurations that are the same as those in the first embodiment will be omitted, and the configurations that are different from those in the first embodiment will be described in detail.

[0137] 1.5.1 Construction of Storage Cell Array

[0138] The planar and cross-sectional structures of the storage cell array 10 are the same as those in the first embodiment.

[0139] exist Figure 4 In this circuit, conductors 33a and 33b are, for example, n-type or p-type semiconductors. Conductors 33a and 33b may contain at least one of silicon and germanium. Conductors 33a and 33b contain impurities (dopants). Impurities may include, for example, boron, phosphorus, arsenic, and antimony. The concentration of impurities in conductor 33b is higher than that in conductor 33a. That is, the resistivity of conductor 33b is lower than that of conductor 33a. Therefore, the closer the contact plug CP1 is to the row selection circuit 14, the higher its resistance value.

[0140] 1.5.2 Manufacturing method of storage device

[0141] use Figures 16-18 The manufacturing method of the storage device 1 according to the second variation of the first embodiment will be described. Figure 16 This is a flowchart illustrating an example of a method for manufacturing the contact plug CP1 in the storage device 1. Figure 17 and Figure 18 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 1. In the manufacturing method of the contact plug CP1 in the storage device 1 according to the second variation of the first embodiment, the first embodiment... Figure 8 S102 and S104 are replaced by S106 and S107. Furthermore, in the first embodiment... Figure 8S105 is discarded. S100, S101, and S103 are the same as in the first embodiment. Hereinafter, we will focus on S106 and S107.

[0142] The following is for reference only. Figure 16 An example of the manufacturing process for the contact plug CP1 is illustrated.

[0143] In S100, a conductor 33a with a relatively low impurity concentration is formed, and in S101, a resist mask 43 is formed. Then, as... Figure 17 As shown, ion implantation of impurities is performed on the conductor 33a in region R2b (S106). This forms a conductor 33b with a higher impurity concentration than the conductor 33a itself on top of the conductor 33a in region R2b. When the impurity concentrations of the conductors 33a in regions R0b to R2b are set to concentrations D10a to D12a respectively, the concentrations D10a to D12a are the same. After ion implantation, the resist mask 43 is stripped.

[0144] A resist mask 44 is formed in S103. Then, as... Figure 18 As shown, impurity ion implantation is performed on each of the conductors 33a in region R2b and region R1b (S107). At this time, the accelerating voltage used in ion implantation is set to be lower than the accelerating voltage used in ion implantation in S106. As a result, the implantation depth of ions into the conductor 33a in region R1b becomes shallower than the ion implantation depth into the conductor 33a in region R2b in S106. Consequently, conductors 33b with a higher impurity concentration than conductors 33a are formed on the upper part of both conductors 33a in region R2b and region R1b. When the impurity concentration of conductor 33b in region R2b is set to D12b, the concentration D12b is higher than the concentration D12a. When the impurity concentration of conductor 33b in region R1b is set to D11b, the concentration D11b is higher than the concentration D11a. Furthermore, the concentration D12b can be the same as or different from the concentration D11b. After ion implantation, the resist mask 44 is stripped.

[0145] By using S106 and S107, the closer the contact plug CP1 is to the row selection circuit 14, the lower the ratio of the conductors 33b included in the contact plug CP1 can be. The closer the contact plug CP1 is to the row selection circuit 14, the lower the height of the conductors 33b included in the contact plug CP1 can be.

[0146] 1.5.3 Effects involved in this variation

[0147] According to this modified example, the same effect as in the first embodiment is achieved. Of course, the first modified example of the first embodiment can also be applied to the contact plug CP1 included in the storage device 1 of this modified example.

[0148] 1.6 Example 3 (Modification)

[0149] The storage device according to the third modification of the first embodiment will be described. In the storage device 1 according to the third modification of the first embodiment, the structure of the contact plug CP1 is different from that of the second modification of the first embodiment. In the following description, the configuration that is the same as that of the second modification of the first embodiment will be omitted, and the configuration that is different from that of the second modification of the first embodiment will be mainly described.

[0150] 1.6.1 Construction of a Storage Cell Array

[0151] The planar structure of the storage cell array 10 is the same as that of the second variation of the first embodiment.

[0152] use Figure 19 The cross-sectional structure of the memory cell array 10 will be described. Figure 19 It is along Figure 3 A sectional view along line II. Furthermore, in Figure 19 The insulating layer is omitted in the example shown.

[0153] like Figure 19 As shown, contact plug CP1 in region R0b includes conductor 33a. Contact plug CP1 in region R1b includes conductor 33b1. Contact plug CP1 in region R2b includes conductor 33b2. Contact plug CP1 in region R3b includes conductor 33b3. Contact plug CP1 in region R4b includes conductor 33b4. Conductors 33a and 33b1-33b4 are made of the same material as in the second variation of the first embodiment. Conductors 33a and 33b1-33b4 are, for example, n-type semiconductors or p-type semiconductors. Conductors 33a and 33b1-33b4 contain, for example, at least one of silicon and germanium. Conductors 33a and 33b1-33b4 contain impurities (dopants). The impurities are made of the same material as in the second variation of the first embodiment.

[0154] The diameters of the contact plugs CP1 in regions R0b to R4b are approximately the same. Furthermore, the cross-sectional shape of the contact plugs CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plugs CP1, the contact area between the contact plugs CP1 and the word line WL in regions R0b to R4b is approximately the same.

[0155] When the impurity concentrations of the contact plugs CP1 (conductors 33a and 33b1 to 33b4) in regions R0b to R4b are set to concentrations D10a and D11b to D14b respectively, concentration D10a is lower than concentration D11b. Concentration D11b is lower than concentration D12b. Concentration D12b is lower than concentration D13b. Concentration D13b is lower than concentration D14b. Thus, the closer the contact plugs CP1 are to the row selection circuit 14, the lower the impurity concentration of the contact plugs CP1 in regions R0b to R4b. For example, if the accelerating voltage used in ion implantation is the same for the contact plugs CP1 (conductors 33b1 to 33b4) in regions R1b to R4b, the closer the contact plugs CP1 are to the row selection circuit 14, the less ion implantation is required. Therefore, the closer the contact plug CP1 is to the row selection circuit 14, the higher its resistance value.

[0156] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the second variation of the first embodiment.

[0157] With k potential lines (BL) (k being an integer greater than or equal to 1), ion implantation is performed (k-1) times to change the concentration of impurities.

[0158] 1.6.2 Effects of this variation

[0159] According to this modified example, the same effect as the first embodiment is achieved.

[0160] 1.7 Example 4 (Modification)

[0161] The storage device according to the fourth modification of the first embodiment will be described. In the storage device 1 according to the fourth modification of the first embodiment, the method for distributing the impurity concentration of the contact plug CP1 is different from that in the third modification of the first embodiment. In the following description, the configurations that are the same as those in the third modification of the first embodiment will be omitted, and the configurations that are different from those in the third modification of the first embodiment will be described.

[0162] 1.7.1 Construction of a Storage Cell Array

[0163] The planar structure of the storage cell array 10 is the same as that of the third variation of the first embodiment.

[0164] use Figure 20 The cross-sectional structure of the memory cell array 10 will be described. Figure 20 It is along Figure 3 A sectional view along line II. Furthermore, in Figure 20 The insulating layer is omitted in the example shown.

[0165] like Figure 20 As shown, the diameters of the contact plugs CP1 in regions R0b to R4b are approximately the same. Furthermore, the cross-sectional shape of the contact plugs CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plugs CP1, the contact area between the contact plugs CP1 in regions R0b to R4b and the word line WL is approximately the same.

[0166] Regions R1b to R4b are divided into group G0, which includes two adjacent regions R1b and R2b, and group G1, which includes two adjacent regions R3b and R4b. The impurity concentrations D11b and D12b of the contact plugs CP1 (conductors 33b1 and 33b2) in regions R1b and R2b are the same. The impurity concentrations D13b and D14b of the contact plugs CP1 (conductors 33b3 and 33b4) in regions R3b and R4b are the same. Concentration D10a is lower than concentrations D11b and D12b. Concentrations D11b and D12b are lower than concentrations D13b and D14b. Thus, the closer the contact plug CP1 is to the group of the row selection circuit 14, the lower the impurity concentration of the contact plug CP1 in groups G0 and G1. Therefore, the closer the contact plug CP1 is to the group of the row selection circuit 14, the higher the resistance value of the contact plug CP1. Furthermore, using... Figure 20 The description addresses the scenario where each group comprises two adjacent regions, but is not limited to this. For example, each group may also comprise three or more adjacent regions. Furthermore, the number of regions included in each group may vary.

[0167] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the third variation of the first embodiment.

[0168] 1.7.2 Effects of this variation

[0169] According to this modified example, the same effect as the first embodiment is achieved.

[0170] Furthermore, according to this modified example, the impurity concentration of the contact plug CP1 varies according to each group. Therefore, the impurity concentration of the contact plug CP1 does not need to be changed according to each region R1b to R4b. As a result, compared to the case where the impurity concentration of the contact plug CP1 is changed individually, the number of contact plugs CP1 with different impurity concentrations is reduced. Therefore, the number of ion implantation repetitions for changing the impurity concentration can be reduced. As a result, process costs can be reduced.

[0171] 2. Second Implementation Method

[0172] The storage device according to the second embodiment will be described. In the storage device 1 according to the second embodiment, the structure of the contact plug CP1 is different from that of the first embodiment. In the following description, the configurations that are the same as those in the first embodiment will be omitted, and the configurations that are different from those in the first embodiment will be mainly described.

[0173] 2.1 Construction of Storage Cell Array

[0174] The planar structure of the storage cell array 10 is the same as that in the first embodiment.

[0175] use Figure 21 The cross-sectional structure of the memory cell array 10 will be described. Figure 21 It is along Figure 3 A sectional view along line II. Furthermore, in Figure 21 The insulating layer is omitted in the example shown.

[0176] like Figure 21 As shown, the contact plugs CP1 in regions R0b to R4b each include a conductor 33a. The conductor 33a is made of the same material as in the first embodiment.

[0177] When the diameters of the contact plugs CP1 in regions R0b to R4b are set to dm0 to dm4 respectively, diameter dm0 is smaller than diameter dm1. Diameter dm1 is smaller than diameter dm2. Diameter dm2 is smaller than diameter dm3. Diameter dm3 is smaller than diameter dm4. Furthermore, the shape of the cross-section (XY cross-section) of the contact plug CP1 is not limited to a circle. For example, the cross-section of the contact plug CP1 can be elliptical or rectangular. Regardless of the shape of the cross-section of the contact plug CP1, the closer the contact plug CP1 is to the row selection circuit 14, the smaller the contact area between the contact plug CP1 in regions R0b to R4b and the word line WL. Therefore, the closer the contact plug CP1 is to the row selection circuit 14, the higher its resistance value.

[0178] The length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R0b is shorter than the length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R1b. The length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R1b is shorter than the length of the word line WL from the row selection circuit 14 to the contact plug CP1 located in region R2b. The same applies to the following.

[0179] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

[0180] 2.2 Effects of this implementation method

[0181] According to the second embodiment, the same effect as the first embodiment is achieved.

[0182] 2.3 Variations

[0183] The storage device according to a variation of the second embodiment will be described. In the storage device 1 according to the variation of the second embodiment, the method of distributing the diameter of the contact plug CP1 is different from that in the second embodiment. In the following description, the configurations that are the same as those in the second embodiment will be omitted, and the configurations that are different from those in the second embodiment will be described in detail.

[0184] 2.3.1 Construction of Storage Cell Array

[0185] The planar structure of the storage cell array 10 is the same as that in the second embodiment.

[0186] use Figure 22 The cross-sectional structure of the memory cell array 10 will be described. Figure 22 It is along Figure 3 A sectional view along line II. Furthermore, in Figure 22 The insulating layer is omitted in the example shown.

[0187] like Figure 22 As shown, regions R1b to R4b are divided into group G0, which includes two adjacent regions R1b and R2b, and group G1, which includes two adjacent regions R3b and R4b. The diameters dm1 and dm2 of the contact plugs CP1 in regions R1b and R2b are the same. The diameters dm3 and dm4 of the contact plugs CP1 in regions R3b and R4b are the same. Diameter dm0 is smaller than diameters dm1 and dm2. Diameters dm1 and dm2 are smaller than diameters dm3 and dm4. Thus, the closer the contact plug CP1 is to the row selection circuit 14, the smaller the diameter of the contact plug CP1 in groups G0 and G1. Furthermore, the shape of the cross-section of the contact plug CP1 is not limited to a circle. Regardless of the shape of the cross-section of the contact plug CP1, the closer the contact plug CP1 is to the row selection circuit 14, the smaller the contact area between the contact plug CP1 in groups G0 and G1 and the word line WL. Therefore, the closer the contact plug CP1 is to the group of rows selected by the row selection circuit 14, the higher its resistance value. Furthermore, using... Figure 22 The description addresses the scenario where each group comprises two adjacent regions, but is not limited to this. For example, each group may also comprise three or more adjacent regions. Furthermore, the number of regions included in each group may vary.

[0188] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the second embodiment.

[0189] 2.3.2 Effects of this variation

[0190] According to this modified example, the same effect as the first embodiment is achieved.

[0191] Furthermore, according to this modified example, the diameter of the contact plug CP1 varies depending on the group. While there is a concern that the manufacturing process would be complicated by having all contact plugs CP1 with different diameters, this modified example eliminates that concern.

[0192] 3. Third Implementation Method

[0193] The storage device according to the third embodiment will be described. In the storage device 1 according to the third embodiment, the configuration of the word line WL, contact plugs CP1 and CP2, and bit line BL is different from that of the first embodiment. In the following description, the configurations that are the same as those in the first embodiment will be omitted, and the configurations that are different from those in the first embodiment will be mainly described.

[0194] 3.1 Construction of Storage Cell Array

[0195] An example of the construction of the memory cell array 10 will be described.

[0196] (Plane Construction)

[0197] use Figure 23 The planar structure of the storage cell array 10 will be described. Figure 23 This is a plan view showing an example of the planar structure of the memory cell array 10. Figure 23 The word lines WL between multiple memory cells MC and row select circuit 14, and the bit lines BL between multiple memory cells MC and column select circuit 15 are shown within the memory cell array 10. Furthermore, in Figure 23 The word lines WL<5> to WL<M>, bit lines BL<5> to BL<N>, and the multiple memory cells MC corresponding to these lines are omitted.

[0198] like Figure 23 As shown, in the memory cell array 10, for example, the memory cell MC is positioned above the bit line BL. The word line WL is positioned above the memory cell MC.

[0199] (Cross-section construction)

[0200] use Figures 24-26 The cross-sectional structure of the memory cell array 10 will be described. Figure 24 It is along Figure 23 A sectional view along line II. Figure 25 It is along Figure 23 A sectional view along line II-II. Figure 26 This is a three-dimensional view of a portion of the storage cell array 10. Furthermore, in Figures 24-26 The example shown omits the insulating layer.

[0201] like Figures 24-26 As shown, a plurality of conductors 38 are disposed above the semiconductor substrate 30, for example, separated by an insulating layer 31. The plurality of conductors 38 are arranged, for example, in the X direction and each extends in the Y direction. Furthermore, in Figure 26 The semiconductor substrate 30 and the insulating layer 31 are omitted.

[0202] A plurality of contact plugs CP2 are disposed on the upper surface of a conductor 38. The plurality of contact plugs CP2 disposed on the upper surface of a conductor 38 are arranged, for example, in the Y direction. The contact plugs CP2 include conductors 37a.

[0203] An element 34 is provided on the upper surface of the contact plug CP2.

[0204] A contact plug CP1 is provided on the upper surface of the conductor 36. The contact plug CP1 in region R0b includes a conductor 33a. The contact plug CP1 in each of regions R1b to R4b includes conductors 33a and 33b. Conductors 33a and 33b are made of the same material as in the first embodiment.

[0205] The diameters of the contact plugs CP1 in regions R0b to R4b are approximately the same. Furthermore, the shape of the cross-section (XY section) of the contact plug CP1 is not limited to a circle. For example, the cross-section of the contact plug CP1 can be either elliptical or rectangular. Regardless of the shape of the cross-section of the contact plug CP1, the contact area between the contact plug CP1 in regions R0b to R4b and the word line WL is approximately the same.

[0206] The closer the contact plug CP1 is to the row selection circuit 14, the lower the ratio of conductors 33b included in each contact plug CP1 in regions R1b to R4b. The closer the contact plug CP1 is to the row selection circuit 14, the lower the height of the conductors 33b included in each contact plug CP1 in regions R1b to R4b. Conductors 33b are disposed on conductors 33a. Alternatively, conductors 33a may be disposed on conductors 33b. Furthermore, each contact plug CP1 in regions R1b to R4b may be composed of three or more conductors with different resistivities. Conductors 33a and 33b may also contain two or more materials.

[0207] A conductor 32 is provided on the upper surface of the contact plug CP1. Multiple conductors 32 are arranged, for example, in the Y direction and each extends in the X direction. For example, multiple contact plugs CP1 arranged in the X direction are connected to one conductor 32.

[0208] like Figure 26 As shown, a storage unit MC is provided at the intersection of conductor 32 and conductor 38.

[0209] 3.2 Effects of this implementation method

[0210] According to the third embodiment, the same effect as in the first embodiment is achieved. Of course, the first to fourth modifications of the first embodiment can also be applied to the contact plug CP1 included in the storage device 1 of this embodiment.

[0211] 4. Fourth Implementation Method

[0212] The storage device according to the fourth embodiment will be described. In the storage device 1 according to the fourth embodiment, the structure of the contact plug CP1 is different from that of the third embodiment. In the following description, the configurations that are the same as those in the third embodiment will be omitted, and the configurations that are different from those in the third embodiment will be mainly described.

[0213] 4.1 Construction of Storage Cell Array

[0214] The planar structure of the storage cell array 10 is the same as that in the third embodiment.

[0215] use Figure 27 The cross-sectional structure of the memory cell array 10 will be described. Figure 27 It is along Figure 23 A sectional view along line II. Furthermore, in Figure 27 The insulating layer is omitted in the example shown.

[0216] like Figure 27 As shown, the contact plugs CP1 in regions R0b to R4b each include a conductor 33a. The conductor 33a is made of the same material as in the second embodiment.

[0217] The diameter dm0 is smaller than the diameter dm1. The diameter dm1 is smaller than the diameter dm2. The diameter dm2 is smaller than the diameter dm3. The diameter dm3 is smaller than the diameter dm4. Furthermore, the shape of the cross-section (XY section) of the contact plug CP1 is not limited to a circle. For example, the cross-section of the contact plug CP1 can be either elliptical or rectangular. Regardless of the shape of the cross-section of the contact plug CP1, the closer the contact plug CP1 is to the row selection circuit 14, the smaller the contact area between the contact plug CP1 in regions R0b to R4b and the word line WL.

[0218] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the third embodiment.

[0219] 4.2 Effects of this implementation method

[0220] According to the fourth embodiment, the same effect as in the first embodiment is achieved. Of course, variations of the second embodiment can also be applied to the contact plug CP1 included in the storage device 1 of this embodiment.

[0221] 5. Fifth Implementation Method

[0222] The storage device according to the fifth embodiment will be described. In the storage device 1 according to the fifth embodiment, the structure of the contact plug CP2 is different from that of the first embodiment. In the following description, the configurations that are the same as those in the first embodiment will be omitted, and the configurations that are different from those in the first embodiment will be mainly described.

[0223] 5.1 Construction of Storage Cell Array

[0224] The planar structure of the storage cell array 10 is the same as that in the first embodiment.

[0225] use Figure 28 and Figure 29 The cross-sectional structure of the memory cell array 10 will be described. Figure 28 It is along Figure 3 A sectional view along line II. Figure 29 It is along Figure 3 A sectional view along line II-II. Furthermore, in Figure 28 and Figure 29 The insulating layer is omitted in the example shown.

[0226] like Figure 28 and Figure 29 As shown, the contact plug CP2 in region R4w includes a conductor 37a. The contact plugs CP2 in regions R0w to R3w each include conductors 37a and 37b. Conductor 37a is made of the same material as conductor 33a. Conductor 37b is made of the same material as conductor 33b.

[0227] The diameters of the contact plugs CP2 in regions R0w to R4w are approximately the same. Furthermore, the shape of the cross-section (XY section) of the contact plug CP2 is not limited to a circle. For example, the cross-section of the contact plug CP2 can be either elliptical or rectangular. Regardless of the shape of the cross-section of the contact plug CP2, the contact area between the contact plug CP2 and the bit line BL in regions R0w to R4w is approximately the same.

[0228] The closer the contact plug CP2 is to the column select circuit 15, the lower the ratio of conductors 37b included in each of the contact plugs CP2 in regions R0w to R3w. The closer the contact plug CP2 is to the column select circuit 15, the lower the height of the conductors 37b included in each of the contact plugs CP2 in regions R0w to R3w. Therefore, the closer the contact plug CP2 is to the column select circuit 15, the higher its resistance value. Conductors 37b are disposed on conductors 37a. Alternatively, conductors 37a can be disposed on conductors 37b. Furthermore, each of the contact plugs CP2 in regions R0w to R3w can be composed of three or more conductors with different resistivities. Conductors 37a and 37b can also contain two or more materials.

[0229] The length of bit line BL from column select circuit 15 to contact plug CP2 located in region R4w is shorter than the length of bit line BL from column select circuit 15 to contact plug CP2 located in region R3w. The length of bit line BL from column select circuit 15 to contact plug CP2 located in region R3w is shorter than the length of bit line BL from column select circuit 15 to contact plug CP2 located in region R2w. The same applies to the following.

[0230] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the first embodiment.

[0231] 5.2 Effects of this implementation method

[0232] According to the fifth embodiment, the same effect as the first embodiment is achieved.

[0233] Furthermore, as described in the first embodiment, the closer a cell is to the column select circuit 15, the lower the resistance value of the bit line BL between the memory cell MC and the column select circuit 15. Assume that the resistance values ​​of the multiple contact plugs CP2 connected to the bit line BL are the same. In this case, depending on the length of the bit line BL from the column select circuit 15 to the contact plug CP2, the resistance value of the wiring path formed by the bit line BL from the column select circuit 15 to the memory cell MC and the contact plug CP2 (hereinafter also referred to as the "column select circuit-cell wiring path") will vary.

[0234] According to this embodiment, by combining the resistance value of the bit line BL and the resistance value of the contact plug CP2, it is possible to suppress the variation in the resistance value of the column selection circuit-cell wiring path caused by the length of the bit line BL.

[0235] Of course, the first to fourth modifications of the first embodiment and the second embodiment and the modifications of the second embodiment can also be applied to the contact plugs CP1 and CP2 included in the storage device 1 of this embodiment.

[0236] 6. Sixth Implementation Method

[0237] The storage device according to the sixth embodiment will be described. In the storage device 1 according to the sixth embodiment, the structure of the contact plug CP2 is different from that of the third embodiment. In the following description, the configurations that are the same as those in the third embodiment will be omitted, and the configurations that are different from those in the third embodiment will be mainly described.

[0238] 6.1 Construction of Memory Cell Array

[0239] The planar structure of the storage cell array 10 is the same as that in the third embodiment.

[0240] use Figure 30 and Figure 31 The cross-sectional structure of the memory cell array 10 will be described. Figure 30 It is along Figure 23 A sectional view along line II. Figure 31 It is along Figure 23 A sectional view along line II-II. Furthermore, in Figure 30 and Figure 31 The insulating layer is omitted in the example shown.

[0241] like Figure 30 and Figure 31 As shown, the contact plug CP2 in region R4w includes a conductor 37a. The contact plugs CP2 in regions R0w to R3w each include conductors 37a and 37b. Conductor 37a is made of the same material as conductor 33a. Conductor 37b is made of the same material as conductor 33b.

[0242] The diameters of the contact plugs CP2 in regions R0w to R4w are approximately the same. Furthermore, the shape of the cross-section (XY section) of the contact plug CP2 is not limited to a circle. For example, the cross-section of the contact plug CP2 can be either elliptical or rectangular. Regardless of the shape of the cross-section of the contact plug CP2, the contact area between the contact plug CP2 and the bit line BL in regions R0w to R4w is approximately the same.

[0243] The closer the contact plug CP2 is to the column selection circuit 15, the lower the ratio of conductors 37b included in each of the contact plugs CP2 in regions R0w to R3w. The closer the contact plug CP2 is to the column selection circuit 15, the lower the height of the conductors 37b included in each of the contact plugs CP2 in regions R0w to R3w. Conductors 37b are disposed on conductors 37a. Alternatively, conductors 37a may be disposed on conductors 37b. Furthermore, each of the contact plugs CP2 in regions R0w to R3w may be composed of three or more conductors with different resistivities. Conductors 37a and 37b may also contain two or more materials.

[0244] The length of bit line BL from column select circuit 15 to contact plug CP2 located in region R4w is shorter than the length of bit line BL from column select circuit 15 to contact plug CP2 located in region R3w. The length of bit line BL from column select circuit 15 to contact plug CP2 located in region R3w is shorter than the length of bit line BL from column select circuit 15 to contact plug CP2 located in region R2w. The same applies to the following.

[0245] The other parts of the cross-sectional structure of the memory cell array 10 are the same as those in the third embodiment.

[0246] 6.2 Effects of this implementation method

[0247] According to the sixth embodiment, the same effect as in the first embodiment is achieved. Furthermore, according to this embodiment, the same effect as in the fifth embodiment is achieved. Of course, the first to fourth modifications of the first embodiment and the second and third embodiments of the second embodiment can also be applied to the contact plugs CP1 and CP2 included in the storage device 1 of this embodiment.

[0248] 7. Variations, etc.

[0249] As described above, the storage device according to the embodiment includes a first storage cell (MC), a second storage cell (MC), a first circuit (14) supplying write current to the first storage cell and the second storage cell, a first wiring (WL) connected to the first circuit, a first plug (CP1) electrically connecting the first storage cell and the first wiring, and a second plug (CP1) electrically connecting the second storage cell and the first wiring. The length of the first wiring (WL) from the first circuit to the first plug is shorter than the length of the first wiring (WL) from the first circuit to the second plug. The resistance value of the first plug (CP1) is higher than the resistance value of the second plug (CP1).

[0250] Furthermore, the implementation method is not limited to the form described above, and various modifications can be made.

[0251] Furthermore, the processing order of the flowcharts described in the above embodiments can be changed whenever feasible.

[0252] Furthermore, in the above embodiments, the description mainly focuses on the case where a memory cell MC can be selected by a group of one word line WL and one bit line BL (referred to as a single-layer structure), but it is not limited to this. For example, any array structure, such as an array structure having multiple such structures stacked in the Z direction, can be applied.

[0253] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and also within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: First storage unit; Second storage unit; The first circuit supplies write current to the first memory cell and the second memory cell; The first wiring is connected to the first circuit; A first plug, which electrically connects the first storage unit and the first wiring; and The second plug electrically connects the second storage unit and the first wiring. The first plug includes a first conductor and a second conductor. The second plug includes a third conductor and a fourth conductor. The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug. The resistance value of the first plug is higher than the resistance value of the second plug. The resistivity of the second conductor is lower than that of the first conductor. The resistivity of the fourth conductor is lower than that of the third conductor. The ratio of the second conductor included in the first plug is lower than the ratio of the fourth conductor included in the second plug.

2. The storage device according to claim 1, The first conductor and the third conductor comprise at least one of tungsten, tungsten nitride, titanium, titanium nitride, carbon, and polycrystalline silicon. The second and fourth conductors comprise at least one of copper and aluminum.

3. The storage device according to claim 1, The first conductor and the third conductor comprise at least one of carbon and polycrystalline silicon. The second and fourth conductors comprise at least one of tungsten, tungsten nitride, titanium, and titanium nitride.

4. The storage device according to claim 1, The first conductor and the third conductor both contain a first semiconductor. The second conductor and the fourth conductor comprise a second semiconductor. The impurity concentration of the first semiconductor is lower than that of the second semiconductor.

5. The storage device according to claim 1, The second conductor is disposed on the first conductor. The fourth conductor is disposed on the third conductor.

6. The storage device according to claim 1, The first plug includes a first semiconductor. The second plug includes a second semiconductor. The impurity concentration of the first semiconductor is lower than that of the second semiconductor.

7. The storage device according to claim 1, The contact area between the first plug and the first wiring is smaller than the contact area between the second plug and the first wiring.

8. The storage device according to claim 7, The cross-sectional shape of the first plug and the second plug is circular.

9. The storage device according to claim 8, The diameter of the first plug is smaller than the diameter of the second plug.

10. The storage device according to claim 1, The first storage unit and the second storage unit are configured above the first wiring.

11. The storage device according to claim 1, The first wiring is positioned above the first storage unit and the second storage unit.

12. The storage device according to claim 1, further comprising: 5th storage unit; 6th storage unit; The second circuit supplies write current to the fifth and sixth memory cells; The second wiring is connected to the second circuit; A fifth plug, which electrically connects the fifth storage cell and the second wiring; and The sixth plug electrically connects the sixth storage unit and the second wiring. The length of the second wiring from the second circuit to the fifth plug is shorter than the length of the second wiring from the second circuit to the sixth plug. The resistance value of the fifth plug is higher than that of the sixth plug.

13. The storage device according to claim 12, The second wiring is positioned above the fifth and sixth storage cells.

14. The storage device according to claim 12, The fifth and sixth storage units are positioned above the second wiring.

15. The storage device according to claim 1, The first storage unit and the second storage unit include variable resistance elements.

16. The storage device according to claim 15, The variable resistance element is a magnetoresistive element.

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