Memory device and operating method thereof

Abstract

The present application relates to memory devices and methods of operating the same. A memory device includes a target memory block and a peripheral circuit configured to float a local word line coupled to the target memory block as an erase voltage rises toward a target level, apply a first voltage to the local word line after the erase voltage reaches the target level, and apply one or more group voltages to the local word line after applying the first voltage.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to semiconductor devices, and more specifically, to memory devices. Background Technology

[0002] The memory device may include a volatile memory device that loses the data stored therein when the power is cut off, and a non-volatile memory device that retains the data stored therein even when the power is cut off.

[0003] Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and NAND flash memory.

[0004] A memory device may include multiple memory cells and can be configured to perform programming, reading, and erasing operations on the memory cells. Under external control, the memory device may interrupt an ongoing internal operation to first execute another operation, and then resume the interrupted internal operation. Summary of the Invention

[0005] Various embodiments of this disclosure pertain to memory devices and methods of operation thereof capable of stably performing erase operations.

[0006] In one embodiment of this disclosure, a memory device may include: a target memory block; and peripheral circuitry configured to float local word lines connected to the target memory block as the erase voltage rises toward a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more groups of voltages to the local word lines after applying the first voltage.

[0007] In one embodiment of this disclosure, a memory device may include: a voltage supply circuit configured to provide one or more group voltages and a first voltage; and a decoder configured to, when performing an erase operation on a target memory block, apply a first voltage to a local word line coupled to the target memory block, and apply one or more group voltages to the local word line after applying the first voltage.

[0008] In one embodiment of this disclosure, a method of operating a memory device may include: floating a local word line connected to a target memory block during a rise period of an erase voltage; applying a first voltage to the local word line after the rise period; and applying one or more groups of voltages to the local word line after applying the first voltage.

[0009] In one embodiment of this disclosure, an operation method of a memory device may include: applying an erase voltage to a memory block; floating a local word line connected to the memory block when the applied erase voltage increases to reach a target voltage; and applying a third voltage to the local word line after the applied erase voltage reaches the target voltage, followed by applying a fourth voltage. The floating step may include turning on a switch with a first voltage to connect a global word line to the local word line; and applying a second voltage to the global word line. The first voltage may be lower than the second voltage, the third voltage may be lower than the first voltage, and the fourth voltage may be lower than the third voltage.

[0010] The memory device and its operation method according to the embodiments of the present disclosure can stably perform the erase operation. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory device according to one embodiment of the present disclosure.

[0012] Figure 2 This is a circuit diagram illustrating a memory block according to one embodiment of the present disclosure.

[0013] Figure 3 This is a circuit diagram illustrating a memory block according to one embodiment of the present disclosure.

[0014] Figure 4 The diagram illustrates in more detail a voltage supply circuit and a decoder according to one embodiment of the present disclosure.

[0015] Figure 5 This is a timing diagram used to describe an erase operation on a target storage block according to one embodiment of the present disclosure.

[0016] Figure 6 This is a flowchart illustrating a method for performing an erase operation using a memory device according to one embodiment of the present disclosure. Detailed Implementation

[0017] The advantages, features, and implementation methods of this disclosure will become more apparent after reading the following embodiments in conjunction with the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to describe this disclosure in detail so that those skilled in the art to which this disclosure pertains can readily implement the technical ideas of this disclosure.

[0018] It should be understood that the embodiments of this disclosure are not limited to the details shown in the accompanying drawings, and the drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated to more clearly depict certain features of this disclosure. Although specific terminology is used herein, it should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0019] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. It should be understood that when an element is referred to as being “on,” “connected to,” or “linked to” another element, the element may be directly on, directly connected to, or directly linked to the other element, or there may be intermediate elements present. As used herein, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise. It should also be understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of at least one of the stated features, steps, operations, and / or elements, but do not preclude the presence or addition of one or more other features, steps, operations, and / or elements.

[0020] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram illustrating a memory device 10 according to one embodiment of the present disclosure.

[0022] Reference Figure 1 The memory device 10 can perform internal operations such as programming, reading, and erasing operations according to external control. The memory device 10 can receive external signals ES that indicate internal operations. External signals ES may include commands, addresses, data, and various control signals for controlling the memory device 10.

[0023] According to external control, the memory device 10 can interrupt the ongoing erase operation, first perform another internal operation (e.g., a read operation or a programming operation), and then resume the interrupted erase operation. Therefore, another internal operation that takes precedence over the erase operation can be executed quickly. However, if the interruption and resumption of the erase operation are repeated with repeated requests for other internal operations, the probability of uneven erasure of memory cells (i.e., some memory cells are over-erased and some other memory cells are under-erased) increases.

[0024] The memory device 10 may include memory blocks MB1 to MBk and peripheral circuitry 100.

[0025] Memory blocks MB1 to MBk can be connected to peripheral circuitry 100 via local word lines LWL1 to LWLk and local select lines LSL1 to LSLk. Each of memory blocks MB1 to MBk can be connected to peripheral circuitry 100 via its corresponding local word line and corresponding local select line. For example, memory block MB1 can be connected to peripheral circuitry 100 via local word line LWL1 and local select line LSL1. Each of the local select lines LSL1 to LSLk can include a drain select line and a source select line.

[0026] A memory block can be the unit in which the memory device 10 performs an erase operation. That is, data stored in a memory block can be erased simultaneously. However, according to one embodiment, the memory device 10 can perform erase operations in units smaller than memory blocks.

[0027] Each of the memory blocks MB1 to MBk may include a plurality of memory cells therein for storing data. The memory cells may be arranged as a two-dimensional structure in which the memory cells are arranged parallel to the substrate, or as a three-dimensional structure in which the memory cells are stacked on the substrate in a vertical direction.

[0028] The peripheral circuit 100 can perform internal operations of the memory device 10 based on the external signal ES.

[0029] Specifically, the peripheral circuit 100 can perform an erase operation on a target memory block (e.g., memory block MB1) among memory blocks MB1 to MBk. The peripheral circuit 100 can apply an erase voltage to the target memory block MB1. As the erase voltage rises toward a target level, i.e., during the rise period of the erase voltage, the peripheral circuit 100 can float the local word line LWL1 connected to the target memory block MB1. After the erase voltage reaches the target level, i.e., after the rise period of the erase voltage, the peripheral circuit 100 can apply a first voltage to the local word line LWL1. After applying the first voltage to the local word line LWL1, the peripheral circuit 100 can apply one or more groups of voltages to the local word line LWL1.

[0030] According to one implementation, the first voltage may be higher than one or more group voltages.

[0031] According to one embodiment, the capacitance of the first voltage can be greater than the capacitance of each of one or more groups of voltages. The first voltage can be a voltage supplied more stably than one or more groups of voltages.

[0032] According to one embodiment, one or more group voltages may correspond to corresponding local word line groups obtained by grouping local word lines LWL1. After applying a first voltage to the local word lines LWL1, the peripheral circuit 100 may apply one or more group voltages to the corresponding local word line groups. The peripheral circuit 100 may sequentially apply one or more group voltages to one or more local word line groups.

[0033] According to one embodiment, to float the local word line LWL1, the peripheral circuit 100 can apply a second voltage as a block select signal corresponding to the target memory block MB1, and can apply a third voltage to the global word line GWL, which is configured to be connected to the local word line LWL1 in response to the block select signal. The block select signal corresponding to the target memory block MB1 can be a signal used to connect the global word line GWL and the local word line LWL1. The block select signal corresponding to the target memory block MB1 can be a signal input to the gate of an NMOS transistor located between the global word line GWL and the local word line LWL1.

[0034] According to one implementation, the second voltage may be lower than the third voltage.

[0035] According to one implementation, the first voltage may be lower than the second and third voltages.

[0036] According to one embodiment, when the local word line LWL1 is floating, the peripheral circuit 100 can cause the local select line LSL1 connected to the target memory block MB1 to float. Furthermore, when a first voltage is applied to the local word line LWL1 and when one or more group voltages are applied to the local word line LWL1, the peripheral circuit 100 can cause the local select line LSL1 to float continuously.

[0037] The peripheral circuit 100 may include a control circuit 110, a voltage supply circuit 120, and a decoder 130.

[0038] Control circuit 110 can control the general operation of memory device 10 based on external signal ES. Control circuit 110 can generate a voltage control signal VCS based on external signal ES and output the voltage control signal VCS to voltage supply circuit 120. Control circuit 110 can generate a decoding control signal DCS based on external signal ES and output the decoding control signal DCS to decoder 130. By controlling voltage supply circuit 120 and decoder 130 via voltage control signal VCS and decoding control signal DCS, control circuit 110 can perform an erase operation on target memory block MB1.

[0039] The voltage supply circuit 120 can generate and output a preset voltage level in response to the voltage control signal VCS. Specifically, during the erase operation, the voltage supply circuit 120 can selectively supply a first voltage, one or more group voltages, and a third voltage to the global word line GWL. During the erase operation, the voltage supply circuit 120 can supply a third voltage to the global select line GSL, which includes a global drain select line and a global source select line. Furthermore, during the erase operation, the voltage supply circuit 120 can supply a third voltage to the source line connected to the target memory block MB1 (see [link to source line]). Figure 4 Supply erase voltage. See below for further details. Figure 4 and Figure 5 The configuration and operation of the voltage supply circuit 120 are described in more detail.

[0040] Decoder 130 can address the memory region among memory blocks MB1 to MBk to which internal operations will be performed in response to the decoding control signal DCS. Specifically, during an erase operation, decoder 130 can select memory block MB1 as the target memory block among memory blocks MB1 to MBk. To select the target memory block, decoder 130 can enable the block select signal corresponding to the target memory block MB1. By enabling the block select signal corresponding to the target memory block MB1, decoder 130 can connect the local word line LWL1 of the target memory block MB1 to the global word line GWL. When the block select signal is enabled, decoder 130 can apply a second voltage as the block select signal. (See below for further details.) Figure 4 and Figure 5 The configuration and operation of decoder 130 are described in more detail.

[0041] The memory device 10 may be a non-volatile memory device. The non-volatile memory device may include flash memory devices such as NAND flash or NOR flash, ferroelectric random access memory (FeRAM), phase-change random access memory (PCRAM), magnetic random access memory (MRAM), or resistive random access memory (ReRAM).

[0042] According to embodiments of this disclosure, even during interruptions and resumptions of repeated erase operations, the memory device 10 can prevent memory cells from being erased unevenly by floating the local word line LWL1 when the level of the erase voltage is rising. Furthermore, by first applying a more stable first voltage to the floating local word line LWL1 before applying one or more sets of voltages to the local word line LWL1 for actual erasure, the memory device 10 can stably perform the erase operation.

[0043] Figure 2 This is a circuit diagram illustrating a memory block MB1 according to one embodiment of the present disclosure. It can be compared with... Figure 2 Storage block MB1 is configured similarly. Figure 1 Each of the other storage blocks in the memory.

[0044] Reference Figure 2 Storage block MB1 may include strings ST11 to ST1m and ST21 to ST2m. Each of strings ST11 to ST1m and ST21 to ST2m may extend in the vertical direction (Z direction). Within storage block MB1, m strings may be arranged in the row direction (X direction). Figure 2 The example illustrates arranging two strings in the column direction (Y direction). However, this is for ease of description, and at least three strings can be arranged in the column direction (Y direction).

[0045] Series ST11 to ST1m and ST21 to ST2m can be configured identically. For example, series ST11 may include a source selection transistor SST, memory cells MC1 to MCn, and a drain selection transistor DST connected in series between the source line SL and the bit line BL1. The source of the source selection transistor SST may be connected to the source line SL, and the drain of the drain selection transistor DST may be connected to the bit line BL1. Memory cells MC1 to MCn may be connected in series between the source selection transistor SST and the drain selection transistor DST.

[0046] The gates of source-select transistors arranged in strings in the same row can be connected to the same source-select line. For example, the gates of the source-select transistors in strings ST11 to ST1m in the first row can be connected to source-select line SSL1. The gates of the source-select transistors in strings ST21 to ST2m in the second row can be connected to source-select line SSL2. In another embodiment, the source-select transistors in strings ST11 to ST1m and ST21 to ST2m can be connected together to a single source-select line.

[0047] The gates of drain-select transistors arranged in strings in the same row can be connected to the same drain-select line. For example, the gates of the drain-select transistors in strings ST11 to ST1m in the first row can be connected to drain-select line DSL1. The gates of the drain-select transistors in strings ST21 to ST2m in the second row can be connected to drain-select line DSL2.

[0048] Strings arranged in the same column can be connected to the same bit line. For example, strings ST11 and ST21 in the first column can be connected to bit line BL1. Strings ST1m and ST2m in the m-th column can be connected to bit line BLm.

[0049] The gates of memory cells located at the same vertical position can be connected to the same word line. For example, in strings ST11 to ST1m and ST21 to ST2m, memory cells located at the same vertical position as memory cell MC1 can be connected to word line WL1. Word lines WL1 to WLn can correspond to... Figure 1 The local character line LWL1.

[0050] In a memory cell, memory cells connected to the same word line in the same row can constitute a single memory region. For example, memory cells connected to word line WL1 in the first row can constitute memory region MR11. Memory cells connected to word line WL1 in the second row can constitute memory region MR12. Depending on the number of rows, each word line can connect to multiple memory regions. Memory cells constituting a single memory region can be programmed simultaneously. A single memory region can, for example, constitute a page.

[0051] According to one embodiment, the memory block MB1 may also be connected to one or more dummy word lines between word lines WL1 to WLn and drain select line DSL1 and / or between word lines WL1 to WLn and source select line SSL1. In this case, the memory block MB1 may also include dummy memory cells connected to the dummy word lines.

[0052] Figure 3 This is a circuit diagram illustrating a memory block MB1 according to one embodiment of the present disclosure. It can be compared with... Figure 3 Storage block MB1 is configured similarly. Figure 1 Each of the other storage blocks in the memory.

[0053] Reference Figure 3 Storage block MB1 may include multiple strings ST11 to ST1m and ST21 to ST2m. Figure 3 Each of the strings ST11 to ST1m and ST21 to ST2m can be connected with Figure 2 Each of the strings ST11 to ST1m and ST21 to ST2m is similarly configured and operates. However, Figure 3 Each of the strings ST11 to ST1m and ST21 to ST2m is formed in a U-shape and may also include a tubular transistor PT. The gate of the tubular transistor PT may be connected to the pipeline PL. In memory cells MC1 to MCn, memory cells MC1 to MCp may be arranged sequentially in opposite directions in the Z direction and may be connected in series between the source selection transistor SST and the tubular transistor PT. In memory cells MC1 to MCn, memory cells MCp+1 to MCn may be arranged sequentially in the Z direction and may be connected in series between the tubular transistor PT and the drain selection transistor DST.

[0054] Figure 4 The diagram illustrates in more detail a voltage supply circuit 120 and a decoder 130 according to one embodiment of the present disclosure.

[0055] Reference Figure 4 The voltage supply circuit 120 may include a third voltage generation circuit 121, a first voltage generation circuit 122, a first group of voltage generation circuits 1231 to an nth group of voltage generation circuits 123n, and an erase voltage generation circuit 124. Although not shown, each circuit included in the voltage supply circuit 120 may operate in response to a voltage control signal VCS sent from the control circuit 110.

[0056] The third voltage generation circuit 121 can be connected to the global word line GWL and the global select line GSL. The third voltage generation circuit 121 can provide a third voltage V3 to the global word line GWL and the global select line GSL. The global select line GSL can be selectively connected to the local select line LSL1 via the SPS circuit. More specifically, the global drain select line and the global source select line included in the global select line GSL can be selectively connected to the drain select line DSL1 and the source select line SSL1, respectively, via the SPS circuit.

[0057] The first voltage generation circuit 122 can be connected to the global word line GWL. The first voltage generation circuit 122 can provide a first voltage V1 to the global word line GWL. The first voltage V1 can be, for example, the core voltage.

[0058] Local word lines LWL1 and global word lines GWL can be grouped according to their respective positions. Local word lines LWL1 can be grouped into first local word line groups LWL1_G1 to nth local word line groups LWL1_Gn. Each of the first local word line groups LWL1_G1 to nth local word line groups LWL1_Gn can include a predetermined number of adjacent local word lines. For example, the predetermined number of local word lines closest to the source select line SSL can be the first local word line group LWL1_G1, and the predetermined number of local word lines closest to the drain select line DSL can be the nth local word line group LWL1_Gn, but embodiments of this disclosure are not limited thereto. Similar to the method of grouping local word lines LWL1, global word lines GWL can be grouped into first global word line groups GWL_G1 to nth global word line groups GWL_Gn. When global word lines GWL and local word lines LWL1 are controlled by grouping rather than individually, switches for individual control can be omitted, thereby suppressing an increase in area.

[0059] The first group of voltage generation circuits 1231 to the nth group of voltage generation circuits 123n can be connected to the first global word line group GWL_G1 to the nth global word line group GWL_Gn, respectively. The first group of voltage generation circuits 1231 to the nth group of voltage generation circuits 123n can generate the first group of voltages VG1 to the nth group of voltages VGn, respectively.

[0060] The first group of voltage generation circuits 1231 to the nth group of voltage generation circuits 123n can be configured and operated in a similar manner. When the first group of voltage generation circuits 1231 is described as an example, it can be connected to a first global word line group GWL_G1. The first global word line group GWL_G1 can include multiple global word lines, which can be connected to corresponding local word lines included in a first local word line group LWL1_G1. The first group of voltage generation circuits 1231 can provide a first group of voltages VG1 to the first global word line group GWL_G1. The first global word line group GWL_G1 can be connected to the first local word line group LWL1_G1 via a first pass circuit PS1. More specifically, multiple global word lines included in the first global word line group GWL_G1 can be connected to corresponding local word lines included in the first local word line group LWL1_G1 via the first pass circuit PS1.

[0061] The erase voltage generation circuit 124 can be connected to the source line SL. The erase voltage generation circuit 124 can provide an erase voltage VER to the source line SL. The erase voltage generation circuit 124 can raise the erase voltage VER to a preset target level during the rise period of the erase voltage VER.

[0062] Decoder 130 may include block decoder 131, selective pass circuit SPS, and first pass circuits PS1 to nth pass circuits PSn.

[0063] During the erase operation on the target memory block MB1, the block decoder 131 can apply the block selection signal BSS corresponding to the target memory block MB1 to the selective pass circuit SPS and the first pass circuits PS1 to the nth pass circuit PSn. The block selection signal BSS can be a signal used to connect the global select line GSL and the local select line LSL1, and to connect the global word line GWL and the local word line LWL1. The block decoder 131 can apply a second voltage V2 as the block selection signal BSS.

[0064] Since the second voltage V2 is lower than the third voltage V3, the local word line LWL1 can be floated when the third voltage V3 is applied to the global word line GWL while the second voltage V2 is applied as the block select signal BSS. Similarly, the local select line LSL1 can be floated when the third voltage V3 is applied to the global select line GSL while the second voltage V2 is applied as the block select signal BSS.

[0065] A selective pass circuit SPS can be connected between the global select line GSL and the local select line LSL1. The selective pass circuit SPS can connect the global select line GSL and the local select line LSL1 in response to the block select signal BSS. More specifically, the selective pass circuit SPS can connect the global drain select line and the global source select line included in the global select line GSL to the drain select line DSL1 and the source select line SSL1 included in the local select line LSL1, respectively. As shown, the selective pass circuit SPS can include an NMOS transistor with the block select signal BSS applied to its gate. However, according to one embodiment, the selective pass circuit SPS can be constructed from other components.

[0066] First pass circuits PS1 to nth pass circuits PSn can be respectively connected between the first global word line group GWL_G1 to the nth global word line group GWL_Gn and the first local word line group LWL1_G1 to the nth local word line group LWL1_Gn. First pass circuits PS1 to nth pass circuits PSn can connect the first global word line group GWL_G1 to the nth global word line group GWL_Gn and the first local word line group LWL1_G1 to the nth local word line group LWL1_Gn respectively in response to the block select signal BSS. First pass circuits PS1 to nth pass circuits PSn can be configured and operated in a similar manner. In describing the first pass circuit PS1 as an example, the first pass circuit PS1 can connect multiple global word lines included in the first global word line group GWL_G1 to corresponding local word lines included in the first local word line group LWL1_G1. As shown, the first pass circuit PS1 may include an NMOS transistor with the block select signal BSS applied to its gate. However, according to one implementation, the first pass circuit PS1 can be composed of other components.

[0067] Although not shown, decoder 130 may also include a pass circuit connecting the local word line and the global word line GWL of another memory block besides memory block MB1. Therefore, when an erase operation is performed on another target memory block besides memory block MB1, block decoder 131 can enable the block select signal corresponding to the target memory block. In this case, the local word line connected to the target memory block can be controlled in response to the enabled block select signal, similar to what has been described above.

[0068] Figure 5 This is a timing diagram used to describe an erase operation on target storage block MB1 according to one embodiment of the present disclosure.

[0069] Reference Figures 1 to 5 The erasure operation on the target storage block MB1 can include operations from the first time period S1 to the fourth time period S4.

[0070] During the first time period S1, a ground voltage VSS can be applied to the global select line GSL and the local select line LSL1, thus turning off the select transistors connected to the local select line LSL1 (i.e., the drain select transistor DST and the source select transistor SST). A ground voltage VSS can also be applied to the global word line GWL and the local word line LWL1.

[0071] The block selection signal BSS corresponding to the target memory block MB1 can be enabled to the second voltage V2.

[0072] Based on the gate-induced drain leakage (GIDL) effect, an erase operation can be performed by applying an erase voltage VER to the source line SL connected to the target memory block MB1. More specifically, the bit lines BL (i.e., bit lines BL1 to BLm) connected to the target memory block MB1 via coupling capacitors can be boosted using the erase voltage VER. The erase voltage VER can be gradually increased and maintained during the second time period S2 and the third time period S3 after reaching the target level VTG. When the voltage levels of the bit line BL and the source line SL rise while the drain select transistor DST and the source select transistor SST are off, the gate-induced drain leakage (GIDL) current flows in the channel direction, and the hot holes generated in the select transistor flow in the channel direction, thereby allowing the channel voltage to rise to the erase voltage VER.

[0073] During the period when the erase voltage VER rises to the target level VTG, i.e., during the rise period of the erase voltage VER, a third voltage V3 may be applied to the global word line GWL and the global select line GSL. For example, the third voltage V3 may be applied to the global word line GWL and the global select line GSL sequentially. However, the order in which the third voltage V3 is applied is not limited to this. The global select line GSL may be continuously supplied with the third voltage V3 until the erase voltage VER discharges to the ground voltage VSS in the fourth period S4.

[0074] The third voltage V3 can be a higher voltage than the second voltage V2 applied as the block select signal BSS, thus allowing the local word line LWL1 and the local select line LSL1 to float. For example, as the third voltage V3 is applied sequentially to the global word line GWL and the global select line GSL, the local word line LWL1 and the local select line LSL1 can float sequentially. However, the floating order is not limited to this. As the level of the erase voltage VER gradually increases, the voltage levels of the local word line LWL1 and the local select line LSL1 can also increase due to coupling effects. When the third voltage V3 is applied to the global select line GSL, the local select line LSL1 can remain continuously floating.

[0075] Therefore, even though the rise period of the erase voltage VER repeats with the interruption and recovery of the erase operation, the memory cell may not be erased at all because the local word line LWL1 is floating. In other words, even with the repeated rise period of the erase voltage VER, uneven erasure of memory cells can be prevented.

[0076] During the second time period S2, a first voltage V1 can be applied to the global word line GWL and the local word line LWL1. The capacitance of the first voltage V1 can be greater than the capacitance of each of the first group of voltages VG1 to the nth group of voltages VGn. Therefore, even when the first voltage V1 is applied to the local word line LWL1 and the local select line LSL1 which are floating at a high voltage level, the first voltage V1 can be stably provided.

[0077] In the third time period S3, the first set of voltages VG1 to the nth set of voltages VGn can be applied sequentially to the first local word line group LWL1_G1 to the nth local word line group LWL1_Gn. More specifically, the first set of voltages VG1 can be applied to the first global word line group GWL1_G1 and the first local word line group LWL1_G1, and then the second set of voltages VG2 can be applied to the second global word line group GWL1_G2 and the second local word line group LWL1_G2. In this way, the nth set of voltages VGn can be applied to the nth global word line group GWL1_Gn and the nth local word line group LWL1_Gn.

[0078] As shown in the figure, the first group of voltages VG1 to the nth group of voltages VGn can be the same, and according to one embodiment, the first group of voltages VG1 to the nth group of voltages VGn can be different from each other.

[0079] According to one implementation, the order in which the first group of voltages VG1 to the nth group of voltages VGn are applied may differ from the order shown.

[0080] Therefore, as the first group of voltages VG1 to the nth group of voltages VGn, which are much lower than the target level VTG, are applied to the first local word line group LWL1_G1 to the nth local word line group LWL1_Gn, the memory cells of the target memory block MB1 can be erased.

[0081] In the fourth time period S4, bit line BL, local word line LWL1, and global word line GWL can discharge to ground voltage VSS. After bit line BL, local word line LWL1, and global word line GWL discharge to ground voltage VSS, global select line GSL can discharge to ground voltage VSS. When global select line GSL discharges to ground voltage VSS, ground voltage VSS can be applied to local select line LSL1. Afterward, block select signal BSS can be disabled to ground voltage VSS.

[0082] According to one implementation, when the target memory block MB1 also includes one or more dummy local word lines, the dummy local word lines can be controlled in a similar manner to the local selection line LSL1.

[0083] According to this disclosure, during the first time period S1 when the erase voltage VER rises, the local word line LWL1 is floated, thus preventing uneven erasure of memory cells despite interruptions and recoveries in the repeated erase operation. Furthermore, by applying a more stable first voltage V1 to the floated local word line LWL1 in the second time period S2 before applying the first group of voltages VG1 to the nth group of voltages VGn in the third time period S3 for actual erasure, the erase operation can be performed more stably.

[0084] Figure 6 This is a flowchart illustrating a method for performing an erase operation on a memory device 10 according to one embodiment of the present disclosure.

[0085] Reference Figures 1 to 6 In operation S110, during the rise period of the erase voltage VER, the peripheral circuit 100 can float the local word line LWL1 connected to the target memory block MB1. Specifically, to float the local word line LWL1, the peripheral circuit 100 can apply a second voltage V2 as the block select signal BSS corresponding to the target memory block MB1, and can apply a third voltage V3 to the global word line GWL. The second voltage V2 can be lower than the third voltage V3. When the local word line LWL1 is floating, the peripheral circuit 100 can also float the local select line LSL1 connected to the target memory block MB1.

[0086] In operation S120, after the rising phase, the peripheral circuit 100 may apply a first voltage V1 to the local word line LWL1. The capacitance of the first voltage V1 may be greater than the capacitance of each of the first group voltages VG1 to the nth group voltages VGn. The first voltage V1 may be higher than the first group voltages VG1 to the nth group voltages VGn. The first voltage V1 may be lower than the second voltage V2 and the third voltage V3.

[0087] In operation S130, the peripheral circuit 100 can apply a first group of voltages VG1 to the nth group of voltages VGn to the local word line LWL1. Specifically, the peripheral circuit 100 can sequentially apply the first group of voltages VG1 to the nth group of local word lines LWL1_G1 to the nth group of local word lines LWL1_Gn. As the first group of voltages VG1 to the nth group of voltages VGn are applied to the local word line LWL1, the memory cells of the target memory block MB1 can be substantially erased.

[0088] Those skilled in the art to which this disclosure pertains will understand that this disclosure can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, the above embodiments should not be construed as restrictive, but rather as illustrative in all respects. The scope of this disclosure is set forth in the appended claims rather than in the specific embodiments, and it should be understood that all modifications or variations derived from the meaning and scope of this disclosure and its equivalents are included within the scope of the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

[0089] Cross-references to related applications

[0090] This application claims priority to Korean Patent Application No. 10-2022-0031969, filed on March 15, 2022, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Target storage block; as well as The peripheral circuitry, during the erase operation, causes a local word line connected to the target memory block to float as the erase voltage rises toward the target level. During the erase operation and after the erase voltage reaches the target level, a first voltage is applied to the local word line, and one or more groups of voltages are applied to the local word line during the erase operation and after the first voltage is applied. Wherein, the one or more group voltages correspond to the corresponding local word line groups obtained by grouping the local word lines.

2. The memory device according to claim 1, wherein, The first voltage is higher than each of the one or more groups of voltages.

3. The memory device according to claim 1, wherein, The peripheral circuit floats the local word line by applying a second voltage as a block select signal corresponding to the target memory block and applying a third voltage to the global word line connected to the local word line in response to the block select signal.

4. The memory device according to claim 3, wherein, The second voltage is lower than the third voltage.

5. The memory device according to claim 3, wherein, The first voltage is lower than the second voltage and the third voltage.

6. The memory device according to claim 1, wherein, The peripheral circuitry applies one or more group voltages to the corresponding local word line group.

7. The memory device according to claim 1, wherein, The peripheral circuit also floats the local select line connected to the target memory block when it floats the local word line.

8. The memory device according to claim 7, wherein, The peripheral circuit also keeps the local selection line floating during the application of the first voltage and the one or more group voltages.

9. A memory device, the memory device comprising: A voltage supply circuit, wherein the voltage supply circuit provides one or more groups of voltages and a first voltage; as well as A decoder, during an erase operation on a target memory block, floats a local word line connected to the target memory block as the erase voltage rises toward a target level; applies the first voltage to the local word line during the erase operation and after the erase voltage reaches the target level; and applies one or more groups of voltages to the local word line during the erase operation and after applying the first voltage. Wherein, the one or more group voltages correspond to the corresponding local word line groups obtained by grouping the local word lines.

10. The memory device according to claim 9, wherein, The voltage supply circuit applies the erase voltage to the source line of the target memory block before applying the first voltage to the local word line during the erase operation.

11. The memory device according to claim 9, wherein, The first voltage is higher than the voltage of the one or more groups.

12. A method for operating a memory device, the method comprising the steps of: During the rise phase of the erase voltage, the local word line connected to the target memory block to which the erase operation is being performed is floated; During the erase operation and after the rise period of the erase voltage, a first voltage is applied to the local word line; as well as During the erase operation and after the first voltage is applied to the local word line, one or more groups of voltages are applied to the local word line. Wherein, the one or more group voltages correspond to the corresponding local word line groups obtained by grouping the local word lines.

13. The method according to claim 12, wherein, The first voltage is higher than the voltage of the one or more groups.

14. The method according to claim 12, wherein, The step of making the local word line float includes the following steps: A second voltage is applied as a block selection signal corresponding to the target memory block; and A third voltage is applied to the global word line that is connected to the local word line in response to the block select signal.

15. The method according to claim 14, wherein, The second voltage is lower than the third voltage.

16. The method of claim 14, wherein, The first voltage is lower than the second voltage and the third voltage.

17. The method according to claim 12, wherein, One or more group voltages are applied to the corresponding local word line group.

18. The method according to claim 12, further comprising the step of: During the floating of the local word line, the local select line connected to the target memory block is floated; as well as During the application of the first voltage and the one or more group voltages, the local selection line is kept floating.

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