Memory device and method of programming operation thereof

Abstract

The present application relates to memory devices and methods of programming operation thereof. A memory device includes an array of memory cells including a plurality of memory cells, a peripheral circuit coupled to the array of memory cells by word lines and bit lines and adapted to perform one or more programming cycles on the memory cells coupled to selected ones of the word lines, each programming cycle including a program voltage application operation and a program verify operation, and a program control circuit adapted to control the peripheral circuit to reduce a level of a precharge voltage applied to the bit lines during the program verify operation when a number of programming cycles performed is greater than a reference number.

Description

Technical Field

[0001] Various embodiments of the present invention relate to semiconductor design techniques, and more specifically, to programming operations for a non-volatile memory device. Background Technology

[0002] Memory devices can be classified into volatile memory devices and non-volatile memory devices.

[0003] Non-volatile memory devices perform read / write operations at a relatively lower speed than volatile memory devices, but retain the stored data even when the power is cut off. Therefore, non-volatile memory devices are often used in portable electronic devices to store data that needs to be retained regardless of whether the device is powered on.

[0004] Examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0005] Flash memory can store a single bit of data or two or more bits of data in a single memory cell. Typically, a memory cell storing a single bit of data is called a single-level cell (SLC), and a memory cell storing two or more bits of data is called a multi-level cell (MLC). SLCs have erase and program states depending on a threshold voltage. MLCs have erase and multiple program states depending on a threshold voltage.

[0006] Recently, various methods have been tried to reduce current consumption during flash memory programming operations. Summary of the Invention

[0007] According to an embodiment of the present invention, a memory device includes: a memory cell array including a plurality of memory cells; peripheral circuitry connected to the memory cell array via word lines and bit lines, and adapted to perform one or more programming cycles on memory cells of selected word lines connected to the word lines, each programming cycle including a programming voltage application operation and a programming verification operation; and programming control circuitry adapted to control the peripheral circuitry to reduce the level of the pre-charge voltage applied to the bit lines during the programming verification operation when the number of programming cycles performed is greater than a reference number.

[0008] According to an embodiment of the present invention, a memory device includes: a memory cell array including a plurality of memory cells; peripheral circuitry connected to the memory cell array via word lines and bit lines, and adapted to perform one or more programming cycles on memory cells of selected word lines connected to the word lines, each programming cycle including a programming voltage application operation and a programming verification operation; and programming control circuitry adapted to control the peripheral circuitry to reduce the level of the pre-charge voltage applied to the bit lines during the programming verification operation when the number of programming cycles performed is less than or equal to a reference number.

[0009] According to an embodiment of the present invention, a method for programming a memory device includes the following steps: setting programming enable voltages and programming disable voltages for multiple bit lines; performing a programming voltage application operation that applies a programming voltage to a memory cell connected to a selected word line among the multiple word lines; and performing a programming verification operation that verifies the programming result by pre-charging the bit lines using a pre-charge voltage and applying a verification voltage to the memory cell connected to the selected word line, wherein the setting, programming voltage application, and programming verification operations are repeatedly performed, and wherein the level of the pre-charge voltage during the programming verification operation is reduced when the number of programming cycles performed is greater than a reference number, and each programming cycle includes a programming voltage application operation and a programming verification operation.

[0010] According to an embodiment of the present invention, a method for programming a memory device includes the following steps: setting programming enable voltages and programming disable voltages for multiple bit lines; performing a programming voltage application operation that applies a programming voltage to a memory cell connected to a selected word line among the multiple word lines; and performing a programming verification operation that verifies the programming result by pre-charging the bit lines using a pre-charge voltage and applying a verification voltage to the memory cell connected to the selected word line, wherein the setting, programming voltage application, and programming verification operations are repeatedly performed, and wherein the level of the pre-charge voltage during the programming verification operation is reduced when the number of programming cycles performed is less than or equal to a reference number, and each programming cycle includes a programming voltage application operation and a programming verification operation. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 The block diagram shown is of the memory device.

[0013] Figure 3 It is shown Figure 2 A diagram representing the structure of multiple storage blocks.

[0014] Figure 4Aand Figure 4B This is a diagram illustrating an exemplary programming operation of a memory device.

[0015] Figure 5 This is a timing diagram illustrating the programming operation according to the Incremental Step Pulse Programming (ISPP) scheme.

[0016] Figure 6 This is a flowchart describing programming operations according to embodiments of the present disclosure.

[0017] Figure 7 It is shown Figure 6 The timing diagram of the programming operations.

[0018] Figure 8 This is a flowchart used to describe programming operations according to another embodiment of the present disclosure.

[0019] Figure 9 It is shown Figure 8 The timing diagram of the programming operations.

[0020] Figure 10A and Figure 10B This is a timing diagram illustrating programming operations according to another embodiment of the present disclosure.

[0021] Figure 11 This illustrates an embodiment according to the present disclosure. Figure 2 The configuration diagram of the programming control circuit.

[0022] Figure 12 This is a diagram illustrating the configuration of a page buffer according to an embodiment of the present disclosure.

[0023] Figure 13 This is a flowchart describing programming operations according to embodiments of the present disclosure.

[0024] Figure 14A and Figure 14B This is a graph showing the current consumption according to a programming cycle according to an embodiment of the present invention. Detailed Implementation

[0025] The specific structural and functional descriptions provided herein relate to embodiments of this disclosure. However, the invention is not limited to the embodiments described herein.

[0026] Although embodiments have been described in detail, the invention is not limited to any specific details. This disclosure may be embodied in many different forms and should not be construed as limited to any specific description. Rather, the invention should be construed as covering not only the disclosed embodiments, but also various alternatives, modifications, equivalents, and other embodiments falling within the spirit and scope of this disclosure.

[0027] It will be understood that although the terms “first,” “second,” etc., may be used herein to identify various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another element that originally had the same or similar name. Without departing from the teachings of this disclosure, a first element in one instance may be referred to as a second element in another instance.

[0028] It will be understood that when an element is referred to as "connected" or "attached" to another element, it may be directly connected to or attached to the other element, or there may be one or more intermediate elements between them. Conversely, it should be understood that when an element is referred to as "directly connected" or "directly attached" to another element, there are no intermediate elements. Other expressions describing relationships between elements (e.g., "between," "directly between," "adjacent to," or "directly adjacent to") should be interpreted in the same way.

[0029] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting. In this disclosure, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, open-ended terms such as “comprising,” “including,” “having,” etc., specify the presence of the stated feature, integer, step, operation, element, component, and / or combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and should not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0031] Detailed descriptions of functions and structures well-known to those skilled in the art may be omitted to avoid obscuring the subject matter of this disclosure. This is intended to omit unnecessary descriptions so that the subject matter of this disclosure remains clear.

[0032] Various embodiments of the present disclosure are described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown, so that those skilled in the art may readily implement and practice the present disclosure.

[0033] Embodiments of the present invention relate to a memory device capable of adjusting the level of a precharge voltage applied to multiple bit lines during a programming verification operation based on the number of programming cycles performed, including programming voltage application operations and programming verification operations.

[0034] According to an embodiment of the present invention, the memory device can stabilize the average current consumption by reducing the internal current consumption (ICC) generated during programming verification operations.

[0035] Figure 1 This is a block diagram illustrating a memory system 10 according to an embodiment of the present disclosure.

[0036] Reference Figure 1 The memory system 10 may include a memory device 100 and a memory controller 200.

[0037] The storage system 10 can be configured to store data under the control of a host 30, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television (TV), tablet PC, or in-vehicle infotainment system.

[0038] Depending on the host interface, which serves as the communication system with host 30, the memory system 10 can be implemented as any of various types of storage devices. For example, the memory system 10 can be configured as any of various types of storage devices, such as SSD, MMC, eMMC, RS-MMC or Micro MMC multimedia cards, SD, mini SD, Micro SD type secure digital card, Universal Serial Bus (USB) storage devices, Universal Flash Memory (UFS) devices, PCMCIA card type storage devices, Peripheral Component Interconnect (PCI) card type storage devices, High Speed ​​PCI (PCI-e or PCIe) type storage devices, Compact Flash Memory (CF) cards, Smart Media Cards and / or Memory Sticks.

[0039] The memory system 10 can be manufactured in any of the various package types. For example, the memory system 10 can be manufactured as a stacked package (POP), a system-in-package (SIP), a system-on-a-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabrication package (WFP), and / or a wafer-level stacked package (WSP).

[0040] Data can be stored in the memory device 100. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array, which includes a plurality of memory cells configured to store data therein. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may be a unit for erasing data stored in the memory device 100. In an embodiment, a memory block may include a plurality of pages. A page may be a unit for storing data in or reading data from the memory device 100.

[0041] In embodiments, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Torque Random Access Memory (STT-RAM). In this specification, as an example, it is assumed that the memory device 100 is NAND flash memory.

[0042] In an embodiment, the memory device 100 may be specifically implemented as a three-dimensional array structure. This disclosure is applicable not only to flash memory where the charge storage layer is formed by a conductive floating gate (FG), but also to charge-trapped flash memory (CTF) where the charge storage layer is formed by an insulating layer.

[0043] The memory device 100 can receive commands and addresses from the memory controller 200 and access address-selectable regions of the memory cell array. In other words, the memory device 100 can perform operations corresponding to commands on the address-selectable regions. For example, the memory device 100 can perform programming operations, read operations, and erase operations. During a programming operation, the memory device 100 can store data in the address-selectable memory cell region. During a read operation, the memory device 100 can read the stored data from the address-selectable memory cell region. During an erase operation, the memory device 100 can erase data from the address-selectable memory cell region.

[0044] In an embodiment, the memory device 100 may include a programming control circuit 132. The memory device 100 may perform a programming operation to store data in a memory cell region according to programming commands provided by a memory controller 200. The programming operation may include one or more programming cycles. Each programming cycle may include a programming voltage application operation for applying a programming voltage and a programming verification operation for verifying the programming result using a verification voltage. The programming control circuit 132 may control the number of programming cycles executed according to the programming state to improve programming performance. Furthermore, during the programming verification operation, all bit lines may be precharged to a precharge voltage. In an embodiment, the programming control circuit 132 may adjust the level of the precharge voltage applied to the bit lines during the programming verification operation according to the number of programming cycles executed, thereby reducing internal current consumption (ICC). The detailed configuration and operation of a memory device according to an embodiment of the present invention will be described using the accompanying drawings described below.

[0045] The storage controller 200 controls the overall operation of the storage system 10. When power is applied to the storage system 10, the storage controller 200 executes firmware (FW). In the case that the storage device 100 is a flash memory device, the storage controller 200 executes firmware such as a flash translation layer (FTL) to control communication between the host 30 and the storage device 100.

[0046] If a write request is received from host 30, storage controller 200 can receive the data to be stored and a logical address used to identify the corresponding data from host 30. Storage controller 200 can translate the input logical address into a physical address to indicate the physical address of the memory cell in memory device 100 where the data to be stored is located. Storage controller 200 can provide storage device 100 with programming commands for storing data, the translated physical address, and the data to be stored.

[0047] If a read request is received from host 30, storage controller 200 can receive a logical address from host 30 to identify the data to be read. Storage controller 200 can obtain the physical address corresponding to the input logical address and can provide a read command and physical address to storage device 100.

[0048] During the erase operation, the storage controller 200 may provide the memory device 100 with erase commands and physical addresses.

[0049] In this implementation, regardless of the request from the host 30, the storage controller 200 can autonomously control the storage device 100 to perform programming, reading, or erasing operations. For example, the storage controller 200 can control the storage device 100 to perform background operations such as wear leveling, garbage collection, and read recycling.

[0050] The host 30 may communicate with the memory system 10 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM) and / or Unloaded DIMM (LRDIMM).

[0051] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 Block diagram of the memory device 100 shown.

[0052] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may include... Figure 1 The programming control circuit 132.

[0053] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may have a three-dimensional (3D) structure. Each of the memory blocks BLK1 to BLKz may include multiple memory cells stacked on a substrate. The memory blocks BLK1 to BLKz may be connected to the peripheral circuitry 120 via multiple row lines RL and via multiple bit lines BL1 to BLn. The memory blocks BLK1 to BLKz may be collectively connected to the first bit line BL1 to the nth bit line BLn.

[0054] In this implementation, the multiple memory cells may be non-volatile memory cells. A row line RL may include at least one source select line, multiple word lines, and at least one drain select line. Memory cells connected to the same word line may be defined as a page. Therefore, each memory block may include multiple pages.

[0055] Each memory cell in the memory cell array 110 can be configured as a single-level cell (SLC) capable of storing a single bit of data or a multi-level cell (MLC) capable of storing two or more bits of data.

[0056] Peripheral circuitry 120 can perform programming, reading, or erasing operations on selected regions of memory cell array 110 under the control of control logic 130. Peripheral circuitry 120 can drive memory cell array 110. For example, under the control of control logic 130, peripheral circuitry 120 can apply various operating voltages to row lines RL and first bit lines BL1 through nth bit lines BLn, or discharge the applied voltages. Programming operations may include one or more programming cycles. Each programming cycle may include a programming voltage application operation for applying a programming voltage and a programming verification operation for verifying the programming result using a verification voltage. Peripheral circuitry 120 can perform one or more programming cycles (including programming voltage application and programming verification operations) on memory cells connected to a selected row line RL.

[0057] In detail, the peripheral circuit 120 may include a row decoder 121, a voltage generation circuit 122, a page buffer group 123, a column decoder 124, a data input / output circuit 125, and a sensing circuit.

[0058] Row decoder 121 can be connected to memory cell array 110 via row line RL. Row decoder 121 operates under the control of control logic 130. Row decoder 121 can receive row address RADD from control logic 130. In one embodiment, row decoder 121 can decode row address RADD to select at least one of memory blocks BLK1 to BLKz. In another embodiment, row decoder 121 can decode row address RADD to select any row line RL of the selected memory block, and can transmit the operating voltage Vop generated by voltage generation circuit 122 to the selected row line RL.

[0059] For example, during a programming voltage application operation, the row decoder 121 can apply a programming voltage to the selected word line and apply a programming pass voltage (at a level lower than the programming voltage) to the unselected word line. During a programming verification operation, the row decoder 121 can apply a verification voltage to the selected word line and apply a verification pass voltage (at a level higher than the verification voltage) to the unselected word line. During a read operation, the row decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage (at a level higher than the read voltage) to the unselected word line. During an erase operation, the row decoder 121 can decode the row address RADD to select a memory block. During an erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0060] In an implementation, the line decoder 121 may include components such as an address buffer, a decoder, etc.

[0061] The voltage generating circuit 122 can generate multiple voltages using the external supply voltage supplied to the memory device 100. The voltage generating circuit 122 can operate under the control of the control logic 130. Specifically, according to the operation signal OPSIG, the voltage generating circuit 122 can generate operating voltages Vop for programming, reading, and erasing operations. For example, the voltage generating circuit 122 can generate programming voltage, verification voltage, pass voltage, verification pass voltage, read voltage, and erase voltage.

[0062] According to one embodiment, the voltage generating circuit 122 can generate an internal supply voltage by adjusting an external supply voltage. The internal supply voltage generated by the voltage generating circuit 122 can be used as the operating voltage of the memory device 100. According to one embodiment, the voltage generating circuit 122 can use either an external supply voltage or an internal supply voltage to generate the operating voltage Vop. For example, the voltage generating circuit 122 may include a plurality of pump capacitors for receiving the internal supply voltage, and the operating voltage Vop can be generated by selectively activating the plurality of pump capacitors under the control of the control logic 130. The generated operating voltage Vop can be supplied to the memory cell array 110 by the row decoder 121.

[0063] Page buffer group 123 may include first page buffer PB1 to nth page buffer PBn. First page buffer PB1 to nth page buffer PBn may be connected to memory cells of memory cell array 110 via bit lines BL. First page buffer PB1 to nth page buffer PBn may operate under the control of control logic 130. For example, first page buffer PB1 to nth page buffer PBn may operate in response to page buffer control signal PBSIGNALS. First page buffer PB1 to nth page buffer PBn may temporarily store data transmitted via first bit line BL1 to nth bit line BLn and sense the voltage or current of first bit line BL1 to nth bit line BLn.

[0064] In this implementation, during the programming voltage application operation, when the programming voltage is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn can receive data to be stored in the memory cell array 110 from the data input / output circuit 125 via the data line DL. The data received from the first page buffer PB1 to the nth page buffer PBn can be stored in the memory cell of the selected word line. The threshold voltage of the memory cell connected to the bit line to which a programming enable voltage (e.g., ground voltage) is applied can be increased, and the threshold voltage of the memory cell connected to the bit line to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained.

[0065] In this implementation, during the programming verification operation, the first page buffer PB1 to the nth page buffer PBn can read data from the selected memory cell via the first bit line BL1 to the nth bit line BLn. During the programming verification operation, the first page buffer PB1 to the nth page buffer PBn can precharge all bit lines to the precharge voltage. In this implementation, the first page buffer PB1 to the nth page buffer PBn can adjust the level of the precharge voltage applied to the bit lines during the programming verification operation according to the buffer control signal PBSIGNALS, thereby reducing internal current consumption (ICC).

[0066] In this implementation, during a read operation, the first page buffer PB1 to the nth page buffer PBn can read data from the selected memory cell via the first bit line BL1 to the nth bit line BLn, and the read data can be output to the data input / output circuit 125 under the control of the column decoder 124. During an erase operation, the first page buffer PB1 to the nth page buffer PBn can float the first bit line BL1 to the nth bit line BLn.

[0067] The column decoder 124 operates under the control of control logic 130. The column decoder 124 can transfer data between the data input / output circuitry 125 and the page buffer group 123 in response to the column address CADD provided from control logic 130. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the nth page buffer PBn via data lines DL, or it can exchange data with the data input / output circuitry 125 via column lines CL.

[0068] Data input / output circuit 125 can input / output data from / to... Figure 1 The storage controller 200 receives / outputs data. Data input / output circuitry 125 is connected to the first page buffer PB1 through the nth page buffer PBn via data lines DL. Data input / output circuitry 125 operates under the control of control logic 130. According to an embodiment, data input / output circuitry 125 may include multiple input / output buffers (not shown) that receive / output data in response to input / output control signals DIO provided from control logic 130. During programming operations, data input / output circuitry 125 may receive data to be stored from storage controller 200. During read operations, data input / output circuitry 125 may output data from the first page buffer PB1 through the nth page buffer PBn to storage controller 200.

[0069] The sensing circuit 126 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal PASS or a failure signal FAIL to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0070] Control logic 130 can be connected to row decoder 121, voltage generation circuit 122, page buffer group 123, column decoder 124, data input / output circuit 125, and sensing circuit 126. Control logic 130 controls the overall operation of memory device 100. Control logic 130 operates in response to commands CMD and addresses ADDR sent from external devices. Control logic 130 can control peripheral circuits 120 by generating various types of signals in response to commands CMD and addresses ADDR. For example, control logic 130 can generate operation signals OPSIG, row address RADD, page buffer control signals PBSIGNALS, column address CADD, input / output control signals DIO, and enable bit signals VRYBIT in response to commands CMD and addresses ADDR. Control logic 130 can output the operation signal OPSIG to the voltage generation circuit 122, the row address RADD to the row decoder 121, the page buffer control signal PBSIGNALS to the page buffer group 123, the column address CADD to the column decoder 124, the input / output control signal DIO to the data input / output circuit 125, and the enable bit signal VRYBIT to the sensing circuit 126. Additionally, control logic 130 can determine whether the verification operation has passed or failed in response to the pass signal PASS or the failure signal FAIL output from the sensing circuit 126.

[0071] In an implementation, control logic 130 may include programmable control circuitry 132.

[0072] Sensing circuit 126 can output a pass signal PASS or a failure signal FAIL to control logic 130, indicating whether the programming verification operation has passed or failed. Programming control circuit 132 can provide page buffer control signal PBSIGNALS to page buffer group 123 in response to the pass signal PASS or the failure signal FAIL, to control the precharge voltage of the first bit line BL1 to the nth bit line BLn during the programming verification operation. For example, when the failure signal FAIL is input to control logic 130, programming control circuit 132 can determine whether the number of programming cycles performed is greater than a preset reference number, and can provide page buffer control signal PBSIGNALS to the first page buffer PB1 to the nth page buffer PBn to adjust the level of the precharge voltage applied to the first bit line BL1 to the nth bit line BLn during the programming verification operation based on the determination result.

[0073] Figure 3 It is shown Figure 2 A diagram showing the structure of the representative storage block BLKi among the multiple storage blocks BLK1 to BLKz.

[0074] Reference Figure 3In a memory block BLKi, multiple word lines WL1 to WL16 arranged in parallel to each other can be connected between a first select line SSL and a second select line DSL. The first select line can be a source select line, and the second select line DSL can be a drain select line. More specifically, the memory block BLKi may include multiple string STs connected between multiple bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be individually connected to string STs, and the source line SL can be collectively connected to string STs. String STs can have the same configuration; therefore, a string ST connected to the first bit line BL1 is described in detail as an example.

[0075] A string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. Each string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and each string ST may include more than sixteen memory cells (i.e., Figure 3 (as shown in MC1 to MC16).

[0076] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST in different string STs can be connected to the source select line SSL. The gate of the drain select transistor DST can be connected to the drain select line DSL. The gate of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. Among the memory cells in different string STs, a group of memory cells connected to each word line can be called a physical page PG. Therefore, the number of physical pages PG in memory block BLKi corresponds to the number of word lines WL1 to WL16.

[0077] exist Figure 3 In this context, the source line SL, source select line SSL, word lines WL1 to WL16, and drain select line DSL can correspond to... Figure 2 The row line RL. That is, the source line SL, source select line SSL, word lines WL1 to WL16, and drain select line DSL can be generated by... Figure 2 The line decoder 121 is controlled. The common source line SL can be controlled by control logic 130.

[0078] When each memory cell is a single-level cell (SLC) capable of storing one bit of data, each physical page (PG) can store the data of one logical page (LPG). When each memory cell can store two or more bits of data, each physical page (PG) can store the data of two or more LPGs.

[0079] Figure 4A and Figure 4B This is a diagram illustrating an exemplary programming operation of a memory device.

[0080] Reference Figure 4A and Figure 4B This illustrates the programming operations for MLC and TLC memory cells. Programming operations can be used to store data into memory cells connected to selected word lines.

[0081] Figure 4A This is a graph showing the threshold voltage (Vth) distribution of an MLC memory cell, where each MLC memory cell can store two bits of data when a programming operation is performed.

[0082] Reference Figure 4A Each MLC memory cell can have an erase state E or any of the first programming states P1 through the third programming states P3 as its target programming state. The target programming state can be determined based on the data to be stored in each memory cell. Before performing a programming operation, each MLC memory cell can be in the erase state E. Subsequently, as the programming operation is performed, each MLC memory cell can reach the target programming state. Programming operations can be performed on individual pages comprising multiple memory cells connected to a word line. The memory cell array can include multiple pages. The page to be programmed among the multiple pages can be determined based on its address. If the programming operation on the corresponding page terminates, the programming operation on the subsequent pages can be performed.

[0083] Programming operations may include a programming voltage application operation and a programming verification operation. The programming voltage application operation may be an operation of applying a programming voltage to a selected word line that is commonly connected to a memory cell included in the corresponding page where the programming operation is to be performed. The programming verification operation may be an operation of using a verification voltage to verify the programming result. Memory cells each having a first programming state P1 as their target programming state may be memory cells that have passed the programming verification operation using a first multi-verification voltage Vmfy_1. Memory cells each having a second programming state P2 as their target programming state may be memory cells that have passed the programming verification operation using a second multi-verification voltage Vmfy_2. Memory cells each having a third programming state P3 as their target programming state may be memory cells that have passed the programming verification operation using a third multi-verification voltage Vmfy_3. If all memory cells connected to the selected word line have reached their target programming states, the programming operation on the selected word line may be considered terminated.

[0084] Figure 4BThis is a graph showing the threshold voltage (Vth) distribution of a TLC memory cell, where each TLC memory cell can store three bits of data when a programming operation is performed.

[0085] Reference Figure 4B Each TLC memory cell can have an erase state E or any one of the first programming states P1 to the seventh programming states P7 as the target programming state. Although the method of performing the programming operation is different... Figure 4A Similarly, but the number of threshold voltage distributions to be generated during programming operations on TLC memory cells can be greater than the number to be generated during programming operations on MLC memory cells, because each TLC memory cell can store three bits of data. In other words, refer to Figure 4A and Figure 4B When programming an MLC memory cell is completed, a total of four threshold voltage distributions can be generated. However, when programming a TLC memory cell is completed, a total of eight threshold voltage distributions can be generated. Although the amount of data that can be stored in a TLC memory cell is greater than the amount of data that can be stored in an MLC memory cell, the programming time for a TLC memory cell can be longer than that for an MLC memory cell because the number of threshold voltage distributions that need to be generated for a TLC memory cell is greater than the number of threshold voltage distributions that need to be generated for an MLC memory cell. Although the memory cells will be assumed to be TLC memory cells in the following embodiments for illustrative purposes, the invention is not limited thereto.

[0086] In addition, programming operations can be performed using an incremental step pulse programming (ISPP) scheme, in which the level of the programming voltage to be applied to the selected word line is increased by a predetermined step voltage Vstep as the programming cycle is executed.

[0087] Figure 5 This is a timing diagram illustrating the programming operations according to the ISPP scheme.

[0088] Reference Figure 5 The memory cell to be programmed can have any one of the first programming state P1 to the seventh programming state P7 as the target programming state.

[0089] Programming operations can be operations that increase the threshold voltage of a memory cell. Programming operations can be performed through iterations of at least one programming cycle PL. Each programming cycle may include a programming voltage application operation (applying a programming voltage) and a programming verification operation (determining whether the threshold voltage of the memory cell exceeds a verification voltage). The programming voltage application operation can be an operation that increases the threshold voltage of the memory cell. The programming verification operation can be an operation that checks the threshold voltage of the corresponding memory cell and determines whether the memory cell has reached the target programming state. In each iteration of the programming cycle PL, the level of the programming voltage to be applied to the selected word line can be increased by a predetermined step voltage Vstep. This scheme is called the ISPP scheme.

[0090] In detail, it can be responded to by reference. Figure 1 The described memory controller 200 provides programming commands to perform programming operations on memory cells connected to selected word lines. Before performing the programming operation, the memory cells connected to the selected word lines may be in an erase state E. As the programming operation is performed, the threshold voltage distribution of the memory cells may shift. In other words, the threshold voltage distribution of memory cells other than those in the erase state E, which have the first programming state P1 to the seventh programming state P7 as target programming states, may shift.

[0091] The following is a detailed description of performing a programming operation on a selected word line according to an embodiment. To perform the programming operation, a programming cycle can be executed on memory cells each having a first programming state P1 as the target programming state. The voltage of the bit line connected to the memory cell each having the first programming state P1 as the target programming state can be set to a programming enable voltage (e.g., ground voltage). If the first programming voltage Vp1 is applied to the selected word line, the corresponding memory cell can be programmed. Subsequently, a programming verification operation can be performed to verify the result of programming the memory cell to the first programming state P1. During the programming verification operation, a first verification voltage Vfy_1 can be applied to the selected word line to sense whether the threshold voltage of the memory cell is greater than the verification voltage. For example, if the sensing result indicates "1", this may mean that the threshold voltage of the memory cell is lower than the first verification voltage Vfy_1. If it is determined that the threshold voltage of the memory cell having the first programming state P1 as the target programming state is lower than the first verification voltage Vfy_1, this may indicate that the programming operation has failed. If the sensing result indicates "0", this may mean that the threshold voltage of the memory cell is greater than the first verification voltage Vfy_1. If the threshold voltage of a memory cell with the first programming state P1 as the target programming state is determined to be higher than the first verification voltage Vfy_1, this indicates that the programming operation has passed.

[0092] If the result of the programming verification operation indicates that the programming operation for the first programming state P1 has failed, a subsequent programming cycle PL can be executed. The voltage of the bit line connected to the memory cell whose programming operation failed can be set as the programming enable voltage. In the subsequent programming cycle PL, a programming voltage higher than the programming voltage applied to the selected word line in the previous programming cycle PL by a step voltage Vstep can be applied to the selected word line. In the ISPP scheme, a second programming voltage Vp2 higher than the first programming voltage Vp1 applied to the selected word line in the previous programming cycle PL by a step voltage Vstep can be applied to the selected word line. The step voltage Vstep can be a fixed value. After the second programming voltage Vp2 has been applied, the programming verification operation to check whether the memory cell has been programmed to the first programming state P1 can be performed again. In the same manner as the previous programming verification operation, the first verification voltage Vfy_1 can be applied to the selected word line. Therefore, the threshold voltage of the memory cell can be sensed. In the implementation, the magnitude of the step voltage Vstep, which is the increment of the programming voltage, may vary with each iteration of the programming cycle PL. For example, in a previous programming cycle PL, suppose that for each applied programming cycle, the programming voltage increases by a single unit step voltage Vstep. If the result of performing a programming verification operation indicates that the programming operation has failed, then in a subsequent programming cycle PL, a programming voltage that increases by 2 units Vstep, instead of the single unit step voltage Vstep of the previous programming cycle PL, can be applied to the selected word line.

[0093] In this implementation, the programming verification operation performed in each programming cycle PL can use two or more verification voltages. In other words, after a programming voltage has been applied, a memory cell with two or more programming states as the target programming state can be verified. For example, after a third programming voltage Vp3 has been applied to the selected word line, a programming verification operation for the first programming state P1 and the second programming state P2 can be performed. To verify the result of the programming operation for the first programming state P1, a first verification voltage Vfy_1 can be applied to the selected word line. Therefore, the threshold voltage of the memory cell can be sensed. Subsequently, to verify the result of the programming operation for the second programming state P2, a second verification voltage Vfy_2 can be applied to the selected word line. Therefore, the threshold voltage of the memory cell can be sensed. If the sensing result indicates 1, the programming operation can be considered a failure. In this case, the programming voltage to be applied to the selected word line can be increased by a step voltage Vstep, and then the subsequent programming cycle PL can be executed.

[0094] As a result of the programming voltage application and programming verification operations, memory cells determined to have passed the verification are no longer programmed in subsequent programming cycles (PL). Therefore, a programming disable voltage (e.g., power supply voltage) can be applied to the bit lines connected to memory cells that have passed the programming verification operation before applying the programming voltage in subsequent programming cycles (PL). Even if a programming voltage is applied to the corresponding word line, memory cells connected to bit lines with applied programming disable voltages will not be programmed. This prevents overprogramming.

[0095] Furthermore, during the programming verification operation, when a verification voltage is applied to the selected word line after all bit lines have been precharged, pass or failure can be identified based on the cell current flowing through the precharged bit lines. Because all bit lines are precharged during the programming verification operation, the internal current consumption (ICC) increases rapidly. Specifically, when a memory cell stores two or more bits of data, the current consumption can increase towards the latter half of the repetitive programming cycle. Therefore, the internal current consumption can increase even more rapidly.

[0096] Hereinafter, according to an embodiment of the present invention, when two or more bits of data are stored in a memory cell, a method for reducing internal current consumption by decreasing the level of the pre-charge voltage applied to the bit line during the programming verification operation will be described.

[0097] Figure 6 This is a flowchart describing programming operations according to embodiments of the present disclosure.

[0098] Reference Figure 6 The peripheral circuit 120 can decode the row address RADD provided from the control logic 130 to select any word line to perform the programming operation (in S710). In an embodiment, a first word line (e.g., WL1) can be selected first in the memory block.

[0099] The peripheral circuit 120 can perform a programming cycle on the memory cell connected to the selected word line under the control of the control logic 130.

[0100] First, peripheral circuitry 120 may perform bit line setting operations (in S720) in response to the page buffer control signal PBSIGNALS provided from control logic 130. For example, peripheral circuitry 120 may set the programming enable voltage to ground and the programming disable voltage to the power supply voltage. Peripheral circuitry 120 may apply the programming enable voltage to the bit line of the programming target cell and may apply the programming disable voltage to the bit line of the programming disable cell.

[0101] In response to the operation signal OPSIG provided from the control logic 130, the peripheral circuit 120 can apply a programming voltage to the selected word line and can apply a programming voltage to the unselected word line. Therefore, a programming voltage application operation can be performed on the memory cell connected to the selected word line (in S730).

[0102] Another cell string ST can be connected to a bit line connected to the cell string ST in the memory block that includes the programming target cell. Additionally, cell strings ST sharing bit lines in the memory block can share word lines. Therefore, the programming enable voltage, programming voltage, and programming pass voltage can be applied equally to the cell string ST sharing the bit lines. To program only the selected cell string ST while disabling programming of the remaining unselected cell strings ST, the peripheral circuit 120 can apply an on-state voltage (e.g., power supply voltage) to the drain select line DSL of the selected cell string ST and an off-state voltage (e.g., ground voltage) to the drain select line DSL of the remaining unselected cell strings ST. As a result, since the channel region of the selected cell string ST remains grounded, the threshold voltage of the programming target cell can increase according to the difference from the programming voltage. Furthermore, since the channel region of the unselected cell strings ST becomes floating, a channel boost occurs, and the threshold voltage of the programming disable cell does not increase as the channel voltage increases.

[0103] Subsequently, peripheral circuitry 120, under the control of control logic 130, performs a programming verification operation on the memory cell connected to the selected word line (in S740). First, peripheral circuitry 120 precharges all bit lines by applying a precharge voltage to the bit lines in response to the page buffer control signal PBSIGNALS. Then, in response to the operation signal OPSIG, peripheral circuitry 120 applies a verification voltage to the selected word line while simultaneously applying a verification pass voltage to the unselected word line. Peripheral circuitry 120 senses the cell current flowing through the bit line based on the sense voltage VPB and outputs a pass signal PASS or a failure signal FAIL to control logic 130 based on the sensing result.

[0104] Control logic 130 can respond to the pass signal PASS or the failure signal FAIL to determine whether the programming verification operation passes or fails (in S750).

[0105] When the programming verification operation fails (S750 is "No"), control logic 130 verifies whether the number of times the programming cycle was executed (i.e., the number of times the programming cycle was executed) is greater than a preset reference number. When the number of times the programming cycle was executed is less than or equal to the reference number (S760 is "No"), peripheral circuit 120 increases the level of the programming voltage applied to the selected word line by a predetermined step voltage Vstep (in S780) in response to the operation signal OPSIG. Thereafter, steps S720 to S750 can be repeated. For reference, although... Figure 6As not shown in the diagram, when the number of times the programming loop is executed reaches the maximum allowed number, the programming operation of the selected word line can be terminated as a failure.

[0106] When the number of programming cycles executed exceeds a reference number (S760 is "Yes"), control logic 130 can control peripheral circuitry 120 to reduce the level of the precharge voltage applied to the bit line during the programming verification operation (in S770). For example, control logic 130 can provide a page buffer control signal PBSIGNALS to page buffer group 123 during the programming verification operation in step S740 to reduce the level of the precharge voltage by a first level Vpre. At this time, the memory cells in memory cell array 110 can be configured as MLC memory cells capable of storing two or more bits of data. Subsequently, peripheral circuitry 120 can increase the level of the programming voltage by a step voltage Vstep (in S780), and steps S720 to S750 can be repeated.

[0107] Once it is determined that the programming verification operation has passed (S750 is "Yes"), the programming operation for the selected word line can be completed.

[0108] Figure 7 It is shown Figure 6 The timing diagram of the programming operations.

[0109] Reference Figure 7 This illustrates the programming operation when storing two or more bits of data in a memory cell. The programming operation can be performed by repeating at least one programming cycle PL within a maximum allowed number of times (e.g., m times). A programming cycle PL may include a programming voltage application operation and one or more programming verification operations. See reference... Figure 5 As described, when performing programming operations using the ISPP scheme, the level of the programming voltage applied to the selected word line can be increased by a step voltage Vstep each time the programming cycle PL repeats.

[0110] When the number of times the programming cycle is executed exceeds the reference number, the level of the precharge voltage applied to the bit line during the programming verification operation of the programming cycle PL can be reduced by the first level Vpre.

[0111] In an embodiment of the present invention, as a method for adjusting the level of the pre-charge voltage applied to the bit line, the switches for connecting the page buffer and the bit line respectively can be adjusted and controlled. Figure 12The voltage level of the sensing control signal PBSENSE (410) can be controlled by the page buffer control signal PBSIGNALS provided from control logic 130. During programming verification operation, after providing a high voltage (VH) level sensing control signal PBSENS to fully turn on switch 410, control logic 130 can provide an intermediate voltage (VM) level sensing control signal PBSENS to apply a voltage higher than ground to the bit line to which a programming enable voltage (e.g., ground voltage) is applied. Subsequently, control logic 130 can provide a sensing control signal PBSENSE of the turn-on voltage VON during programming verification operation to apply a pre-charge voltage to the bit line. Then, control logic 130 can provide a sensing control signal PBSENSE of the turn-on voltage VON during programming verification operation to apply a pre-charge voltage to the bit line. In one implementation, if the number of programming loops performed exceeds a reference number, during the programming verification operation, control logic 130 can control the voltage level of the sensing control signal PBSENSE to decrease from the on-state voltage VON to a predetermined first level Vpb, thereby reducing the pre-charge voltage applied to the bit line to a first level Vpre. For example, as... Figure 7 As shown, when the reference number is set to 10, the voltage level of the sensing control signal PBSENSE in the programming verification operation from the 11th programming cycle can be reduced by a first level Vpb compared to the sensing control signal PBSENSE in the previous programming cycle (i.e., the 10th programming cycle).

[0112] As described above, in embodiments of the present invention, when a memory cell stores two or more bits of data, the level of the pre-charge voltage applied to the bit line can be reduced when the number of executed programming cycles exceeds a reference number. Therefore, the average current consumption can be stabilized by reducing the internal current consumption generated during the programming verification operation.

[0113] Figure 8 This is a flowchart used to describe programming operations according to another embodiment of the present disclosure.

[0114] Reference Figure 8 The peripheral circuit 120 can select any word line to perform the programming operation (in S910).

[0115] The peripheral circuit 120 can perform a programming cycle on the memory cell connected to the selected word line. First, the peripheral circuit 120 performs a bit line setting operation (in S920) by applying a programming enable voltage to the bit line of the programming target cell and a programming disable voltage to the bit line of the programming disable cell.

[0116] The peripheral circuit 120 performs a programming voltage application operation on the selected word line by applying a programming voltage to the selected word line and applying a programming voltage to the unselected word line (in S930). See reference... Figure 6 As described, the peripheral circuit 120 can apply a turn-on voltage to the drain select line DSL of the selected cell string ST and a cut-off voltage to the drain select line DSL of the remaining unselected cell string ST, thereby raising the threshold voltage of the programming target cell without raising the threshold voltage of the programming disable cell.

[0117] Subsequently, peripheral circuitry 120 can perform programming verification operations on the selected word lines (in S940). Peripheral circuitry 120 can precharge all bit lines by applying a precharge voltage to the bit lines, and can apply a verification voltage to the selected word lines while applying a verification pass voltage to the unselected word lines. Peripheral circuitry 120 can sense the cell current flowing through the bit lines based on the sense voltage VPB, and can output a pass signal PASS or a failure signal FAIL to control logic 130 based on the sensing result.

[0118] Control logic 130 can respond to the pass signal PASS or the failure signal FAIL to determine whether the programming verification operation passed or failed (in S950).

[0119] When the programming verification operation fails (S950 is "No"), the control logic 130 verifies whether the number of times the programming cycle has been executed (i.e., the number of times the programming cycle has been executed) is less than or equal to the first reference number (R1). When the number of times the programming cycle has been executed is less than or equal to the first reference number (R1) (S960 is "Yes"), the peripheral circuit 120 increases the level of the programming voltage applied to the selected word line by a predetermined step voltage Vstep (in S980). Thereafter, steps S920 to S9750 can be repeated until the number of times the programming cycle has been executed reaches the maximum allowed number.

[0120] When the number of times the programming loop is executed is greater than the first reference number (R1) (S960 is "No"), the control logic 130 can verify whether the number of times the programming loop is executed is less than or equal to the second reference number (R2). At this time, the second reference number (R2) can be greater than the first reference number (R1).

[0121] When the number of programming cycles executed is less than or equal to the second reference number (R2) (S970 is "Yes"), control logic 130 can control peripheral circuitry 120 to reduce the level of the precharge voltage applied to the bit line during the programming verification operation (in S972). For example, control logic 130 can provide a page buffer control signal PBSIGNALS to page buffer group 123 during the programming verification operation in step S940 to reduce the level of the precharge voltage to a first level Vpre1. At this time, the memory cells in memory cell array 110 can be configured as MLC memory cells capable of storing two or more bits of data. Thereafter, peripheral circuitry 120 can increase the level of the programming voltage by a step voltage Vstep (in S980), and steps S920 to S950 can be repeated.

[0122] When the number of programming cycles executed is greater than the second reference number (R2) (S970 is "No"), control logic 130 can control peripheral circuitry 120 to reduce the level of the precharge voltage applied to the bit line during the programming verification operation (in S974). For example, control logic 130 can provide a page buffer control signal PBSIGNALS to page buffer group 123 during the programming verification operation in step S940 to reduce the level of the precharge voltage to a second level Vpre2. According to an embodiment, the first level Vpre1 ​​may have the same level as the second level Vpre2. According to an embodiment, the first level Vpre1 ​​may be set to a level different from the second level Vpre2. Thereafter, peripheral circuitry 120 can increase the level of the programming voltage by a step voltage Vstep (in S980), and steps S920 to S950 can be repeated.

[0123] Once it is determined that the programming verification operation has passed (S950 is "Yes"), the programming operation for the selected word line can be completed.

[0124] Figure 9 It is shown Figure 8 The timing diagram of the programming operations.

[0125] Reference Figure 9 This illustrates the programming operation when two or more bits of data are stored in a memory cell. When the number of programming cycles executed exceeds a first reference number (R1) and is less than or equal to a second reference number (R2), the level of the pre-charge voltage applied to the bit line during the programming verification operation of programming cycle PL can be reduced by a first level Vpre1. Furthermore, when the number of programming cycles executed exceeds the second reference number (R2), the level of the pre-charge voltage applied to the bit line during the programming verification operation of programming cycle PL can be reduced by a second level Vpre2.

[0126] In an embodiment of the invention, during a programming verification operation, control logic 130 can control the voltage level of the sensing control signal PBSENSE to decrease from the on-state voltage VON to a predetermined level Vpb1 or Vpb2, thereby reducing the pre-charge voltage applied to the bit line to a first level Vpre1 ​​or a second level Vpre2. For example, as Figure 9 As shown, when the first reference count (R1) is set to 10 and the second reference count (R2) is set to 11, the voltage level of the sensing control signal PBSENSE in the programming verification operation from the 11th programming cycle can be reduced by a first level Vpb1 compared to the sensing control signal PBSENSE in the previous programming cycle (i.e., the 10th programming cycle). Furthermore, compared to the sensing control signal PBSENSE in the previous programming cycle (i.e., the 11th programming cycle), the voltage level of the sensing control signal PBSENSE in the programming verification operation from the 12th programming cycle can be reduced by a second level Vpb2.

[0127] As described above, in embodiments of the present invention, multiple reference counts can be set, and the level of the pre-charge voltage applied to the bit line during the programming verification operation can be sequentially reduced whenever the number of executed programming cycles exceeds each reference count. Therefore, the average current consumption can be stabilized by reducing the internal current consumption generated during the programming verification operation.

[0128] Figure 10A and Figure 10B This is a timing diagram illustrating programming operations according to another embodiment of the present disclosure.

[0129] Reference Figure 10A This illustrates a programming operation where two or more bits of data are stored in a memory cell. When the number of programming cycles performed exceeds a reference number, the voltage level of the sensing control signal PBSENSE during the programming verification operation can be reduced from the on-state voltage VON by a predetermined first level Vpb. At this time, the level of the verification voltage applied to the selected word line can be increased by a third level Vpv compared to the verification voltage of the previous programming cycle. For example, as... Figure 10A As shown, when the reference count is set to 10, the voltage level of the sensing control signal PBSENSE in the programming verification operation from the 11th programming cycle is reduced by a first level Vpb compared to the sensing control signal PBSENSE in the previous programming cycle (i.e., the 10th programming cycle), and the level of the verification voltage in the programming verification operation from the 11th programming cycle is reduced by a third level Vpv compared to the verification voltage in the previous programming cycle (i.e., the 10th programming cycle). Therefore, internal current consumption can be reduced and shift of the threshold voltage distribution of the memory cell can be prevented.

[0130] Reference Figure 10BThis illustrates a programming operation where two or more bits of data are stored in a memory cell. When the number of programming cycles executed exceeds a first reference number (R1) and is less than or equal to a second reference number (R2), the voltage level of the sensed control signal PBSENSE during the programming verification operation of programming cycle PL can be reduced by a first level Vpb1. At this time, the level of the verification voltage applied to the selected word line can be increased by a third level Vpv1 compared to the verification voltage of the previous programming cycle. Furthermore, when the number of programming cycles executed exceeds the second reference number (R2), the voltage level of the sensed control signal PBSENSE during the programming verification operation of programming cycle PL can be reduced by a second level Vpb2. At this time, the level of the verification voltage applied to the selected word line can be increased by a fourth level Vpv2 compared to the verification voltage of the previous programming cycle.

[0131] For example, such as Figure 10B As shown, when the first reference count (R1) is set to 10 and the second reference count (R2) is set to 11, the voltage level of the sensing control signal PBSENSE during the programming verification operation from the 11th programming cycle can decrease by a first level Vpb1 compared to the sensing control signal PBSENSE during the previous programming cycle (i.e., the 10th programming cycle), and the verification voltage level can increase by a third level Vpv1 compared to the verification voltage level during the previous programming cycle (i.e., the 10th programming cycle). Furthermore, during the programming verification operation from the 12th programming cycle, the voltage level of the sensing control signal PBSENSE can decrease by a second level Vpb2 compared to the sensing control signal PBSENSE during the previous programming cycle (i.e., the 11th programming cycle), and the verification voltage level can increase by a fourth level Vpv2 compared to the verification voltage level during the previous programming cycle (i.e., the 11th programming cycle). Therefore, internal current consumption can be reduced and programming performance degradation can be prevented.

[0132] Figure 11 This illustrates an embodiment according to the present disclosure. Figure 2 Configuration diagram of the programming control circuit 132.

[0133] Reference Figure 11 The programming control circuit 132 may include a programming loop determination circuit 310, a row control circuit 320, and a column control circuit 330.

[0134] The programming cycle determination circuit 310 can receive a pass signal PASS or a failure signal FAIL from the sensing circuit 126, indicating whether the programming verification operation has passed or failed. The programming cycle determination circuit 310 can determine whether to continue the programming cycle based on the pass signal PASS or the failure signal FAIL. For example, the programming cycle determination circuit 310 can generate a programming control signal PGMCONT to notify the start of the next programming cycle based on the failure signal FAIL indicating a programming verification operation failure. When the number of executed programming cycles exceeds a preset reference number, the programming cycle determination circuit 310 can enable the loop control signal LOOPOVER. According to an embodiment, when multiple reference numbers are set, the programming cycle determination circuit 310 can generate multiple loop control signals LOOPOVER to distinguish the reference numbers. Furthermore, when the number of executed programming cycles reaches the maximum allowed number, the programming cycle determination circuit 310 can notify the selected word line that the programming operation has failed.

[0135] The line control circuit 320 can output an operation signal OPSIG to the voltage generation circuit 122 in response to the programming control signal PGMCONT. The voltage generation circuit 122 can generate an operation voltage Vop based on the operation signal OPSIG. For example, the voltage generation circuit 122 can generate a programming voltage and provide it to the line decoder 121 by increasing the level of the programming voltage by a predetermined step voltage Vstep during the programming voltage application operation. The line decoder 121 can apply the programming voltage increased by the step voltage Vstep to the selected word line. In an embodiment, when the loop control signal LOOPOVER is enabled, the line control circuit 320 can output the operation signal OPSIG to the voltage generation circuit 122, causing the level of the verification voltage to increase by a predetermined level Vpv1 or Vpv2. Therefore, when the number of programming loops executed exceeds a reference number, the line decoder 121 can apply a verification voltage increased by the predetermined level Vpv1 or Vpv2.

[0136] The column control circuit 330 can output a page buffer control signal PBSIGNALS to the page buffer group 123 in response to the programming control signal PGMCONT. During the programming voltage application operation, according to the page buffer control signal PBSIGNALS, the first page buffer PB1 to the nth page buffer PBn of the page buffer group 123 can apply a programming enable voltage to the bit line of the programming target cell and can apply a programming disable voltage to the bit line of the programming disable cell. The page buffer control signal PBSIGNALS provided from the column control circuit 330 may include a precharge signal PRECH_B, a select signal SEL, and a first preliminary control signal PRE1 and a second preliminary control signal PRE2.

[0137] In this implementation, when the LOOPOVER control signal is enabled, during the programming verification operation, the column control circuit 330 can provide a first preliminary control signal PRE1 to adjust the voltage level of the sensing control signal PBSENSE, and simultaneously provide a second preliminary control signal PRE2 to decrease the voltage level of the sensing control signal PBSENSE. Additionally, when the LOOPOVER control signal is enabled, the column control circuit 330 can provide a selection signal SEL for selecting the second preliminary control signal PRE2. Therefore, when the number of programming cycles performed exceeds a reference number, the level of the pre-charge voltage applied to the bit lines can be adjusted according to the sensing control signal PBSENSE during the programming verification operation, from the first page buffer PB1 to the nth page buffer PBn.

[0138] Figure 12 This is a configuration diagram showing the first page buffer PB1 of the page buffer group 123 according to an embodiment of the present disclosure.

[0139] Reference Figure 12 The first page shows buffer PB1 and switch 410.

[0140] Switch 410 can be connected to the first bit line BL1 and the first page buffer PB1 according to the sensing control signal PBSENSE. For example, switch 410 can be implemented using an NMOS transistor N1 having a gate that receives the sensing control signal PBSENSE, and can be connected between the first bit line BL1 and the sensing node S0. However, the invention is not limited to this embodiment, and switch 410 can be implemented as various types of transistors depending on the circuit configuration.

[0141] The first page buffer PB1 may include a sensing control circuit 421, a pre-charging circuit 422, and a latching circuit 423.

[0142] The sensing control circuit 421 can generate a sensing control signal PBSENSE corresponding to either the first preliminary control signal PRE1 or the second preliminary control signal PRE2 in response to the selection signal SEL. The first preliminary control signal PRE1 and the second preliminary control signal PRE2 can be voltage levels used for the sensing control signal PBSENSE, and can swing to high voltage (VH), intermediate voltage (VM), and on-state voltage (VON) levels, such as... Figure 7 , Figure 9 , Figure 10A and Figure 10B As described in the text. Specifically, during the programming verification operation, the sensing control circuit 421 may select a second preliminary control signal PRE2 in response to the selection signal SEL, thereby reducing the voltage level of the sensing control signal PBSENSE according to the second preliminary control signal PRE2.

[0143] The pre-charge circuit 422 can pre-charge the sensing node S0 to a pre-charge voltage VBLP according to the pre-charge signal PRECH_B. The pre-charge voltage VBLP can be a power supply voltage. For example, the pre-charge circuit 422 can be implemented using a PMOS transistor P1 having a gate that receives the pre-charge signal PRECH_B, and can be connected between the pre-charge voltage (VBLP) terminal and the sensing node S0. However, the invention is not limited to this embodiment, and the pre-charge circuit 422 can be implemented with various types of transistors depending on the circuit configuration.

[0144] The latch circuit 423 can store data in the sensing node S0. The number of latches can vary depending on the number of data bits that the memory cell can store.

[0145] When the precharge signal PRECH_B is enabled to a logic low level during the programming verification operation, the precharge circuit 422 can be turned on to precharge the sensing node S0 to the precharge voltage VBLP. During the programming verification operation, the sensing control circuit 421 can decrease the voltage level of the sensing control signal PBSENSE according to the second preliminary control signal PRE2. The switch 410 can be turned on to electrically connect the first line BL1 to the sensing node S0, and the first line BL1 can be precharged to the precharge voltage VBLP. At this time, the level at which the first line BL1 is precharged can vary according to the voltage level of the sensing control signal PBSENSE applied to the switch 410. That is, as the voltage level (driving force) of the sensing control signal PBSENSE decreases, the driving force of the switch 410 decreases, and therefore, the precharge voltage applied to the first line BL1 can decrease.

[0146] Furthermore, in the above embodiments, the case where the memory cell stores two or more bits of data was described as an example, but the present invention is not limited to this embodiment. Hereinafter, in embodiments of the present invention, when the memory cell is a single-level cell (SLC) storing single-bit data, a method for reducing internal current consumption will be described by decreasing the level of the pre-charge voltage applied to the bit line during the programming verification operation until the number of programming cycles performed reaches a preset reference number.

[0147] Figure 13 This is a flowchart describing programming operations according to embodiments of the present disclosure.

[0148] Reference Figure 13 This illustrates the programming operation when the memory cell is a single-level cell (SLC). The programming operation can be performed by repeating at least one programming cycle PL within a maximum allowed number of times (e.g., m times).

[0149] In the case of SLC, when the number of programming cycles executed is less than or equal to the reference number, during the programming verification operation, control logic 130 can control the voltage level of the sense control signal PBSENSE to decrease from the on-state voltage VON to a predetermined first level Vpb. When the number of programming cycles executed is greater than the reference number, control logic 130 can control the voltage level of the sense control signal PBSENSE to the level of the on-state voltage VON. For example, as... Figure 13 As shown, when the reference number is set to 2, the voltage level of the sensing control signal PBSENSE can be set to decrease by a first level Vpb from the on-state voltage VON during the programming verification operation of the first and second programming cycles. From the third programming cycle, compared with the sensing control signal PBSENSE of the previous programming cycles (i.e., the first and second programming cycles), the voltage level of the sensing control signal PBSENSE can increase by a first level Vpb. Therefore, the voltage level of the sensing control signal PBSENSE can be set to the level of the on-state voltage VON. Thus, in the case of SLC, when the number of programming cycles performed is less than or equal to the reference number, the level of the pre-charge voltage applied to the bit line during the programming verification operation can be set to decrease by a first level Vpre, thereby reducing the internal current consumption generated during the programming verification operation and stabilizing the average current consumption.

[0150] In the case of SLC, when the loop control signal LOOPOVER is enabled, during the programming verification operation, Figure 11The column control circuit 330 of the programming control circuit 132 can provide a first preliminary control signal PRE1 to adjust the voltage level of the sensing control signal PBSENSE, and simultaneously provide a second preliminary control signal PRE2 to increase the voltage level of the sensing control signal PBSENSE. During the programming verification operation, the column control circuit 330 can provide the first preliminary control signal PRE1 to reduce the voltage level of the sensing control signal PBSENSE from the on-state voltage VON to a first level Vpb. The sensing control circuit 421 of the first page buffer PB1 can generate a sensing control signal PBSENSE corresponding to either the first preliminary control signal PRE1 or the second preliminary control signal PRE2. That is, when the number of programming cycles performed is less than or equal to the reference number, according to the first preliminary control signal PRE1, during the programming verification operation, the sensing control circuit 421 can reduce the voltage level of the sensing control signal PBSENSE from the on-state voltage VON to a first level Vpb. As the voltage level (driving force) of the sensing control signal PBSENSE decreases, the driving force of the switch 410 decreases, therefore, the precharge voltage applied to the first bit line BL1 can decrease. Furthermore, when the number of programming loops executed is greater than the reference number, the sensing control circuit 421 can set the voltage level of the sensing control signal PBSENSE to the level of the on-state voltage VON.

[0151] Furthermore, according to the implementation, in the case of SLC, when the number of programming cycles performed is less than or equal to the reference number, the control logic 130 can control the peripheral circuit 120 to increase the level of the verification voltage applied to the selected word line during the programming verification operation by a predetermined level.

[0152] According to the implementation, in the case of SLC, multiple reference cycles can be set, and the control logic 130 can control the peripheral circuit 120 to set the initial level of the pre-charge voltage to a low level. Furthermore, the control logic 130 can control the peripheral circuit 120 such that the level of the pre-charge voltage increases sequentially each time the number of executed programming cycles exceeds each reference cycle, ultimately reaching the level of the turn-on voltage VON. Therefore, the average current consumption can be stabilized by reducing the internal current consumption generated during the programming verification operation.

[0153] Figure 14A and Figure 14B This is a graph showing the current consumption according to a programming cycle according to an embodiment of the present invention.

[0154] Reference Figure 14AIn the case where two or more bits of data are stored in a memory cell, the current consumed during the programming verification operation according to the programming cycle is shown. In the case of multi-stage cells, contrary to the prior art (shown as dashed lines), the increased current consumption during the programming verification operation, compared to the dashed lines, can decrease towards the latter half of the programming cycle. According to an embodiment of the invention, when the number of programming cycles performed exceeds a reference number, the current consumption during the programming verification operation can be minimized by reducing the level of the pre-charge voltage.

[0155] Reference Figure 14B In the case where a single bit of data is stored in a memory cell, the current consumed during the programming verification operation according to the programming cycle is shown. In the case of a single-stage cell, compared with the prior art (shown as dashed lines), the current consumption in the first half of the programming cycle during the programming verification operation can be reduced compared to the dashed lines. According to an embodiment of the invention, when the number of programming cycles performed is less than or equal to the reference number, the current consumption during the programming verification operation can be minimized by reducing the level of the pre-charge voltage.

[0156] Various embodiments of this disclosure are described in the accompanying drawings and specification. Although specific terminology is used herein, it is for the purpose of describing embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. These embodiments may be combined to form additional embodiments.

[0157] It should be noted that although the technical spirit of this disclosure has been described in conjunction with its embodiments, this is for descriptive purposes only and should not be construed as limiting. Those skilled in the art will understand that various changes can be made without departing from the technical spirit of this disclosure and the following claims.

[0158] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types depending on the polarity of the input signal. Furthermore, these embodiments can be combined to form additional embodiments.

[0159] Cross-reference to related applications

[0160] This application claims the benefit of Korean Patent Application No. 10-2022-0029259, filed on March 8, 2022, the entirety of which is incorporated herein by reference.

Claims

1. A memory device comprising: A memory cell array comprising multiple memory cells; Peripheral circuitry, connected to the memory cell array via word lines and bit lines, performs one or more programming cycles on memory cells connected to selected word lines, each programming cycle including a programming voltage application operation and a programming verification operation; as well as In the case where each of the memory cells comprises a multi-level cell, when the number of programming cycles executed is greater than a reference number, the programming control circuit controls the peripheral circuit to reduce the level of the pre-charge voltage applied to the bit line during the programming verification operation; and in the case where each of the memory cells comprises a single-level cell, when the number of programming cycles executed is less than or equal to the reference number, the programming control circuit controls the peripheral circuit to reduce the level of the pre-charge voltage applied to the bit line during the programming verification operation.

2. The memory device according to claim 1, wherein, In the case where each of the memory cells includes the multi-level cells, when the number of programming cycles executed is greater than the reference number, the programming control circuit controls the peripheral circuit to increase the level of the verification voltage applied to the selected word line during the programming verification operation.

3. The memory device according to claim 1, wherein, In the case that each of the memory cells includes the multi-level cells, the programming control circuitry is as follows: When the number of executed programming loops is greater than the first reference number and less than or equal to the second reference number, the level of the pre-charge voltage is controlled to be lower than the level of the pre-charge voltage of the previous programming loop, and When the number of times the programming loop is executed is greater than the second reference number, the level of the pre-charge voltage is controlled to be lower than the level of the pre-charge voltage of the previous programming loop.

4. The memory device according to claim 3, wherein, In the case that each of the memory cells includes the multi-level cells, the programming control circuitry is as follows: When the number of executed programming cycles is greater than the first reference number and less than or equal to the second reference number, the level of the verification voltage applied to the selected word line during the programming verification operation is increased compared to the level of the verification voltage in the previous programming cycle, and When the number of times the programming loop is executed is greater than the second reference number, the level of the verification voltage is increased compared to the level of the verification voltage in the previous programming loop.

5. The memory device according to claim 1, wherein, The peripheral circuit includes: Multiple page buffers, which apply the precharge voltage to the bit line during the programming verification operation; and Multiple switches, which are respectively connected to the bit line and the page buffer in response to a sensing control signal. In the case where each of the memory cells includes the multi-level cells, when the number of executed programming cycles is greater than the reference number, the programming control circuit controls the driving force of the sensing control signal to decrease.

6. The memory device according to claim 1, wherein, In the case where each of the memory cells includes the single-level cell, when the number of programming cycles executed is less than or equal to the reference number, the programming control circuit controls the peripheral circuit to increase the level of the verification voltage applied to the selected word line during the programming verification operation.

7. The memory device according to claim 1, wherein, The peripheral circuit includes: Multiple page buffers, which apply the precharge voltage to the bit line during the programming verification operation; and Multiple switches, which are respectively connected to the bit line and the page buffer in response to a sensing control signal. Wherein, in the case that each of the memory cells includes the single-level cell, when the number of programming cycles executed is less than or equal to the reference number, the programming control circuit controls the driving force of the sensing control signal to decrease.

8. A method for programming a memory device, the method comprising the following steps: Set the programming enable voltage and programming disable voltage for multiple bit lines; Perform a programming voltage application operation that applies a programming voltage to a memory cell connected to a selected word line among multiple word lines; as well as A programming verification operation is performed to verify the programming result by precharging the bit line with a precharge voltage and applying a verification voltage to the memory cell connected to the selected word line. The steps of setting the programming enable and disable voltages for multiple bit lines, the programming voltage application operation, and the programming verification operation are repeatedly performed, and Wherein, in the case that each of the memory cells includes a multi-level memory, when the number of programming cycles executed is greater than a reference number, the level of the pre-charge voltage during the programming verification operation is reduced; and in the case that each of the memory cells includes a single-level memory, when the number of programming cycles executed is less than or equal to the reference number, the level of the pre-charge voltage during the programming verification operation is reduced, and each programming cycle includes the programming voltage application operation and the programming verification operation.

9. The programming method according to claim 8, further comprising the following steps: In the case where each of the memory cells includes the multi-level memory, when the number of programming cycles executed is greater than the reference number, the level of the verification voltage is increased during the programming verification operation.

10. The programming method according to claim 8, wherein, In the case where each of the memory cells includes the multi-level memory, the level of the pre-charge voltage during the programming verification operation is reduced by the following steps: When the number of executed programming loops is greater than the first reference number and less than or equal to the second reference number, the level of the pre-charge voltage is reduced by a first level compared to the previous programming loop, and When the number of times the programming loop is executed is greater than the second reference number, the level of the pre-charge voltage is reduced by a second level compared to the previous programming loop.

11. The programming method according to claim 10, further comprising the following steps: In the case where each of the memory cells includes the multi-level memory... When the number of executed programming loops is greater than the first reference number and less than or equal to the second reference number, during the programming verification operation, the level of the verification voltage is increased by a third level compared to the level of the verification voltage in the previous programming loop, and When the number of programming loops executed is greater than the second reference number, the level of the verification voltage is increased by a fourth level during the programming verification operation, compared with the level of the verification voltage in the previous programming loop.

12. The programming method according to claim 8, wherein, The programming loop is executed using the Incremental Step Pulse Programming (ISPP) scheme.

13. The programming method according to claim 8, further comprising the following steps: In the case where each of the memory cells includes the single-level memory, when the number of programming cycles executed is less than or equal to the reference number, the level of the verification voltage is increased during the programming verification operation.

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