Memory failure test method and device, storage medium and electronic equipment

Abstract

This disclosure relates to a memory failure testing method, a memory failure testing apparatus, a computer-readable storage medium, and an electronic device. The memory failure testing method includes: writing preset stored data into the memory array; increasing the bit line voltage to control a portion of the word lines of the memory array to enter a test mode; waiting for a preset time and then exiting the test mode; turning off the sensitive amplifiers of the preset portion of the bit lines and reading the data of the remaining bit lines; comparing the read data of the remaining bit lines with the preset stored data to obtain a comparison result; and determining the failure state of the memory based on the comparison result. This disclosure can improve the testing efficiency and accuracy of memory failure states.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a memory failure testing method, a memory failure testing apparatus, a computer-readable storage medium, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low price, it has been widely used in the computer field and the electronics industry.

[0003] In cell-to-cell leakage testing of DRAM product memory array cells, the potential voltage difference can be used to test cell leakage and detect chips with potential risks.

[0004] However, existing testing methods require continuously and gradually refreshing the potential difference between array cells, resulting in a long testing time and low testing accuracy.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a memory failure testing method, a memory failure testing apparatus, a computer-readable storage medium, and an electronic device.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0008] According to a first aspect of this disclosure, a memory failure testing method is provided, comprising: writing preset stored data into the memory array; raising the bit line voltage to control a portion of the word lines of the memory array to enter a test mode; waiting for a preset time and then exiting the test mode; turning off the sensitive amplifiers of the preset portion of the bit lines and reading the data of the remaining portion of the bit lines; comparing the read data of the remaining portion of the bit lines with the preset stored data to obtain a comparison result; and determining the failure state of the memory based on the comparison result.

[0009] In one exemplary embodiment of this disclosure, raising the bit line voltage includes: raising the voltage of the bit line from a precharge voltage to an operating voltage.

[0010] In one exemplary embodiment of this disclosure, the preset time is the time from activation to pre-charging of the word line.

[0011] In one exemplary embodiment of this disclosure, reading the data of the remaining bit lines includes: acquiring test data of the memory cell under test.

[0012] In one exemplary embodiment of this disclosure, determining the failure state of the memory based on the comparison result includes: the preset storage data includes writing preset data into the storage cell under test, and determining whether the test data is the same as the preset data.

[0013] In one exemplary embodiment of this disclosure, the preset data is "0". If the test data is not "0", it is determined that the data of the storage unit under test is distorted and the storage unit under test is invalid.

[0014] In one exemplary embodiment of this disclosure, controlling a portion of the word lines of the memory array to enter a test mode includes: controlling the odd-numbered or even-numbered row word lines of the memory array to power on and enter the test mode.

[0015] In one exemplary embodiment of this disclosure, the preset storage data includes first topology data. After the memory writes the first topology data, "1" is written into the storage cells corresponding to the odd-numbered row word lines and the storage cells corresponding to the odd-numbered column word lines, and "0" is written into the remaining storage cells.

[0016] In one exemplary embodiment of this disclosure, the method further includes: when writing the first topology data, controlling the odd-numbered row word lines of the storage array to power on; turning off the sensitive amplifiers of the odd-numbered column word lines, and reading the data of the even-numbered column word lines.

[0017] In one exemplary embodiment of this disclosure, the preset storage data includes second topology data. After the memory writes the second topology data, "1" is written into the storage cells corresponding to the odd-numbered row word lines and the storage cells corresponding to the even-numbered column word lines, and "0" is written into the remaining storage cells.

[0018] In one exemplary embodiment of this disclosure, the method further includes: when writing the second topology data, controlling the odd-numbered row word lines of the storage array to power on; turning off the sensitive amplifiers of the even-numbered column bit lines, and reading the data of the odd-numbered column bit lines.

[0019] In one exemplary embodiment of this disclosure, the preset storage data includes third topology data. After the memory writes the third topology data, "1" is written into the storage cells corresponding to even-numbered row word lines and odd-numbered column word lines, and "0" is written into the remaining storage cells.

[0020] In one exemplary embodiment of this disclosure, the method further includes: when writing the third topology data, controlling the even-numbered row word lines of the storage array to power on; turning off the sensitive amplifiers of the odd-numbered column bit lines, and reading the data of the even-numbered column bit lines.

[0021] In one exemplary embodiment of this disclosure, the preset storage data includes fourth topology data. After the memory writes the fourth topology data, "1" is written into the storage cells corresponding to the even-numbered row word lines and the even-numbered column bit lines, and "0" is written into the remaining storage cells.

[0022] In one exemplary embodiment of this disclosure, the method further includes: when writing the fourth topology data, controlling the even-numbered row word lines of the storage array to power on; turning off the sensitive amplifiers of the even-numbered column bit lines, and reading the data of the odd-numbered column bit lines.

[0023] According to a second aspect of this disclosure, a memory failure testing apparatus is provided, comprising: a data writing module for writing preset stored data into the memory's storage array; a testing module for raising the bit line voltage to control a portion of the word lines of the storage array to enter a test mode, and exiting the test mode after waiting for a preset time; a data reading module for turning off the sensitive amplifiers of the preset portion of the bit lines and reading the data of the remaining portion of the bit lines; a comparison module for comparing the read data of the remaining portion of the bit lines with the preset stored data to obtain a comparison result; and a determination module for determining the failure state of the memory based on the comparison result.

[0024] According to a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the memory failure test method described above.

[0025] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the memory failure test method described above by executing the executable instructions.

[0026] The technical solution provided in this disclosure may include the following beneficial effects:

[0027] In an exemplary embodiment of this disclosure, on the one hand, by writing preset stored data into the memory array and raising the bit line voltage, when some word lines of the memory array enter the test mode, the data in the memory cells corresponding to these word lines can be kept at "1", i.e., high potential, thereby ensuring a potential difference between them and adjacent memory cells with "0" stored data. Furthermore, by turning off the sensitive amplifiers of the preset bit lines, only the data of the remaining bit lines is read, and the read data is compared with the preset stored data. Based on the comparison result, the failure state of the memory can be determined. On the other hand, since this embodiment raises the bit line voltage and controls some word lines to enter the test mode, by keeping the data in the memory cells corresponding to some word lines at "1", a state with a potential difference can be continuously provided, eliminating the need for continuous gradual refreshing of the array cells, thereby reducing the total test time and improving test efficiency. Moreover, the data in other adjacent memory cells around the memory cell under test with preset stored data of "0" is always kept at "1". By acquiring the data in the memory cell under test, it is possible to quickly and accurately determine whether the memory cell under test is faulty.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0030] Figure 1 The illustration schematically shows a structural diagram of a memory cell in a DRAM according to an exemplary embodiment of the present disclosure;

[0031] Figure 2 The schematic diagram illustrates a structural schematic of a memory array in DRAM according to an exemplary embodiment of the present disclosure;

[0032] Figure 3 A flowchart illustrating an exemplary embodiment of a memory failure testing method according to the present disclosure is shown schematically.

[0033] Figure 4 A schematic flowchart of a memory failure testing method according to an exemplary embodiment of the present disclosure is shown.

[0034] Figure 5A block diagram schematically illustrates a memory failure testing apparatus according to an exemplary embodiment of the present disclosure;

[0035] Figure 6 The illustration schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0037] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0038] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0039] Semiconductor memories are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A semiconductor memory comprises multiple memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Therefore, the following description of embodiments is made with reference to DRAM as a non-limiting example.

[0040] In DRAM integrated circuit devices, memory cell arrays are typically arranged in rows and columns, allowing specific memory cells to be addressed by specifying their row and column in the array. During a read operation, the corresponding sense amplifier is selected to output the data from the memory cell.

[0041] Reference Figure 1Each memory cell 100 in a DRAM typically includes a capacitor 110, a transistor 120, a word line (WL) 130, and a bit line (BL) 140. The gate of transistor 120 is connected to word line 130, the drain of transistor 120 is connected to bit line 140, and the source of transistor 120 is connected to capacitor 110. The voltage signal on word line 130 can control transistor 120 to turn on or off, thereby reading data information stored in capacitor 110 through bit line 140, or writing data information into capacitor 110 for storage through bit line 140.

[0042] A storage array typically consists of multiple storage cells, as shown in the reference. Figure 2 As shown, one bit line BL corresponds to multiple word lines WL arranged at intervals. The word lines WL can control the on / off state of the corresponding transistors 120. When there is leakage in the memory cell composed of word lines 130, bit lines 140 and transistors 120, the electrons stored in the cell will leak out through the leakage point, causing the potential stored in the cell to be distorted.

[0043] Therefore, it is of great significance to conduct failure tests on memory in order to determine the failure state of memory.

[0044] The memory failure testing method provided in the exemplary embodiments of this disclosure refers to... Figure 3 This may include the following steps:

[0045] Step S310: Write preset storage data into the storage array of the memory;

[0046] Step S320: Increase the bit line voltage to control some word lines of the memory array to enter test mode;

[0047] Step S330: Exit the test mode after waiting for the preset time;

[0048] Step S340: Turn off the sensitive amplifier of the preset part of the bit lines and read the data of the remaining part of the bit lines;

[0049] Step S350: Compare the data of the remaining bit lines read with the preset stored data to obtain the comparison result;

[0050] Step S360: Determine the failure status of the memory based on the comparison results.

[0051] In the memory failure testing method provided by the exemplary embodiments of this disclosure, on the one hand, by writing preset storage data into the memory array and raising the bit line voltage, when some word lines of the memory array enter the test mode, the data in the memory cells corresponding to these word lines can be kept at "1", i.e., high potential, thereby ensuring a potential difference between them and the adjacent memory cells with data of "0". Furthermore, by turning off the sensitive amplifiers of the preset bit lines, only the data of the remaining bit lines is read, and the read data is compared with the preset storage data. Based on the comparison result, the failure state of the memory can be determined. On the other hand, since this embodiment of the disclosure raises the bit line voltage and controls some word lines to enter the test mode, by keeping the data in the memory cells corresponding to some word lines at "1", a state with a potential difference can be continuously provided, eliminating the need to constantly refresh the array cells, thereby reducing the total test time and improving test efficiency. Moreover, the data in other adjacent memory cells around the memory cell under test with preset storage data of "0" is always kept at "1". By acquiring the data in the memory cell under test, it is possible to quickly and accurately determine whether the memory cell under test has failed.

[0052] The memory failure testing method provided by the exemplary embodiments of this disclosure will now be described in detail, using different preset storage data:

[0053] In practical applications, the preset storage data may include first topology data, second topology data, third topology data, or fourth topology data. Different topology data are used for different storage cell cells for testing.

[0054] Referring to Table 1, the distribution structure of the first topology data SUR1_0 is shown. After the first topology data is written, the memory writes "1" into the memory cells corresponding to the odd row word lines (WL1, WL3, WL5, WL7...) and the odd column word lines (BL1, BL3, BL5, BL7...), and writes "0" into the remaining memory cells.

[0055] Table 1

[0056] BL0 0 1 0 1 0 1 0 1 BL1 1 1 1 1 1 1 1 1 BL2 0 1 0 1 0 1 0 1 BL3 1 1 1 1 1 1 1 1 BL4 0 1 0 1 0 1 0 1 BL5 1 1 1 1 1 1 1 1 BL6 0 1 0 1 0 1 0 1 BL7 1 1 1 1 1 1 1 1

[0057] In an exemplary embodiment of this disclosure, after writing the first topology data into the memory array, the bit line BL voltage is increased, that is, the voltage of the bit line BL is increased from the pre-charge voltage to the operating voltage, which is equivalent to turning on the bit line BL. The voltage on the bit line BL will become 1V. Figure 2 As shown.

[0058] Next, some word lines of the memory array are controlled to enter test mode, which is equivalent to turning on some word lines WL in the entire memory array, so that the charge on bit line BL can be shared on the transistor capacitors corresponding to some word lines WL, so that the data stored in the capacitors corresponding to some word lines WL remains "1".

[0059] For the first, second, third, and fourth topology data mentioned above, control a portion of the word lines of the storage array to enter test mode. This includes powering on either the odd-numbered or even-numbered row word lines of the storage array to enter test mode. Specifically, for the first topology data, this mainly involves powering on the odd-numbered row word lines of the storage array to enter test mode, that is, maintaining a high potential on the odd-numbered row word lines, as described above. Figure 2 .

[0060] In this exemplary embodiment of the present disclosure, the test mode is exited after a preset time. The preset time refers to the time from activation to pre-charging of the word line WL, that is, the opening time of the word line WL. During this time period, the voltage of a portion of the word line can be maintained at 1V.

[0061] It should be noted that the memory failure test method provided in this disclosure embodiment can also turn off all sense amplifiers (SA) before raising the bit line voltage, thereby turning off the data reading function and not reading data in the entire test mode.

[0062] After exiting the test mode, the sensitive amplifiers of a preset portion of the bit lines can be turned off, and the data of the remaining bit lines can be read. For the first topology data shown in Table 1, the sensitive amplifiers SA of the odd-numbered bit lines can be turned off, and the data of the even-numbered bit lines can be read. As can be seen from Table 1, the data on the odd-numbered bit lines are all "1", and only the data on the even-numbered bit lines contains the data "0". The memory cells with these data "0" are the memory cells under test. Reading the data of the remaining bit lines is equivalent to obtaining the test data of the memory cells under test.

[0063] Finally, the data from the remaining bit lines can be compared with the preset stored data to obtain the comparison result, which mainly involves comparing the test data in the memory cell under test with the preset stored data. Furthermore, the failure status of the memory can be determined based on the comparison result.

[0064] Specifically, the aforementioned preset storage data may include writing preset data into the storage unit under test, and judging the comparison result may include: judging whether the test data in the storage unit under test is the same as the preset data.

[0065] In an exemplary embodiment of this disclosure, the preset data is "0". If the test data is not "0", it can be determined that the data of the storage unit under test is distorted and the storage unit under test is faulty.

[0066] In an exemplary embodiment of this disclosure, by writing the first topology data as preset storage data into the storage array, the failure status of the storage cell under test containing the data "0" in the even-numbered column bit lines of the memory can be tested.

[0067] Referring to Table 2, the distribution structure of the second topology data SUR1_1 is shown. After the second topology data is written, the memory cells corresponding to the odd row word lines (WL1, WL3, WL5, WL7...) and the even column word lines (BL0, BL2, BL4, BL8...) are all written with "1", and the remaining memory cells are all written with "0".

[0068] Table 2

[0069] BL0 1 1 1 1 1 1 1 1 BL1 0 1 0 1 0 1 0 1 BL2 1 1 1 1 1 1 1 1 BL3 0 1 0 1 0 1 0 1 BL4 1 1 1 1 1 1 1 1 BL5 0 1 0 1 0 1 0 1 BL6 1 1 1 1 1 1 1 1 BL7 0 1 0 1 0 1 0 1

[0070] In an exemplary embodiment of this disclosure, after writing the second topology data into the memory array, the voltage of the bit line BL is increased, that is, the voltage of the bit line BL is increased from the pre-charge voltage to the operating voltage, which is equivalent to turning on the bit line BL, and the voltage on the bit line BL will become 1V.

[0071] Next, some word lines of the memory array are controlled to enter test mode, which is equivalent to turning on some word lines WL in the entire memory array, so that the charge on bit line BL can be shared on the transistor capacitors corresponding to some word lines WL, so that the data stored in the capacitors corresponding to some word lines WL remains "1".

[0072] For the second topology data, controlling some word lines of the storage array to enter the test mode mainly involves controlling the odd-numbered row word lines of the storage array to power on and enter the test mode, that is, keeping the potential on the odd-numbered row word lines at a high potential.

[0073] In this exemplary embodiment of the present disclosure, the test mode is exited after a preset time. The preset time refers to the time from activation to pre-charging of the word line WL, that is, the opening time of the word line WL. During this time period, the voltage on a portion of the word line can be maintained at 1V.

[0074] It should be noted that the memory failure test method provided in this disclosure embodiment can also turn off all sense amplifiers (SA) before raising the bit line voltage, thereby turning off the data reading function and not reading data in the entire test mode.

[0075] After exiting the test mode, the sensitive amplifiers of a preset portion of the bit lines can be turned off, and the data of the remaining bit lines can be read. For the second topology data shown in Table 2, the sensitive amplifiers SA of the even-numbered bit lines can be turned off, and the data of the odd-numbered bit lines can be read. As can be seen from Table 2, the data on the even-numbered bit lines are all "1", and only the data on the odd-numbered bit lines contains the data "0". The memory cells with these data "0" are the memory cells under test. Reading the data of the remaining bit lines is equivalent to obtaining the test data of the memory cells under test.

[0076] Finally, the data from the remaining bit lines can be compared with the preset stored data to obtain the comparison result, which mainly involves comparing the test data in the memory cell under test with the preset stored data. Furthermore, the failure status of the memory can be determined based on the comparison result.

[0077] Specifically, the aforementioned preset storage data may include writing preset data into the storage unit under test, and judging the comparison result may include: judging whether the test data in the storage unit under test is the same as the preset data.

[0078] In an exemplary embodiment of this disclosure, the preset data is "0". If the test data is not "0", it can be determined that the data of the storage unit under test is distorted and the storage unit under test is faulty.

[0079] In an exemplary embodiment of this disclosure, by writing the second topology data as preset storage data into the storage array, the failure status of the storage cell under test containing the data "0" in the odd-numbered column bit lines of the memory can be tested.

[0080] Referring to Table 3, the distribution structure of the third topology data SUR1_2 is shown. After the second topology data is written, the memory cells corresponding to the even-numbered row word lines (WL0, WL2, WL4, WL6...) and the odd-numbered column word lines (BL1, BL3, BL5, BL7...) are all written with "1", and the remaining memory cells are all written with "0".

[0081] Table 3

[0082] BL0 1 0 1 0 1 0 1 0 BL1 1 1 1 1 1 1 1 1 BL2 1 0 1 0 1 0 1 0 BL3 1 1 1 1 1 1 1 1 BL4 1 0 1 0 1 0 1 0 BL5 1 1 1 1 1 1 1 1 BL6 1 0 1 0 1 0 1 0 BL7 1 1 1 1 1 1 1 1

[0083] In an exemplary embodiment of this disclosure, after writing third topology data into the memory array, the voltage of bit line BL is increased, that is, the voltage of bit line BL is increased from the pre-charge voltage to the operating voltage, which is equivalent to turning on bit line BL, and the voltage on bit line BL will become 1V.

[0084] Next, some word lines of the memory array are controlled to enter test mode, which is equivalent to turning on some word lines WL in the entire memory array, so that the charge on bit line BL can be shared on the transistor capacitors corresponding to some word lines WL, so that the data stored in the capacitors corresponding to some word lines WL remains "1".

[0085] For the third topology data, controlling some word lines of the storage array to enter the test mode mainly involves controlling the even-numbered row word lines of the storage array to power on and enter the test mode, that is, keeping the potential on the even-numbered row word lines at a high potential.

[0086] In this exemplary embodiment of the present disclosure, the test mode is exited after a preset time. The preset time refers to the time from activation to pre-charging of the word line WL, that is, the opening time of the word line WL. During this time period, the voltage on a portion of the word line can be maintained at 1V.

[0087] It should be noted that the memory failure test method provided in this disclosure embodiment can also turn off all sense amplifiers (SA) before raising the bit line voltage, thereby turning off the data reading function and not reading data in the entire test mode.

[0088] After exiting the test mode, the sensitive amplifiers of a preset portion of the bit lines can be turned off, and the data of the remaining bit lines can be read. For the third topology data shown in Table 3, the sensitive amplifiers SA of the odd-numbered bit lines can be turned off, and the data of the even-numbered bit lines can be read. As can be seen from Table 3, the data on the odd-numbered bit lines are all "1", and only the data on the even-numbered bit lines contains the data "0". The memory cells with these data "0" are the memory cells under test. Reading the data of the remaining bit lines is equivalent to obtaining the test data of the memory cells under test.

[0089] Finally, the data from the remaining bit lines can be compared with the preset stored data to obtain the comparison result, which mainly involves comparing the test data in the memory cell under test with the preset stored data. Furthermore, the failure status of the memory can be determined based on the comparison result.

[0090] Specifically, the aforementioned preset storage data may include writing preset data into the storage unit under test, and judging the comparison result may include: judging whether the test data in the storage unit under test is the same as the preset data.

[0091] In an exemplary embodiment of this disclosure, the preset data is "0". If the test data is not "0", it can be determined that the data of the storage unit under test is distorted and the storage unit under test is faulty.

[0092] In an exemplary embodiment of this disclosure, by writing third topology data as preset storage data into the storage array, the failure state of the storage cell under test containing the data "0" in the even-numbered column bit lines of the memory can be tested. Furthermore, the storage cell tested by the third topology data is precisely the storage cell on the even-numbered column bit line that was not tested by the first topology data.

[0093] Referring to Table 4, the distribution structure of the fourth topology data SUR1_3 is shown. After the fourth topology data is written, the memory cells corresponding to the even-numbered row word lines (WL0, WL2, WL4, WL6...) and the even-numbered column word lines (BL1, BL3, BL5, BL7...) are all written with "1", and the remaining memory cells are all written with "0".

[0094] Table 4

[0095] BL0 1 1 1 1 1 1 1 1 BL1 1 0 1 0 1 0 1 0 BL2 1 1 1 1 1 1 1 1 BL3 1 0 1 0 1 0 1 0 BL4 1 1 1 1 1 1 1 1 BL5 1 0 1 0 1 0 1 0 BL6 1 1 1 1 1 1 1 1 BL7 1 0 1 0 1 0 1 0

[0096] In an exemplary embodiment of this disclosure, after writing fourth topology data into the memory array, the voltage of bit line BL is increased, that is, the voltage of bit line BL is increased from the pre-charge voltage to the operating voltage, which is equivalent to turning on bit line BL, and the voltage on bit line BL will become 1V.

[0097] Next, some word lines of the memory array are controlled to enter test mode, which is equivalent to turning on some word lines WL in the entire memory array, so that the charge on bit line BL can be shared on the transistor capacitors corresponding to some word lines WL, so that the data stored in the capacitors corresponding to some word lines WL remains "1".

[0098] For the fourth topology data, controlling some word lines of the storage array to enter the test mode mainly involves controlling the even-numbered row word lines of the storage array to power on and enter the test mode, that is, keeping the potential on the even-numbered row word lines at a high potential.

[0099] In this exemplary embodiment of the present disclosure, the test mode is exited after a preset time. The preset time refers to the time from activation to pre-charging of the word line WL, that is, the opening time of the word line WL. During this time period, the voltage on a portion of the word line can be maintained at 1V.

[0100] It should be noted that the memory failure test method provided in this disclosure embodiment can also turn off all sense amplifiers (SA) before raising the bit line voltage, thereby turning off the data reading function and not reading data in the entire test mode.

[0101] After exiting the test mode, the sensitive amplifiers of a preset portion of the bit lines can be turned off, and the data of the remaining bit lines can be read. For the fourth topology data shown in Table 4, the sensitive amplifiers SA of the even-numbered bit lines can be turned off, and the data of the odd-numbered bit lines can be read. As can be seen from Table 4, the data on the even-numbered bit lines are all "1", and only the data on the odd-numbered bit lines contains the data "0". The memory cells with these data "0" are the memory cells under test. Reading the data of the remaining bit lines is equivalent to obtaining the test data of the memory cells under test.

[0102] Finally, the data from the remaining bit lines can be compared with the preset stored data to obtain the comparison result, which mainly involves comparing the test data in the memory cell under test with the preset stored data. Furthermore, the failure status of the memory can be determined based on the comparison result.

[0103] Specifically, the aforementioned preset storage data may include writing preset data into the storage unit under test, and judging the comparison result may include: judging whether the test data in the storage unit under test is the same as the preset data.

[0104] In an exemplary embodiment of this disclosure, the preset data is "0". If the test data is not "0", it can be determined that the data of the storage unit under test is distorted and the storage unit under test is faulty.

[0105] In an exemplary embodiment of this disclosure, by writing fourth topology data as preset storage data into the storage array, the failure state of the storage cell under test containing the data "0" in the odd-numbered column bits of the memory can be tested. Furthermore, the storage cell tested by the fourth topology data is precisely the storage cell on the odd-numbered column bits that were not tested by the second topology data.

[0106] In practical applications, one or more of the first, second, third, or fourth topology data can be selected as preset storage data to determine the failure of some storage cells in the memory; alternatively, the first, second, third, and fourth topology data can be combined to determine the failure of all storage cells in the memory. Specifically, in the combination process, the failure determination is still performed separately for each of the four topology data sets, which will not be elaborated further here.

[0107] Although the specific bit lines or word lines that are turned on or off differ across the four topology data sets, the memory failure testing procedure remains the same for all four topology data sets. (Refer to...) Figure 4The diagram illustrates a flowchart of a memory failure testing method according to an embodiment of the present disclosure. First, preset storage data is written into the memory array, specifically along the word line direction. Next, the bit line voltage is increased. Then, a test mode is entered, and the odd-numbered or even-numbered word lines of the memory array are powered on. After a preset time, the test mode is exited. Next, the sensitive amplifiers for the odd-numbered or even-numbered word lines are turned off, and the data from the even-numbered or odd-numbered word lines is read. Finally, a comparison result is obtained, and a failure determination is performed.

[0108] In summary, the memory failure testing method provided by the exemplary embodiments of this disclosure can maintain the odd-numbered or even-numbered column word lines at a high potential by raising the bit line voltage and controlling the odd-numbered or even-numbered column word lines to be powered on, thereby maintaining the potential difference between memory cells and thus realizing the testing of the memory cell under test.

[0109] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0110] Furthermore, in this example embodiment, a memory failure testing apparatus is also provided. (Refer to...) Figure 5 The memory failure testing device 500 may include: a data writing module 510, a testing module 520, a data reading module 530, a comparison module 540, and a judgment module 550, wherein:

[0111] The data writing module 510 can be used to write preset stored data into the storage array of the memory;

[0112] Test module 520 can be used to raise the bit line voltage, control some word lines of the memory array to enter the test mode, and exit the test mode after waiting for a preset time;

[0113] The data reading module 530 can be used to turn off the sensitive amplifier of a preset portion of the bit lines and read the data of the remaining bit lines;

[0114] The comparison module 540 can be used to compare the data of the remaining bit lines read with the preset stored data to obtain the comparison result;

[0115] The determination module 550 can be used to determine the failure status of the memory based on the comparison results.

[0116] In one exemplary embodiment of this disclosure, the test module 520 can also be used to increase the voltage of the bit line from the precharge voltage to the operating voltage.

[0117] In one exemplary embodiment of this disclosure, the preset time is the time from word line activation to pre-charging.

[0118] In one exemplary embodiment of this disclosure, the data reading module 530 can be used to acquire test data of the storage unit under test.

[0119] In one exemplary embodiment of this disclosure, the determination module 550 can be used to preset stored data including writing preset data into the storage unit under test, and to determine whether the test data is the same as the preset data.

[0120] In one exemplary embodiment of this disclosure, the preset data is "0". The determination module 550 can be used to determine that the data of the storage unit under test is distorted and the storage unit under test is invalid if the test data is not "0".

[0121] In one exemplary embodiment of this disclosure, the test module 520 can be used to control the odd-numbered or even-numbered row word lines of the storage array to power on and enter the test mode.

[0122] In one exemplary embodiment of this disclosure, the preset storage data includes first topology data. After the memory writes the first topology data, "1" is written into the storage cells corresponding to the odd-numbered row word lines and the storage cells corresponding to the odd-numbered column word lines, and "0" is written into the remaining storage cells.

[0123] In one exemplary embodiment of this disclosure, when writing the first topology data, the test module 520 can be used to control the odd-numbered row word lines of the storage array to power on; the data reading module 530 can be used to turn off the sensitive amplifiers of the odd-numbered column word lines and read the data of the even-numbered column word lines.

[0124] In one exemplary embodiment of this disclosure, the preset storage data includes second topology data. After the memory writes the second topology data, "1" is written into the storage cells corresponding to the odd-numbered row word lines and the storage cells corresponding to the even-numbered column word lines, and "0" is written into the remaining storage cells.

[0125] In one exemplary embodiment of this disclosure, when writing the second topology data, the test module 520 can be used to control the odd-numbered row word lines of the storage array to power on; the data reading module 530 can be used to turn off the sensitive amplifiers of the even-numbered column bit lines and read the data of the odd-numbered column bit lines.

[0126] In one exemplary embodiment of this disclosure, the preset storage data includes third topology data. After the memory writes the third topology data, "1" is written into the storage cells corresponding to the even-numbered row word lines and the storage cells corresponding to the odd-numbered column word lines, and "0" is written into the remaining storage cells.

[0127] In one exemplary embodiment of this disclosure, when writing third topology data, the test module 520 can be used to control the even-numbered row word lines of the storage array to power on; the data reading module 530 can be used to turn off the sensitive amplifiers of the odd-numbered column bit lines and read the data of the even-numbered column bit lines.

[0128] In one exemplary embodiment of this disclosure, the preset storage data includes fourth topology data. After the memory writes the fourth topology data, "1" is written into the storage cells corresponding to the even-numbered row word lines and the even-numbered column bit lines, and "0" is written into the remaining storage cells.

[0129] In one exemplary embodiment of this disclosure, when writing fourth topology data, the test module 520 can be used to control the even-numbered row word lines of the storage array to power on; the data reading module 530 can be used to turn off the sensitive amplifiers of the even-numbered column bit lines and read the data of the odd-numbered column bit lines.

[0130] The specific details of the virtual modules of each memory failure test device mentioned above have been described in detail in the corresponding memory failure test methods, so they will not be repeated here.

[0131] It should be noted that although several modules or units of the memory failure testing apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0132] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0133] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0134] The following reference Figure 6To describe an electronic device 600 according to this embodiment of the present invention. Figure 6 The electronic device 600 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0135] like Figure 6 As shown, the electronic device 600 is presented in the form of a general-purpose computing device. The components of the electronic device 600 may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different system components (including storage unit 620 and processing unit 610), and a display unit 640.

[0136] The storage unit 620 stores program code that can be executed by the processing unit 610, causing the processing unit 610 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 610 can perform actions such as... Figure 3 The steps are shown in the figure.

[0137] Storage unit 620 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 6201 and / or cache memory 6202, and may further include a read-only memory (ROM) 6203.

[0138] Storage unit 620 may also include a program / utility 6204 having a set (at least one) program module 6205, such program module 6205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0139] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0140] Electronic device 600 can also communicate with one or more external devices 670 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 660. As shown, network adapter 660 communicates with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0141] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0142] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.

[0143] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0144] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0145] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0146] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0147] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0148] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0149] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0150] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A memory failure testing method, characterized in that, include: Preset storage data is written into the storage array of the memory; Increase the bit line voltage to control some word lines of the memory array to enter test mode; Exit the test mode after waiting for the preset time; Turn off the sensitive amplifiers of the preset portion of the bit lines and read the data of the remaining bit lines; The data of the remaining bit lines read is compared with the preset stored data to obtain a comparison result; The failure status of the memory is determined based on the comparison results; Specifically, controlling a portion of the word lines of the storage array to enter test mode means activating a portion of the word lines in the entire storage array.

2. The memory failure testing method according to claim 1, characterized in that, The step-up voltage includes: increasing the voltage of the bit line from the pre-charge voltage to the operating voltage.

3. The memory failure testing method according to claim 1, characterized in that, The preset time is the time from activation to pre-charging of the word line.

4. The memory failure testing method according to claim 1, characterized in that, The process of reading the remaining bit lines includes: acquiring test data of the memory cell under test.

5. The memory failure testing method according to claim 4, characterized in that, Determining the failure status of the memory based on the comparison result includes: the preset storage data includes writing preset data into the storage unit under test, and determining whether the test data is the same as the preset data.

6. The memory failure testing method according to claim 5, characterized in that, The preset data is "0". If the test data is not "0", the data of the storage unit under test is determined to be distorted and the storage unit under test is deemed to be faulty.

7. The memory failure test method according to any one of claims 1-6, characterized in that, Controlling a portion of the word lines of the memory array to enter test mode includes: Power on either the odd-numbered or even-numbered row word lines of the storage array to enter the test mode.

8. The memory failure testing method according to claim 7, characterized in that, The preset storage data includes first topology data. After the memory writes the first topology data, "1" is written into the storage cells corresponding to the odd-numbered row word lines and the odd-numbered column word lines, and "0" is written into the remaining storage cells.

9. The memory failure testing method according to claim 8, characterized in that, The method further includes: When writing the first topology data, the odd-numbered row word lines of the storage array are powered on; the sensitive amplifiers of the odd-numbered column word lines are turned off, and the data of the even-numbered column word lines is read.

10. The memory failure testing method according to claim 7, characterized in that, The preset storage data includes second topology data. After the memory writes the second topology data, "1" is written into the storage cells corresponding to the odd-numbered row word lines and the even-numbered column word lines, and "0" is written into the remaining storage cells.

11. The memory failure testing method according to claim 10, characterized in that, The method further includes: When writing the second topology data, the odd-numbered row word lines of the storage array are powered on; the sensitive amplifiers of the even-numbered column bit lines are turned off, and the data of the odd-numbered column bit lines is read.

12. The memory failure testing method according to claim 7, characterized in that, The preset storage data includes third topology data. After the memory writes the third topology data, "1" is written into the storage cells corresponding to the even-numbered row word lines and the storage cells corresponding to the odd-numbered column word lines, and "0" is written into the remaining storage cells.

13. The memory failure testing method according to claim 12, characterized in that, The method further includes: When writing the third topology data, the even-numbered row word lines of the storage array are powered on; the sensitive amplifiers of the odd-numbered column bit lines are turned off, and the data of the even-numbered column bit lines is read.

14. The memory failure testing method according to claim 7, characterized in that, The preset storage data includes fourth topology data. After the memory writes the fourth topology data, "1" is written into the storage cells corresponding to the even-numbered row word lines and the even-numbered column bit lines, and "0" is written into the remaining storage cells.

15. The memory failure testing method according to claim 14, characterized in that, The method further includes: When writing the fourth topology data, the even-numbered row word lines of the storage array are powered on; the sensitive amplifiers of the even-numbered column bit lines are turned off, and the data of the odd-numbered column bit lines is read.

16. A memory failure testing device, characterized in that, include: A data writing module is used to write preset stored data into the storage array of the memory; The test module is used to raise the bit line voltage, control some word lines of the memory array to enter the test mode, and exit the test mode after waiting for a preset time. The data reading module is used to turn off the sensitive amplifiers of a preset portion of the bit lines and read the data of the remaining bit lines; The comparison module is used to compare the data of the remaining bit lines read with preset stored data to obtain a comparison result; The determination module is used to determine the failure status of the memory based on the comparison result; Specifically, controlling a portion of the word lines of the storage array to enter test mode means activating a portion of the word lines in the entire storage array.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory failure test method according to any one of claims 1-15.

18. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to implement the memory failure test method according to any one of claims 1-15 by executing the executable instructions.

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