Test method and device of storage chip, storage medium and electronic equipment

Abstract

The present disclosure provides a test method of a storage chip, a test device of a storage chip, a computer readable storage medium and an electronic device, and belongs to the technical field of semiconductors. The method comprises: determining a storage block corresponding to each core in a multi-core processor, the storage block being a local storage area formed by part of storage units in a storage chip; performing read-write testing on the corresponding storage block by each core in the multi-core processor, and determining a test result of the storage chip according to the test results of each storage block obtained by testing. The present disclosure can improve the utilization rate of the multi-core processor and improve the test efficiency of the storage chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for testing memory chips, a testing apparatus for memory chips, a computer-readable storage medium, and an electronic device. Background Technology

[0002] Memory chips are a component of most electronic products. To ensure the performance of memory chips after they are put into production, semiconductor manufacturers often test them before they leave the factory to check their performance.

[0003] Currently, in order to improve the testing efficiency of memory chips such as DRAM (Dynamic Random Access Memory), manufacturers usually choose a multi-tasking operating system environment for testing. However, since the operating system runs in DRAM, it occupies a portion of storage space, which cannot be tested, resulting in insufficient comprehensiveness of the entire memory chip test.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a testing method for memory chips, a testing apparatus for memory chips, a computer-readable storage medium, and an electronic device, thereby improving, to at least some extent, the problem of insufficient comprehensiveness in the testing of memory chips in the prior art.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to a first aspect of this disclosure, a method for testing a memory chip is provided. The method includes: determining a memory block corresponding to each core in a multi-core processor, wherein the memory block is a local storage region composed of some storage cells in the memory chip; performing read and write tests on the corresponding memory blocks by each core in the multi-core processor; and determining the test result of the memory chip based on the test results of each memory block obtained from the tests.

[0008] In one exemplary embodiment of this disclosure, the memory chip is divided into multiple memory blocks by means of the following method: the memory chip is divided into memory blocks having memory regions of the same or different sizes according to the memory address of each memory cell in the memory chip.

[0009] In one exemplary embodiment of this disclosure, determining the memory block corresponding to each core in the multi-core processor includes: determining the memory block corresponding to each core based on the address information of the memory block corresponding to each core in the multi-core processor, wherein the address information includes the storage address of the memory cell contained in each memory block in the memory chip; and performing read / write tests on the corresponding memory blocks by each core in the multi-core processor includes: performing read / write tests on the corresponding memory blocks by each core in the multi-core processor until all memory blocks in the memory chip have been read / written, thereby obtaining the test results for each memory block.

[0010] In one exemplary embodiment of this disclosure, the step of each core in the multi-core processor performing read and write tests on the corresponding memory blocks further includes: each core in the multi-core processor simultaneously performing read and write tests on any one or more memory blocks corresponding to itself; or each core in the multi-core processor sequentially performing read and write tests on any one or more memory blocks corresponding to itself.

[0011] In one exemplary embodiment of this disclosure, the test results of each storage block include whether a read / write error occurred in the storage cell of the corresponding storage block and the number of address bits that caused the read / write error. The step of determining the test results of the storage chip based on the test results of each storage block includes: determining the storage cell in the storage chip that caused the read / write error and the number of address bits of the storage cell that caused the read / write error based on the test results of each storage block, so as to obtain the test results of the storage chip.

[0012] In one exemplary embodiment of this disclosure, before performing read / write tests on the corresponding storage blocks by each of the cores in the multi-core processor, the method further includes: loading and running a bootloader by the multi-core processor to activate each of the cores in the multi-core processor, so that each core performs read / write tests on the corresponding storage blocks when it is in an activated state; wherein, the bootloader runs in static random access memory, and each core runs in the bootloader when it is in the activated state.

[0013] In one exemplary embodiment of this disclosure, when performing read / write tests on corresponding memory blocks by each core in the multi-core processor, the method further includes: determining a test strategy for each memory block in the memory chip when performing read / write tests on each memory block, the test strategy including a test process for performing data read operations and / or data write operations on each memory block; and having each core in the multi-core processor perform data read operations and / or data write operations on its respective corresponding memory block according to the test process.

[0014] In one exemplary embodiment of this disclosure, the testing strategy further includes test data for each of the test processes. The step of each core in the multi-core processor performing data read and / or data write operations on its corresponding storage block according to the test process further includes: determining the target test data for the currently executed test process; and having each core perform data read and / or data write operations on the target test data in its corresponding storage block according to the currently executed test process.

[0015] In one exemplary embodiment of this disclosure, the method further includes: when all cores in the multi-core processor complete the read / write test of their respective corresponding memory blocks according to the currently executed test process, controlling each core to perform read / write test of its respective corresponding memory blocks according to the next test process.

[0016] In one exemplary embodiment of this disclosure, the method further includes: when performing read / write tests on each of the memory blocks, when any one or more cores in the multi-core processor complete the read / write test on their respective memory blocks according to the currently executed test process, controlling the one or more cores to enter a waiting state and triggering a counter to count; when it is determined from the counter's counting result that all cores in the multi-core processor have entered the waiting state, reactivating each of the cores in the multi-core processor and controlling each core to perform read / write tests on their respective memory blocks according to the next test process.

[0017] In one exemplary embodiment of this disclosure, the testing strategy further includes an operation process for performing global control operations on the storage cells in the storage chip, and the method further includes: any one core of the multi-core processor performing global control operations on all storage cells in the storage chip according to the operation process of the global control operations; wherein, the global control operations include data retention operations and / or data refresh operations performed on the storage cells in the storage chip.

[0018] In one exemplary embodiment of this disclosure, the method further includes: when any one or more memory blocks have not been tested, monitoring the testing progress of each core, and using the cores in the multi-core processor that have completed testing to perform read and write tests on any one of the one or more memory blocks, until the read and write tests on all memory blocks in the memory chip are completed.

[0019] In one exemplary embodiment of this disclosure, the memory chip includes dynamic random access memory.

[0020] According to a second aspect of this disclosure, a testing apparatus for a memory chip is provided. The apparatus includes: a determining module, configured to determine a memory block corresponding to each core in a multi-core processor, wherein the memory block is a local storage region composed of some storage units in the memory chip; and a testing module, configured to perform read and write tests on the corresponding memory blocks by each core in the multi-core processor, and determine the test result of the memory chip based on the test results of each memory block obtained from the tests.

[0021] In one exemplary embodiment of this disclosure, the determining module divides the memory chip into multiple memory blocks by performing the following method: dividing the memory chip into memory blocks with memory regions of the same or different sizes according to the memory address of each memory cell in the memory chip.

[0022] In one exemplary embodiment of this disclosure, the determining module is used to determine the storage block corresponding to each core based on the address information of the storage block corresponding to each core in the multi-core processor, wherein the address information includes the storage address of the storage unit contained in each storage block in the storage chip; the testing module is used to have each core in the multi-core processor perform read and write tests on the corresponding storage block until the read and write tests on all storage blocks in the storage chip are completed, and to obtain the test results of each storage block.

[0023] In one exemplary embodiment of this disclosure, the testing module is further configured to have each core in the multi-core processor simultaneously perform read / write tests on any one or more memory blocks corresponding to it; or to have each core in the multi-core processor sequentially perform read / write tests on any one or more memory blocks corresponding to it.

[0024] In one exemplary embodiment of this disclosure, the test results of each storage block include whether a read / write error occurred in the storage cell of the corresponding storage block and the number of address bits that caused the read / write error. The test module is further configured to determine the storage cell in the storage chip that caused the read / write error and the number of address bits of the storage cell that caused the read / write error based on the test results of each storage block, so as to obtain the test results of the storage chip.

[0025] In one exemplary embodiment of this disclosure, before performing read / write tests on the corresponding memory blocks by each of the cores in the multi-core processor, the test module is further configured to load and run a bootloader by the multi-core processor to activate each of the cores in the multi-core processor, so that each core performs read / write tests on the corresponding memory blocks when it is in the activated state; wherein, the bootloader runs in static random access memory, and each core runs in the bootloader when it is in the activated state.

[0026] In one exemplary embodiment of this disclosure, when performing read / write tests on corresponding memory blocks by each core in the multi-core processor, the test module is further configured to determine a test strategy for each memory block in the memory chip during the read / write tests. The test strategy includes a test process for performing data read operations and / or data write operations on each memory block, and each core in the multi-core processor performs data read operations and / or data write operations on its respective corresponding memory block according to the test process.

[0027] In one exemplary embodiment of this disclosure, the testing strategy further includes test data for each of the test processes, and the testing module is further configured to determine the target test data for the currently executed test process; each of the cores performs data reading and / or data writing operations on the target test data in its respective corresponding storage block according to the currently executed test process.

[0028] In one exemplary embodiment of this disclosure, the test module is further configured to control each core to perform read and write tests on its corresponding memory block according to the next test process when all cores in the multi-core processor complete the read and write tests on their respective memory blocks according to the currently executed test process.

[0029] In one exemplary embodiment of this disclosure, the testing module is further configured to, when performing read / write tests on each of the storage blocks, control any one or more cores in the multi-core processor to enter a waiting state and trigger a counter to count when any one or more cores in the multi-core processor complete the read / write test on their respective corresponding storage blocks according to the currently executed test process. When it is determined from the counter count result that all cores in the multi-core processor have entered the waiting state, the module reactivates each of the cores in the multi-core processor and controls each core to perform read / write tests on their respective corresponding storage blocks according to the next test process.

[0030] In one exemplary embodiment of this disclosure, the test strategy further includes an operation process for performing global control operations on the storage cells in the storage chip. The test module is further configured to have any one core of the multi-core processor perform global control operations on all storage cells in the storage chip according to the operation process of the global control operations. The global control operations include data retention operations and / or data refresh operations performed on the storage cells in the storage chip.

[0031] In one exemplary embodiment of this disclosure, the testing module is further configured to monitor the testing progress of each core when any one or more memory blocks have not been tested, and to use the cores of the multi-core processor that have completed testing to perform read and write tests on any one of the one or more memory blocks until the read and write tests on all memory blocks in the memory chip are completed.

[0032] In one exemplary embodiment of this disclosure, the memory chip includes dynamic random access memory.

[0033] According to a third aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the testing method for any of the above-described memory chips.

[0034] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform a test method for any of the above-described memory chips by executing the executable instructions.

[0035] This disclosure has the following beneficial effects:

[0036] According to the memory chip testing method, memory chip testing apparatus, computer-readable storage medium, and electronic device in this exemplary embodiment, the memory blocks corresponding to each core in a multi-core processor can be determined. Read and write tests are then performed on the corresponding memory blocks by each core in the multi-core processor, and the test results of the memory chip are determined based on the test results of each memory block. This solution divides the memory cells in the memory chip into multiple memory blocks and allocates them to different cores of the multi-core processor. By utilizing each core to perform read and write tests on the corresponding memory blocks, the processing performance of the multi-core processor can be fully utilized, improving the testing efficiency of the memory chip.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0039] Figure 1 A flowchart illustrating a testing method for a memory chip in this exemplary embodiment is shown;

[0040] Figure 2 This example illustrates a method for determining a storage block in this exemplary embodiment;

[0041] Figure 3 A sub-flowchart of a testing method for a memory chip is shown in this exemplary embodiment;

[0042] Figure 4 This diagram illustrates a structural block diagram of a testing apparatus for a memory chip according to this exemplary embodiment.

[0043] Figure 5 This illustration shows a computer-readable storage medium for implementing the above-described method in this exemplary embodiment;

[0044] Figure 6 An electronic device for implementing the above method is shown in this exemplary embodiment. Detailed Implementation

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0046] The exemplary embodiments of this disclosure first provide a testing method for memory chips. This method can utilize multiple cores of a multi-core processor to perform read and write tests on local storage areas within the memory chip, thereby detecting the read and write performance of the memory chip. Simultaneously, it enables flexible testing of the memory chip, improving testing efficiency. In this exemplary embodiment, the memory chip can be a dynamic random access memory (DRAM), a semiconductor memory that can include multiple storage cells. Each storage cell is a unit within the memory chip that has the function of storing data and reading / writing data. Structurally, a storage cell can consist of a transistor and a capacitor. By controlling the amount of charge stored in the capacitor, a binary bit can be represented as 0 or 1. Generally, a memory chip can include multiple storage cells, and these cells can be arranged in any shape, such as a storage array of any shape.

[0047] Figure 1 A process of this exemplary embodiment is shown, which may include the following steps S110 to S120:

[0048] Step S110. Determine the memory block corresponding to each core in the multi-core processor.

[0049] In this context, a memory block refers to a local storage area composed of a portion of memory cells within a memory chip. The number of memory cells contained in each memory block can be the same or different. A multi-core processor integrates two or more complete computing engines, or cores, into a single processor. In this case, the processor can support multiple processors on the system bus, with the bus controller providing all bus control and command signals. A multi-core processor can decompose the task to be processed into multiple parts, assigning each part to different core registers for multiple arithmetic units to perform joint calculations. The calculation results are then aggregated and processed by one arithmetic unit before being distributed to the next step, or the program can directly control the distribution of each calculation result to the next step.

[0050] In this exemplary embodiment, the memory chip can be divided into multiple memory blocks. During testing, the memory block corresponding to each core can be determined first. For example, as... Figure 2 As shown, CPU1, CPU2, CPU3...CPUN, CPUa, and CPUb are different cores. Following the rule that one core corresponds to one memory block, each memory block in the memory chip is assigned to each core in the multi-core processor; for example, the memory block corresponding to CPU1 is memory block 1. In this method, the memory blocks corresponding to each core are different. This method allows for the determination of the memory block corresponding to each core, i.e., a combination of multiple memory units, achieving effective grouping of memory units and improving the testing flexibility of the memory chip.

[0051] As the storage capacity of memory chips increases, the number of storage cells within them also increases. To facilitate the determination of the storage block corresponding to each core in a multi-core processor, in one optional implementation, the memory chip can first be divided into storage blocks of the same or different sizes according to the storage addresses of each storage cell. The storage address is the number of the storage cell within the memory chip, which uniquely identifies each storage cell.

[0052] Based on the storage addresses of the individual storage cells in a memory chip, the storage cells can be divided into multiple storage blocks. The size of each storage block can be arbitrary, and within each block, the storage cells can be adjacent or non-adjacent. For example, X consecutive storage cells can be grouped into one storage block based on their storage addresses, thus dividing the memory chip into multiple storage blocks according to the continuity of their storage addresses. Here, X is a positive integer. Alternatively, storage cells with the same row or column address can be grouped into one storage block, i.e., the storage cells are divided into multiple storage blocks according to the row and column relationships of the storage cells forming the memory array. By dividing the storage cells of a memory chip into multiple storage blocks, arbitrary grouping of storage cells can be achieved, and the grouping rules can be customized by the testers, meeting various different testing and grouping needs and offering high flexibility.

[0053] Based on the above method, when determining the memory block corresponding to each core in a multi-core processor, in one optional implementation, the memory block corresponding to each core can be determined according to the address information of the memory block corresponding to each core in the multi-core processor. The address information of the memory block can include the storage addresses of the storage cells contained in each memory block of the memory chip. For example, for N cores of a multi-core processor, the memory blocks corresponding to each core can be determined sequentially according to the address order of the memory blocks. Alternatively, according to the rule that one core corresponds to a fixed number of storage cells, the memory block corresponding to each core can be determined as a storage area consisting of X storage cells in the memory chip based on the storage addresses of the storage cells in the memory chip. That is, one core corresponds to X storage cells, and the storage cells in the memory blocks corresponding to each core are not repeated.

[0054] In addition, in an optional implementation, the address correspondence between each core and the storage block can be pre-configured by the tester. For example, the tester can pre-establish a configuration table based on the address correspondence between the core and the storage block. When determining the storage block corresponding to each core, the storage block corresponding to each core and the storage address of the storage unit in the storage block can be determined according to the configuration table, thereby finding the storage block corresponding to each core in the storage chip.

[0055] Because the storage address identifies the uniqueness of the storage unit, the method described above for determining the storage block corresponding to each core based on the address information of the storage block can ensure that the storage units in the storage block corresponding to each core are unique. That is, there is no duplication of storage units in any two storage blocks. This can avoid the problems of low test efficiency and test disorder caused by testing duplicate units, which affect the test results.

[0056] Step S120. Perform read and write tests on the corresponding memory blocks using each core of the multi-core processor, and determine the test results of the memory chip based on the test results of each memory block.

[0057] Read / write testing refers to fully writing to or fully reading from the memory cells of the memory chip being tested, or traversing the memory cells in a read-then-write or other different read / write combinations. The test results are used to characterize whether read / write errors occur in each memory cell, such as whether there are memory cells that cannot be written to normally or whose read data is inconsistent with the written data.

[0058] After identifying the memory blocks corresponding to each core, each core can perform read and write tests on its respective memory block. Each core then determines the test results for its corresponding memory block. The multi-core processor can then analyze and process these test results, such as performing statistical analysis and deduplication, to determine the final test results for the memory chip. In this approach, the multi-core processor can run multiple cores simultaneously to execute test tasks, thus significantly improving the testing efficiency of the memory chip.

[0059] To ensure the comprehensiveness of the memory chip testing, in one optional implementation, the following method may also be performed before step S120:

[0060] The startup loader is loaded and run by a multi-core processor to activate each core in the multi-core processor, so that each core can perform read and write tests on the corresponding memory blocks when it is in an activated state.

[0061] The bootloader, also known as the startup loader, is the first piece of code executed by an embedded system after power-on. It initializes hardware devices and establishes a memory space mapping table, essentially setting up the appropriate system hardware and software environment to prepare for calling the various cores of a multi-core processor. The bootloader can run in static random-access memory (SRAM), and when active, each core runs within the bootloader. In other words, when active, each core executes a test task for the memory block, while simultaneously running within its bootloader. SRAM is a type of memory with static access capabilities; it retains its internal data without needing to be refreshed while powered on.

[0062] For a computer system, from power-on to operating system startup, a multi-core processor can load and run a bootloader to complete the boot process, activate each core of the processor, and perform multi-core scheduling for memory chip testing tasks. This allows each core to perform read and write tests on its corresponding memory blocks while active. Because each core runs the bootloader in SRAM during testing, it does not occupy the memory space of the memory chip, thus meeting the comprehensive testing needs of the memory chip and improving testing efficiency.

[0063] In a multi-core processor, each core can be used to independently complete processing tasks. Therefore, in order to perform read and write tests on each memory block, in one optional implementation, the following method can be performed to perform read and write tests on each memory block:

[0064] Each core in the multi-core processor performs read and write tests on its corresponding memory blocks until all memory blocks in the memory chip have been tested, and the test results for each memory block are obtained.

[0065] Each core performs read and write tests on its corresponding memory block. For example, a certain number of cores can be controlled to perform read and write tests on their respective memory blocks simultaneously. After the read and write tests are completed, each core can obtain the test results for its tested memory block. Furthermore, when a core corresponds to two or more memory blocks, it can sequentially perform read and write tests on each of its associated memory blocks until all memory blocks corresponding to that core have been tested. This method allows control of the cores in a multi-core processor to test memory blocks according to predetermined rules, satisfying diverse testing needs.

[0066] Furthermore, in an alternative implementation, the following method may also be performed:

[0067] The multi-core processor can simultaneously perform read and write tests on any one or more memory blocks corresponding to each core; or the multi-core processor can sequentially perform read and write tests on any one or more memory blocks corresponding to each core.

[0068] When each core simultaneously performs read / write tests on different memory blocks, each core executes the test program for each memory block concurrently. In this method, the cores run in parallel, maximizing the processing performance of the multi-core processor and improving the testing efficiency of the memory chip. Conversely, when each core sequentially performs read / write tests on different memory blocks, each core executes the test program for each memory block sequentially. This method allows for asynchronous core execution, fully leveraging the processing flexibility of the multi-core processor. For example, at any given moment, one core can execute a write test while another core executes a read test. Through these methods, the multi-core processor can be controlled to perform read / write tests on memory blocks according to different operating modes, offering high flexibility.

[0069] In this exemplary embodiment, the testing methods for each storage block can be the same or different. For example, the testing method for one storage block can be represented by the test algorithm primitive: (w), (r, w), (r), (w), (r, w, r), (r). This method requires traversing the storage cells of the storage chip 6 times. The testing method for another storage block can be represented by the test algorithm primitive: (w, r), (w), (r), (w). This method only requires traversing the storage cells of the storage chip 4 times. Here, (w) or (r) represents performing a write or read operation on all storage cells of the storage chip. (r, w) represents performing a read-then-write operation on the storage cells of the storage chip according to the size of one access, such as 1 byte, 4 bytes, 8 bytes, etc., to traverse all storage cells of the storage chip. (r, w, r) represents performing a read-then-write-then-read operation on the storage cells of the storage chip according to the size of one access, to traverse all storage cells of the storage chip. In the above process, the data written in the two steps can be the same or different. Based on this, in one optional implementation, when performing read / write tests on the corresponding memory blocks using each core of the multi-core processor, reference is made to... Figure 3 As shown, the following methods can also be executed:

[0070] Step S310: When performing read and write tests on each storage block, determine the test strategy for each storage block in the storage chip.

[0071] The testing strategy may include a test procedure for performing data read and / or data write operations on each storage block. A test procedure refers to the stages of performing data read and write operations on each storage block. Data read and write operations on the same test data can be considered as one test procedure, or any type of data read or write operation can be considered as one test procedure. The test procedure may include the order and frequency of data read and write operations on each storage block. In addition, the testing strategy may also include test parameters when performing data read or write operations, such as the voltage values ​​of control signals.

[0072] When performing read / write tests on the associated storage blocks using each core, the test process for each storage block can be predetermined. For example, the operation steps required for each storage block and the order of each operation step can be determined based on a pre-configured test rule table.

[0073] In step S320, each core in the multi-core processor performs data read and / or data write operations on its corresponding memory block according to the test procedure.

[0074] During testing, a multi-core processor can control each core to perform data read and write operations on its corresponding storage block according to a unified testing procedure. This method ensures that all storage blocks are tested using a unified testing procedure, guaranteeing the consistency, comprehensiveness, and accuracy of the tests. Furthermore, since the testing procedure can be configured by the testers, it also improves the flexibility and convenience of the testing process.

[0075] Furthermore, for different test processes, the test data written to or read from the storage block may be different. Therefore, in an optional implementation, the test strategy may also include the test data for each test process, and step S320 may also be implemented by the following method:

[0076] Determine the target test data for the currently executed test process;

[0077] Each core performs data read and / or data write operations on the target test data in its respective storage block.

[0078] Test data refers to the data written to test the read and write functions of the storage unit. Since storage chips store data in binary format, test data can be any binary sequence. Target test data refers to the test data that needs to be read or written in the currently executed data read or write operation.

[0079] In this exemplary embodiment, the multi-core processor can control each core to execute test tasks on the corresponding memory blocks. During test task execution, each core can determine the currently executed test process, i.e., the target test data corresponding to data read operations and / or data write operations. Each core then writes or reads the target test data from its respective memory block. This method ensures the correctness of data writing at each test stage and allows for the determination of data correctness based on the read data and test data during read operations. This improves the efficiency of determining test results, and testers can set different test data for different test stages to meet the testing requirements of each stage.

[0080] In addition, data read and write operations in the test process can be executed sequentially. Therefore, in an optional implementation, while all cores in the multi-core processor are completing the read and write tests on their respective memory blocks according to the currently executed test process, each core can be controlled to perform read and write tests on its respective memory blocks according to the next test process.

[0081] For test tasks with multiple test processes, each core executes each test process sequentially. Only when each core completes the current test process for each storage block will the next test process be executed for each storage block, thus avoiding test errors to a certain extent.

[0082] In this exemplary embodiment, since the size of the storage blocks may vary, and the speed of each core in a multi-core processor may also differ, even if the access order of each core to the storage block is corresponding at the beginning of the test, as the test process switches or the storage block is repeatedly accessed, it may be possible that each core is executing different test processes at the same time, causing test errors in the storage block. Therefore, in order to achieve synchronous testing of each core, in an optional embodiment, the following method can also be performed:

[0083] When performing read / write tests on each storage block, once any one or more cores in the multi-core processor complete the read / write test on their respective storage blocks according to the currently executed test process, control any one or more cores to enter a waiting state and trigger a counter to count.

[0084] When the counter determines that all cores in the multi-core processor have entered a waiting state, the cores in the multi-core processor are reactivated, and each core is controlled to perform read and write tests on its corresponding memory block according to the next test procedure.

[0085] In the waiting state, cores do not execute test tasks. For example, when a multi-core processor controls each core to begin testing its corresponding memory block, each core is activated one by one, and the count continuously increments by 1. When the count value equals the total number of activated cores, all cores enter the waiting state, indicating that core synchronization is complete. Then, the multi-core processor can control the activated cores to execute the test process for their respective memory blocks according to the corresponding memory block allocation rules. When a core completes its current test process, the multi-core processor can control that core to enter the waiting state, and a counter can be used to count, such as decrementing the count by 1. As other cores also complete their current test processes, the counter is continuously decremented by 1 until it reaches zero. At this point, all cores in the waiting state are reactivated, and the counter is incremented by 1, until all cores return to the waiting state, at which point all cores are controlled to execute the next test process. Here, count represents the number of cores in the waiting state at the current moment. When the counter result determines that all cores have entered the waiting state, it means that all cores have completed their current test process, and the multi-core processor can then control each core to execute the next test process for its corresponding memory block. This method ensures that the core can complete the testing process within the specified limits, ensures the synchronization of the core's execution of the testing process, prevents false test results caused by test process disorder, avoids misjudgment, and improves test accuracy.

[0086] When testing memory chips, it is sometimes necessary to perform non-access operations on them. Therefore, in one optional implementation, the test strategy may also include a process of global control operations on the memory cells within the memory chip. These global control operations are the non-access operations performed on the memory chip, and may include data retention operations and / or data refresh operations on the memory cells. Specifically, a data retention operation refers to controlling the data written to the memory chip to remain for a period of time to ensure that the written data does not change unexpectedly due to time or leakage current. A data refresh operation refers to the periodic charging operation performed on the high-potential capacitors in the memory cells. This operation can maintain the stability of the high-potential capacitors, allowing them to continuously store data. Data refresh operations may include self-refresh operations or controller-controlled refresh operations.

[0087] Therefore, during read / write tests on each memory block, any core in the multi-core processor can perform global control operations on all memory cells in the memory chip according to the global control operation flow. For example, after completing any one or more test processes, the multi-core processor can control the core that last completed the test process to perform data retention and data refresh operations on all memory cells in the memory chip. The execution time of this operation can be preset by the tester. By executing global control operations, continuous data storage can be ensured during read / write tests on the memory chip, thereby avoiding the influence of external factors on subsequent test results.

[0088] Furthermore, as mentioned earlier, one core can correspond to one or more storage blocks. In this way, such as Figure 2 As shown, when the number of cores N in the multi-core processor is equal to the number of memory blocks M, the completion of read / write tests by all cores signifies the end of the entire test task. Similarly, when the number of cores N in the multi-core processor is greater than the number of memory blocks M, the completion of read / write tests by all cores allocated memory blocks also signifies the end of the entire test task. When the number of cores N in the multi-core processor is less than the number of memory blocks M, after all cores have completed read / write tests, there are still remaining memory blocks in the memory chip. In an optional implementation, to complete the read / write tests of these remaining memory blocks, the following method can also be performed:

[0089] When any one or more memory blocks have not been tested, monitor the testing progress of each core, and use the cores in the multi-core processor that have completed the testing to perform read and write tests on any one of the memory blocks until all memory blocks in the memory chip have been tested.

[0090] In the above method, there is a one-to-one correspondence between memory blocks and cores. When a core completes the test of its corresponding memory block, the multi-core processor can detect untested memory blocks and then use the cores that have completed the tests to perform read and write tests on the untested memory blocks. For example, in... Figure 2 In the storage block partitioning example shown, assuming CPUa is the core that completes the test first, then for the remaining untested storage block, i.e. the N+1th storage block, CPUa can be used to perform read and write tests on the N+1th storage block first, while monitoring the test progress of all cores. Then, CPUb, the core that has just completed the read and write test, can be used to perform read and write tests on the N+2th storage block, until all storage blocks have completed the read and write tests.

[0091] After each core completes the read / write test of its corresponding memory block, the test results of that memory block can be obtained. In order to obtain the test results of the entire memory chip, in one optional implementation, the test results of each memory block may include whether a read / write error occurred in the memory cell of the corresponding memory block and the number of address bits where the read / write error occurred. Therefore, the test results of the memory chip can be obtained by the following method:

[0092] Based on the test results of each memory block, the memory cell in the memory chip that experienced read / write errors and the number of address bits of the memory cell that experienced read / write errors are determined in order to obtain the test results of the memory chip.

[0093] After obtaining the test results of each memory block, the memory cells that experienced read / write errors and the address bits of those memory cells can be counted in each memory block. This allows us to obtain the memory cells that experienced read / write errors and their address bits in the entire memory chip, thus obtaining the test results of the memory chip.

[0094] In summary, according to the memory chip testing method in this exemplary embodiment, the memory blocks corresponding to each core in a multi-core processor can be determined, and read / write tests can be performed on the corresponding memory blocks by each core in the multi-core processor. The test results of the memory chip are then determined based on the test results of each memory block. This solution, by dividing the memory cells in the memory chip into multiple memory blocks and allocating them to different cores of the multi-core processor, and utilizing each core to perform read / write tests on the corresponding memory blocks, can fully utilize the processing performance of the multi-core processor and improve the testing efficiency of the memory chip.

[0095] This exemplary embodiment also provides a testing apparatus for a memory chip, with reference to... Figure 4 As shown, the memory chip testing device 400 may include: a determination module 410, which can be used to determine the memory block corresponding to each core in the multi-core processor, wherein the memory block is a local memory area composed of some memory cells in the memory chip; and a testing module 420, which can be used to perform read and write tests on the corresponding memory blocks through each core in the multi-core processor, and determine the test results of the memory chip based on the test results of each memory block obtained from the test.

[0096] In one exemplary embodiment of this disclosure, the determining module 410 divides the memory chip into multiple memory blocks by performing the following method: dividing the memory chip into memory blocks with memory regions of the same or different sizes according to the memory address of each memory cell in the memory chip.

[0097] In one exemplary embodiment of this disclosure, the determining module 410 can be used to determine the memory block corresponding to each core based on the address information of the memory block corresponding to each core in the multi-core processor. The address information includes the storage address of the memory cell contained in each memory block in the memory chip. The testing module 420 can be used to perform read and write tests on the corresponding memory block by each core in the multi-core processor until the read and write tests on all memory blocks in the memory chip are completed, and the test results of each memory block are obtained.

[0098] In one exemplary embodiment of this disclosure, the test module 420 can also be used to perform read and write tests on any one or more memory blocks corresponding to each core of the multi-core processor simultaneously; or to perform read and write tests on any one or more memory blocks corresponding to each core of the multi-core processor sequentially.

[0099] In one exemplary embodiment of this disclosure, the test results of each storage block include whether a read / write error occurred in the storage cell of the corresponding storage block and the number of address bits that caused the read / write error. The test module 420 can also be used to determine the storage cell in the storage chip that caused the read / write error and the number of address bits of the storage cell that caused the read / write error based on the test results of each storage block, so as to obtain the test results of the storage chip.

[0100] In one exemplary embodiment of this disclosure, before performing read / write tests on the corresponding storage blocks by each core in the multi-core processor, the test module 420 can also be used to load and run a bootloader through the multi-core processor to activate each core in the multi-core processor, so that each core performs read / write tests on the corresponding storage blocks when it is in an activated state; wherein, the bootloader runs in the static random access memory, and each core runs in the bootloader when it is in an activated state.

[0101] In one exemplary embodiment of this disclosure, when performing read / write tests on the corresponding memory blocks by each core in the multi-core processor, the test module 420 can also be used to determine the test strategy for each memory block in the memory chip when performing read / write tests on each memory block. The test strategy includes a test process for performing data read operations and / or data write operations on each memory block, and each core in the multi-core processor performs data read operations and / or data write operations on its corresponding memory block according to the test process.

[0102] In one exemplary embodiment of this disclosure, the test strategy also includes test data for each test process, and the test module 420 can also be used to determine the target test data for the currently executed test process; each core performs data reading and / or data writing operations on the target test data in its corresponding storage block according to the currently executed test process.

[0103] In one exemplary embodiment of this disclosure, the test module 420 can also be used to control each core to perform read and write tests on its corresponding memory block according to the next test process when all cores in the multi-core processor complete the read and write tests on their respective memory blocks according to the currently executed test process.

[0104] In one exemplary embodiment of this disclosure, the test module 420 can also be used to control any one or more cores to enter a waiting state and trigger a counter to count when any one or more cores in the multi-core processor complete the read and write test of their respective corresponding storage blocks according to the currently executed test process during read and write tests of each storage block. When it is determined from the count result of the counter that all cores in the multi-core processor have entered the waiting state, the cores in the multi-core processor are reactivated and each core is controlled to perform read and write tests of their respective corresponding storage blocks according to the next test process.

[0105] In one exemplary embodiment of this disclosure, the test strategy further includes an operation process for performing global control operations on the storage cells in the storage chip. The test module 420 can also be used to perform global control operations on all storage cells in the storage chip by any one core of the multi-core processor according to the operation process of the global control operation. The global control operation includes data retention operations and / or data refresh operations on the storage cells in the storage chip.

[0106] In one exemplary embodiment of this disclosure, the test module 420 can also be used to monitor the test progress of each core when there are any one or more memory blocks that have not been tested, and use the cores in the multi-core processor that have completed the test to perform read and write tests on any one of the one or more memory blocks until the read and write tests on all memory blocks in the memory chip are completed.

[0107] In one exemplary embodiment of this disclosure, the memory chip includes dynamic random access memory.

[0108] The specific details of each module in the above-mentioned device have been described in detail in the method section of the implementation plan. For details of the undisclosed scheme, please refer to the implementation plan of the method section, and therefore will not be repeated here.

[0109] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0110] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0111] refer to Figure 5 As shown, a program product 500 for implementing the above-described method according to an exemplary embodiment of the present disclosure is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0112] The program product 500 may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0113] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0114] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0115] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing devices can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0116] Exemplary embodiments of this disclosure also provide an electronic device capable of implementing the above-described method. Referring below... Figure 6 To describe an electronic device 600 according to such an exemplary embodiment of the present disclosure. Figure 6 The electronic device 600 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0117] like Figure 6 As shown, the electronic device 600 can be manifested in the form of a general-purpose computing device. The components of the electronic device 600 may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different system components (including storage unit 620 and processing unit 610), and a display unit 640.

[0118] The storage unit 620 stores program code, which can be executed by the processing unit 610 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 610 can execute... Figure 1 and Figure 3 The methods and steps shown are as follows.

[0119] Storage unit 620 may include readable media in the form of volatile storage units, such as random access memory (RAM) 621 and / or cache memory 622, and may further include read-only memory (ROM) 623.

[0120] Storage unit 620 may also include a program / utility 624 having a set (at least one) of program modules 625, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0121] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0122] Electronic device 600 can also communicate with one or more external devices 700 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 660. As shown, network adapter 660 communicates with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0123] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to exemplary embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0124] Furthermore, the above figures are merely illustrative representations of the processes included in the methods according to exemplary embodiments of this disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0125] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the exemplary embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method according to the exemplary embodiments of this disclosure.

[0126] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A testing method for a memory chip, characterized in that, The method includes: Determine the memory block corresponding to each core in a multi-core processor, wherein the memory block is a local memory region composed of some memory cells in a memory chip; The multi-core processor loads and runs a bootloader to activate each core in the multi-core processor, so that each core, when in the activated state, performs read and write tests on the corresponding memory block; wherein, the bootloader runs in static random access memory, and each core runs in the bootloader when in the activated state; The cores in the multi-core processor perform read and write tests on the corresponding memory blocks, and the test results of the memory chip are determined based on the test results of each memory block.

2. The method according to claim 1, characterized in that, When dividing the memory chip into multiple memory blocks, at least one of the following division methods is included: Multiple consecutive memory locations are grouped into one memory block; or memory locations with the same row address or the same column address are grouped into one memory block.

3. The method according to claim 1, characterized in that, The memory chip is divided into multiple memory blocks using the following method: According to the storage address of each storage cell in the storage chip, the storage chip is divided into storage blocks with storage areas of the same or different sizes.

4. The method according to claim 1, characterized in that, The process of determining the memory block corresponding to each core in a multi-core processor includes: Based on the address information of the memory block corresponding to each core in the multi-core processor, the memory block corresponding to each core is determined, wherein the address information includes the memory address of the memory unit contained in each memory block in the memory chip; The step of performing read / write tests on the corresponding memory blocks using each core of the multi-core processor includes: Each core in the multi-core processor performs read and write tests on its corresponding memory block until all memory blocks in the memory chip have been tested, and the test results for each memory block are obtained.

5. The method according to claim 4, characterized in that, The step of having each core in the multi-core processor perform read / write tests on the corresponding memory blocks also includes: Each of the cores in the multi-core processor simultaneously performs read and write tests on any one or more corresponding memory blocks; or Each core in the multi-core processor sequentially performs read and write tests on any one or more memory blocks corresponding to it.

6. The method according to claim 4, characterized in that, The test results for each memory block include whether read / write errors occurred in the memory cells within the corresponding memory block and the number of address bits where read / write errors occurred. Determining the test results of the memory chip based on the test results of each memory block includes: Based on the test results of each memory block, the memory cell in the memory chip that experienced a read / write error and the number of address bits of the memory cell that experienced the read / write error are determined to obtain the test results of the memory chip.

7. The method according to claim 1, characterized in that, When performing read / write tests on the corresponding memory blocks using each of the cores in the multi-core processor, the method further includes: When performing read and write tests on each of the storage blocks, a test strategy for each of the storage blocks in the storage chip is determined. The test strategy includes a test process for performing data read operations and / or data write operations on each of the storage blocks. Each core in the multi-core processor performs data read and / or data write operations on its corresponding storage block according to the test procedure.

8. The method according to claim 7, characterized in that, The testing strategy also includes test data for each of the test processes, and the step of each core in the multi-core processor performing data read and / or data write operations on its corresponding storage block according to the test process further includes: Determine the target test data for the currently executed test process; Each of the aforementioned cores performs data reading and / or data writing operations on the target test data in its respective storage block according to the currently executed test process.

9. The method according to claim 8, characterized in that, The method further includes: When all cores in the multi-core processor complete the read / write test of their respective memory blocks according to the currently executed test process, control each core to perform read / write test of its respective memory blocks according to the next test process.

10. The method according to claim 9, characterized in that, The method further includes: When performing read / write tests on each of the aforementioned storage blocks, when any one or more cores in the multi-core processor complete the read / write test on their respective storage blocks according to the currently executed test process, the one or more cores are controlled to enter a waiting state and a counter is triggered to count. When it is determined from the counter's count that all cores in the multi-core processor have entered the waiting state, each core in the multi-core processor is reactivated, and each core is controlled to perform read and write tests on its corresponding memory block according to the next test procedure.

11. The method according to claim 7, characterized in that, The testing strategy also includes an operation process for performing global control operations on the memory cells in the memory chip, and the method further includes: Any one core of the multi-core processor performs global control operations on all memory cells in the memory chip according to the operation flow of the global control operation. The global control operation includes data retention operations and / or data refresh operations performed on the storage cells in the storage chip.

12. The method according to claim 4, characterized in that, The method further includes: When any one or more memory blocks have not been tested, the testing progress of each core is monitored, and the cores in the multi-core processor that have completed testing are used to perform read and write tests on any one of the memory blocks until all memory blocks in the memory chip have been tested.

13. The method according to claim 1, characterized in that, The memory chip includes dynamic random access memory.

14. A testing apparatus for a memory chip, characterized in that, The device includes: The determination module is used to determine the memory block corresponding to each core in a multi-core processor, wherein the memory block is a local memory region composed of some memory cells in a memory chip; The testing module is used to load and run a bootloader through the multi-core processor, activate each core in the multi-core processor, so that each core performs read and write tests on the corresponding memory block when it is in the activated state; wherein, the bootloader runs in static random access memory, and each core runs in the bootloader when it is in the activated state; and to perform read and write tests on the corresponding memory block through each core in the multi-core processor, and determine the test result of the memory chip based on the test results of each memory block obtained from the test.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-13.

16. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1-13 by executing the executable instructions.

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