A silicon carbide field effect transistor and a method of fabricating the same

Abstract

The application discloses a silicon carbide field effect transistor and a preparation method thereof, and relates to the technical field of semiconductors. A deeper PWELL body region (also called a PWELL doped region) increases the electric field shielding effect of a lateral electric field between the PWELL and an N-drift region on a Schottky junction, reduces the electric field of the Schottky junction, and lowers leakage. The Schottky junction has smaller leakage, when experiencing a UIS working condition, a part of the current is shunted from the PWELL body region to an external electrode, thereby reducing the local current density and power consumption, lowering the heating of the device, and increasing the UIS capability and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide field-effect transistor and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor material, is widely used in power systems due to its advantages such as large bandgap, strong thermal stability, high thermal conductivity, and strong radiation resistance. These systems include applications in new energy vehicles, photovoltaic power generation, high-speed rail, and urban rail transit. SiC MOSFET devices, as switches in power systems, are also widely used in various power electronic systems.

[0003] To save on production costs, the parasitic body diode in SiC MOSFET devices is often used as a freewheeling diode in power electronic systems. The bipolar conduction effect of the body diode leads to a large reverse recovery peak charge and voltage and current oscillations during reverse recovery, resulting in increased switching losses, transistor false turn-on, and electromagnetic interference. Some researchers have proposed integrating a junction barrier Schottky diode (JBS) into the SiC MOSFET chip. While this method solves the problems associated with bipolar conduction, the characteristics of the Schottky junction increase leakage current, reduce UIS immunity, and compromise reliability. Therefore, how to reduce leakage current and enhance UIS immunity and reliability in SiC MOSFET chips with integrated JBS is a crucial issue. Summary of the Invention

[0004] To address the above problems, this invention provides a silicon carbide field-effect transistor and its fabrication method that reduce leakage current and enhance UIS capability and reliability.

[0005] The technical solution of this invention is: a method for fabricating a silicon carbide field-effect transistor, comprising the following steps: Step 100: Fabricate the device drift region; Step 200, PWELL body region preparation S210 involves depositing a silicon dioxide layer and a polysilicon layer on a lightly doped epitaxial layer N-, then etching away the unwanted silicon dioxide layer and polysilicon layer, leaving the remaining layer as a hard mask. S220, searching Ion implantation was performed on the crystal orientation of the sample to form a 2µm PWELL bulk region; Step 300: Preparation of NN and PP regions S310 involves depositing a silicon dioxide layer on the wafer surface and then etching the silicon dioxide layer to form sidewalls. S320, the top of the PWELL bulk region, the PP region to be implanted is blocked by photoresist, and the NN region is formed by nitrogen ion implantation in the blocked region; S330 uses photoresist to block the top surface of the NN region, removes the photoresist from the top surface of the PP region to be implanted, and forms the PP region through photolithography, development, and ion implantation of aluminum. S340 sputters a carbon film onto the wafer surface and anneals it at high temperature to activate all implanted ions; Step 400: Prepare a silicon dioxide layer as the gate oxide. S410: After removing the carbon film on the wafer surface, a first silicon dioxide layer is grown with wet oxygen, and then the first silicon dioxide layer is removed to improve the surface roughness of the wafer. S420 uses a 50nm second silicon dioxide layer grown in dry oxygen at a high temperature of 1300°C as the gate oxide. S430, after the gate oxide is grown, is cooled to 1200°C and nitric oxide and nitrogen are introduced for surface passivation treatment. Step 500: Prepare a saturated doped first polycrystalline silicon layer on the second silicon dioxide layer; Step 600: Nickel metal is evaporated from the wafer to form a Schottky contact and an ohmic contact on the front side, and an ohmic contact on the back side.

[0006] Specifically, the preparation method in step S100 is as follows: At 1E19 / cm 3 A 1E16 / cm layer is grown on a heavily doped N-type epitaxial substrate N+. 3 The lightly doped N-type epitaxial layer serves as the drift region of the device.

[0007] Specifically, the preparation method of step S500 is as follows: A first polysilicon layer is deposited on the second silicon dioxide layer. Phosphorus ions are implanted into the first polysilicon for saturation doping. Then, excess first polysilicon is etched away through photolithography, development, etching and other processes.

[0008] Specifically, the preparation method of step S600 is as follows: An interlayer dielectric is deposited on a saturated doped polysilicon layer. Excess ILD is then etched away using photolithography, development, and etching processes. Nickel metal is then evaporated on the front side of the wafer, and Schottky and ohmic contacts are formed through rapid thermal annealing. Ohmic contacts are formed on the back side using the same process.

[0009] Specifically, in step S340, the carbon film is annealed at a high temperature of 1800°C.

[0010] Specifically, in step S410, after removing the carbon film on the wafer surface, a 30nm first silicon dioxide layer is grown using wet oxygen.

[0011] A silicon carbide field-effect transistor includes an N-type epitaxial substrate N+, an N-type epitaxial layer N-, a second silicon dioxide layer and a polysilicon layer connected sequentially from bottom to top. The N-type epitaxial layer N- has a PWELL body region extending downward from the top surface, and the depth of the PWELL body region is greater than 1 μm; the PWELL body region has an NN region and a PP region extending downward from the top surface. The second silicon dioxide layer and the polysilicon layer are located in the middle of the N-type epitaxial layer N-, and are wrapped on the outside by an interlayer dielectric. The top surface of the N-type epitaxial layer is provided with nickel metal that is connected to the interlayer dielectric, and the nickel metal is connected to the PP region.

[0012] The depth of the NN region is less than the depth of the PP region.

[0013] Beneficial effects of this invention: Mass-produced SiMOS devices typically lack a Schottky junction. To mitigate the bipolar conduction effect of SiMOS, researchers have introduced an additional Schottky junction, commonly referred to as a JMOS. However, Schottky junction leakage current is highly sensitive to the electric field and can be significant. Furthermore, it is prone to overheating and damage when the UIS is in an open environment. The issue of high leakage current in JMOS devices remains unresolved.

[0014] The deeper PWELL body region (also called the PWELL doped region) in this case increases the lateral electric field shielding effect of the PWELL and N-drift regions on the Schottky junction, reducing the electric field of the Schottky junction and thus reducing leakage current. With reduced leakage current, during UIS (Underlying Current Injection) conditions, a portion of the current is shunted from the PWELL body region to the external electrodes, thereby reducing local current density and power consumption, lowering device heat generation, and ultimately increasing the device's UIS capability and reliability. Attached Figure Description

[0015] Figure 1 This is a structural schematic diagram of step 100 of the present invention. Figure 2 This is a structural schematic diagram of step 200 of the present invention. Figure 3 This is a structural schematic diagram of step S310 of the present invention. Figure 4 This is a structural schematic diagram of step S330 of the present invention. Figure 5 This is a structural schematic diagram of step S340 of the present invention. Figure 6 This is a structural schematic diagram of step S430 of the present invention. Figure 7 This is a structural schematic diagram of step 500 of the present invention. Figure 8 This is a structural schematic diagram of step 600 of the present invention. Figure 9 This is the curve showing the relationship between IDSS and VDS; In the diagram, 100 is the hard mask, 200 is the sidewall, 300 is the carbon film, 400 is the second silicon dioxide layer, 500 is the first polysilicon layer, 600 is the interlayer dielectric, and 700 is nickel metal. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0018] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0019] The present invention is as follows Figure 1-9 As shown; A method for fabricating a silicon carbide field-effect transistor includes the following steps: Step 100, Drift Region Preparation At 1E19 / cm 3 A 1E16 / cm layer is grown on a heavily doped N-type epitaxial substrate N+. 3 A lightly doped N-type epitaxial layer serves as the drift region of the device; reference Figure 1 As shown; Step 200, PWELL body region preparation S210, a silicon dioxide (SiO2) layer and a polysilicon (PolySi) layer are deposited on a lightly doped epitaxial layer N-. The unwanted silicon dioxide layer and polysilicon layer are removed by etching process, and the remainder is used as a hard mask (100). S220, searching The crystal orientation is determined by low- to medium-energy Channerling ion implantation or implantation using a 1000 keV high-energy ion implanter to form a 2 μm PWELL bulk region (pw region in the figure); refer to Figure 2 As shown; Step 300: Preparation of NN and PP regions S310 involves depositing a silicon dioxide layer on the wafer surface, followed by etching the silicon dioxide layer to form the spacer 200; (Refer to...) Figure 3 As shown; S320, the top of the PWELL bulk region, the PP region to be implanted is blocked by photoresist, and the NN region is formed by nitrogen ion implantation in the blocked region; S330 utilizes photoresist to mask the top surface of the NN region, removes the photoresist from the top surface of the PP region to be implanted, and forms the PP region through photolithography, development, and ion implantation of aluminum; (Refer to...) Figure 4 As shown; S340 involves sputtering a carbon film 300 onto the wafer surface and annealing it at 1800°C to activate all implanted ions; (Refer to...) Figure 5 As shown; Step 400: Prepare a silicon dioxide layer as the gate oxide. In S410, after removing the carbon film 300 on the wafer surface, a 30nm first silicon dioxide layer is grown using wet oxygen. This 30nm first silicon dioxide layer is then removed to improve the wafer surface roughness. The improved roughness is 1nm. Lower roughness leads to higher carrier mobility and reduces the device's characteristic resistance. The preceding ion implantation process damages the crystal lattice to a depth of approximately 30nm; removing this 30nm layer involves removing the damaged portion of the lattice.

[0020] S420, a 50nm second silicon dioxide layer 400 is grown in dry oxygen at a high temperature of 1300°C as the gate oxide; S430, after gate oxide growth, is cooled to 1200°C and then passivated with nitric oxide (NO) and nitrogen (N2); (Refer to...) Figure 6 As shown; Step 500: Prepare a saturated doped polycrystalline silicon layer A first polysilicon layer 500 is deposited on the second silicon oxide layer 400. Phosphorus ions are implanted into the first polysilicon 500 for saturation doping. Excess polysilicon 500 is then etched away using photolithography, development, and etching processes. (Refer to...) Figure 7As shown; Step 600: Form Schottky and Ohmic contacts. An interlayer dielectric (ILD) 600 is deposited on the saturated doped first polysilicon layer 500. Excess ILD is then etched away using photolithography, development, and etching processes. Nickel metal 700 is then evaporated on the front side of the wafer, and Schottky and ohmic contacts are formed through rapid thermal annealing. An ohmic contact reference is formed on the back side using the same process. Figure 8 As shown.

[0021] A silicon carbide field-effect transistor includes an N-type epitaxial substrate N+, an N-type epitaxial layer N-, a second silicon dioxide layer 400 and a polysilicon layer 500 connected sequentially from bottom to top. The N-type epitaxial layer N- has a PWELL body region extending downward from the top surface, and the depth of the PWELL body region is greater than 1 μm; the PWELL body region has an NN region and a PP region extending downward from the top surface. The second silicon dioxide layer 400 and the polysilicon layer 500 are located in the middle of the N-type epitaxial layer N-, and are wrapped on the outside by the interlayer dielectric 600; The top surface of the N-type epitaxial layer N- is provided with nickel metal 700 connected to the interlayer medium 600, and the nickel metal 700 is connected to the PP region.

[0022] The depth of the NN region is less than the depth of the PP region.

[0023] The improved silicon carbide field-effect transistor was compared with existing technology products in the following table: From Table 1 and Figure 9 It can be seen that the new structure proposed in the patent significantly reduces the leakage current of the device, thereby improving its resistance to UIS and reliability.

[0024] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for fabricating a silicon carbide field-effect transistor, characterized in that, Includes the following steps: Step 100: Fabricate the device drift region; Step 200, PWELL body region preparation; S210, a silicon dioxide layer and a polysilicon layer are deposited on a lightly doped epitaxial layer N-. The unwanted silicon dioxide layer and polysilicon layer are removed by etching process, and the remaining layer is used as a hard mask (100). S220, searching Ion implantation was performed on the crystal orientation of the target to form a PWELL bulk region with a depth of 2 μm; Step 300: Preparation of NN and PP regions; S310, a silicon dioxide layer is deposited on the wafer surface, and then the silicon dioxide layer is etched to form sidewalls (200). S320, the top of the PWELL bulk region, the PP region to be implanted is blocked by photoresist, and the NN region is formed by nitrogen ion implantation in the blocked region; S330: The top surface of the NN region is masked by photoresist, the photoresist on the top surface of the PP region to be implanted is removed, and the PP region is formed by photolithography, development, and ion implantation of aluminum; the depth of the NN region is less than the depth of the PP region. S340, a carbon film (300) is sputtered on the wafer surface and annealed at high temperature to activate all implanted ions; Step 400: Prepare a silicon dioxide layer as the gate oxide; S410, after removing the carbon film (300) on the wafer surface, a 30nm thick first silicon dioxide layer is grown by wet oxygen, and then the first silicon dioxide layer is removed to remove the lattice damage layer caused by ion implantation, in order to improve the roughness of the wafer surface. S420, a 50nm second silicon dioxide layer (400) is grown in dry oxygen at a high temperature of 1300°C as the gate oxide; S430, after the gate oxide is grown, is cooled to 1200°C and nitric oxide and nitrogen are introduced for surface passivation treatment. Step 500: Prepare a saturated doped first polycrystalline silicon layer (500) on the second silicon dioxide layer (400). Step 600: Nickel metal is evaporated from the wafer (700) to form a JMOS silicon carbide field-effect transistor with integrated JBS Schottky contact. Schottky contact and ohmic contact connected to the PP region are formed simultaneously on the front side of the nickel metal, and ohmic contact is formed on the back side.

2. The method for fabricating a silicon carbide field-effect transistor according to claim 1, characterized in that, The preparation method in step S100 is as follows: At 1E19 / cm 3 A 1E16 / cm layer is grown on a heavily doped N-type epitaxial substrate N+. 3 The lightly doped N-type epitaxial layer serves as the drift region of the device.

3. The method for fabricating a silicon carbide field-effect transistor according to claim 1, characterized in that, The preparation method of step S500 is as follows: A first polysilicon layer (500) is deposited on the second silicon dioxide layer (400), phosphorus ions are implanted into the first polysilicon layer (500) for saturation doping, and then excess first polysilicon layer (500) is etched away by photolithography, development and etching processes.

4. The method for fabricating a silicon carbide field-effect transistor according to claim 1, characterized in that, The preparation method of step S600 is as follows: An interlayer dielectric (600) is deposited on the first polysilicon layer (500) with saturated doping. The excess ILD is then etched away by photolithography, development and etching processes. Nickel metal (700) is then evaporated on the front side of the wafer, and Schottky contacts and ohmic contacts are formed by rapid thermal annealing. Ohmic contacts are formed on the back side using the same process.

5. The method for fabricating a silicon carbide field-effect transistor according to claim 1, characterized in that, In step S340, the carbon film (300) is annealed at a high temperature of 1800°C.

6. A silicon carbide field-effect transistor fabricated by the method described in claim 1, characterized in that, It includes an N-type epitaxial substrate N+, an N-type epitaxial layer N-, a second silicon dioxide layer (400), and a first polysilicon layer (500) connected sequentially from bottom to top. The N-type epitaxial layer N- has a PWELL body region extending downward from the top surface, and the depth of the PWELL body region is 2 μm; the PWELL body region has an NN region and a PP region extending downward from the top surface, and the depth of the NN region is less than the depth of the PP region. The second silicon dioxide layer (400) and the first polysilicon layer (500) are located in the middle of the N-type epitaxial layer N-, and are wrapped on the outside by an interlayer dielectric (600); The top surface of the N-type epitaxial layer N- is provided with nickel metal (700) connected to the interlayer medium (600). The front side of the nickel metal (700) forms both a Schottky contact and an ohmic contact connected to the PP region, and the back side forms an ohmic contact.

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