Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising an array region, a first peripheral region and a second peripheral region; forming a first hard mask layer and a second hard mask layer stacked in sequence on the substrate, the first hard mask layer and the second hard mask layer each having an opening exposing the first peripheral region, the material of the first hard mask layer being different from the material of the second hard mask layer; forming a first epitaxial layer on the first peripheral region with the second hard mask layer as a mask, the material of the first epitaxial layer being different from the material of the substrate; removing the second hard mask layer; forming a second epitaxial layer on the first epitaxial layer with the first hard mask layer as a mask, the material of the second epitaxial layer being different from the material of the first epitaxial layer; and removing the first hard mask layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, including methods for preparing semiconductor structures and semiconductor structures themselves. Background Technology

[0002] Minimizing device size is crucial for increasing the integration density of semiconductor devices. As transistor sizes continue to shrink, the quantum tunneling effect becomes increasingly significant, leading to leakage current between the gate and channel. Using high-k materials as the gate dielectric can reduce leakage current, but this reduces channel carrier mobility, impacting transistor performance. Channel carrier mobility can be improved by fabricating specific epitaxial layers on the substrate. In practical device fabrication, multiple epitaxial layers are typically involved; however, achieving optimal performance across these layers is challenging, making their fabrication difficult. Summary of the Invention

[0003] Therefore, in order to reduce the difficulty of fabricating multilayer epitaxial layers in semiconductor devices, it is necessary to provide a method for fabricating semiconductor structures.

[0004] According to some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0005] A substrate is provided, the substrate including an array region, a first peripheral region, and a second peripheral region;

[0006] A first hard mask layer and a second hard mask layer are formed sequentially on the substrate. Both the first hard mask layer and the second hard mask layer have openings that expose the first peripheral region. The material of the first hard mask layer is different from the material of the second hard mask layer.

[0007] Using the second hard mask layer as a mask, a first epitaxial layer is formed on the first peripheral region, wherein the material of the first epitaxial layer is different from the material of the substrate;

[0008] Remove the second hard mask layer;

[0009] Using the first hard mask layer as a mask, a second epitaxial layer is formed on the first epitaxial layer, wherein the material of the second epitaxial layer is different from the material of the first epitaxial layer; and,

[0010] Remove the first hard mask layer.

[0011] In some embodiments of this disclosure, a first hard mask layer and a second hard mask layer are formed sequentially on the substrate, including:

[0012] A first hard mask material layer, a second hard mask material layer, and a third hard mask material layer are formed sequentially on the substrate, wherein the material of the third hard mask material layer is the same as the material of the first hard mask material layer.

[0013] A patterned first photoresist layer is formed on the third hard mask material layer, the first photoresist layer having an opening that exposes the third hard mask material layer located on the first peripheral region;

[0014] Using the first photoresist layer as a mask, the third hard mask material layer located on the first peripheral region is removed by wet etching, and the remaining third hard mask material layer is used as the third hard mask layer.

[0015] Remove the first photoresist layer;

[0016] Using the third hard mask layer as a mask, the second hard mask material layer on the first peripheral area is removed by wet etching, and the remaining second hard mask material layer is used as the second hard mask layer.

[0017] The third hard mask layer and the first hard mask material layer on the first peripheral region are removed by wet etching, and the remaining first hard mask material layer is used as the first hard mask layer.

[0018] In some embodiments of this disclosure, the ratio of the thickness of the first hard mask material layer to the thickness of the third hard mask material layer is greater than or equal to 1 and less than or equal to 1.1.

[0019] In some embodiments of this disclosure, after removing the first hard mask layer, the method further includes:

[0020] A first dielectric layer and a second dielectric layer are formed sequentially on the substrate. Both the first dielectric layer and the second dielectric layer have an opening that exposes the second epitaxial layer located on the first peripheral region and an opening that exposes the second peripheral region.

[0021] The second epitaxial layer is oxidized to transform it into a first gate oxide layer, and a second gate oxide layer is formed on the second peripheral region.

[0022] A first gate structure is formed on the first gate oxide layer, and P-type source and drain regions are formed on opposite sides of the first gate structure to form a P-type transistor, wherein the channel region of the P-type transistor includes the first epitaxial layer.

[0023] A second gate structure is formed on the second gate oxide layer, and N-type source / drain regions are formed on opposite sides of the second gate structure to form an N-type transistor, wherein the channel region of the N-type transistor is located within the substrate.

[0024] In some embodiments of this disclosure, a first dielectric layer and a second dielectric layer are formed sequentially on the substrate, including:

[0025] A first dielectric material layer, a second dielectric material layer, and a third dielectric material layer are formed sequentially on the substrate, wherein the material of the third dielectric material layer is the same as the material of the first dielectric material layer;

[0026] A patterned second photoresist layer is formed on the third dielectric material layer, the second photoresist layer having an opening that exposes the third dielectric material layer located on the first peripheral region and the second peripheral region;

[0027] Using the second photoresist layer as a mask, the third dielectric material layer located on the first peripheral region and the second peripheral region is removed by wet etching, and the remaining third dielectric material layer is used as the third dielectric layer.

[0028] Remove the second photoresist layer;

[0029] Using the third dielectric layer as a mask, wet etching is used to remove the second dielectric material layer located on the first peripheral region and the second peripheral region, and the remaining second dielectric material layer is used as the second dielectric layer.

[0030] The third dielectric layer and the first dielectric material layer located on the first peripheral region and the second peripheral region are removed by wet etching, and the remaining first dielectric material layer is used as the first dielectric layer.

[0031] In some embodiments of this disclosure, the ratio of the thickness of the first dielectric material layer to the thickness of the third dielectric material layer is greater than or equal to 1 and less than or equal to 1.1.

[0032] In some embodiments of this disclosure, the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes one or more of silicon nitride and silicon oxynitride.

[0033] In some embodiments of this disclosure, the second epitaxial layer is formed on the first epitaxial layer using the first hard mask layer as a mask, including:

[0034] A second epitaxial material layer is formed on the first epitaxial layer and the first hard mask layer. The second epitaxial material layer on the first epitaxial layer is in a single crystal state, and the second epitaxial material layer on the first hard mask layer is in a polycrystalline state.

[0035] The second epitaxial material layer located on the first hard mask layer is selectively removed, and the second epitaxial material layer located on the first epitaxial layer is retained, with the retained second epitaxial material layer serving as the second epitaxial layer.

[0036] In some embodiments of this disclosure, the substrate is made of silicon, the first epitaxial layer is made of silicon germanium, the second epitaxial layer is made of silicon, the first hard mask layer is made of silicon oxide, and the second hard mask layer is made of one or more of silicon nitride and silicon oxynitride.

[0037] In some embodiments of this disclosure, embedded transistors are formed in the array region.

[0038] In some embodiments of this disclosure, the thickness of the first epitaxial layer is 7-15 nm.

[0039] In some embodiments of this disclosure, the thickness of the second epitaxial layer is 3-7 nm.

[0040] Traditional techniques typically employ only a single mask to fabricate multiple epitaxial layers. However, this disclosure reveals a close relationship between the performance of the epitaxial layer and the mask used during growth. The semiconductor structure fabrication method provided in this disclosure creatively proposes using multiple masks. First, a second hard mask layer is used to fabricate the first epitaxial layer, followed by the first hard mask layer to fabricate the second epitaxial layer. This allows both the first and second epitaxial layers to be fabricated within a more suitable mask, making it easier to balance the performance of both layers. This not only results in better performance for each epitaxial layer but also reduces the process window requirements for fabricating multiple epitaxial layers, thereby lowering the difficulty of fabricating multiple epitaxial layers in semiconductor devices.

[0041] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0043] Figure 1 A schematic diagram illustrating the steps of a semiconductor structure fabrication method;

[0044] Figure 2This is a schematic diagram of the cross-sectional structure of a substrate;

[0045] Figure 3 In order to be in Figure 2 A schematic diagram of the structure for fabricating a first hard mask material layer, a second hard mask material layer, and a third hard mask material layer based on the structure shown;

[0046] Figure 4 In order to be in Figure 3 A schematic diagram of the structure for fabricating the first photoresist layer based on the structure shown;

[0047] Figure 5 In order to be in Figure 4 A schematic diagram of a structure in which a third hard mask layer is formed based on the structure shown;

[0048] Figure 6 In order to be in Figure 5 A schematic diagram showing the formation of a second hard mask layer and a first hard mask layer based on the structure shown;

[0049] Figure 7 In order to be in Figure 6 A schematic diagram of the structure in which the first epitaxial layer is formed based on the structure shown;

[0050] Figure 8 In order to be in Figure 7 A schematic diagram of the structure shown below with the second hard mask layer removed;

[0051] Figure 9 In order to be in Figure 8 A schematic diagram of the structure for fabricating the second epitaxial layer based on the structure shown;

[0052] Figure 10 In order to be in Figure 9 A schematic diagram of the structure shown below with the first mask layer removed;

[0053] Figure 11 In order to be in Figure 10 A schematic diagram of a structure for fabricating a first dielectric material layer, a second dielectric material layer, a third dielectric material layer, and a second photoresist layer based on the structure shown.

[0054] Figure 12 In order to be in Figure 11 A schematic diagram of a structure in which a third dielectric layer is formed based on the structure shown;

[0055] Figure 13 In order to be in Figure 12 A schematic diagram of a structure in which a second dielectric layer and a first dielectric layer are formed based on the structure shown;

[0056] Figure 14 In order to be in Figure 13 A schematic diagram showing the formation of a first gate structure and a second gate structure based on the structure shown.

[0057] The reference numerals and their meanings in the accompanying drawings are as follows:

[0058] 100. Substrate; 101. First peripheral region; 102. Second peripheral region; 103. Array region; 1031. Active region; 1032. Shallow trench isolation structure; 1033. Buried word line structure; 110. First epitaxial layer; 120. Second epitaxial layer; 130. First gate oxide layer; 140. First gate structure; 150. Second gate oxide layer; 160. Second gate structure; 210. First hard mask layer; 21 1. First hard mask material layer; 220. Second hard mask layer; 221. Second hard mask material layer; 230. Third hard mask layer; 231. Third hard mask material layer; 240. First dielectric layer; 241. First dielectric material layer; 250. Second dielectric layer; 251. Second dielectric material layer; 260. Third dielectric layer; 261. Third dielectric material layer; 310. First photoresist layer; 320. Second photoresist layer. Detailed Implementation

[0059] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0061] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0064] In conventional techniques for fabricating stacks of silicon-germanium epitaxial layers and silicon epitaxial layers, if the uniformity of the silicon-germanium epitaxial layer is good, the etching selectivity of the silicon epitaxial layer is often poor; conversely, if the etching selectivity of the silicon epitaxial layer is good, the uniformity of the silicon-germanium epitaxial layer is often poor. This disclosure, during its research, found that: if good uniformity of the silicon-germanium epitaxial layer is required, silicon nitride can be used as a mask. However, the etching rates of the silicon epitaxial layer grown on silicon nitride and the silicon epitaxial layer grown on the already fabricated silicon-germanium epitaxial layer are quite similar during the etching process, making it difficult to selectively remove only the silicon epitaxial layer on the mask. If selective removal of the silicon epitaxial layer is required, silicon oxide can be used as a mask, but the overall uniformity of the silicon-germanium epitaxial layer grown on a silicon oxide mask is poor. Balancing the performance of multilayer epitaxial layers places extremely high demands on the process, making it difficult to fabricate multilayer epitaxial layers, and even when fabricated, it is difficult to simultaneously obtain multilayer epitaxial layers with good performance.

[0065] This disclosure provides a method for fabricating a semiconductor structure. Figure 1 This is a schematic diagram illustrating the steps of a semiconductor structure fabrication method. (Refer to...) Figure 1 As shown, the method for fabricating this semiconductor structure includes steps S1 to S5.

[0066] Step S1: Provide a substrate, which includes an array region, a first peripheral region, and a second peripheral region.

[0067] Figure 2 This is a schematic diagram of a cross-sectional structure of a substrate 100. (Refer to...) Figure 2 As shown, the substrate 100 includes an array region 103 and a peripheral region, the peripheral region further including a first peripheral region 101 and a second peripheral region 102. The first peripheral region 101, the second peripheral region 102 and the array region 103 are located at different positions on the substrate 100.

[0068] It is understood that the semiconductor structure to be fabricated may include a memory cell array and peripheral circuitry. The peripheral circuitry may be electrically connected to the memory cell array and conduct electricity to an external circuit. The array region 103 may serve as the fabrication region for the memory cell array, while the peripheral region may serve as the fabrication region for the peripheral circuitry. In some examples of this embodiment, buried transistors are formed in the substrate of the array region 103, and these buried transistors may participate in the formation of the memory cell array.

[0069] Reference Figure 2 As shown, in some examples of this embodiment, the array region 103 may include an active region 1031, a shallow trench isolation structure 1032, and a buried word line structure 1033. The shallow trench isolation structure 1032 can space out multiple active regions 1031 in the array region 103. The active regions 1031 can be used to form channels for transistors, and the buried word line structure 1033 is used to control the on / off state of the channels.

[0070] In some examples of this embodiment, the substrate 100 in the first peripheral region 101 and the substrate 100 in the second peripheral region 102 may have different doping types. For example, the substrate 100 in the first peripheral region 101 may be N-type doped, and the substrate 100 in the second peripheral region 102 may be P-type doped. Correspondingly, the first peripheral region 101 may serve as the fabrication region for a P-type transistor (PMOS) in the peripheral circuit, and the second peripheral region 102 may serve as the fabrication region for an N-type transistor (NMOS) in the peripheral circuit.

[0071] In some examples of this embodiment, the material of substrate 100 may include a semiconductor material. For example, the material of substrate 100 may be silicon, germanium, silicon-germanium, gallium nitride, or silicon carbide. Further, the substrate 100 may be a wafer.

[0072] Step S2: A first hard mask layer and a second hard mask layer are formed on the substrate in sequence.

[0073] In some examples of this embodiment, the step of forming a first hard mask layer 210 and a second hard mask layer 220 sequentially stacked on the substrate 100 may include:

[0074] A first hard mask material layer 211, a second hard mask material layer 221, and a third hard mask material layer 231 are formed on the substrate 100 in a single layer. The material of the third hard mask material layer 231 is the same as that of the first hard mask material layer 211.

[0075] A patterned first photoresist layer 310 is formed on the third hard mask material layer 231, the first photoresist layer 310 having an opening that exposes the third hard mask material layer 231 located on the first peripheral region 101;

[0076] Under the cover of the first photoresist layer 310, the third hard mask material layer 231 located on the first peripheral region 101 is removed by wet etching, and the remaining third hard mask material layer 231 is used as the third hard mask layer 230.

[0077] Remove the first photoresist layer 310, and use the third hard mask layer 230 as a mask to remove the second hard mask material layer 221 located on the first peripheral region 101 by wet etching, and use the remaining second hard mask material layer 221 as the second hard mask layer 220.

[0078] The third hard mask layer 230 is removed by wet etching, and the first hard mask material layer 211 located on the first peripheral region 101 is etched based on the second hard mask layer 220, so that the retained first hard mask material layer 211 serves as the first hard mask layer 210.

[0079] Figure 3 In order to be in Figure 2 A schematic diagram showing the fabrication of a first hard mask material layer 211, a second hard mask material layer 221, and a third hard mask material layer 231 based on the structure shown. (Refer to...) Figure 3 As shown, a first hard mask material layer 211, a second hard mask material layer 221, and a third hard mask material layer 231 are sequentially stacked on the substrate 100, covering the array region 103, the first peripheral region 101, and the second peripheral region 102. The materials of the first hard mask material layer 211 and the second hard mask material layer 221 are different, while the materials of the first hard mask material layer 211 and the third hard mask material layer 231 are the same.

[0080] In some examples of this embodiment, the material of the first hard mask material layer 211 may include silicon oxide.

[0081] In some examples of this embodiment, the material of the second hard mask material layer 221 may include one or more of silicon nitride and silicon oxynitride.

[0082] Figure 4 In order to be in Figure 3 A schematic diagram of the structure for fabricating the first photoresist layer 310 based on the structure shown. (Refer to...) Figure 4 As shown, a first photoresist layer 310 is disposed on a third hard mask material layer 231, and the first photoresist layer 310 has an opening located on a first peripheral region 101. It can be understood that this opening exposes the third hard mask material layer 231 located on the first peripheral region 101.

[0083] In some examples of this embodiment, the step of preparing the first photoresist layer 310 may include: coating a photoresist material on a third hard mask material layer 231, drying the photoresist material and performing exposure and development to obtain a first photoresist layer 310 with openings.

[0084] Figure 5 In order to be in Figure 4 This is a schematic diagram of a structure in which a third hard mask layer 230 is formed based on the structure shown. The third hard mask layer 230 can be obtained by etching a third hard mask material layer 231. For example, using a first photoresist layer 310 as a mask, since the opening of the first photoresist layer 310 is located on the first peripheral region 101, when the third hard mask material layer 231 is etched, the third hard mask material layer 231 on the first peripheral region 101 is etched away, and the remaining portion of the third hard mask material layer 231 serves as the third hard mask layer 230. It can be understood that after etching, the third hard mask layer 230 has the same pattern as the first photoresist layer 310.

[0085] In some examples of this embodiment, when etching the third hard mask material layer 231, the second hard mask material layer 221 can be used as an etching stop layer. Therefore, during the etching process, the third hard mask material layer 231 and the second hard mask material layer 221 should have a high etching selectivity ratio. For example, the etching selectivity ratio of the third hard mask material layer 231 to the second hard mask material layer 221 can be (10~100):1.

[0086] In some examples of this embodiment, in order to achieve a high etch selectivity ratio between the third hard mask material layer 231 and the second hard mask material layer 221, wet etching can be used. Furthermore, the etchant used for wet etching may include diluted hydrofluoric acid (DHF), which has a significantly higher etch selectivity ratio for silicon oxide and silicon nitride.

[0087] In some examples of this embodiment, after etching the third hard mask material layer 231, a step of removing the first photoresist layer 310 is included. The photoresist layer can be removed by ashing.

[0088] Figure 6 In order to be in Figure 5 This is a schematic diagram showing the structure in which a second hard mask layer 220 and a first hard mask layer 210 are formed based on the structure shown. (Refer to...) Figure 6 As shown, the first hard mask layer 210 and the second hard mask layer 220 are stacked sequentially on the substrate 100, and both the first hard mask layer 210 and the second hard mask layer 220 have openings that expose the substrate 100 in the first peripheral region 101.

[0089] The second hard mask layer 220 can be obtained by etching the second hard mask material layer 221. For example, using the third hard mask layer 230 as a mask, since the opening of the third hard mask layer 230 is located on the first peripheral region 101, when etching the second hard mask material layer 221, only the second hard mask material layer 221 on the first peripheral region 101 is etched away, and the remaining part of the second hard mask material layer 221 serves as the second hard mask layer 220.

[0090] In some examples of this embodiment, when etching the second hard mask material layer 221, the first hard mask material layer 211 can be used as an etching stop layer. Therefore, during the etching process, the second hard mask material layer 221 and the first hard mask material layer 211 should have a high etching selectivity ratio. For example, the etching selectivity ratio of the second hard mask material layer 221 to the first hard mask material layer 211 can be (10~100):1.

[0091] In some examples of this embodiment, wet etching can be used to achieve a high etch selectivity between the second hard mask material layer 221 and the first hard mask material layer 211. Further, the etchant used in the wet etching can include phosphoric acid, which has a significantly higher etch selectivity for silicon nitride and silicon oxide. Additionally, during the etching of the second hard mask material layer 221 with phosphoric acid, the third hard mask layer 230, being made of the same material as the first hard mask material layer 211, is difficult to etch with phosphoric acid and therefore serves as a suitable mask. In this process, if photoresist is used as the mask, the photoresist will fail due to the reaction between phosphoric acid and the photoresist.

[0092] Furthermore, the first hard mask layer 210 can be obtained by etching the first hard mask material layer 211. When etching the first hard mask material layer 211, the second hard mask layer 220 can be used as a mask for etching. Since the first hard mask material layer 211 and the third hard mask material layer 231 are made of the same material, the third hard mask layer 230 will also be etched away during the etching of the first hard mask material layer 211, thereby exposing the second hard mask layer 220.

[0093] In some examples of this embodiment, the ratio of the thickness of the first hard mask material layer 211 to the thickness of the third hard mask material layer 231 is 1 to 1.1, that is, the ratio of the thickness of the first hard mask material layer 211 to the thickness of the third hard mask material layer 231 is greater than or equal to 1 and less than or equal to 1.1. Controlling the thickness of the first hard mask material layer 211 to be slightly thicker than the thickness of the third hard mask material layer 231 ensures that the third hard mask layer 230 is etched away before the first hard mask material layer 211, thereby exposing the second hard mask layer 220, while also minimizing damage to the second hard mask layer 220.

[0094] In some examples of this embodiment, when etching the first hard mask material layer 211, the etching selectivity of the third hard mask layer 230 and the second hard mask layer 220 can be controlled to be relatively high, thereby further reducing damage to the second hard mask layer 220. Therefore, the etching method in this step can be the same as the etching method used when forming the third hard mask layer 230.

[0095] Step S3: Using the second hard mask layer as a mask, a first epitaxial layer is formed on the first peripheral region.

[0096] Figure 7 In order to be in Figure 6 The diagram illustrates a structure in which a first epitaxial layer 110 is formed based on the structure shown. In this embodiment, the material of the first epitaxial layer 110 is different from the material of the substrate 100. For example, in this embodiment, the material of the substrate 100 may be silicon, and the material of the first epitaxial layer 110 may be silicon-germanium.

[0097] In some examples of this embodiment, the first epitaxial layer 110 can be prepared by epitaxial growth. In the actual preparation process, since epitaxial growth has high selectivity for the growth substrate, the first epitaxial layer 110 can be controlled to grow on the substrate 100 and not on the second hard mask layer 220.

[0098] It is understood that since the second hard mask layer 220 is located above the first hard mask layer 210, it is used as the mask during the formation of the first epitaxial layer 110. Compared to using other dielectric materials (such as silicon oxide) as a mask to prepare silicon-germanium, using the second hard mask layer 220 containing silicon nitride and / or silicon oxynitride as a mask to prepare the first epitaxial layer 110 including silicon-germanium can result in higher surface uniformity of the first epitaxial layer 110. Uniformity refers to the difference in thickness of the first epitaxial layer 110 at different locations; higher uniformity results in smaller differences in thickness at different locations.

[0099] In some examples of this embodiment, during the step of fabricating the first epitaxial layer 110, the thickness of the first epitaxial layer 110 can be controlled to be 7 nm to 15 nm. For example, the thickness of the first epitaxial layer 110 can be controlled to be 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, or 15 nm, or the thickness of the first epitaxial layer 110 can be controlled within any two of the above thicknesses. By controlling the thickness of the first epitaxial layer 110 within the above range, the absolute value of the thickness difference of the first epitaxial layer 110 at different locations can be effectively reduced while improving the channel carrier mobility.

[0100] Step S4: Remove the second hard mask layer.

[0101] Figure 8 In order to be in Figure 7 A schematic diagram showing the structure with the second hard mask layer 220 removed from the structure shown. (Refer to...) Figure 8 As shown, a first hard mask layer 210 is disposed on a substrate 100, and the first hard mask layer 210 is located at the top of the substrate 100. The first hard mask layers 210 have openings located on a first peripheral region 101, and a first epitaxial layer 110 is disposed in the openings of the first hard mask layers 210.

[0102] In some examples of this embodiment, wet etching can be used to remove the second hard mask layer 220. When removing the second hard mask layer 220, the etching selectivity ratio between the second hard mask layer 220 and the first hard mask layer 210 can be controlled to be high; for example, the etching selectivity ratio between the second hard mask layer 220 and the first hard mask layer 210 can be (10-100):1. Alternatively, the etching selectivity ratio between the second hard mask layer 220 and the first epitaxial layer 110 can also be controlled to be high; for example, the etching selectivity ratio between the second hard mask layer 220 and the first epitaxial layer 110 can also be (10-100):1. Because the second hard mask layer 220 has a high etching rate, during the etching process, only chemical cleaning of the second hard mask layer 220 on the substrate 100 with an etchant is needed to effectively remove the second hard mask layer 220 while essentially not damaging the first epitaxial layer 110 and the first hard mask layer 210.

[0103] In some examples of this embodiment, the etchant used for wet etching in the step of removing the second hard mask layer 220 may include phosphoric acid.

[0104] Step S5: Using the first hard mask layer as a mask, a second epitaxial layer is formed on the first epitaxial layer.

[0105] Figure 9 In order to be in Figure 8 A schematic diagram of the fabrication of the second epitaxial layer 120 based on the structure shown. (Refer to...) Figure 9 As shown, in this embodiment, the second epitaxial layer 120 can be formed on the first epitaxial layer 110 and the first hard mask layer 210. The material of the second epitaxial layer 120 is different from the material of the first epitaxial layer 110.

[0106] In some examples of this embodiment, the step of forming a second epitaxial layer 120 on the first epitaxial layer 110 includes: forming a second epitaxial material layer on the first epitaxial layer 110 and the first hard mask layer 210, wherein the second epitaxial material layer on the first epitaxial layer 110 is in a single crystal state and the second epitaxial material layer on the first hard mask layer 210 is in a polycrystalline state; selectively removing the second epitaxial material layer on the first hard mask layer 210, and retaining the second epitaxial material layer on the first epitaxial layer 110 as the second epitaxial layer 120.

[0107] In some examples of this embodiment, the material of the second epitaxial material layer may include silicon. The silicon material can be deposited in single-crystal form on the first epitaxial layer 110 including silicon germanium, and in polycrystalline form on the first mask layer including silicon oxide.

[0108] Since the polycrystalline second epitaxial material layer has a higher etching rate than the monocrystalline second epitaxial material layer, the second epitaxial material layer located on the first hard mask layer 210 can be selectively removed by etching. The etching method can be wet etching. By controlling the etching time, the polycrystalline second epitaxial material layer can be completely removed, while the monocrystalline second epitaxial material layer located on the first epitaxial layer 110 is retained as the second epitaxial layer 120.

[0109] In some examples of this embodiment, the thickness of the second epitaxial layer 120 can be 3nm to 7nm. For example, the thickness of the second epitaxial layer 120 can be 3nm, 4nm, 5nm, 6nm or 7nm, or the thickness of the second epitaxial layer 120 can be within any two of the above-mentioned thicknesses.

[0110] Step S6: Remove the first hard mask layer.

[0111] Figure 10 In order to be in Figure 9 A schematic diagram of the structure shown, with the first hard mask layer 210 removed. (Refer to...) Figure 9 As shown, the first hard mask layer 210 is removed, and the substrate 100 has a first epitaxial layer 110 and a second epitaxial layer 120 located on the first peripheral region 101.

[0112] In this embodiment, the material of the first hard mask layer 210 is different from the material of the second epitaxial layer 120, so the first hard mask layer 210 can be selectively removed while the second epitaxial layer 120 is retained. In some examples of this embodiment, the first hard mask layer 210 can be removed by etching. Further, the first mask layer can be removed by wet etching. For example, diluted hydrofluoric acid can be used as the etchant.

[0113] In some examples of this embodiment, after removing the first hard mask layer 210, the following may also be included:

[0114] A first dielectric layer 240 and a second dielectric layer 250 are sequentially stacked on a substrate 100. Both the first dielectric layer 240 and the second dielectric layer 250 have openings located on the first peripheral region 101 and the second peripheral region 102. It can be understood that the second epitaxial layer 120 and the substrate 100 of the second peripheral region 102 are exposed through these openings. An oxidation process is used to transform the second epitaxial layer 120 into a first gate oxide layer 130 and to transform a portion of the substrate 100 of the second peripheral region 102 into a second gate oxide layer 150. A first gate structure 140 and P-type source / drain regions located on both sides of the first gate structure 140 are formed on the first gate oxide layer 130 to obtain a P-type transistor (PMOS). The channel region of the P-type transistor includes the first epitaxial layer 110. A second gate structure 160 and N-type source / drain regions located on both sides of the second gate structure 160 are formed on the second gate oxide layer 150 to obtain an N-type transistor (NMOS). The channel region of the N-type transistor is located in the substrate 100 of the second peripheral region 102.

[0115] In some examples of this embodiment, forming a first dielectric layer 240 and a second dielectric layer 250 sequentially stacked on the substrate 100 includes:

[0116] A first dielectric material layer 241, a second dielectric material layer 251 and a third dielectric material layer 261 are formed on a substrate 100 in sequence, wherein the material of the third dielectric material layer 261 is the same as the material of the first dielectric material layer 241.

[0117] A patterned second photoresist layer 320 is formed on the third dielectric material layer 261, the second photoresist layer 320 having an opening that exposes the third dielectric material layer 261 located on the first peripheral region 101 and the second peripheral region 102;

[0118] Under the cover of the second photoresist layer 320, the third dielectric material layer 261 located on the first peripheral region 101 and the second peripheral region 102 is removed by wet etching, and the remaining third dielectric material layer 261 is used as the third dielectric layer 260.

[0119] Remove the second photoresist layer 320, and use the third dielectric layer 260 as a mask to remove the second dielectric material layer 251 located on the first peripheral region 101 and the second peripheral region 102 by wet etching, and use the remaining second dielectric material layer 251 as the second dielectric layer 250.

[0120] The third dielectric layer 260 is removed by wet etching, and the first dielectric material layer 241 located on the first peripheral region 101 and the second peripheral region 102 is etched based on the second dielectric layer 250, so that the retained first dielectric material layer 241 serves as the first dielectric layer 240.

[0121] Figure 11In order to be in Figure 10 A schematic diagram showing the fabrication of a first dielectric material layer 241, a second dielectric material layer 251, a third dielectric material layer 261, and a second photoresist layer 320 based on the structure shown. (Refer to...) Figure 11 As shown, the first dielectric material layer 241, the second dielectric material layer 251 and the third dielectric material layer 261 are stacked sequentially on the substrate 100, and the second photoresist layer 320 is disposed on the third dielectric material layer 261, and the second photoresist layer 320 has openings located on the first peripheral region 101 and the second peripheral region 102.

[0122] In some examples of this embodiment, the material of the first dielectric material layer 241 and the material of the third dielectric material layer 261 are the same. The material of the first dielectric material layer 241 and the material of the second dielectric material layer 251 are different.

[0123] In some examples of this embodiment, the material of the first dielectric material layer 241 may include silicon oxide.

[0124] In some examples of this embodiment, the material of the second dielectric material layer 251 may include one or more of silicon nitride and silicon oxynitride.

[0125] Figure 12 In order to be in Figure 11 A schematic diagram showing the formation of a third dielectric layer 260 based on the structure shown. (Refer to...) Figure 12 As shown, the third dielectric layer 260 is disposed on the second dielectric material layer 251, and the third dielectric layer 260 has openings located on the first peripheral region 101 and the second peripheral region 102.

[0126] The third dielectric layer 260 can be obtained by etching the third dielectric material layer 261. During the etching process, the second photoresist layer 320 can be used as a mask. In some examples of this embodiment, the second dielectric material layer 251 can be used as an etching stop layer when etching the third dielectric material layer 261. Therefore, during the etching process, the third dielectric material layer 261 and the second dielectric material layer 251 should have a high etching selectivity ratio. For example, the etching selectivity ratio of the third dielectric material layer 261 to the second dielectric material layer 251 can be (10-100):1. Furthermore, wet etching can be used to etch the third dielectric material layer 261, and the etchant used can include diluted hydrofluoric acid.

[0127] Figure 13 In order to be in Figure 12 A schematic diagram showing the formation of a second dielectric layer 250 and a first dielectric layer 240 based on the structure shown. (Refer to...) Figure 12As shown, the second dielectric layer 250 is disposed on the first dielectric material layer 241, and the second dielectric layer 250 has openings located on the first peripheral region 101 and the second peripheral region 102.

[0128] The second dielectric layer 250 can be obtained by etching the second dielectric material layer 251. During the etching process, a third dielectric layer 260 can be used as a mask. In some examples of this embodiment, a first dielectric material layer 241 can be used as an etching stop layer when etching the second dielectric material layer 251. Therefore, during the etching process, the second dielectric material layer 251 and the first dielectric material layer 241 should have a high etching selectivity ratio. For example, the etching selectivity ratio of the second dielectric material layer 251 to the first dielectric material layer 241 can be (10-100):1. Furthermore, wet etching can be used to etch the second dielectric material layer 251, and the etchant used can include phosphoric acid.

[0129] The first dielectric layer 240 can be obtained by etching the first dielectric material layer 241. When etching the first dielectric material layer 241, the second dielectric layer 250 can be used as a mask for etching. Since the first dielectric material layer 241 and the third dielectric material layer 261 are made of the same material, the third dielectric layer 260 will also be etched away when the first dielectric material layer 241 is etched, thereby exposing the second dielectric layer 250.

[0130] In some examples of this embodiment, the ratio of the thickness of the first dielectric material layer 241 to the thickness of the third dielectric material layer 261 is 1 to 1.1, that is, the ratio of the thickness of the first dielectric material layer 241 to the thickness of the third dielectric material layer 261 is greater than or equal to 1 and less than or equal to 1.1.

[0131] Reference Figure 13 As shown, the second dielectric layer 250 and the first dielectric layer 240 have openings located on the first peripheral region 101 and the second peripheral region 102, so that the substrate 100 in the second epitaxial layer 120 and the second peripheral region 102 is exposed through the openings. The second dielectric layer 250 and the first dielectric layer 240 are used to protect the structures in the array region 103 during the subsequent formation of the first gate structure 140 and the second gate structure 160.

[0132] Figure 14 In order to be in Figure 13 This is a schematic diagram showing the formation of a first gate structure 140 and a second gate structure 160 based on the structure shown. Further, Figure 14 A first gate oxide layer 130 and a second gate oxide layer 150 are also shown. (Refer to...) Figure 14As shown, the first gate oxide layer 130 is disposed on the first epitaxial layer 110, the first gate structure 140 is disposed on the first gate oxide layer 130, the second gate oxide layer 150 is disposed on the substrate 100, and the second gate structure 160 is disposed on the second gate oxide layer 150.

[0133] In some examples of this embodiment, the thickness of the first gate oxide layer 130 can be 1 nm to 2 nm, and the thickness of the second gate oxide layer 150 can also be 1 nm to 2 nm.

[0134] The first gate oxide layer 130 can be formed by oxidizing the second epitaxial layer 120, and the material of the first gate oxide layer 130 is related to the material of the second epitaxial layer 120. For example, if the material of the second epitaxial layer 120 is silicon, then the material of the first gate oxide layer 130 is silicon oxide.

[0135] The first epitaxial layer 110 is disposed on the side of the first gate oxide layer 130 away from the first gate structure 140. The first epitaxial layer 110 can be part of the channel region. The first epitaxial layer 110 can effectively improve the carrier mobility, thereby improving the response speed of the transistor.

[0136] The second gate oxide layer 150 can be formed by oxidizing the substrate 100, and the material of the second gate oxide layer 150 is related to the material of the substrate 100. For example, if the material of the substrate 100 is silicon, then the material of the second gate oxide layer 150 is silicon oxide.

[0137] It is understood that the semiconductor structure fabrication method provided in this disclosure can be completed through the above steps S1 to S6.

[0138] Traditional techniques typically employ only a single mask to fabricate multiple epitaxial layers. However, this disclosure reveals a close relationship between the performance of the epitaxial layer and the mask used during growth. The semiconductor structure fabrication method provided in this disclosure creatively proposes using multiple masks. First, a second hard mask layer is used to fabricate the first epitaxial layer, followed by the first hard mask layer to fabricate the second epitaxial layer. This allows both the first and second epitaxial layers to be fabricated within a more suitable mask, making it easier to balance the performance of both layers. This not only results in better performance for each epitaxial layer but also reduces the process window requirements for fabricating multiple epitaxial layers, thereby lowering the difficulty of fabricating multiple epitaxial layers in semiconductor devices.

[0139] Please note that the above embodiments are for illustrative purposes only and are not intended to limit this disclosure.

[0140] It should be understood that, unless explicitly stated herein, there is no strict order in which the steps are performed; these steps may be performed in other orders. Moreover, at least some steps in the preparation process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0141] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0142] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region, a first peripheral region, and a second peripheral region; A first hard mask layer and a second hard mask layer are formed sequentially on the substrate. Both the first hard mask layer and the second hard mask layer have openings that expose the first peripheral region. The material of the first hard mask layer is different from the material of the second hard mask layer. Using the second hard mask layer as a mask, a first epitaxial layer is formed on the first peripheral region, wherein the material of the first epitaxial layer is different from the material of the substrate; Remove the second hard mask layer; Using the first hard mask layer as a mask, a second epitaxial layer is formed on the first epitaxial layer, wherein the material of the second epitaxial layer is different from the material of the first epitaxial layer; as well as, Remove the first hard mask layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming a first hard mask layer and a second hard mask layer sequentially stacked on the substrate includes: A first hard mask material layer, a second hard mask material layer, and a third hard mask material layer are formed sequentially on the substrate, wherein the material of the third hard mask material layer is the same as the material of the first hard mask material layer. A patterned first photoresist layer is formed on the third hard mask material layer, the first photoresist layer having an opening that exposes the third hard mask material layer located on the first peripheral region; Using the first photoresist layer as a mask, the third hard mask material layer located on the first peripheral region is removed by wet etching, and the remaining third hard mask material layer is used as the third hard mask layer. Remove the first photoresist layer; Using the third hard mask layer as a mask, the second hard mask material layer on the first peripheral area is removed by wet etching, and the remaining second hard mask material layer is used as the second hard mask layer. The third hard mask layer and the first hard mask material layer on the first peripheral region are removed by wet etching, and the remaining first hard mask material layer is used as the first hard mask layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The ratio of the thickness of the first hard mask material layer to the thickness of the third hard mask material layer is greater than or equal to 1 and less than or equal to 1.

1.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that, After removing the first hard mask layer, the process also includes: A first dielectric layer and a second dielectric layer are formed sequentially on the substrate. Both the first dielectric layer and the second dielectric layer have an opening that exposes the second epitaxial layer located on the first peripheral region and an opening that exposes the second peripheral region. The second epitaxial layer is oxidized to transform it into a first gate oxide layer, and a second gate oxide layer is formed on the second peripheral region. A first gate structure is formed on the first gate oxide layer, and P-type source and drain regions are formed on opposite sides of the first gate structure to form a P-type transistor, wherein the channel region of the P-type transistor includes the first epitaxial layer. A second gate structure is formed on the second gate oxide layer, and N-type source / drain regions are formed on opposite sides of the second gate structure to form an N-type transistor, wherein the channel region of the N-type transistor is located within the substrate.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, Forming a first dielectric layer and a second dielectric layer sequentially stacked on the substrate includes: A first dielectric material layer, a second dielectric material layer, and a third dielectric material layer are formed sequentially on the substrate, wherein the material of the third dielectric material layer is the same as the material of the first dielectric material layer; A patterned second photoresist layer is formed on the third dielectric material layer, the second photoresist layer having an opening that exposes the third dielectric material layer located on the first peripheral region and the second peripheral region; Using the second photoresist layer as a mask, the third dielectric material layer located on the first peripheral region and the second peripheral region is removed by wet etching, and the remaining third dielectric material layer is used as the third dielectric layer. Remove the second photoresist layer; Using the third dielectric layer as a mask, wet etching is used to remove the second dielectric material layer located on the first peripheral region and the second peripheral region, and the remaining second dielectric material layer is used as the second dielectric layer. The third dielectric layer and the first dielectric material layer located on the first peripheral region and the second peripheral region are removed by wet etching, and the remaining first dielectric material layer is used as the first dielectric layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The ratio of the thickness of the first dielectric material layer to the thickness of the third dielectric material layer is greater than or equal to 1 and less than or equal to 1.

1.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, The material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes one or more of silicon nitride and silicon oxynitride.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 3 and 5 to 7, characterized in that, Using the first hard mask layer as a mask, a second epitaxial layer is formed on the first epitaxial layer, including: A second epitaxial material layer is formed on the first epitaxial layer and the first hard mask layer. The second epitaxial material layer on the first epitaxial layer is in a single crystal state, and the second epitaxial material layer on the first hard mask layer is in a polycrystalline state. The second epitaxial material layer located on the first hard mask layer is selectively removed, and the second epitaxial material layer located on the first epitaxial layer is retained, with the retained second epitaxial material layer serving as the second epitaxial layer.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 3 and 5 to 7, characterized in that, The substrate is made of silicon, the first epitaxial layer is made of silicon-germanium, the second epitaxial layer is made of silicon, the first hard mask layer is made of silicon oxide, and the second hard mask layer is made of one or more of silicon nitride and silicon oxynitride; and / or Embedded transistors are formed in the array region.

10. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that, The thickness of the first epitaxial layer is 7-15 nm; and / or, The thickness of the second epitaxial layer is 3-7 nm.

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