Display substrate, manufacturing method thereof and display device

Abstract

The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. The display substrate comprises a substrate, a first signal transmission line disposed on the substrate, comprising a first sub-transmission line and a second sub-transmission line disposed in the same layer, the first sub-transmission line and the second sub-transmission line are disposed side by side and electrically connected, a first insulating layer disposed on the side of the first signal transmission line away from the substrate, a second signal transmission line disposed on the side of the first insulating layer away from the substrate, and connected with the first sub-transmission line through a first via hole penetrating the first insulating layer, a second insulating layer disposed on the side of the second signal transmission line away from the substrate, and a first connecting piece disposed on the side of the second insulating layer away from the substrate, the first connecting piece is connected with the second signal transmission line through a second via hole penetrating the second insulating layer, and connected with the second sub-transmission line through a third via hole penetrating the first insulating layer and the second insulating layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate and its manufacturing method, and a display device. Background Technology

[0002] In the display substrate, a gate driving circuit is provided in the non-display area, which includes multiple cascaded shift register units. These shift register units sequentially provide scan signals to the gate lines on the display substrate. Each shift register unit is also connected to a clock signal line, thereby outputting a scan signal under the control of the clock signal on the clock signal line. Therefore, the stability of the connection between the shift register unit and the clock signal line directly affects the output of the shift register unit. Summary of the Invention

[0003] This disclosure presents a display substrate, a method for manufacturing the same, and a display device.

[0004] In a first aspect, this disclosure provides a display substrate, comprising:

[0005] Substrate;

[0006] A first signal transmission line is disposed on the substrate, which includes a first sub-transmission line and a second sub-transmission line disposed on the same layer. The first sub-transmission line and the second sub-transmission line are arranged side by side and electrically connected.

[0007] A first insulating layer is disposed on the side of the first signal transmission line away from the substrate.

[0008] The second signal transmission line is disposed on the side of the first insulating layer away from the substrate, and is connected to the first sub-transmission line through a first via penetrating the first insulating layer;

[0009] A second insulating layer is disposed on the side of the second signal transmission line away from the substrate.

[0010] A first connector is disposed on the side of the second insulating layer away from the substrate. The first connector is connected to the second signal transmission line through a second via penetrating the second insulating layer, and is connected to the second sub-transmission line through a third via penetrating the first insulating layer and the second insulating layer.

[0011] In some embodiments, the orthogonal projection of the second via on the substrate is located within the orthogonal projection range of the first via on the substrate.

[0012] In some embodiments, the orthographic projection of the first via on the substrate is located within the orthographic projection range of the second signal transmission line on the substrate.

[0013] In some embodiments, the second signal transmission line includes: a conductive portion and a transmission portion connected to the conductive portion, the conductive portion extending along the length direction of the first sub-transmission line, and the extension direction of the transmission portion intersecting the extension direction of the conductive portion; the orthogonal projection of the first via on the substrate is located within the orthogonal projection range of the conductive portion on the substrate.

[0014] The first via has a dimension in the width direction of the conductive part that is 0.4 to 0.6 times the width of the conductive part, and the second via has a dimension in the width direction of the conductive part that is 0.2 to 0.5 times the width of the conductive part.

[0015] In some embodiments, the first connector includes: a first connecting portion, a second connecting portion, and a first ramp portion connected between the two. The first connecting portion is disposed opposite to the second signal transmission line. The orthographic projection of the second connecting portion on the substrate is disposed opposite to the interval region between the first sub-transmission line and the second sub-transmission line. The first connecting portion includes: a first overlapping portion and a second ramp portion. The second ramp portion is located inside the second via. The first overlapping portion is located outside the second via and connects the first ramp portion and the second ramp portion.

[0016] The slope angle of the first climbing section is between 35° and 64°; the slope angle of the second climbing section is between 35° and 62°.

[0017] In some embodiments, the depth of the first via is... Between, the depth of the second via is Between, the depth of the third via is between.

[0018] In some embodiments, the second signal transmission line includes: a conductive portion and a transmission portion connected to the conductive portion, the conductive portion extending along the length direction of the first sub-transmission line, and the extension direction of the transmission portion intersecting the extension direction of the conductive portion;

[0019] The orthographic projection of the first via on the substrate is the first projection, and the orthographic projection of the conductive portion on the substrate is the second projection; a portion of the first projection extends beyond the second projection and is located on the side of the second projection closer to the second sub-transmission line.

[0020] In some embodiments, the first connector includes: a first connecting portion, a second connecting portion, and a first ramp portion connected between the two. The first connecting portion is disposed opposite to the second signal transmission line. The orthographic projection of the second connecting portion on the substrate is disposed opposite to the interval region between the first sub-transmission line and the second sub-transmission line. The first connecting portion includes: a first overlapping portion and a second ramp portion. The second ramp portion is located inside the second via. The first overlapping portion is located outside the second via and connects the first ramp portion and the second ramp portion.

[0021] The slope angle of the first climbing section is between 20° and 45°; the slope angle of the second climbing section is between 20° and 42°.

[0022] In some embodiments, the depth of the first via is... Between, the depth of the second via is Between, the depth of the third via is between.

[0023] In some embodiments, the size of the first via in the width direction of the conductive portion is 0.4 to 0.6 times the width of the conductive portion, and the size of the second via in the width direction of the conductive portion is 0.7 to 1.1 times the width of the conductive portion.

[0024] In some embodiments, the cross-sectional area of ​​the first via and the cross-sectional area of ​​the second via gradually decrease along the direction close to the substrate.

[0025] The slope angle of the wall of the first through hole is smaller than that of the wall of the second through hole.

[0026] In some embodiments, the thickness of the second insulating layer is between.

[0027] In some embodiments, there are multiple first connectors and multiple second signal transmission lines. The first signal transmission line is connected to multiple first connectors. Each first connector is connected to a second signal transmission line through multiple second vias and to a second sub-transmission line through multiple third vias. Multiple third vias corresponding to the same first connector are arranged along the extension direction of the first signal transmission line, and multiple second vias corresponding to the same first connector are arranged along the extension direction of the first signal transmission line.

[0028] In some embodiments, the orthographic projections of a plurality of second vias corresponding to the same first connector on the substrate are located within the orthographic projection range of the same first via on the substrate.

[0029] In some embodiments, the display substrate includes a display area and a non-display area, the display area including a plurality of sub-pixels, each of the sub-pixels being provided with a thin-film transistor;

[0030] The first signal transmission line, the second signal transmission line, and the first connector are all located in the non-display area. The first signal transmission line is disposed on the same layer as the gate of the thin-film transistor, and the second signal transmission line is disposed on the same layer as the source and drain of the thin-film transistor.

[0031] In some embodiments, each sub-pixel further comprises a pixel electrode and a second connector. Both the first insulating layer and the second insulating layer cover the display area. The pixel electrode is located between the first insulating layer and the substrate. The second connector is located on the side of the second insulating layer away from the substrate and is connected to the drain of the thin-film transistor through a fourth via penetrating the second insulating layer, and to the pixel electrode through a fifth via penetrating the first and second insulating layers.

[0032] The second connector is disposed on the same layer as the first connector.

[0033] In some embodiments, the source and drain of the thin-film transistor are located on the side of the active layer of the thin-film transistor away from the substrate, and both the source and the drain are in direct contact with the active layer, and the orthogonal projections of the source and the drain on the substrate are both within the orthogonal projection range of the active layer on the substrate.

[0034] In some embodiments, the second signal transmission line includes an overlap portion, the orthographic projection of which on the substrate is located outside the orthographic projection of the first via on the substrate.

[0035] The display substrate further includes a semiconductor redundancy portion located between the first insulating layer and the overlapping portion, and the semiconductor redundancy portion is formed synchronously with the active layer of the thin-film transistor.

[0036] In some embodiments, the display substrate includes a display area and a non-display area, the first signal transmission line and the second signal transmission line are both located in the non-display area, and a plurality of shift register units are also provided in the non-display area;

[0037] The first signal transmission line is a clock signal line, and there are multiple second signal transmission lines. Each second signal transmission line is connected between the first signal transmission line and one of the shift register units, and different second signal transmission lines are connected to different shift register units.

[0038] In some embodiments, the first signal transmission line further includes a plurality of connecting portions connected between the first sub-transmission line and the second sub-transmission line.

[0039] Secondly, this disclosure provides a method for manufacturing a display substrate, comprising:

[0040] A pattern including a first signal transmission line is formed on a substrate, the first signal transmission line including a first sub-transmission line and a second sub-transmission line arranged side by side and electrically connected.

[0041] A first insulating layer is formed on the side of the first signal transmission line away from the substrate.

[0042] A first via is formed at a position corresponding to the first sub-transmission line, penetrating the first insulating layer;

[0043] A pattern including a second signal transmission line is formed on the side of the first insulating layer away from the substrate, and the second signal transmission line is connected to the first sub-transmission line through the first via.

[0044] A second insulating layer is formed on the side of the second signal transmission line away from the substrate.

[0045] A second via is formed at a position corresponding to the second signal transmission line, penetrating the second insulating layer; and a third via is formed at a position corresponding to the second sub-transmission line, penetrating the first insulating layer and the second insulating layer.

[0046] A pattern including a first connector is formed on the side of the second insulating layer away from the substrate. The first connector is connected to the second signal transmission line through the second via and to the second sub-transmission line through the third via.

[0047] In some embodiments, the display substrate includes a display area and a non-display area, the display area including a plurality of sub-pixels; the fabrication method further includes: forming a thin-film transistor in each sub-pixel;

[0048] The first signal transmission line, the second signal transmission line, and the first connector are all located in the non-display area. The first signal transmission line is formed synchronously with the gate of the thin-film transistor, and the second signal transmission line is formed synchronously with the source and drain of the thin-film transistor.

[0049] In some embodiments, both the first insulating layer and the second insulating layer cover the display area, and the manufacturing method further includes:

[0050] Before the first insulating layer is formed, a pixel electrode is formed in each of the sub-pixels;

[0051] After the second insulating layer is formed, a fourth via penetrating the second insulating layer and a fifth via penetrating the first insulating layer and the second insulating layer are formed.

[0052] A second connector is formed, which is connected to the drain of the thin-film transistor through the fourth via and to the pixel electrode through the fifth via;

[0053] The second connector is formed simultaneously with the first connector.

[0054] In some embodiments, prior to forming the first via, the fabrication method further includes: forming a semiconductor layer;

[0055] The step of forming the first via includes etching the semiconductor layer and the first insulating layer to form the first via.

[0056] In some embodiments, the second signal transmission line, the source, drain, and active layer of the thin-film transistor are formed by the following steps:

[0057] A source / drain metal layer and a photoresist layer are sequentially formed on the side of the semiconductor layer away from the substrate.

[0058] The photoresist layer is subjected to step exposure and development to form at least a first photoresist portion and a second photoresist portion. The first photoresist portion is located in the region where the active layer is to be formed and includes: a first portion corresponding to the source electrode, a second portion corresponding to the drain electrode, and a third portion located between the first portion and the second portion. The second photoresist portion is located in the region where the second signal transmission line is to be formed, and the thicknesses of the first portion, the second portion, and the second photoresist portion are all greater than the thickness of the third portion.

[0059] The source / drain metal layer and semiconductor layer are etched to form an active layer and an intermediate electrode corresponding to the first photoresist portion, as well as a second signal transmission line and a semiconductor redundancy portion corresponding to the second photoresist portion;

[0060] The photoresist pattern is grayed out to thin the first portion, the second portion, and the second photoresist portion of the first photoresist portion, and the third portion of the first photoresist portion is removed;

[0061] The intermediate electrode is etched to form the source and the drain.

[0062] Thirdly, this disclosure provides a display device including the aforementioned display substrate. Attached Figure Description

[0063] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0064] Figure 1 This is a schematic diagram of a gate drive circuit provided in an example.

[0065] Figure 2A This is a schematic diagram of a clock signal line provided in an example.

[0066] Figure 2B for Figure 2A A magnified schematic diagram of the Q region.

[0067] Figure 3 For along Figure 2B A cross-sectional view of line A-A' in the middle.

[0068] Figure 4 This is a plan view of a partial area of ​​a display substrate provided in some embodiments of this disclosure.

[0069] Figure 5A The following are provided in some embodiments of this disclosure: Figure 4 A cross-sectional view of line B-B' in the middle.

[0070] Figure 5B for Figure 5A A schematic diagram of the first connector in the diagram.

[0071] Figure 5C Other embodiments of this disclosure provide for the following: Figure 4 A partial sectional view of line B-B' in the middle.

[0072] Figure 6 This is a plan view of a partial area of ​​the display substrate provided in some other embodiments of this disclosure.

[0073] Figure 7 For along Figure 6 A cross-sectional view of line C-C' in the middle.

[0074] Figure 8 This is a partial plan view of the display area of ​​a display substrate provided in some embodiments of this disclosure.

[0075] Figure 9 This is a cross-sectional view of a display substrate provided in some embodiments of this disclosure.

[0076] Figure 10 This is a cross-sectional view of a display substrate provided in some other embodiments of this disclosure.

[0077] Figure 11 This is a flowchart illustrating a method for manufacturing a display substrate provided in some embodiments of this disclosure.

[0078] Figures 12 to 18 This is a schematic diagram of the structure during the fabrication process of a display substrate provided in some embodiments of this disclosure.

[0079] Figures 19 to 30 This is a structural schematic diagram of the display substrate manufacturing process provided in some other embodiments of this disclosure. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0081] The terminology used herein to describe embodiments of this disclosure is not intended to limit and / or restrict the scope of this disclosure. For example, unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense as would be understood by one of ordinary skill in the art to which this invention pertains. It should be understood that the terms “first,” “second,” and similar terms used herein do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as “comprising” or “including” mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, but do not exclude other elements or objects. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0082] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0083] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0084] Figure 1 Here is a schematic diagram of a gate drive circuit provided in an example, such as... Figure 1 As shown, the gate drive circuit includes: multiple cascaded shift register units (such as...) Figure 1 As shown in GOA1, GOA2, GOA3, GOA4..., the input terminal INPUT of the first-stage shift register unit GOA1 is connected to the start signal line STV. The input terminal INPUT of the second-stage and subsequent shift register units is connected to the output terminal OUTPUT of the previous-stage shift register unit. The output terminal OUTPUT of each shift register unit except the last stage is connected to the reset terminal RESET of the previous-stage shift register unit. The first voltage terminal VSS of each shift register unit is connected to the first power supply line V1, which can be a low-level signal line. The clock signal terminal CLK of each shift register unit is connected to a clock signal line, for example, as shown in... Figure 1 As shown, the clock signal terminal CLK of the odd-numbered shift register units is connected to clock signal line CLK1, and the clock signal terminal CLK of the even-numbered shift register units is connected to clock signal line CLK2. The output terminal OUTPUT of each shift register unit (e.g., ...) Figure 1 The OUT1, OUT2, OUT3, OUT4, etc. in the multi-stage shift register unit are connected to a gate line, and the multi-stage shift register unit outputs scan signals to the corresponding gate line in sequence.

[0085] In each shift register unit, during the output phase, the clock signal on its connected clock signal line is at a valid level (e.g., high level). Simultaneously, the clock signal terminal CLK and the output terminal OUTPUT of the shift register unit are connected, thus enabling the shift register unit to output a valid level signal. Therefore, the stability of the connection between the shift register unit and the clock signal line is a crucial factor determining whether the shift register unit can output correctly.

[0086] The clock signal line can be a solid line or a grid structure, depending on the actual production process. Figure 2A Here is a schematic diagram of a clock signal line provided in an example, such as Figure 2A As shown, the clock signal line includes multiple sub-signal lines and multiple connectors CLKc. The multiple sub-signal lines include: a first sub-signal line CLKa, a second sub-signal line CLKb, and multiple third sub-signal lines CLKd. The first sub-signal line CLKa can be a continuous solid line, or it can be... Figure 2A As shown, this includes two branch lines, CLKa1 and CLKa2, connected together. The positions of CLKd and CLKa are interchangeable, meaning that one or more CLKd lines can be placed between CLKa and CLKb. Multiple sub-signal lines and multiple connecting parts CLKc are arranged on the same layer and intersect to form a grid-like structure. This allows more light to pass through the grid-like clock signal lines during the display panel encapsulation process, thus facilitating the curing of the sealant.

[0087] Figure 2B for Figure 2A Enlarged diagram of the mid-Q region, Figure 2B Connector 3 in the middle can be used as Figure 2A Connecting nodes in region A. Figure 3 For along Figure 2B A cross-sectional view of line A-A', as shown Figures 2A to 3 As shown, the clock signal terminal CLK of the shift register unit is connected to the clock signal line CLK1 via signal transmission line 2. The first sub-signal line CLKa and the second sub-signal line CLKb of clock signal line CLK1 are disposed on the same layer. A first insulating layer 4 is disposed on the side of clock signal line CLK1 away from the substrate 1. Signal transmission line 2 is located on the side of the first insulating layer 4 away from the substrate 1. The orthographic projection of signal transmission line 2 on the substrate 1 at least partially overlaps with the orthographic projection of the first sub-signal line CLKa on the substrate 1. Signal transmission line 2 is connected to clock signal line CLK1 via connector 3. Figure 1 and Figure 3 As shown, a second insulating layer 5 is provided on the side of the signal transmission line 2 away from the substrate 1. The connector 3 is located on the side of the second insulating layer 5 away from the substrate 1. The connector 3 is connected to the signal transmission line 2 through a via V1' penetrating the second insulating layer 5, and is connected to the clock signal line CLK1 through a via V2' penetrating the first insulating layer 4 and the second insulating layer 5.

[0088] like Figure 3As shown, the first part 3a of the connector 3 is located on the side of the signal transmission line 2 away from the substrate 1, and the second part 3b of the connector 3 is located at the interval between the first sub-signal line CLKa and the second sub-signal line CLKb. Since the signal transmission line 2 and the first sub-signal line CLKa have a certain thickness, a ramp 3c will be formed between the first part 3a and the second part 3b of the connector 3. This will cause the ramp 3c to break easily when static electricity is generated on the display substrate. For example, the top of the ramp 3c will break from the first part 3a, and / or the bottom of the ramp 3c will break from the second part 3b of the connector 3. As a result, the signal on the clock signal line CLK1 cannot be transmitted to the signal transmission line 2 through the connector 3, which in turn causes the shift register unit to be unable to output the scan signal normally.

[0089] To address the aforementioned technical problems, this disclosure provides a display substrate. Figure 4 This is a plan view of a partial area of ​​the display substrate provided in some embodiments of this disclosure. Figure 5A The following are provided in some embodiments of this disclosure: Figure 4 Sectional view of line B-B' in the middle. Figure 5B for Figure 5A A schematic diagram of the first connector. (See diagram below.) Figures 4 to 5B As shown, the display substrate includes a substrate 10, and disposed on the substrate 10: a first signal transmission line 60, a first insulating layer 40, a second signal transmission line 20, a second insulating layer 50, and a first connector 30.

[0090] The substrate 10 can be a rigid substrate made of glass or a flexible substrate made of materials such as PI. The first signal transmission line 60 includes a first sub-transmission line 61 and a second sub-transmission line 62 disposed on the same layer, arranged side-by-side and electrically connected. Furthermore, multiple connecting portions 63 can be provided between the first sub-transmission line 61 and the second sub-transmission line 62, and these connecting portions 63 can be connected to the first sub-transmission line 61 and the second sub-transmission line 62 to form an integral structure. The extending directions of the first sub-transmission line 61 and the second sub-transmission line 62 can be the same or substantially the same.

[0091] It should be noted that "same-layer configuration" in this disclosure means that the two structures are formed by the same material layer through a patterning process, so they are in the same layer in terms of stacking relationship; however, this does not mean that the distance between the two and the substrate 10 must be the same.

[0092] The first insulating layer 40 is located on the side of the first signal transmission line 60 away from the substrate 10, and a first via V1 is provided at the position corresponding to the first sub-transmission line 61. The material of the first insulating layer 40 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0093] The second signal transmission line 20 is located on the side of the first insulating layer 40 away from the substrate 10, and is connected to the first sub-transmission line 61 through the first via V1.

[0094] The second insulating layer 50 is disposed on the side of the second signal transmission line 20 away from the substrate 10, and its material may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. A second via V2 is disposed on the second insulating layer 50 corresponding to the position of the second signal transmission line 20.

[0095] The first connector 30 is disposed on the side of the second insulating layer 50 away from the substrate 10. The first connector 30 is connected to the second signal transmission line 20 through the second via V2, and is connected to the second sub-transmission line 62 through the third via V3 penetrating the first insulating layer 40 and the second insulating layer 50. Specifically, as shown... Figure 5A As shown, the first connector 30 includes a first connecting portion 31, a second connecting portion 32, and a third connecting portion 34. The first connecting portion 31 is disposed opposite to the second signal transmission line 20 and is located on the side of the second signal transmission line 20 away from the substrate 10. The first connecting portion 31 is connected to the second signal transmission line 20 through a second via V2. The second connecting portion 32 is disposed opposite to the spaced area between the first sub-transmission line 61 and the second sub-transmission line 62. The third connecting portion 34 is located on the side of the second sub-transmission line 62 away from the substrate 10 and is connected to the second sub-transmission line 62 through a third via V3. Furthermore, since the film layer thickness below the first connecting portion 31 is larger and the film layer thickness below the second connecting portion 32 is smaller, a first ramp portion 33 is formed between the first connecting portion 31 and the second connecting portion 32 of the first connector 30. Similarly, a third ramp portion 35 is formed between the second connecting portion 32 and the third connecting portion 34. In this embodiment, the term "relatively disposed" means that the orthographic projections of the two structures on the substrate 10 overlap.

[0096] In this embodiment, the first connector 30 connects the second signal transmission line 20 to the second sub-transmission line 62 of the first signal transmission line 60. Simultaneously, the second signal transmission line 20 is also connected to the first sub-transmission line 61 of the first signal transmission line 60 via a first via V1. Therefore, even if the first ramp portion 33 of the first connector 30 breaks due to static electricity or other factors, the signal on the first signal transmission line 60 can still be transmitted to the second signal transmission line 20 through the first via V1. When the first ramp portion of the first connector 30 does not break, the signal on the first signal transmission line 60 can be transmitted to the second signal transmission line 20 through the first via V1 or through the first connector 30, thereby ensuring the reliability and current resistance of the connection between the first signal transmission line 60 and the second signal transmission line 20. In other words, compared to the prior art, the first signal transmission line 60 and the second signal transmission line 20 can carry a larger input current.

[0097] This disclosure does not limit the number of first signal transmission lines 60 and second signal transmission lines 20. In some embodiments, there is one first signal transmission line 60 and multiple second signal transmission lines 20, with the first signal transmission line 60 connected to multiple second signal transmission lines 20; or, there are multiple first signal transmission lines 60 and multiple second signal transmission lines 20, with each first signal transmission line 60 connected to multiple second signal transmission lines 20. It should be understood that regardless of the number of first signal transmission lines 60 and second signal transmission lines 20, each second signal transmission line 20 is connected to the first signal transmission line 60 via a first connector 30, and different second signal transmission lines 20 are connected to different first connectors 30.

[0098] In a specific example, the display substrate includes a display area and a non-display area. The non-display area is provided with multiple shift register units. A first signal transmission line 60, a second signal transmission line 20, and a first connector 30 are all located in the non-display area. There can be one first signal transmission line 60, which can be used as a clock signal line. There can be multiple second signal transmission lines 20, each connected between a first signal transmission line 60 and a shift register unit, with different second signal transmission lines 20 connected to different shift register units. Alternatively, there can be multiple first signal transmission lines 60, each used as a different clock signal line; and multiple second signal transmission lines 20, each connected to one first signal transmission line 60 and one shift register unit, with different second signal lines 20 connected to different shift register units.

[0099] It should be noted that in the above example, using the first signal transmission line 60 as a clock signal line and the second signal transmission line 20 as a transmission line between the clock signal line and the shift register unit is merely an illustrative example. In practical applications, the first signal transmission line 60 and the second signal transmission line 20 can also be used in other structures. For example, the first signal transmission line 60 can be used as a fan-out line, and the second signal transmission line 20 can be used as a data line lead-out section. The data line lead-out section is the part of the data line extending into the non-display area, and the fan-out line connects the data line lead-out section and the data driver chip, thereby transmitting the data signal provided by the data driver chip to the corresponding data line. As another example, a portion of the multiple first signal transmission lines 60 can be used as clock signal lines, and the remaining first signal transmission lines 60 can be used as fan-out lines; a portion of the multiple second signal transmission lines 20 can be used as a transmission line between the clock signal line and the shift register unit, and the remaining second signal transmission lines 20 can be used as data line leads-out sections.

[0100] like Figure 4 As shown, the second sub-transmission line 62 of the first signal transmission line 60 is located on one side of the first sub-transmission line 61 along the first direction. Both the first sub-transmission line 61 and the second sub-transmission line 62 extend along the second direction, for example, the first direction is perpendicular to the second direction. The second signal transmission line 20 may include a conductive part 21 and a transmission part 22 connected as one unit. The conductive part 21 extends along the second direction, and the orthographic projection of the first via V1 on the substrate 10 is located within the orthographic projection range of the conductive part 21 on the substrate. The conductive part 21 is connected to the first sub-transmission line 61 through the first via V1, and the transmission part 22 extends along the first direction. When the first signal transmission line 60 is used as a clock signal line, the transmission part 22 can be connected between the conductive part 21 and the clock signal terminal of the shift register unit.

[0101] like Figure 4 and Figure 5A As shown, in some embodiments, the orthographic projection of the second via V2 on the substrate 10 is located within the orthographic projection range of the second signal transmission line 20 on the substrate 10, so as to ensure the connection stability between the first connector 30 and the second signal transmission line 20. Of course, the orthographic projection of the second via V2 on the substrate 10 may also exceed the orthographic projection of the second signal transmission line 20 on the substrate 10.

[0102] In some embodiments, the orthographic projection of the second via V2 on the substrate 10 can be located within the orthographic projection range of the first via V1 on the substrate 10. This ensures that the bottom of the second via V2 is located on a flat surface, thereby further improving the connection reliability between the first connector 30 and the second signal transmission line 20.

[0103] like Figure 4 and Figure 5AAs shown, in some embodiments, the orthographic projection of the first via V1 on the substrate 10 is located within the orthographic projection range of the conductive portion 21 of the second signal transmission line 20 on the substrate 10.

[0104] In some embodiments, the dimension d1 of the first via V1 in the width direction (i.e., the first direction) of the conductive portion 21 is 0.4 to 0.6 times the width of the conductive portion 21, and the dimension d2 of the second via V2 in the first direction is 0.2 to 0.5 times the width of the conductive portion 21.

[0105] In one example, the width of the conductive portion 21 is between 15 μm and 25 μm, the dimension d1 of the first via V1 in the first direction is between 8 μm and 12 μm, and the dimension d2 of the second via V2 in the first direction is between 4 μm and 8 μm. For example, the width of the conductive portion 21 is 19.6 μm, the dimension d1 of the first via V1 in the first direction is 9.6 μm, and the dimension d2 of the second via V2 in the first direction is 6.0 μm. The conductive portion 21 has a first edge and a second edge that are disposed opposite to each other and extend along the second direction. The distance d3 between the orthographic projection of the first via V1 on the substrate 10 and the orthographic projection of the first edge on the substrate 10 can be equal to the distance d4 between the orthographic projection of the first via V1 on the substrate 10 and the orthographic projection of the second edge on the substrate 10. The distance d5 between the orthographic projection of the second via V2 on the substrate 10 and the orthographic projection of the first edge on the substrate 10 can be equal to d6 between the orthographic projection of the second via V2 on the substrate 10 and the orthographic projection of the second edge on the substrate 10. For example, both d5 ​​and d6 can be between 3 and 6 μm. In this case, even if process fluctuations occur during the fabrication process, it can be ensured that the orthographic projection of the second via V2 on the substrate 10 is located within the orthographic projection of the conductive part 61 on the substrate 10, thereby ensuring a stable connection between the first connector 30 and the conductive part.

[0106] The shapes of the first via V1 and the second via V2 are not limited in this embodiment. In one example, the orthographic projections of the first via V1 and the second via V2 on the substrate 10 can both be rectangular. Furthermore, in this embodiment, each first connector 30 can be connected to the second signal transmission line 20 through multiple second vias V2, and to the second sub-transmission line 62 of the first signal transmission line 60 through multiple third vias V3, thereby ensuring connection reliability. In one example, the multiple third vias V3 corresponding to the same first connector 30 are arranged along the extension direction (i.e., the second direction) of the first signal transmission line 60, and the multiple second vias V2 corresponding to the same first connector 30 are arranged along the second direction.

[0107] In this case, the orthographic projections of multiple second vias V2 corresponding to the same first connector 30 on the substrate 10 are located within the orthographic projection range of the same first via V1 on the substrate 10, thereby reducing the process difficulty.

[0108] In some embodiments, such as Figure 4 and Figure 5A As shown, the orthographic projection of the second via V2 on the substrate 10 lies within the orthographic projection of the first connector 30 on the substrate 10, and the boundaries of the two orthographic projections do not contact. For example, the first connector 30 has a first side and a second side extending along a second direction. The first side is located on the side of the second via V2 away from the third via V3, and the second side is located on the side of the third via V3 away from the second via V2. The distance d7 between the orthographic projection of the first side on the substrate 10 and the orthographic projection of the second via V2 on the substrate 10 is between 5 μm and 8 μm. Thus, even if there are process fluctuations during the fabrication of the first connector 30, it can be ensured that the first connector 30 completely covers the second via V2, thereby ensuring a stable connection between the first connector 30 and the second signal transmission line 20. For example, the distance d7 between the orthographic projection of the first side on the substrate 10 and the orthographic projection of the first via V1 on the substrate 10 is 5 μm, 6 μm, 7 μm, or 8 μm. Similarly, the distance d8 between the orthographic projection of the second side on the substrate 10 and the orthographic projection of the third via V3 on the substrate 10 is between 5 μm and 8 μm. This ensures that, even with process variations during the fabrication of the first connector 30, the first connector 30 completely covers the third via V3, thereby guaranteeing a stable connection between the first connector 30 and the second sub-transmission line 62. For example, the distance d8 between the orthographic projection of the second side on the substrate 10 and the orthographic projection of the third via V3 on the substrate 10 is 5 μm, 6 μm, 7 μm, or 8 μm.

[0109] In some embodiments, the thickness of the second insulating layer 50 is... Between, for example, the thickness of the second insulating layer 50 is This arrangement helps to reduce the tilt angle of the first ramp portion 33 of the first connector 30, thereby reducing the possibility of breakage of the first connector 30. For example, the thickness of the second insulating layer 50 is... or or or

[0110] In some embodiments, the thickness of the first signal transmission line 60 can be [missing information]. Between, for example, the thickness of the first signal transmission line 60 is or or or or The thickness of the first insulating layer 40 can be Between, for example, the thickness of the first insulating layer 40 is or or or or The thickness of the second signal transmission line 20 can be Between, for example, the thickness of the second signal transmission line 20 is or or or or

[0111] In some embodiments, the depth difference between the second via V2 and the first via V1 can be... Between these two points, the sum of the depths of the first via V1 and the second via V2, minus the depth of the third via V3, can be obtained as follows: Between these two points, the difference between the depth of the third via V3 and the depth of the second via V2 can be less than or equal to [the value of the difference]. The depth of the first via V1 can be the same as the thickness of the first insulating layer 40, and the depth of the third via V3 can be the sum of the thicknesses of the first insulating layer 40 and the second insulating layer 50. The depth of the second via V2 refers to the height difference between the portion of the first connector 30 located on the upper surface of the second insulating layer 50 and the portion of the first connector 30 falling into the bottom of the second via V2. Optionally, the depth of the first via V1 can be... Between, the depth of the second via V2 can be Between, the depth of the third via V3 can be This helps to reduce the slope at each position of the first connector 30.

[0112] Combination Figure 5A and Figure 5BAs shown, the first connecting portion 31 of the first connector 30 may specifically include: a first overlapping portion 31a, a second ramp portion 31b, and a first flat portion 31c, wherein the second ramp portion 31b and the first flat portion 31c are both located within the second via V2. The second signal transmission line 20 includes a first contact portion located within the first via V1 and in direct contact with the first sub-transmission line 61, the first contact portion being located at the bottom of the first via V1; the aforementioned first flat portion 31c is the portion of the first connector 30 in direct contact with the first contact portion, and compared to the second ramp portion 31b, the first flat portion 31c is in a generally flat state. The first overlapping portion 31a is located outside the second via V2 and connects the first ramp portion 33 and the second ramp portion 31b. The slope angle α of the first ramp portion 33 is between 35° and 64°; the slope angle β of the second ramp portion 31b is between 35° and 62°. The slope angle of the first climbing section 33 / second climbing section 31b refers to the angle between the line connecting the starting point and the ending point of the climbing section 33 / second climbing section 31b and the plane containing the substrate 10. In other words, the tangent of the slope angle of the first climbing section 33 / second climbing section 31b is the ratio of its dimension in the vertical direction to its dimension in the first direction, where the vertical direction is perpendicular to the substrate 10. The starting point of the climb refers to the end closer to the substrate 10, and the ending point refers to the end farther from the substrate 10.

[0113] When there are no other film layers between the first overlapping portion 31a and the first sub-transmission line 61 besides the first insulating layer 40, the second insulating layer 50, and the second signal transmission line 20, the tangent of the slope angle of the first climbing portion 33 is: (thickness of the first sub-transmission line 61 + thickness of the second signal transmission line 20) / dimension of the first climbing portion 33 in the first direction; the tangent of the slope angle of the second climbing portion 31b is: (thickness of the first insulating layer 40 + thickness of the second insulating layer 50) / dimension of the first climbing portion 33 in the first direction.

[0114] The dimensions of the first ramp portion 33 and the second ramp portion 31b in the first direction are related to the etching process. For example, under a certain etching process, the dimensions of the first ramp portion 33 and the second ramp portion 31b in the first direction are both [missing information]. The thicknesses of the first sub-transmission line 61, the second signal transmission line 20, the first insulating layer 40, and the second insulating layer 50 are all... Therefore, tanα = (1500 + 1500) / 4000, α = 36.9°; tanβ = (1500 + 1500) / 4000, β = 36.9°. For example, the dimensions of the first climbing section 33 and the second climbing section 31b in the first direction are both... The thicknesses of the first sub-transmission line 61, the second signal transmission line 20, and the first insulating layer 40 are all... The thickness of the second insulating layer 50 is Then, tanα=(4000+4000) / 4000, α=63.4°; tanβ=(3500+4000) / 4000, β=61.9°.

[0115] Figure 5C Other embodiments of this disclosure provide for the following: Figure 4 A partial sectional view of line B-B' in the middle, as shown below. Figure 5C As shown, in some examples, due to limitations in process conditions, the walls of the first via V1 and the second via V2 do not exhibit a specific shape. Figure 5A The regular tilt state in the middle leads to the second climbing part 31b not being a regular tilt state, but rather a concave-convex curved state. In this case, the slope angle of the first climbing part 33 / second climbing part 31b can still be regarded as the angle between the line connecting the starting point and the ending point of the first climbing part 33 / second climbing part 31b and the plane where the substrate 10 is located.

[0116] Additionally, in some examples, such as Figure 5C As shown, along direction 10 near the substrate, the cross-sectional area of ​​the first via V1 on the first insulating layer 40 gradually decreases, and the cross-sectional area of ​​the second via V2 on the second insulating layer 50 gradually decreases. The slope angle of the wall of the first via V1 is smaller than that of the wall of the second via V2; that is, the wall of the first via V1 is gentler than that of the second via V2. It should be noted that the slope angle of the via wall is the angle between the line connecting the bottom and top of the via wall and the substrate 10. By making the wall of the first via V1 have a smaller slope angle, the possibility of breakage of the first connector 30 can be further reduced, and the film uniformity of the first connector 30 can be improved.

[0117] Figure 6 This is a plan view of a partial area of ​​the display substrate provided in some other embodiments of this disclosure. Figure 7 For along Figure 6 A sectional view of line C-C' in the middle. Figure 6 and Figure 5A The structures shown are largely similar, differing only in the coverage area of ​​the orthographic projection of the first via V1 onto the substrate 10. Specifically, the orthographic projection of the first via V1 onto the substrate 10 is denoted as the first projection, and the orthographic projection of the conductive portion 21 of the second signal transmission line 20 onto the substrate 10 is denoted as the second projection, as shown below. Figure 7As shown, a portion of the first projection extends beyond the second projection, and the extended portion is located on the side of the second projection closer to the second sub-transmission line 62. In this case, at least a portion of the conductive part 21 near the third via V3 can be located in the first via V1, thereby reducing the climbing height of the climbing part 33 and further reducing the possibility of the first connector 30 breaking.

[0118] exist Figures 6 to 7 In the embodiment shown, the depth difference between the second via V2 and the first via V1 can be less than [amount missing]. The sum of the depths of the first via V1 and the second via V2 can be approximately equal to the depth of the third via V3. The difference between the depth of the third via V3 and the depth of the second via V2 can be... Between. Wherein, the depth of the first via V1 can be the same as the thickness of the first insulating layer 40, the depth of the second via V2 can be the same as the thickness of the second insulating layer 50, and the depth of the third via V3 can be the sum of the thicknesses of the first insulating layer 40 and the second insulating layer 50. Optionally, the depth of the first via V1 is between... Between, the depth of the second via V2 is Between, the depth of the third via V3 is This helps to reduce the slope at each position of the first connector 30.

[0119] and Figure 5A Similarly, the first connector 30 includes: a first connecting portion 31, a second connecting portion 32, a third connecting portion 34, and a first climbing portion 33. The first connecting portion 31 specifically includes: a first overlapping portion 31a and a second climbing portion 31b, wherein the second climbing portion 31b is located inside the second through hole V2, and the first overlapping portion 31a is located outside the second through hole V2, connecting the first climbing portion 33 and the second climbing portion 31b. Figure 5A The difference is that, Figure 7 The slope angle γ of the first climbing section 33 is compared to Figure 5B The slope angle α of the first climbing section 33 is smaller. Figure 7 The slope angle θ of the second climbing section 31b is compared to Figure 5B The slope angle β of the second climbing section 31b is smaller. Specifically, in Figure 7 In the first climbing section 33, the slope angle γ is between 20° and 45°; the slope angle θ of the second climbing section 31b is between 20° and 42°.

[0120] Wherein, when there are no other film layers between the first overlapping part 31a and the first sub-transmission line 61 besides the second insulating layer 50 and the second signal transmission line 20, the tangent value of the slope angle γ of the first climbing part 33 is: (thickness of the first sub-transmission line 61 + thickness of the second signal transmission line 20 - thickness of the first insulating layer 40) / dimension of the first climbing part 33 in the first direction; the tangent value of the slope angle θ of the second climbing part 31b is: thickness of the second insulating layer 50 / dimension of the first climbing part 33 in the first direction.

[0121] For example, in a certain etching process, the dimensions of the first ramp portion 33 in the first direction and the dimensions of the second ramp portion 31b in the first direction are both... The thicknesses of the first sub-transmission line 61, the second signal transmission line 20, the first insulating layer 40, and the second insulating layer 50 are all... Then for Figure 7 The slope angle γ of the first climbing section 33 has a tangent value of tanγ = 1500 / 4000, and α = 20.56°; the slope angle θ of the second climbing section 31b has a tangent value of tanθ = 1500 / 4000, and θ = 20.56°. For example, the dimensions of the first climbing section 33 and the second climbing section 31b in the first direction are both... The thicknesses of the first sub-transmission line 61, the second signal transmission line 20, and the first insulating layer 40 are all... The thickness of the second insulating layer 50 is Then the tangent of the slope angle γ of the first climbing section 33 is tanγ=(4000+4000—4000) / 4000, γ=45°, and the tangent of the slope angle θ of the second climbing section 31b is tanθ=3500 / 4000, θ=41.18°.

[0122] Among them, Figure 7 In this configuration, the dimension of the first via V1 in the first direction is 0.4 to 0.6 times the width of the conductive portion 21, and the dimension of the second via V2 in the first direction is 0.7 to 1.1 times the width of the conductive portion 21. In one example, the width of the conductive portion 21 is between 15 μm and 25 μm, the dimension of the first via V1 in the first direction is between 17.6 μm and 20.6 μm, and the dimension of the second via V2 in the first direction is between 4 μm and 8 μm. For example, the width of the conductive portion 21 is 19.6 μm, the dimension of the first via V1 in the first direction is 17.6 μm, 18 μm, 19 μm, 20 μm, or 20.6 μm, and the dimension of the second via V2 in the first direction is 6.0 μm.

[0123] exist Figure 6 and Figure 7In the embodiment shown, the conductive part 21 has a first edge and a second edge extending along the second direction. The first edge is close to the second via V2, and the second edge is close to the third via V3. The distance between the orthographic projection of the first edge on the substrate 10 and the orthographic projection of the second via V2 on the substrate 10 is the aforementioned distance d6, which is between 3μm and 6μm. In this case, even if process fluctuations occur during the fabrication process, it can be ensured that the orthographic projection of the second via V2 on the substrate 10 is within the orthographic projection of the conductive part 21 on the substrate 10, thereby ensuring a stable connection between the first connector 30 and the conductive part 21.

[0124] In addition, for Figure 6 and Figure 7 In the embodiment shown, the morphology of the first via V1 and the second via V2 can also be set such that the cross-sectional area of ​​the first via V1 and the cross-sectional area of ​​the second via V2 gradually decrease along the direction close to the substrate 10. In addition, the slope angle of the hole wall of the first via V1 is smaller than the slope angle of the hole wall of the second via V2, thereby further reducing the possibility of the first connector 30 breaking.

[0125] Figure 8 This is a partial plan view of the display area of ​​the display substrate provided in some embodiments of this disclosure. Figure 9 This is a cross-sectional view of a display substrate provided in some embodiments of this disclosure. Figure 9 The diagram only schematically illustrates part of the structure of the display area and non-display area. (Combined) Figure 8 and Figure 9 As shown, the display area AA of the display substrate is provided with multiple gate lines GL and multiple data lines DL. The multiple gate lines GL and multiple data lines DL are arranged intersectingly, thereby defining multiple sub-pixels in the display area AA. Each sub-pixel is provided with a thin-film transistor 80, a pixel electrode 71, and other structures. The thin-film transistor 80 includes a gate 81, an active layer 82, a source 83, and a drain 84. The active layer 82 is disposed opposite to the gate 81 and is insulated from it. The active layer 82 includes a source contact region, a drain contact region, and a channel region located between the two. The source 83 contacts the source contact region, and the drain 84 contacts the drain contact region. Furthermore, the source 83 of the thin-film transistor 80 is electrically connected to the data line DL, and the drain 84 is electrically connected to the pixel electrode 71.

[0126] In some embodiments, such as Figure 9 As shown, the first insulating layer 40 and the second insulating layer 50 both cover the display area AA and the non-display area NA. The gate 81 and the gate line GL of the thin film transistor 80 can be an integral structure, which is located between the first insulating layer 40 and the substrate 10. The active layer 82 of the thin film transistor 80 is located on the side of the first insulating layer 40 away from the substrate 10. The source 83 and the drain 84 are both located on the side of the active layer 82 away from the substrate 10.

[0127] The pixel electrode 71 is located between the first insulating layer 40 and the substrate 10. The sub-pixel is also provided with a second connector 72. The second connector 72 is located on the side of the second insulating layer 50 away from the substrate 10, and is connected to the drain 84 of the thin film transistor 80 through a fourth via V4 penetrating the second insulating layer 50, and is connected to the pixel electrode 71 through a fifth via V5 penetrating the first insulating layer 40 and the second insulating layer 50.

[0128] The display substrate also includes multiple common electrodes 70 and multiple common electrode lines CL. The common electrodes 70 are located in the display area and on the side of the second insulating layer 50 away from the substrate 10. Each common electrode 70 has multiple slits. The common electrode lines CL can be disposed in the same layer as the gate lines GL, and their extension directions are approximately the same. The common electrodes 70 are connected to the common electrode lines CL through a sixth via (not shown) penetrating the first insulating layer 40 and the second insulating layer 50.

[0129] In some embodiments, the first signal transmission line 60 is disposed in the same layer as the gate 81 of the thin-film transistor 80, and its material may include one or more of molybdenum, aluminum, and copper. The second signal transmission line 20 is disposed in the same layer as the source 83 and drain 84 of the thin-film transistor 80, and its material may include one or more of molybdenum, aluminum, and copper. The first connector 30, the second connector 72, and the common electrode 70 are disposed in the same layer, and they may be made of a transparent conductive material such as indium tin oxide (ITO).

[0130] Figure 10 This is a cross-sectional view of a display substrate provided in some other embodiments of this disclosure. Figure 10 The diagram only schematically illustrates part of the structure of the display area and the non-display area. Figure 10 The structure shown is Figure 9 The structures shown are largely similar, the only difference being that... Figure 10In the first insulating layer 40, a semiconductor redundancy portion 90 is also provided on the side away from the substrate 10. Specifically, the second signal transmission line 20 includes a portion 20a located inside the first via V1 and an overlapping portion 20b located outside the first via V1. The orthographic projection of the overlapping portion 20b on the substrate 10 is located outside the orthographic projection of the first via V1 on the substrate 10. The semiconductor redundancy portion 90 is located between the first insulating layer 40 and the overlapping portion 20b. The semiconductor redundancy portion 90 is formed synchronously with the active layer 82 of the thin film transistor 80. In addition, the source 83 and drain 84 of the thin-film transistor 80 are in direct contact with the active layer 82 (here, "direct contact" means that no other insulating layer is provided between the layers containing the source 83 and drain 84 and the active layer 82, so that the source 83 and drain 84 are directly connected to the active layer 82 without the need for via connection), and the orthographic projections of the source 83 and drain 84 on the substrate 10 are both within the orthographic projection range of the active layer 82 on the substrate 10. This helps to simplify the fabrication process of the thin-film transistor 80. The specific fabrication process of the thin-film transistor 80 will be described below, and will not be repeated here.

[0131] This disclosure also provides a method for manufacturing the above-mentioned display substrate. Figure 11 This is a flowchart illustrating a method for manufacturing a display substrate provided in some embodiments of this disclosure, such as... Figure 11 As shown, the method for manufacturing the display substrate includes:

[0132] S11. A pattern including a first signal transmission line is formed on a substrate. The first signal transmission line includes a first sub-transmission line and a second sub-transmission line that are arranged side by side and electrically connected.

[0133] S12. A first insulating layer is formed on the side of the first signal transmission line away from the substrate.

[0134] S13. A first via is formed at a position corresponding to the first sub-transmission line, penetrating the first insulating layer.

[0135] S14. A pattern including a second signal transmission line is formed on the side of the first insulating layer away from the substrate, and the second signal transmission line is connected to the first sub-transmission line through a first via.

[0136] S15. A second insulating layer is formed on the side of the second signal transmission line away from the substrate.

[0137] S16. A second via penetrating the second insulating layer is formed at a position corresponding to the second signal transmission line, and a third via penetrating the first insulating layer and the second insulating layer is formed at a position corresponding to the second sub-transmission line.

[0138] S17. A pattern including a first connector is formed on the side of the second insulating layer away from the substrate. The first connector is connected to the second signal transmission line through a second via and to the second sub-transmission line through a third via.

[0139] In some embodiments, the first signal transmission line, the second signal transmission line, and the first connector are all located in a non-display area. In some embodiments, the fabrication method further includes: forming a thin-film transistor in each sub-pixel of the display area, wherein the gate of the thin-film transistor is formed synchronously with the first signal transmission line, the second signal transmission line, and the first connector, and the source, drain, and second signal transmission line of the thin-film transistor are formed synchronously.

[0140] In some embodiments, both the first insulating layer and the second insulating layer cover the display area. The fabrication method further includes: forming a pixel electrode in each sub-pixel before forming the first insulating layer; forming a fourth via penetrating the second insulating layer and a fifth via penetrating the first and second insulating layers after forming the second insulating layer; forming a second connector, which is connected to the drain of the thin-film transistor through the fourth via and to the pixel electrode through the fifth via; wherein the second connector is formed simultaneously with the first connector.

[0141] Figures 12 to 18 This is a schematic diagram of the structure during the fabrication process of a display substrate provided in some embodiments of this disclosure. Figures 12 to 18 The manufacturing process is used to produce Figure 9 The display substrate in the image. For example... Figures 12 to 18 As shown, the method for manufacturing a display substrate includes the following steps S20 to S28:

[0142] S20, such as Figure 12 As shown, a plurality of pixel electrodes 71 are formed on the substrate 10, and each sub-pixel of the display area AA is provided with a pixel electrode 71. The pixel electrodes 71 are formed by photolithography, and the material of the pixel electrodes 71 may include transparent conductive materials such as ITO, and their thickness is within [specified range]. Between, for example

[0143] S21, such as Figure 13 As shown, a first conductive pattern layer is formed on a substrate 10. The first conductive pattern layer includes the gate 81 of the thin film transistor 80 in each sub-pixel, and also includes a gate line GL, a common electrode line CL, and a first signal transmission line 60. The first signal transmission line 60 includes a first sub-transmission line and a second sub-transmission line arranged side by side, and a connection portion connecting the two. Both the first sub-transmission line and the second sub-transmission line extend along a second direction.

[0144] In one example, the first conductive patterned layer can be a stack of Mo / Al / Mo, for example, the thicknesses of Mo / Al / Mo are respectively...

[0145] S22, such as Figure 14 As shown, a first insulating layer 40 and a semiconductor layer 82a are formed sequentially. The material of the first insulating layer 40 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the thickness of the first insulating layer 40 may be [missing information]. Between, for example The material of semiconductor layer 82a may include a-Si, and its thickness may be [missing information]. Between, for example

[0146] S23, such as Figure 15 As shown, the first via V1 is formed.

[0147] Specifically, the steps for forming the first via V1 may include S231 to S232:

[0148] S231. A photoresist layer is formed on the semiconductor layer 82a, and the photoresist layer is exposed and developed to remove the photoresist in the area where the first via V1 is to be formed.

[0149] S232. The semiconductor layer 82a and the first insulating layer 40 are etched to form the first via V1. After etching, the portion of the semiconductor layer 82a corresponding to the first via V1 is also etched away.

[0150] S24, such as Figure 16 As shown, the semiconductor layer 82a is etched again to form the active layer 82 of the thin film transistor 80.

[0151] It should be noted that in step S22, only the first insulating layer 40 may be formed without forming the semiconductor layer. In step S23, a photoresist layer is formed on the first insulating layer 40, and after exposing and developing the photoresist layer, only the first insulating layer 40 is etched to form the first via V1. Then, the semiconductor layer 82 is formed and patterned to form the active layer 82.

[0152] S25. Form a source / drain metal layer and perform a patterning process on the source / drain metal layer to form a second conductive pattern layer. The second conductive pattern layer includes a second signal transmission line 20, a source 83 and a drain 84 of a thin-film transistor 80, such as... Figure 17 As shown.

[0153] The source / drain metal layers can be a stack of Mo / Al / Mo, with the thicknesses of Mo / Al / Mo being:

[0154] S26. Forming a second insulating layer 50. The material of the second insulating layer 50 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, and its thickness may be [missing information]. Between, for example

[0155] S27, such as Figure 18 As shown, a second via V2 penetrating the second insulating layer 50, a third via V3 penetrating the first insulating layer 40 and the second insulating layer 50, a fourth via V4 penetrating the second insulating layer 50, a fifth via V5 penetrating the first insulating layer 40 and the second insulating layer 50, and a sixth via penetrating the first insulating layer 40 and the second insulating layer 50 are formed. The orthogonal projection of the second via V2 on the substrate 10 lies within the orthogonal projection range of the second signal transmission line 20 on the substrate 10. The orthogonal projection of the third via V3 on the substrate 10 lies within the orthogonal projection range of the second sub-transmission line 62 on the substrate 10. The orthogonal projection of the fourth via V4 on the substrate 10 lies within the orthogonal projection range of the drain 84 of the thin-film transistor 80 on the substrate 10. The orthogonal projection of the fifth via V5 on the substrate 10 lies within the orthogonal projection range of the pixel electrode 71 on the substrate 10. The orthogonal projection of the sixth via on the substrate 10 lies within the orthogonal projection range of the common electrode line CL on the substrate 10.

[0156] S28, such as Figure 19 As shown, a pattern is formed including a first connector 30, a second connector 72, and a common electrode. The first connector 30 is connected to the second signal transmission line 20 via a second via V2 and to the second sub-transmission line 62 via a third via V3. The second connector 72 is connected to the drain 84 of the thin-film transistor 80 via a fourth via V4 and to the pixel electrode 71 via a fifth via V5. The common electrode can be connected to a common electrode line via a sixth via.

[0157] Figures 20 to 30 This is a structural schematic diagram of the display substrate manufacturing process provided in some other embodiments of this disclosure. Figures 20 to 30 The manufacturing process is used to produce Figure 10 The display substrate in the image. For example... Figures 20 to 30 As shown, the method for manufacturing the display substrate includes:

[0158] S30, such as Figure 20 As shown, a plurality of pixel electrodes 71 are formed on the substrate 10. Step S30 can be the same as step S20, and will not be described again here.

[0159] S31, such as Figure 21As shown, a first conductive pattern layer is formed on the substrate 10. The first conductive pattern layer includes the gate 81 of the thin-film transistor 80 in each sub-pixel, and also includes a gate line GL, a common electrode line CL, and a first signal transmission line 60. The first signal transmission line 60 includes a first sub-transmission line 61 and a second sub-transmission line 62 arranged side-by-side, and a connection portion connecting the two. Both the first sub-transmission line 61 and the second sub-transmission line 62 extend along a second direction. This step S31 can be the same as step S21, and will not be described again here.

[0160] S32, such as Figure 22 As shown, a first insulating layer 40 and a semiconductor layer 82a are formed sequentially. The material of the first insulating layer 40 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the thickness of the first insulating layer 40 may be [missing information]. Between, for example The material of semiconductor layer 82a may include a-Si, and its thickness may be [missing information]. Between, for example

[0161] S33, such as Figure 23 As shown, the first via V1 is formed.

[0162] Specifically, the steps for forming the first via V1 may include S331 to S332:

[0163] S331. A photoresist layer is formed on the semiconductor layer 82a, and the photoresist layer is exposed and developed to remove the photoresist in the area where the first via V1 is to be formed.

[0164] S332, the semiconductor layer 82a and the first insulating layer 40 are etched to form the first via V1, and after etching, the portion of the semiconductor layer 82a corresponding to the first via V1 is also etched away.

[0165] S34. Synchronously form the second signal transmission line 20 and the source 83, drain 84, and active layer 82 of the thin-film transistor 80. Specifically, step S34 may include S341 to S345:

[0166] S341, such as Figure 24 As shown, a source / drain metal layer 83a and a photoresist layer PR are sequentially formed on the side of the semiconductor layer away from the substrate 10. The source / drain metal layer 83a can be a Mo / Al / Mo stack, with the thicknesses of Mo / Al / Mo being:

[0167] S342, such as Figure 25As shown, the photoresist layer PR undergoes stepped exposure and development to form a photoresist pattern. This photoresist layer includes at least a first photoresist portion PR1 in each sub-pixel. The first photoresist portion PR1 is located in the region where the active layer 82 is located and includes: a first portion PR11 corresponding to the source electrode 83, a second portion PR12 corresponding to the drain electrode 84, and a third portion PR13 located between the first portion PR11 and the second portion PR12. The thicknesses of both the first portion PR11 and the second portion PR12 of the first photoresist portion PR11 are greater than the thickness of the third portion PR13. In each sub-pixel, the photoresist layer PR outside the region where the active layer 82 is located can be removed.

[0168] In particular, when exposing the photoresist layer PR, a half-tone mask can be used to perform stepped exposure of the photoresist layer.

[0169] Furthermore, after step exposure and development of the photoresist layer PR, the resulting pattern may also include a second photoresist layer PR2 and a third photoresist layer. The second photoresist layer PR2 is located in the region where the second signal transmission line 20 is to be formed, and the third photoresist layer is located in the region where the data line DL is to be formed. The thickness of both the second photoresist layer PR2 and the third photoresist layer is greater than the thickness of the third portion PR13 of the first photoresist layer PR1.

[0170] S343, such as Figure 26 As shown, the source / drain metal layer 83a and semiconductor layer 82a are etched to remove the portions of the source / drain metal layer 83a and semiconductor layer 82a that are not covered by the photoresist pattern, thereby forming the active layer 82 and intermediate electrode 83b corresponding to the first photoresist section PR1, as well as the second signal transmission line 20 and semiconductor redundancy section 90 corresponding to the second photoresist section PR2, and the data line and semiconductor redundancy section corresponding to the third photoresist section.

[0171] The second signal transmission line 20 is connected to the first sub-transmission line 61 through the first via V1. The second signal transmission line 20 includes a portion located inside the first via V1 and an overlapping portion located outside the first via V1. The orthographic projection of the overlapping portion on the substrate 10 is located outside the orthographic projection of the first via V1 on the substrate 10. The semiconductor redundancy portion 90 is located between the overlapping portion 20b and the first insulating layer 40.

[0172] S344, such as Figure 27 As shown, the first photoresist portion PR1 and the second photoresist portion PR2 are ashed to thin the first portion PR11 and the second portion PR12 of the first photoresist portion PR1 and the second photoresist portion PR2, and remove the third portion PR13 of the first photoresist portion PR1.

[0173] S345, such as Figure 28As shown, the intermediate electrode 83b is etched to form the source 83 and the drain 84.

[0174] After that, the remaining photoresist is removed.

[0175] The above step S34 can utilize the same photolithography patterning process to form the second signal transmission line 20 and the source 83, drain 84 and active layer 82 of the thin film transistor 80, thereby simplifying the fabrication process and reducing the process cost.

[0176] S35. Forming a second insulating layer 50. The material of the second insulating layer 50 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride, and its thickness may be [missing information]. Between, for example

[0177] S36, such as Figure 29 As shown, a second via V2 penetrating the second insulating layer 50, a third via V3 penetrating the first insulating layer 40 and the second insulating layer 50, a fourth via penetrating the second insulating layer 50, a fifth via penetrating the first insulating layer 40 and the second insulating layer 50, and a sixth via penetrating the first insulating layer 40 and the second insulating layer 50 are formed. The orthographic projection of the second via V2 on the substrate 10 lies within the orthographic projection range of the second signal transmission line 20 on the substrate 10. The orthographic projection of the third via V3 on the substrate 10 lies within the orthographic projection range of the second sub-transmission line 62 on the substrate 10. The orthographic projection of the fourth via on the substrate 10 lies within the orthographic projection range of the drain 84 of the thin-film transistor 80 on the substrate 10. The orthographic projection of the fifth via on the substrate 10 lies within the orthographic projection range of the pixel electrode 71 on the substrate 10. The orthographic projection of the sixth via on the substrate 10 lies within the orthographic projection range of the common electrode line CL on the substrate 10.

[0178] S37, such as Figure 30 As shown, a first connector 30, a second connector 72, and a common electrode 70 are formed. The first connector 30 is connected to the second signal transmission line 20 via a second via V2 and to the second sub-transmission line 62 via a third via V3. The second connector 72 is connected to the drain 84 of the thin-film transistor 80 via a fourth via and to the pixel electrode 71 via a fifth via. The common electrode 70 can be connected to the common electrode line CL via a sixth via.

[0179] This disclosure also provides a display device, which includes the display substrate described in the above embodiments. The display device can be any product or component with display functionality, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0180] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising: Substrate; A first signal transmission line is disposed on the substrate, which includes a first sub-transmission line and a second sub-transmission line disposed on the same layer. The first sub-transmission line and the second sub-transmission line are arranged side by side and electrically connected. A first insulating layer is disposed on the side of the first signal transmission line away from the substrate. The second signal transmission line is disposed on the side of the first insulating layer away from the substrate and is connected to the first sub-transmission line through a first via penetrating the first insulating layer; the second signal transmission line includes a first contact portion located in the first via and in direct contact with the first sub-transmission line; A second insulating layer is disposed on the side of the second signal transmission line away from the substrate. A first connector is disposed on the side of the second insulating layer away from the substrate. The first connector is connected to the second signal transmission line through a second via penetrating the second insulating layer, and is connected to the second sub-transmission line through a third via penetrating the first insulating layer and the second insulating layer. The second signal transmission line includes: a conductive portion and a transmission portion connected to the conductive portion, the conductive portion extending along the length direction of the first sub-transmission line, and the extension direction of the transmission portion intersecting the extension direction of the conductive portion; The orthographic projection of the first via on the substrate is the first projection, and the orthographic projection of the conductive portion on the substrate is the second projection; a portion of the first projection extends beyond the second projection and is located on the side of the second projection closer to the second sub-transmission line.

2. The display substrate according to claim 1, wherein, The orthographic projection of the second via on the substrate is within the orthographic projection range of the first via on the substrate.

3. The display substrate according to claim 1, wherein, The first connector includes: a first connecting portion, a second connecting portion, and a first ramp portion connecting the two. The first connecting portion is disposed opposite to the second signal transmission line. The orthographic projection of the second connecting portion on the substrate is disposed opposite to the interval region between the first sub-transmission line and the second sub-transmission line. The first connecting portion includes: a first overlapping portion and a second ramp portion. The second ramp portion is located inside the second via. The first overlapping portion is located outside the second via and connects the first ramp portion and the second ramp portion. The slope angle of the first climbing section is between 20° and 45°; the slope angle of the second climbing section is between 20° and 42°.

4. The display substrate according to claim 1, wherein, The depth of the first via is between 1500 Å and 4000 Å, the depth of the second via is between 1500 Å and 4000 Å, and the depth of the third via is between 3000 Å and 8000 Å.

5. The display substrate according to claim 1, wherein, The first via has a dimension in the width direction of the conductive part that is 0.4 to 0.6 times the width of the conductive part, and the second via has a dimension in the width direction of the conductive part that is 0.7 to 1.1 times the width of the conductive part.

6. The display substrate according to any one of claims 1 to 5, wherein, Along the direction close to the substrate, the cross-sectional area of ​​both the first via and the second via gradually decreases; The slope angle of the wall of the first through hole is smaller than that of the wall of the second through hole.

7. The display substrate according to any one of claims 1 to 5, wherein, The thickness of the second insulating layer is between 1000 Å and 4000 Å.

8. The display substrate according to any one of claims 1 to 5, wherein, There are multiple first connectors and multiple second signal transmission lines. The first signal transmission line is connected to multiple first connectors. Each first connector is connected to a second signal transmission line through multiple second vias and to a second sub-transmission line through multiple third vias. Multiple third vias corresponding to the same first connector are arranged along the extension direction of the first signal transmission line, and multiple second vias corresponding to the same first connector are arranged along the extension direction of the first signal transmission line.

9. The display substrate according to claim 8, wherein, The orthographic projections of multiple second vias corresponding to the same first connector on the substrate are located within the orthographic projection range of the same first via on the substrate.

10. The display substrate according to any one of claims 1 to 5, wherein, The display substrate includes a display area and a non-display area. The display area includes a plurality of sub-pixels, and each sub-pixel is provided with a thin-film transistor. The first signal transmission line, the second signal transmission line, and the first connector are all located in the non-display area. The first signal transmission line is disposed on the same layer as the gate of the thin-film transistor, and the second signal transmission line is disposed on the same layer as the source and drain of the thin-film transistor.

11. The display substrate according to claim 10, wherein, Each sub-pixel also includes a pixel electrode and a second connector. Both the first insulating layer and the second insulating layer cover the display area. The pixel electrode is located between the first insulating layer and the substrate. The second connector is located on the side of the second insulating layer away from the substrate and is connected to the drain of the thin-film transistor through a fourth via penetrating the second insulating layer. It is also connected to the pixel electrode through a fifth via penetrating the first and second insulating layers. The second connector is disposed on the same layer as the first connector.

12. The display substrate according to claim 10, wherein, The source and drain of the thin-film transistor are located on the side of the active layer of the thin-film transistor away from the substrate. The source and drain are in direct contact with the active layer, and the orthogonal projections of the source and drain on the substrate are both within the orthogonal projection range of the active layer on the substrate.

13. The display substrate according to claim 10, wherein, The second signal transmission line includes an overlap portion, the orthographic projection of which on the substrate is located outside the orthographic projection of the first via on the substrate. The display substrate further includes a semiconductor redundancy portion located between the first insulating layer and the overlapping portion, and the semiconductor redundancy portion is formed synchronously with the active layer of the thin-film transistor.

14. The display substrate according to any one of claims 1 to 5, wherein, The display substrate includes a display area and a non-display area. The first signal transmission line and the second signal transmission line are both located in the non-display area. The non-display area is also provided with a plurality of shift register units. The first signal transmission line is a clock signal line, and there are multiple second signal transmission lines. Each second signal transmission line is connected between the first signal transmission line and one of the shift register units, and different second signal transmission lines are connected to different shift register units.

15. The display substrate according to any one of claims 1 to 5, wherein, The first signal transmission line further includes a plurality of connecting parts, which are connected between the first sub-transmission line and the second sub-transmission line.

16. A method for manufacturing a display substrate, comprising: A pattern including a first signal transmission line is formed on a substrate, the first signal transmission line including a first sub-transmission line and a second sub-transmission line arranged side by side and electrically connected; A first insulating layer is formed on the side of the first signal transmission line away from the substrate. A first via is formed at a position corresponding to the first sub-transmission line, penetrating the first insulating layer; A pattern including a second signal transmission line is formed on the side of the first insulating layer away from the substrate. The second signal transmission line is connected to the first sub-transmission line through the first via. The second signal transmission line includes a first contact portion located in the first via and in direct contact with the first sub-transmission line. A second insulating layer is formed on the side of the second signal transmission line away from the substrate. A second via is formed at the position corresponding to the second signal transmission line, penetrating the second insulating layer; and a third via is formed at the position corresponding to the second sub-transmission line, penetrating the first insulating layer and the second insulating layer. A pattern including a first connector is formed on the side of the second insulating layer away from the substrate. The first connector is connected to the second signal transmission line through the second via and to the second sub-transmission line through the third via. The second signal transmission line includes a conductive portion and a transmission portion connected to the conductive portion. The conductive portion extends along the length direction of the first sub-transmission line, and the extension direction of the transmission portion intersects the extension direction of the conductive portion. The orthographic projection of the first via on the substrate is a first projection, and the orthographic projection of the conductive portion on the substrate is a second projection. A portion of the first projection extends beyond the second projection and is located on the side of the second projection closer to the second sub-transmission line.

17. The manufacturing method according to claim 16, wherein, The display substrate includes a display area and a non-display area, and the display area includes a plurality of sub-pixels; the manufacturing method further includes: forming a thin-film transistor in each sub-pixel; The first signal transmission line, the second signal transmission line, and the first connector are all located in the non-display area. The first signal transmission line is formed synchronously with the gate of the thin-film transistor, and the second signal transmission line is formed synchronously with the source and drain of the thin-film transistor.

18. The manufacturing method according to claim 17, wherein, Both the first insulating layer and the second insulating layer cover the display area, and the manufacturing method further includes: Before the first insulating layer is formed, a pixel electrode is formed in each of the sub-pixels; After the second insulating layer is formed, a fourth via penetrating the second insulating layer and a fifth via penetrating the first insulating layer and the second insulating layer are formed. A second connector is formed, which is connected to the drain of the thin-film transistor through the fourth via and to the pixel electrode through the fifth via; The second connector is formed simultaneously with the first connector.

19. The manufacturing method according to claim 17, wherein, Before forming the first via, the fabrication method further includes: forming a semiconductor layer; The step of forming the first via includes etching the semiconductor layer and the first insulating layer to form the first via.

20. The manufacturing method according to claim 19, wherein, The second signal transmission line, the source, drain, and active layer of the thin-film transistor are formed through the following steps: A source / drain metal layer and a photoresist layer are sequentially formed on the side of the semiconductor layer away from the substrate. The photoresist layer is subjected to step exposure and development to form at least a first photoresist portion and a second photoresist portion. The first photoresist portion is located in the region where the active layer is to be formed and includes: a first portion corresponding to the source electrode, a second portion corresponding to the drain electrode, and a third portion located between the first portion and the second portion. The second photoresist portion is located in the region where the second signal transmission line is to be formed, and the thicknesses of the first portion, the second portion, and the second photoresist portion are all greater than the thickness of the third portion. The source / drain metal layer and semiconductor layer are etched to form an active layer and an intermediate electrode corresponding to the first photoresist portion, as well as a second signal transmission line and a semiconductor redundancy portion corresponding to the second photoresist portion; The photoresist pattern is grayed out to thin the first portion, the second portion, and the second photoresist portion of the first photoresist portion, and the third portion of the first photoresist portion is removed; The intermediate electrode is etched to form the source and the drain.

21. A display device comprising the display substrate according to any one of claims 1 to 15.

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