Reverse conducting lateral insulated gate bipolar transistor and method for manufacturing the same, chip

Abstract

The application belongs to the technical field of power devices, and provides an inverse-conducting lateral insulated gate bipolar transistor (LIGBT) and a preparation method and a chip thereof. By arranging a first polysilicon layer and a second polysilicon layer, the area of the LIGBT trench polysilicon is reduced as much as possible, the Miller capacitance is reduced, the switching loss is reduced, and the independent channel diode formed by the second polysilicon layer is used to achieve the purpose of freewheeling, the reverse recovery characteristic of the device is improved, the unique structure formed by the electron blocking layer, the horizontal polysilicon field plate, the dielectric oxide layer and the emitter metal layer is used to achieve the purpose of repelling electrons, so that the electrons flowing out of the N-type source region can only be recombined with the holes injected from the P-type collector region to the N-type buffer layer and the N-type drift layer under the condition that the first polysilicon layer applies a positive bias voltage, and the negative resistance phenomenon generated when the semiconductor device works is avoided.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a reverse-conducting lateral insulated gate bipolar transistor and its fabrication method and chip. Background Technology

[0002] A reverse-conducting insulated-gate bipolar transistor (RC-IGBT) is a semiconductor device that integrates a fast recovery diode (FRD) within an insulated-gate bipolar transistor (IGBT). An IGBT is a composite device combining a voltage-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor (BJT), possessing the main advantages of both: low on-state voltage, fast switching speed, and simple control circuitry. It is widely used in white goods, industrial frequency conversion, and new energy fields.

[0003] As power devices, vertically oriented IGBTs are commonly found in high-voltage, high-current applications, either discretely or in simple integrated forms. However, they occupy a large area in smart power integrated circuits, and their manufacturing processes are difficult to integrate with those of other devices in the circuit. Laterally insulated-gate bipolar transistors (LIGBTs), on the other hand, offer advantages such as good insulation, low parasitic capacitance, low leakage current, and high integration density, making them the most widely used IGBT structure in the field of power integrated circuits.

[0004] However, LIGBTs are equivalent to two back-to-back diodes in reverse conduction and do not possess reverse conduction capability. Later, fast recovery diodes (FRDs) were integrated into RC-LIGBTs. An electron-collecting region (N-Collector) replaces the hole-collecting region (P-Collector) in the collector section, allowing electrons to be injected into the drift region from the N-Collector during reverse conduction, thus enabling reverse conduction. In traditional RC-IGBTs, under low current conditions during forward conduction, electrons injected into the drift region from the channel flow directly out of the N+ collector region, preventing the collector junction from turning on; this is the unipolar conduction mode of a MOSFET. When the electron current increases to a certain value, the collector junction turns on, and holes are injected from the hole-collector region into the drift region, creating a conductivity modulation effect. The voltage (VCE) between the collector and emitter drops rapidly, resulting in a negative resistance phenomenon in the current-voltage curve. This is more pronounced at low temperatures, and in severe cases, it can prevent the device from turning on properly, affecting the stability of the power electronic system. Meanwhile, RC-LIGBT still suffers from problems such as poor FRD reverse recovery and high losses. Summary of the Invention

[0005] The purpose of this application is to provide a reverse-conducting lateral insulated gate bipolar transistor and its fabrication method and chip, which aims to solve the problem that the traditional RC-IGBT has a negative resistance phenomenon during forward conduction, which affects the device performance.

[0006] The first aspect of this application provides a reverse-conducting lateral insulated-gate bipolar transistor, the reverse-conducting lateral insulated-gate bipolar transistor comprising:

[0007] A P-type substrate, a buried dielectric layer, and an N-type drift layer are stacked sequentially; wherein, the front side of the N-type drift layer has a first isolation trench and a second isolation trench that do not contact each other;

[0008] A first polysilicon layer and a second polysilicon layer are formed within the first isolation trench;

[0009] A first gate oxide layer is formed between the first polysilicon layer and the N-type drift layer;

[0010] A second gate oxide layer is formed between the second polysilicon layer and the N-type drift layer;

[0011] A third gate oxide layer is used to isolate the first polysilicon layer and the second polysilicon layer, and the third gate oxide layer is in contact with the N-type drift layer;

[0012] A P-type base layer is disposed on the N-type drift layer and is in contact with the first gate oxide layer;

[0013] A P-type ohmic contact region and an N-type source region are disposed on the P-type substrate, and the N-type source region is disposed between the first gate oxide layer and the P-type ohmic contact region.

[0014] A silicon oxide isolation layer is formed within the second isolation trench;

[0015] An electron blocking layer, a first N-type buffer layer, and an N-type collector region are sequentially stacked on the first side of the silicon oxide isolation layer, and all of them are in contact with the silicon oxide isolation layer.

[0016] A second N-type buffer layer and a P-type current collector region are sequentially stacked on the second side of the silicon oxide isolation layer, with the second side opposite to the first side.

[0017] An isolation oxide layer covers the first polysilicon, the third gate oxide layer, and the first gate oxide layer, and also covers a portion of the second polysilicon.

[0018] A horizontal gate oxide layer, a polysilicon field plate, and a dielectric oxide layer are stacked sequentially, wherein the horizontal gate oxide layer is formed on the surface of the N-type drift layer between the first isolation trench and the second isolation trench;

[0019] An emitter metal layer is formed on the P-type ohmic contact region, the N-type source region, the isolation oxide layer, and the dielectric oxide layer, and is in contact with the second polysilicon layer;

[0020] A collector metal layer is formed on the silicon oxide isolation layer and is in contact with the N-type collector region and the P-type collector region.

[0021] In one embodiment, the depth of the first isolation groove is greater than the depth of the second isolation groove.

[0022] In one embodiment, the first isolation groove is a U-shaped groove structure.

[0023] In one embodiment, the width of the first isolation groove gradually decreases from the opening to the bottom.

[0024] In one embodiment, the thickness of the electron blocking layer is 0.2 μm to 0.6 μm.

[0025] In one embodiment, the first gate oxide layer and the second gate oxide layer have an arc-shaped structure, and the bottom of the first gate oxide layer is in contact with the bottom of the second gate oxide layer.

[0026] In one embodiment, the width ratio of the first polysilicon layer to the width ratio of the second polysilicon layer is 2:3.

[0027] In one embodiment, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0028] A second aspect of this application also provides a method for fabricating a reverse-conducting lateral insulated-gate bipolar transistor, comprising:

[0029] A dielectric buried layer and an N-type drift layer are sequentially formed on a P-type substrate;

[0030] P-type impurities are injected into a predetermined area on the front side of the N-type drift layer to form an electron blocking layer, and N-type material is further epitaxially formed to form the N-type drift layer encapsulating the electron blocking layer.

[0031] An N-type impurity is injected into the electron blocking layer to form an N-type buffer layer, and a first isolation trench is formed on the left side of the N-type drift layer 130, and a second isolation trench is formed on the right side of the N-type drift layer, so as to divide the buffer layer into a first N-type buffer layer and a second N-type buffer layer; wherein, the first N-type buffer layer is located on the electron blocking layer;

[0032] An oxide layer is formed on the surface of the N-type drift layer, the first isolation trench, the second isolation trench, the first N-type buffer layer, the second N-type buffer layer, and the electron blocking layer. A first gate oxide layer, a second gate oxide layer, and a third gate oxide layer are formed in the first isolation trench by filling and etching silicon oxide material in the first isolation trench and the second isolation trench. A silicon oxide isolation layer is formed in the second isolation trench.

[0033] After depositing polysilicon material, an etching process is performed to form a first polysilicon layer and a second polysilicon layer in the first isolation trench, and a polysilicon field plate is formed on the horizontal gate oxide layer between the first isolation trench and the second isolation trench.

[0034] A P-type base layer, a P-type ohmic contact region, and an N-type source region are formed on the left side of the first isolation trench; an N-type collector region is formed on the left side of the second isolation trench; and a P-type collector region is formed on the right side of the second isolation trench.

[0035] A silicon oxide isolation layer is formed on the polysilicon field plate, and an emitter metal layer is formed on the P-type ohmic contact region, the N-type source region, the isolation oxide layer, and the dielectric oxide layer. A collector metal layer is formed on the silicon oxide isolation layer. The emitter metal layer is in contact with the second polysilicon layer, and the collector metal layer is in contact with the N-type collector region and the P-type collector region.

[0036] A third aspect of this application also provides a chip, the chip comprising a reverse-conducting lateral insulated-gate bipolar transistor as described in any of the preceding claims; or the chip comprising a reverse-conducting lateral insulated-gate bipolar transistor prepared by any of the preceding claims.

[0037] The beneficial effects of the embodiments of this application are as follows: by setting the first polysilicon layer and the second polysilicon layer to minimize the area of ​​the LIGBT trench polysilicon, the Miller capacitance and switching losses are reduced. Furthermore, the second polysilicon layer is used to form an independent channel diode to achieve freewheeling and improve the reverse recovery characteristics of the device. The unique structure formed by the electron blocking layer, the horizontal polysilicon field plate, the dielectric oxide layer and the emitter metal layer achieves the purpose of repelling electrons. This ensures that when a positive bias voltage is applied to the first polysilicon layer, electrons flowing out from the N-type source region can only recombine with holes injected into the N-type buffer layer and the N-type drift layer from the P-type collector region, thus avoiding the negative resistance phenomenon generated when the semiconductor device is working. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a reverse-conducting lateral insulated gate bipolar transistor provided in an embodiment of this application;

[0039] Figure 2 This is a schematic flowchart illustrating a method for fabricating a reverse-conducting lateral insulated gate bipolar transistor according to an embodiment of this application.

[0040] Figure 3 This is a schematic diagram of the embedded medium 120 provided in the embodiments of this application.

[0041] Figure 4 This is a schematic diagram of the formation of the N-type drift layer 130 and the electron blocking layer 421 provided in the embodiments of this application.

[0042] Figure 5 This is a schematic diagram of the N-type drift layer 130 after further epitaxial growth according to an embodiment of this application.

[0043] Figure 6 This is a schematic diagram of the formation of the buffer layer 430 provided in the embodiments of this application.

[0044] Figure 7 This is a schematic diagram of the formation of the first isolation groove 101 provided in an embodiment of this application.

[0045] Figure 8 This is a schematic diagram of the formation of the second isolation groove 102 provided in an embodiment of this application.

[0046] Figure 9 This is a schematic diagram of the formation of oxide layer 103 provided in the embodiments of this application.

[0047] Figure 10 This is a schematic diagram of the formation of the third gate oxide layer 313 and the silicon oxide isolation layer 410 provided in the embodiments of this application.

[0048] Figure 11This is a schematic diagram of the formation of the first polysilicon layer 211, the second polysilicon layer 212, and the polysilicon field plate 241 provided in the embodiments of this application.

[0049] Figure 12 This is a schematic diagram of the formation of the N-type source region 231 and the N-type collector region 441 provided in the embodiments of this application.

[0050] Figure 13 This is a schematic diagram of the formation of the P-type ohmic contact region 222 and the P-type collector region 442 provided in the embodiments of this application.

[0051] Figure 14 This is a schematic diagram of the formation of the isolation oxide layer 321 and the dielectric oxide layer 341 provided in the embodiments of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0054] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0056] In reverse conduction, a LIGBT is equivalent to two back-to-back diodes and does not possess reverse conduction capability. Later, fast recovery diodes were integrated into RC-LIGBTs. An electron-collecting region (N-Collector) replaced the hole-collecting region (P-Collector) in the collector section, allowing electrons to be injected into the drift region from the N-Collector during reverse conduction, thus enabling reverse conduction. However, in traditional reverse-conducting lateral insulated-gate bipolar transistors (LCBs), under low current conditions during forward conduction, electrons injected into the drift region from the channel flow directly out of the N+ collector region, preventing the collector junction from turning on; this is the MOSFET unipolar conduction mode. When the electron current increases to a certain value, the collector junction turns on, and holes are injected into the drift region from the P+ collector region, creating a conductance modulation effect. VCE drops rapidly, resulting in a negative resistance (snapback) phenomenon in the current-voltage curve. This is more pronounced at low temperatures, and in severe cases, it can prevent the device from turning on properly, affecting the stability of the power electronic system. Meanwhile, RC-LIGBTs still suffer from poor reverse recovery (FRD) and high losses.

[0057] To address the aforementioned technical problems, embodiments of this application provide a reverse-conducting lateral insulated-gate bipolar transistor, see [link to relevant documentation]. Figure 1 As shown, the reverse-conducting lateral insulated gate bipolar transistor in this embodiment includes: a P-type substrate 110, a buried dielectric layer 120, an N-type drift layer 130, a first polysilicon layer 211, a second polysilicon layer 212, a first gate oxide layer 311, a second gate oxide layer 312, a third gate oxide layer 313, a P-type base layer 221, a P-type ohmic contact region 222, an N-type source region 231, a silicon oxide isolation layer 410, an electron blocking layer 421, a first N-type buffer layer 431, an N-type collector region 441, a second N-type buffer layer 432, a P-type collector region 442, an isolation oxide layer 321, a horizontal gate oxide layer 331, a polysilicon field plate 241, a dielectric oxide layer 341, an emitter metal layer 510, and a collector metal layer 520. A P-type substrate 110, a buried dielectric layer 120, and an N-type drift layer 130 are stacked sequentially. A first isolation trench and a second isolation trench, which are not in contact with each other, are formed on the front side of the N-type drift layer 130. A first polysilicon layer 211 and a second polysilicon layer 212 are formed within the first isolation trench. A first gate oxide layer 311 is formed between the first polysilicon layer 211 and the N-type drift layer 130; a second gate oxide layer 312 is formed between the second polysilicon layer 212 and the N-type drift layer 130; and a third gate oxide layer 313 is used to isolate the first polysilicon layer 211 and the second polysilicon layer 212, and the third gate oxide layer 313 is in contact with the N-type drift layer 130.

[0058] See Figure 1As shown, a P-type substrate 221 is disposed on an N-type drift layer 130 and is in contact with the first gate oxide layer 311; a P-type ohmic contact region 222 and an N-type source region 231 are disposed on the P-type substrate 221, with the N-type source region 231 located between the first gate oxide layer 311 and the P-type ohmic contact region 222. A silicon oxide isolation layer 410 is formed within a second isolation trench; an electron blocking layer 421, a first N-type buffer layer 431, and an N-type collector region 441 are sequentially stacked on the first side of the silicon oxide isolation layer 410 and are all in contact with the silicon oxide isolation layer 410. The first side of the silicon oxide isolation layer 410 is the side closest to the second isolation trench, and a second N-type buffer layer 432 and a P-type collector region 442 are sequentially stacked on the second side of the silicon oxide isolation layer 410, with the second side opposite to the first side. An isolation oxide layer 321 covers the first polysilicon 211, the third gate oxide layer 313, and a portion of the second polysilicon 212. A horizontal gate oxide layer 331, a polysilicon field plate 241, and a dielectric oxide layer 341 are sequentially stacked. The horizontal gate oxide layer 331 is formed on the surface of the N-type drift layer 130 between the first and second isolation trenches. An emitter metal layer 510 is formed on the P-type ohmic contact region 222, the N-type source region 231, the isolation oxide layer 321, and the dielectric oxide layer 341, and is in contact with the second polysilicon layer 212. A collector metal layer 520 is formed on the silicon oxide isolation layer 410 and is in contact with the N-type collector region 441 and the P-type collector region 442.

[0059] In this embodiment, the first isolation trench is divided into left and right parts by the third gate oxide layer 313, forming a first polysilicon layer 211 and a second polysilicon layer 212 respectively. The first polysilicon layer 211 can serve as the polysilicon gate of the LIGBT, and the second polysilicon layer 212 can serve as the polysilicon of the channel diode. This can minimize the area of ​​polysilicon in the LIGBT trench, thereby minimizing Miller capacitance, improving switching losses, and improving the reverse recovery characteristics of the RC-IGBT by utilizing the independent channel diode for freewheeling. By utilizing the structure composed of electron blocking layer 421, horizontal gate oxide layer 331, polysilicon field plate 241, and emitter metal layer 510, electrons are repelled, preventing electrons flowing out of N-type source region 231 from flowing out of N-type collector region 441 and collector metal layer 520 through the channel formed in P-type base layer 221 by applying a positive bias voltage to the first polysilicon layer 211, and then through N-type drift layer 130 and first N-type buffer layer 431. This ensures that electrons flowing out of N-type source region 231 can only recombine with holes injected into the first N-type buffer layer 431, second N-type buffer layer 432, and N-type drift layer 130 through P-type collector region 442, thus completely eliminating the negative resistance phenomenon.

[0060] When the first polysilicon layer 211 is forward biased and the collector metal layer 520 is connected to the bus voltage, the emitter metal layer 510 is connected to a low potential. Because the polysilicon field plate 241 and the emitter metal layer 510 are partially connected, and the emitter metal layer 510 acts as a metal field plate above the polysilicon field plate 241, the entire polysilicon field plate 241 is at a low potential. This repels electrons and attracts holes, and together with the electron blocking layer 421, completely blocks the path of electrons to the N-type collector region 441. When the LIGBT reverses and recovers, the emitter metal layer 510 is connected to a high voltage, so the polysilicon field plate 241 is also connected to a high voltage. This repels holes and attracts electrons to form an electron accumulation layer, thus turning on the channel diode. The current flows through the emitter metal layer 510, the second polysilicon layer 212, the second gate oxide layer 312, the N-type drift layer 130, the electron accumulation layer under the polysilicon field plate 241, the depletion layer at the edge of the polysilicon field plate 241, the first N-type buffer layer 431, the N-type collector region 441, and the collector metal layer 520, achieving a lower forward voltage (VF).

[0061] In one embodiment, the depth of the second isolation groove is less than the depth of the first isolation groove.

[0062] In one embodiment, a first gate oxide layer 311 and a second gate oxide layer 312 are formed on the inner wall of a first isolation trench, with the first gate oxide layer 311 attached to the left inner wall of the first isolation trench and the second gate oxide layer 312 attached to the right inner wall of the first isolation trench.

[0063] In one embodiment, the first isolation groove is a U-shaped groove structure.

[0064] In one embodiment, the width of the first isolation groove gradually decreases from the opening to the bottom. For example... Figure 1 As shown, the width of the first isolation groove gradually decreases from top to bottom, and the left and right walls of the first isolation groove are arc-shaped structures with respect to its bottom.

[0065] In one embodiment, such as Figure 1 As shown, the first gate oxide layer 311 has an arc-shaped structure, the second gate oxide layer 312 has an arc-shaped structure, and the bottoms of the first gate oxide layer 311 and the second gate oxide layer 312 are in contact. This can prevent charge accumulation caused by the bottom tip of the first isolation trench, and can also minimize the area of ​​the LIGBT trench polysilicon, thereby minimizing Miller capacitance and improving the switching loss of the device.

[0066] In one embodiment, the P-type substrate 110 is P-type doped, and the doping element can be boron. The doping concentration of the P-type substrate 110 is 1 to 9 × 10⁻⁶. 14 cm -3 .

[0067] In one embodiment, the thickness of the P-type substrate 110 is 300um to 500um.

[0068] In one embodiment, the dielectric layer 120 can be a buried oxide layer resist.

[0069] In one embodiment, an electron blocking layer 421 can be fabricated by implanting phosphorus ion impurities into a specific region on the right side of the N-type drift layer 130. In this embodiment, the doping concentration of the electron blocking layer 421 is 2 to 9 × 10⁻⁶. 18 cm -3 .

[0070] In one embodiment, the thickness of the electron blocking layer 421 is 0.2 μm to 0.6 μm.

[0071] In one embodiment, the first polysilicon layer 211 can serve as a LIGBT polysilicon gate, and the second polysilicon layer 212 can serve as a channel diode polysilicon.

[0072] In this embodiment, both the first polysilicon layer 211 and the second polysilicon layer 212 are P-doped N-type polysilicon, and their doping concentration can be 1 to 9*10⁻⁶. 19 cm -3 .

[0073] In one embodiment, the width of the first isolation groove is 6µm to 12µm.

[0074] In one embodiment, the width of the first polysilicon layer 211 is 2µm to 4µm, occupying half of the first isolation trench.

[0075] In one embodiment, the width of the third gate oxide layer 313 is 0.5 μm to 2 μm.

[0076] In one embodiment, the width ratio of the first polysilicon layer 211 to the width ratio of the second polysilicon layer 212 is 2:3, so that the ratio of the area of ​​the LIGBT to the area of ​​the channel diode is approximately 2:3, which can minimize the Miller capacitance.

[0077] In one embodiment, the width of the channel diode is the same as the width of the second polysilicon layer 212, which has a width of 3µm to 6µm.

[0078] In one embodiment, the thickness of the second gate oxide layer 312 is less than the thickness of the first gate oxide layer 311.

[0079] In one embodiment, the thickness of the first gate oxide layer 311 is approximately 100 nm to 120 nm.

[0080] In one embodiment, the thickness of the second gate oxide layer 312 is approximately 60 nm to 80 nm.

[0081] In one embodiment, the P-type substrate 221 is P-type doped, for example, its doping element is boron, and the doping concentration is 2 to 5 × 10⁻⁶. 17 cm -3 .

[0082] In one embodiment, in the direction from the P-type substrate 110 to the N-type drift layer 130, the bottom of the P-type base layer 221 is higher than the bottom of the first isolation trench. For example, the bottom of the P-type base layer 221 is higher than the arc-shaped structure between the left inner wall and the bottom of the first isolation trench.

[0083] In one embodiment, the thickness of the P-type base layer 221 is 1µm to 3µm.

[0084] In one embodiment, a P-type ohmic contact region 222 and an N-type source region 231 are formed side-by-side on a P-type substrate 221. The N-type source region 231 is N-type doped, and the doping element is phosphorus or arsenic, with a doping concentration of 1 to 9 × 10⁻⁶. 19 cm -3 .

[0085] In one embodiment, the upper surfaces of the P-type ohmic contact region 222 and the N-type source region 231 are flush with the top of the first gate oxide layer 311 and with the plane where the bottom of the isolation oxide layer 321 is located.

[0086] In one embodiment, see Figure 1 As shown, the isolation oxide layer 321 is used to isolate the first polysilicon layer 211 and the emitter metal layer 510. The first polysilicon layer 211 fills the cavity formed by the first gate oxide layer 311, the third gate oxide layer 313, and the isolation oxide layer 321. The second polysilicon layer 212, the P-type ohmic contact region 222, and the N-type source region 231 are all in contact with the emitter metal layer 510.

[0087] In one embodiment, the thickness of the N-type source region 231 is 0.3 μm to 1 μm.

[0088] In one embodiment, the doping concentration of the P-type ohmic contact region 222 is greater than the doping concentration of the P-type substrate 221. For example, the P-type ohmic contact region 222 is heavily P-type doped, and the doping concentration of the P-type ohmic contact region 222 is at least 100 times the doping concentration of the P-type substrate 221.

[0089] In one embodiment, the doping element of the P-type ohmic contact region 222 is boron, and the doping concentration is 1 to 9 × 10⁻⁶. 19 cm -3 .

[0090] In one embodiment, the thickness of the N-type source region 231 is the same as the thickness of the P-type ohmic contact region 222.

[0091] In one embodiment, the thickness of the P-type ohmic contact region 222 is 0.3µm to 1µm.

[0092] In one embodiment, the electron blocking layer 421 is p-type doped, the doping element of the electron blocking layer 421 is boron, and the doping concentration of the electron blocking layer 421 is 2 to 9 × 10⁻⁶. 18 cm -3 .

[0093] In one embodiment, the thickness of the electron blocking layer 421 is 0.2 μm to 0.6 μm.

[0094] In one embodiment, the N-type collector region 441 is N-type doped, and the doping element is phosphorus or arsenic, with a doping concentration of 1 to 9 × 10⁻⁶. 19 cm -3 .

[0095] In one embodiment, the doping element of the P-type collector region 442 is boron, and its doping concentration is 1 to 9 × 10⁻⁶. 19 cm -3 .

[0096] In one embodiment, the thickness of the P-type collector region 442 is the same as the thickness of the N-type collector region 441.

[0097] In one embodiment, the thickness of the P-type collector region 442 is 0.3µm to 1µm.

[0098] In one embodiment, the dielectric oxide layer 341 is a SiO2 material containing phosphorus, boron, or both, and the thickness of the dielectric oxide layer 341 is 0.5 μm to 1.5 μm.

[0099] In one embodiment, the emitter metal layer 510 and the collector metal layer 520 can be Al / Ti / Ni / Ag multilayer metal electrode materials, which facilitates the formation of ohmic contacts.

[0100] In this embodiment, the emitter metal layer 510 is also in contact with the P-type ohmic contact region 222, the N-type source region 231, the second polysilicon layer 212, and the N-type drift layer 130.

[0101] In one specific application embodiment, a Ni / Ti / Ni / Ag multilayer metal is deposited on the front side of the device and etched to form an emitter metal layer 510 and a collector metal layer 520.

[0102] In one embodiment, the emitter metal layer 510 can be an aluminum / titanium / nickel / silver multilayer metal material to facilitate the formation of an ohmic contact with the P-type ohmic contact region 222 and the N-type source region 231.

[0103] In one embodiment, the collector metal layer 520 may be an aluminum / titanium / nickel / silver multilayer metal material to facilitate the formation of an ohmic contact with the P-type collector region 442 and the N-type collector region 441.

[0104] This application also provides a method for fabricating a reverse-conducting lateral insulated-gate bipolar transistor, see [link to relevant documentation]. Figure 2 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0105] In step S100, as Figure 3 and Figure 4 As shown, a dielectric buried layer 120 and an N-type drift layer 130 are sequentially formed on a P-type substrate 110.

[0106] In one embodiment, the P-type substrate 110 is P-type doped, and the doping element can be boron. The doping concentration of the P-type substrate 110 is 1 to 9 × 10⁻⁶. 14 cm -3 .

[0107] In one embodiment, the thickness of the P-type substrate 110 is 300um to 500um.

[0108] In one embodiment, the dielectric buried layer 120 can be a buried oxide layer or a resist layer.

[0109] In step S200, P-type impurities are injected into a predetermined area on the front side of the N-type drift layer 130 to form an electron blocking layer 421, and N-type material is further epitaxially formed to form an N-type drift layer 130 that encapsulates the electron blocking layer 421.

[0110] See Figure 4 As shown, an electron blocking layer 421 is fabricated in a specific region on the right side of the surface of the N-type drift layer 130 by implanting phosphorus ion impurities. The doping concentration of the fabricated electron blocking layer 421 is 2 to 9 × 10⁻⁶. 18 cm -3 .

[0111] In one embodiment, the thickness of the electron blocking layer 421 is 0.2 μm to 0.6 μm.

[0112] See Figure 5 As shown, based on the fabrication of the electron blocking layer 421, an N-type material is epitaxially grown to form an N-type drift layer 130 encapsulating the electron blocking layer 421. The thickness of the N-type material grown epitaxially again is 5 μm to 10 μm, and the doping concentration is 5 to 9 × 10⁻⁶.14 cm -3 .

[0113] In step S300, an N-type impurity is injected into the electron blocking layer 421 to form an N-type buffer layer 430, and a first isolation trench 101 is formed on the left side of the N-type drift layer 130, and a second isolation trench 102 is formed in the region of the N-type buffer layer 430 to divide the buffer layer 430 into a first N-type buffer layer 431 and a second N-type buffer layer 432; wherein the first N-type buffer layer 431 is located on the electron blocking layer 421.

[0114] See Figure 6 As shown, using photoresist as a barrier layer, N-type impurities are implanted into a designated area on the surface of the N-type drift layer 130 and then annealed to form a buffer layer 430. The doping concentration of the buffer layer 430 is 1 to 9 × 10⁻⁶. 17 cm -3 The thickness is 2um to 4um.

[0115] See Figure 7 and Figure 8 As shown, the surface of the N-type drift layer 130 is etched by inductively coupled plasma dry etching in a specific area, reaching deep into the N-type drift layer 130, forming a first isolation trench with a cross-sectional area of ​​U. The depth of the first isolation trench is 3um to 4um, and the width of the first isolation trench 101 is 6um to 12um.

[0116] See Figure 8 As shown, a second isolation trench 102 is formed on the surface of the buffer layer 430 by plasma dry etching in a region defined at the right end of the surface of the N-type drift layer 130. The depth of the second isolation trench 102 is 2um to 3um, and the width of the second isolation trench is 1um to 2um.

[0117] See Figure 8 As shown, the second isolation trench 102 extends to the bottom of the electron blocking layer 421, and the depth of the second isolation trench 102 is greater than the sum of the thicknesses of the buffer layer 430 and the electron blocking layer 421.

[0118] In step S400, an oxide layer 103 is formed on the surface of the N-type drift layer 130, the first isolation trench 101, the second isolation trench 102, the first N-type buffer layer 431, the second N-type buffer layer 432, and the electron blocking layer 421. By filling and etching silicon oxide material in the first isolation trench 101 and the second isolation trench 102, a first gate oxide layer 311, a second gate oxide layer 312, and a third gate oxide layer 313 are formed in the first isolation trench 101, and a silicon oxide isolation layer 410 is formed in the second isolation trench 102.

[0119] See Figure 9 As shown, in a dry oxygen environment, Figure 8The silicon wafer surface is oxidized in a dry oxygen environment at a temperature of 1100℃ for 2 hours, thereby forming an oxide layer 103 on the surface of the N-type drift layer 130, the first isolation trench 101, the second isolation trench 102, the first N-type buffer layer 431, the second N-type buffer layer 432, and the electron blocking layer 421. The thickness of the oxide layer 103 is 80nm to 120nm.

[0120] See Figure 10 As shown, based on the oxide layer 103 formed above, SiO2 material is deposited and filled in the first isolation trench 101 and the second isolation trench 102, and SiO2 is etched at the position where polysilicon material needs to be deposited to reserve the polysilicon position, forming the third gate oxide layer 313. Using photoresist as a mask, the oxide layer on the left and right inner walls of the first isolation trench is etched to make its thickness thinner, forming the first gate oxide layer 311 and the second gate oxide layer 312.

[0121] In one embodiment, the thickness of the second gate oxide layer 312 is 60 nm to 80 nm.

[0122] See Figure 10 As shown, a silicon oxide isolation layer 410 is formed by depositing and filling SiO2 material in the second isolation trench 102.

[0123] In step S500, after depositing polysilicon material, an etching process is performed to form a first polysilicon layer 211 and a second polysilicon layer 212 in the first isolation trench, and a polysilicon field plate 241 is formed on the horizontal gate oxide layer 331 between the first isolation trench and the second isolation trench.

[0124] See Figure 11 As shown, polysilicon material is deposited inside the first isolation trench and on the surface of the horizontal gate oxide layer 331. The polysilicon material can be N-type doped, for example, the doping element is phosphorus, and the doping concentration is 1 to 10*10. 19 cm -3 .

[0125] A photoresist is used as a mask on the surface of polysilicon to etch the polysilicon material to form a first polysilicon layer 211 and a second polysilicon layer 212.

[0126] In step S600, a P-type base layer 221, a P-type ohmic contact region 222, and an N-type source region 231 are formed on the left side of the first isolation trench, an N-type collector region 441 is formed on the left side of the second isolation trench, and a P-type collector region 442 is formed on the right side of the second isolation trench.

[0127] See Figure 12 As shown, a P-type base layer 221 is fabricated on the left side of the N-type drift layer 130 on the silicon wafer surface by implanting phosphorus ion impurities and annealing, using photoresist as a barrier layer.

[0128] The doping concentration of the fabricated P-type substrate 221 is 1–9 × 10⁻⁶. 13 cm -3 The depth of boron ion impurity implantation is 2µm to 3µm. Using photoresist as a barrier layer, N-type impurities are implanted on the silicon wafer surface on the left side of the first isolation trench to form an N-type source region 231, and N-type impurities are implanted on the left side of the second isolation trench to form an N-type collector region 441.

[0129] In one embodiment, the doping concentration of the N-type source region 231 and the N-type collector region 441 is 1 to 9 × 10⁻⁶. 19 cm -3 The width of the N-type source region 231 and the N-type collector region 441 is approximately 1µm to 2µm, and the depth of the N-type source region 231 and the N-type collector region 441 is approximately 0.2µm to 0.3µm.

[0130] See Figure 13 As shown, P-type ohmic contact region 222 and P-type collector region 442 are fabricated by ion implantation of P-type impurities and annealing, using photoresist as a barrier layer.

[0131] In one embodiment, the doping concentration of the P-type ohmic contact region 222 and the P-type collector region 442 is 1 to 9 × 10⁻⁶. 19 cm -3 The width of the P-type ohmic contact region 222 and the P-type collector region 442 is approximately 1µm to 2µm, and the depth of the P-type ohmic contact region 222 and the P-type collector region 442 is approximately 0.2µm to 0.3µm.

[0132] In step S700, a dielectric oxide layer 341 is formed on the polysilicon field plate 241, and an emitter metal layer 510 is formed on the P-type ohmic contact region 222, the N-type source region 231, the isolation oxide layer 321, and the dielectric oxide layer 341. A collector metal layer 520 is formed on the silicon oxide isolation layer 410. The emitter metal layer 510 is in contact with the second polysilicon layer 212, and the collector metal layer 520 is in contact with the N-type collector region 441 and the P-type collector region 442.

[0133] See Figure 14 As shown, SiO2 material is deposited on the upper surfaces of the P-type ohmic contact region 222, the N-type source region 231, the first isolation trench, and the first gate oxide layer 311. Photoresist is used as a mask to etch the SiO2 material to expose the N-type source region 231, part of the P-type ohmic contact region 222, and part of the second polysilicon layer 212, forming an isolation oxide layer 321 and a dielectric oxide layer 341.

[0134] See Figure 1 As shown, a Ni / Ti / Ni / Ag multilayer metal is deposited on the front side of the device, and the multilayer metal is etched to form an emitter metal layer 510 and a collector metal layer 520.

[0135] This application also provides a chip. In one embodiment, the chip includes a reverse-conducting lateral insulated-gate bipolar transistor as described in any of the above embodiments. In another embodiment, the chip may further include a reverse-conducting lateral insulated-gate bipolar transistor prepared by any of the above methods.

[0136] In this embodiment, the chip includes a chip substrate, on which one or more reverse-conducting lateral insulated-gate bipolar transistors are disposed. The reverse-conducting lateral insulated-gate bipolar transistors can be fabricated by the fabrication method in any of the above embodiments, or the reverse-conducting lateral insulated-gate bipolar transistors in any of the above embodiments can be disposed on the chip substrate.

[0137] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the reverse-conducting lateral insulated gate bipolar transistor.

[0138] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0139] This application provides a reverse-conducting lateral insulated gate bipolar transistor and its fabrication method. In the chip, by setting a first polysilicon layer and a second polysilicon layer, the area of ​​the LIGBT trench polysilicon is minimized as much as possible, thereby reducing Miller capacitance and switching losses. Furthermore, the second polysilicon layer is used to form an independent channel diode to achieve freewheeling, improving the reverse recovery characteristics of the device. The unique structure formed by the electron blocking layer, the horizontal polysilicon field plate, the dielectric oxide layer, and the emitter metal layer achieves the purpose of repelling electrons. This ensures that when a positive bias voltage is applied to the first polysilicon layer, electrons flowing out from the N-type source region can only recombine with holes injected into the N-type buffer layer and the N-type drift layer from the P-type collector region, thus avoiding the negative resistance phenomenon generated during the operation of the semiconductor device.

[0140] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above-described functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0141] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0142] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A reverse-conducting lateral insulated-gate bipolar transistor, characterized in that, The reverse-conducting lateral insulated-gate bipolar transistor includes: A P-type substrate, a buried dielectric layer, and an N-type drift layer are stacked sequentially; wherein, the front side of the N-type drift layer has a first isolation trench and a second isolation trench that do not contact each other; A first polysilicon layer and a second polysilicon layer are formed within the first isolation trench; A first gate oxide layer is formed between the first polysilicon layer and the N-type drift layer; A second gate oxide layer is formed between the second polysilicon layer and the N-type drift layer; A third gate oxide layer is used to isolate the first polysilicon layer and the second polysilicon layer, and the third gate oxide layer is in contact with the N-type drift layer; A P-type base layer is disposed on the N-type drift layer and is in contact with the first gate oxide layer; A P-type ohmic contact region and an N-type source region are disposed on the P-type substrate, and the N-type source region is disposed between the first gate oxide layer and the P-type ohmic contact region. A silicon oxide isolation layer is formed within the second isolation trench; An electron blocking layer, a first N-type buffer layer, and an N-type collector region are sequentially stacked on the first side of the silicon oxide isolation layer, and all of them are in contact with the silicon oxide isolation layer. A second N-type buffer layer and a P-type current collector region are sequentially stacked on the second side of the silicon oxide isolation layer, with the second side opposite to the first side. An isolation oxide layer covers the first polysilicon, the third gate oxide layer, and the first gate oxide layer, and also covers a portion of the second polysilicon. A horizontal gate oxide layer, a polysilicon field plate, and a dielectric oxide layer are stacked sequentially, wherein the horizontal gate oxide layer is formed on the surface of the N-type drift layer between the first isolation trench and the second isolation trench; An emitter metal layer is formed on the P-type ohmic contact region, the N-type source region, the isolation oxide layer, and the dielectric oxide layer, and is in contact with the second polysilicon layer; A collector metal layer is formed on the silicon oxide isolation layer and is in contact with the N-type collector region and the P-type collector region.

2. The reverse-conducting lateral insulated-gate bipolar transistor as described in claim 1, characterized in that, The depth of the first isolation groove is greater than the depth of the second isolation groove.

3. The reverse-conducting lateral insulated-gate bipolar transistor as described in claim 2, characterized in that, The first isolation groove is a U-shaped groove structure.

4. The reverse-conducting lateral insulated-gate bipolar transistor as described in claim 2, characterized in that, The width of the first isolation groove gradually decreases from the opening to the bottom.

5. The reverse-conducting lateral insulated-gate bipolar transistor as described in any one of claims 1-4, characterized in that, The thickness of the electron blocking layer is 0.2µm to 0.6µm.

6. The reverse-conducting lateral insulated-gate bipolar transistor as described in claim 1, characterized in that, The first gate oxide layer and the second gate oxide layer have an arc-shaped structure, and the bottom of the first gate oxide layer is in contact with the bottom of the second gate oxide layer.

7. The reverse-conducting lateral insulated-gate bipolar transistor as described in claim 6, characterized in that, The width ratio of the first polysilicon layer to the width ratio of the second polysilicon layer is 2:

3.

8. The reverse-conducting lateral insulated-gate bipolar transistor as described in any one of claims 1-4, characterized in that, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

9. A method for fabricating a reverse-conducting lateral insulated-gate bipolar transistor, characterized in that, include: A dielectric buried layer and an N-type drift layer are sequentially formed on a P-type substrate; P-type impurities are injected into a predetermined area on the front side of the N-type drift layer to form an electron blocking layer, and N-type material is further epitaxially formed to form the N-type drift layer encapsulating the electron blocking layer. An N-type impurity is implanted into the electron blocking layer to form an N-type buffer layer, and a first isolation trench is formed on the left side of the N-type drift layer, and a second isolation trench is formed on the right side of the N-type drift layer; wherein, the second isolation trench divides the buffer layer into a first N-type buffer layer and a second N-type buffer layer, and the first N-type buffer layer is located on the electron blocking layer; An oxide layer is formed on the surface of the N-type drift layer, the first isolation trench, the second isolation trench, the first N-type buffer layer, the second N-type buffer layer, and the electron blocking layer. A first gate oxide layer, a second gate oxide layer, and a third gate oxide layer are formed in the first isolation trench by filling and etching silicon oxide material in the first isolation trench and the second isolation trench. A silicon oxide isolation layer is formed in the second isolation trench. After depositing polysilicon material, an etching process is performed to form a first polysilicon layer and a second polysilicon layer in the first isolation trench, and a polysilicon field plate is formed on the horizontal gate oxide layer between the first isolation trench and the second isolation trench. A P-type base layer, a P-type ohmic contact region, and an N-type source region are formed on the left side of the first isolation trench; an N-type collector region is formed on the left side of the second isolation trench; and a P-type collector region is formed on the right side of the second isolation trench. A dielectric oxide layer is formed on the polysilicon field plate, and an emitter metal layer is formed on the P-type ohmic contact region, the N-type source region, and the dielectric oxide layer. A collector metal layer is formed on the silicon oxide isolation layer. The emitter metal layer is in contact with the second polysilicon layer, and an isolation oxide layer is disposed between the emitter metal layer and the first polysilicon layer. The collector metal layer is in contact with the N-type collector region and the P-type collector region.

10. A chip, characterized in that, The chip comprises a reverse-conducting lateral insulated-gate bipolar transistor as described in any one of claims 1-8; or The chip includes a reverse-conducting lateral insulated gate bipolar transistor fabricated by the method of claim 9.

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