Integrated circuit comprising a high voltage transistor and corresponding manufacturing method

Abstract

An integrated circuit includes at least one transistor including a separate gate structure and a field plate arranged on a front side of a semiconductor substrate, and a doped conductive region in the semiconductor substrate located perpendicularly to an edge of the gate structure and perpendicularly to an edge of the field plate.

Description

Technical Field

[0001] The various embodiments and implementations relate to integrated circuits, specifically high-voltage transistors. Background Technology

[0002] Some types of integrated circuits use high voltages (that is, voltages greater than 12V) for their operation, while being constrained by the size of their components. This is especially true for non-volatile memories that use high voltages for write operations. High voltages can also be used for decode operations in memory when memory cell arrays are designed based on a dense grid of high-voltage transistors.

[0003] The evolution of transistor morphology tends towards increasingly narrower transistors (without a significant reduction in length due to breakdown voltage constraints). Because of the spike effect in the doped region morphology and the increase in doping concentration, reducing the transistor width leads to a decrease in the avalanche voltage between the source-drain conductive region and the substrate, thus satisfying the scaling rules after size reduction.

[0004] Therefore, refer to Figure 1 , Figure 1 An example of a high-voltage transistor 100 comprising two stacked, non-self-aligned gate layers typically used in non-volatile memories is illustrated. The high-voltage transistor 100 includes a gate structure comprising a first gate G1 located on the surface of a semiconductor substrate PSUB and a second gate G2 covering the first gate and protruding beyond the surface of the substrate PSUB. The high-voltage transistor 100 includes a conventional drain region D and a lightly doped drain region LDD located below the protruding portion of the second gate G2. In a conventional manner known to those skilled in the art, the lightly doped drain region LDD is implanted to a depth less than that of the conductive region D, and the doping concentration is lower than that of the conductive region D, allowing for prevention of avalanche phenomena at the drain side of the conductive channel of the transistor 100.

[0005] However, as the width of the photolithography node and the high-voltage transistor 100 continues to decrease, avalanche phenomena at the exterior of the drain D may pose a problem for the high voltage used in the operating circuit. In fact, in the partition of the junction between the drain D and the substrate PSUB on the exterior side of the drain D—that is, in the partition BRD located along the lateral isolation region—the spatial variation in dopant concentration is greater than the spatial variation between the remaining volume of the substrate PSUB and the conductive region D. Furthermore, in the partition of the junction BRD on the exterior side of the drain D, the curvature of the junction morphology becomes even greater as the width of the transistor 100 decreases. The width of the transistor 100 and the channel region and drain region D are perpendicular to... Figure 1The range corresponds to the direction of the cross-section. Through an effect comparable to the peak effect, the curvature of the junction in the partitioned BRD at the end of transistor 100 helps to locally increase the electric field, thus reducing the avalanche voltage. The narrower the transistor, the greater the curvature, and the more the avalanche voltage is locally reduced. However, the development of integrated circuits tends towards transistors that are increasingly narrower (in width).

[0006] Therefore, the junction PN between the drain region D and the substrate PSUB includes a localized BRD with high dopant concentration and high curvature morphology, resulting in a smaller breakdown voltage locality in the junction.

[0007] However, if the high voltage cannot be reduced to accompany the reduction in transistor size, as is the case for operating non-volatile memory, then avalanche voltage becomes a technical obstacle to reducing the size of integrated circuit transistors.

[0008] Therefore, a solution is needed that allows for increasing the withstand voltage of high-voltage transistors (that is, increasing the avalanche voltage while reducing the size of high-voltage transistors). Summary of the Invention

[0009] According to one aspect, an integrated circuit is provided, comprising at least one transistor including a separate gate structure and a field plate disposed on the front side of a semiconductor substrate; and a doped conductive region located in the semiconductor substrate, the doped conductive region being perpendicular to the edge of the gate structure and perpendicular to the edge of the field plate.

[0010] On the one hand, the field plate can modulate the electric field present in the semiconductor substrate facing the field plate through the field effect. On the other hand, in terms of manufacturing steps, the field plate allows the definition of the lightly doped region, which is typically on the channel side of the conductive region, to be freely extended to the outside of the conductive region. Therefore, in addition to the generally improved breakdown voltage on the channel side of the transistor, the breakdown voltage at the edge of the conductive region can also be improved.

[0011] Therefore, according to one embodiment, the at least one transistor further includes a lightly doped conductive region implanted in a semiconductor substrate, the lightly doped conductive region extending from the edge of the gate structure on either side of the conductive region below the gate structure, and extending from the edge of the field plate below the field plate.

[0012] In terms of the manufacturing process steps, this allows the avalanche voltage of the transistor to be increased from 0.5V to 1V for free.

[0013] According to one embodiment, the conductive region has a first dopant concentration and extends from the front side into the substrate to a first depth, and the lightly doped conductive region has a second dopant concentration lower than the first concentration and extends from the front side into the substrate to a second depth less than the first depth.

[0014] According to one embodiment, the gate structure includes a first gate region and a second gate region. The first gate region includes a first conductive layer disposed on a first dielectric layer and located on the front side of a substrate. The second gate region includes a second conductive layer disposed on a second dielectric layer. The second gate region includes an inner portion on the first gate region and an outer portion protruding from the first gate region on the front side of the substrate. The conductive region is located perpendicularly to the edge of the outer portion of the second gate region.

[0015] According to one embodiment, the lightly doped conductive region extends below the outer portion of the second gate region.

[0016] According to one embodiment, the field plate includes a third conductive layer disposed on a third dielectric layer and located on the front side of the substrate. The third conductive layer has the same composition and the same thickness as the second conductive layer, and the third dielectric layer has the same composition and the same thickness as the second dielectric layer on the outer portion of the second gate region.

[0017] In other words, the field plate is produced using the same method steps as the second gate region, which in particular allows for the implantation of self-aligned conductive regions onto the material masking the second gate region, so as to hide such implantation under the field plate and maintain the lightly doped conductive regions under the field plate.

[0018] According to one embodiment, the field plate includes a third conductive layer disposed on a third dielectric layer and located on the front side of the substrate. The third conductive layer has the same composition and the same thickness as the first conductive layer, and the third dielectric layer has the same composition and the same thickness as the first dielectric layer.

[0019] In other words, the field plate is produced using the same method steps as the first gate region, thereby allowing, for example, the formation of a lightly doped conductive region beneath the field plate that partially penetrates the first gate region during the implantation of the conductive region.

[0020] According to one embodiment, the field plate is electrically connected to the conductive area.

[0021] This allows the transistor to benefit from field effects in the outer portion of the conductive region, which are adapted to additionally and independently of the presence of the lightly doped conductive region to increase the avalanche voltage.

[0022] According to one embodiment, the edge of the field plate opposite to the edge perpendicular to the conductive region is located above the dielectric volume of the shallow isolation trench.

[0023] Because the field plate occupies the non-active surface facing the shallow isolation trench, this is advantageous in terms of the alignment and surface coverage area of ​​the field plate formation.

[0024] According to another aspect, a method for manufacturing an integrated circuit is provided, the integrated circuit including at least forming a transistor, the forming of the transistor including: forming a separate gate structure and a field plate disposed on the front side of a semiconductor substrate; and forming a doped conductive region in the semiconductor substrate, the doped conductive region being perpendicular to the edge of the gate structure and perpendicular to the edge of the field plate.

[0025] According to one implementation, the at least one transistor forming further includes: forming a lightly doped conductive region implanted in a semiconductor substrate, the lightly doped conductive region extending below the gate structure from the edge of the gate structure and below the field plate from the edge of the field plate on either side of the conductive region.

[0026] According to one implementation, forming a conductive region includes: injecting a dopant at a first concentration and a first energy; forming a lightly doped conductive region includes: injecting a dopant at a second concentration lower than the first concentration and a second energy lower than the first energy.

[0027] According to one implementation, forming the gate structure includes:

[0028] A first dielectric layer is formed on the front side of the substrate, a first conductive layer is formed on the first dielectric layer, and the first conductive layer is etched to define a first gate region.

[0029] A second dielectric layer is formed, a second conductive layer is formed on the second dielectric layer, and the second conductive layer is etched to define a second gate region, such that the second gate region includes an inner portion on the first gate region and an outer portion protruding from the first gate region on the front side of the substrate.

[0030] Forming the conductive region includes implanting a self-aligned dopant into the second gate region.

[0031] According to one implementation, forming a lightly doped conductive region includes implanting a self-aligned dopant into the first gate region prior to the step of forming the second gate region.

[0032] According to one implementation, forming a field plate includes: forming a third dielectric layer on the front side of a substrate, forming a third conductive layer on the third dielectric layer, and etching the third conductive layer to define the field plate, while simultaneously forming a second gate region and etching the second gate region.

[0033] According to one implementation, forming a field plate includes: forming a third dielectric layer on the front side of a substrate, forming a third conductive layer on the third dielectric layer, and etching the third conductive layer to define the field plate, while simultaneously forming a first gate region and etching the first gate region; forming a lightly doped conductive region includes: implanting a dopant through the field plate during the implantation of the conductive region.

[0034] According to one implementation, the method further includes forming an electrical connection between the field plate and the conductive region.

[0035] According to one embodiment, the method includes: forming a dielectric volume of a shallow isolation trench prior to forming a field plate, wherein forming the field plate includes: defining the field plate such that an edge of the field plate opposite to the edge perpendicular to the conductive region is located above the dielectric volume of the shallow isolation trench. Attached Figure Description

[0036] Other advantages and features of this disclosure will become apparent upon review of the detailed description of the non-limiting embodiments and implementations, as well as the accompanying drawings, in which

[0037] The previously described Figure 1 The diagram illustrates a traditional high-voltage transistor;

[0038] Figure 2 The illustration shows a top view and a cross-sectional view of a transistor suitable for high voltage according to an embodiment;

[0039] Figure 3 The diagram shows... Figure 2 A partial cross-sectional view of the transistor shown;

[0040] Figure 4 The illustration shows a top view and a cross-sectional view of a transistor suitable for high voltage according to an embodiment;

[0041] Figure 5 The diagram shows... Figure 4 A partial cross-sectional view of the transistor shown;

[0042] Figure 6 The diagram shows... Figure 1 , Figure 2 and Figure 4 Measurement results of the avalanche voltage between the drain region and the substrate of the embodiment of the transistor;

[0043] Figure 7 The diagram illustrates a portion of the memory plane of an EEPROM memory; and

[0044] Figure 8 The illustrations show embodiments and implementations of this disclosure. Detailed Implementation

[0045] Figure 2The illustration shows a top view and a cross-sectional view of a first example of a transistor 200 suitable for high voltage (i.e., typically greater than 12V (volts)). The transistor 200 is fabricated in an integrated manner, for example, in a non-volatile memory integrated circuit of the type "EEPROM" (for "Electrically Erasable Programmable Read-Only Memory").

[0046] Transistor 200 includes a separate gate structure STG and a field plate FP, which are disposed on the front side FA of a semiconductor substrate PSUB. The field plate FP is structurally equivalent to a typical single-gate region of a transistor. The field plate FP is adapted to generate a field effect in the underlying semiconductor substrate (such as a conventional transistor gate), but is not intended to form a conductive channel between the two conductive regions (unlike a conventional transistor gate).

[0047] The front face (FA) of a semiconductor substrate PSUB, typically made of P-type doped silicon, is usually the side of the substrate. Components for integrated circuits are fabricated from this face in a section commonly referred to as the "FEOL" ("front-end"). The areas of the PSUB on the sides of the front face (where and on which components for integrated circuits are fabricated) typically include P-type doped wells, the same type as the substrate, and / or N-type doped wells, the opposite of the substrate. In the following text, wells are not distinguished from the substrate, and they are referred to by the term "substrate".

[0048] Lateral isolation structures (e.g., shallow trench type lateral isolation structures (shallow trench isolation (STI)) allow defining an active region ACT in a substrate PSUB, in which and facing the active region ACT, transistor 200 is fabricated. The active region ACT extends along a length in a first direction, that is, in Figure 2 The diagram extends horizontally in its orientation and is perpendicular to... Figure 2 The image extends across the width of the cutting plane and, Figure 2 The top view extends vertically in the orientation of the image. Typically, because this may involve a reduction in the length of the transistor channel, which can reduce the source-drain breakdown voltage (typically "Vds"), the length of the active region of transistor 200 is particularly constrained for reducing transistor size. Furthermore, reducing the width of the active region ACT typically reduces the avalanche voltage between the drain and the substrate. Transistor 200 is advantageously configured to limit this reduction in avalanche voltage and withstand higher voltages than conventional transistors.

[0049] Transistor 200 includes two conductive regions doped in the semiconductor substrate PSUB on either side of the gate structure STG, namely, source region S and drain region D.

[0050] On the one hand, the gate structure STG is advantageously configured to withstand high voltages, that is, specifically, at a voltage of approximately 12V, for example, at a voltage between 12V and 13V, no avalanche phenomenon is generated in the channel region. To this end, the gate structure STG includes a superimposed first gate region RG1 and a second gate region RG2, thereby allowing lightly doped conductive regions LDD, LDDs to be obtained in the substrate PSUB. These lightly doped conductive regions have a larger extent under the gate structure STG than those of conventional single-gate region transistors. Typically, the lightly doped conductive regions LDD1, LDD2, LDD2 are referred to as "lightly doped drains," regardless of their location on the source side S or drain side D.

[0051] The first gate region RG1 includes a first dielectric layer D1, typically made of silicon oxide, located on the front side of the substrate FA, and a first conductive layer P1, typically made of polysilicon, disposed on the first dielectric layer D1.

[0052] The second gate region RG2 includes a second dielectric layer D2, typically made of silicon oxide and / or silicon nitride, and a second conductive layer P2, typically made of polysilicon, disposed on the second dielectric layer D2. The second gate region RG2 covers the entire width of the first gate region RG1 in the inner portion RG2int of the second gate region RG2, and protrudes on each side of the first gate region RG1 so as to cover the front side of the substrate FA in the outer portion RG2ext of the second gate region RG2.

[0053] Lightly doped conductive regions LDDs are located below the outer portion RG2ext of the second gate region RG2, and their ends on the transistor channel side are positioned perpendicularly or laterally to the corresponding edge of the first gate region RG1.

[0054] In fact, as mentioned below Figure 8 As can be seen, the first gate region RG1 can be used as a self-aligned mask for implanting lightly doped conductive regions (LDDs).

[0055] The drain region D of transistor 200 is located perpendicular to the edge of the gate structure STG, that is, perpendicular to the edge RG2brd of the outer portion RG2ext of the second gate region RG2 and perpendicular to the edge FPbrd1 of the field plate FP.

[0056] In fact, as mentioned below Figure 8 As can be seen, the second gate region RG2 and the field plate FP can be used as self-aligned masks for injecting conductive regions S and D.

[0057] In addition, the field plate FP includes a "third" dielectric layer D2 located on the front side of the substrate FA and a "third" conductive layer P2 disposed on the third dielectric layer D2.

[0058] The field plate FP can be defined to extend beyond the active region ACT in a first direction (that is, in the length direction of the active region ACT) such that the edge FPbrd2 opposite to the edge FRbrd1 of the field plate FP perpendicular to the drain D is located above the dielectric volume of the shallow isolation trench STI.

[0059] In this first example of transistor 200, the field plate FP advantageously has the same properties and composition as the second gate region RG2. For this purpose, the field plate FP and the second gate region RG2 are formed during the same manufacturing steps (see [link to documentation]). Figure 8 Therefore, the third conductive layer P2 has the same composition (polysilicon) and the same (measurable) thickness as the second conductive layer P2, and the third dielectric layer D2 of the field plate FP has the same composition (oxide and / or silicon nitride) and the same (measurable) thickness as the second dielectric layer D2 located at the outer portion RG2ext of the second gate region RG2.

[0060] In this framework, the field plate FP produces the same self-aligned masking effect for the injection of conductive regions S and D as the second gate region RG2.

[0061] Therefore, the ranges of the lightly doped conductive regions LDD1 and LDD2 are defined by the overflow RG2ext of the second gate region RG2 relative to the first gate region RG1 facing the active region ACT and the position of the field plate FP facing the active region ACT.

[0062] Therefore, on the side surface of the drain region D, lightly doped conductive regions LDD1 and LDD2 extend along a first direction from the edge of the second gate region RG2brd under the gate structure STG on either side of the conductive region D, and from the edge of the field plate FPbrd1 under the field plate FP. On the side surface of the source region S, a lightly doped conductive region LDD extends along a first direction under the gate structure STG from the edge of the implanted second gate region RG2brd defining the source S.

[0063] Conductive regions S and D have a first dopant concentration and extend from the front FA into the substrate PSUB to a first depth. Lightly doped conductive regions LDD1, LDD2, and LDD2 (as in the case of conventional lightly doped drain regions) have a second concentration lower than the first concentration and extend from the front FA into the substrate PSUB to a second depth less than the first depth.

[0064] Furthermore, the field plate FP is advantageously electrically connected to the drain region D, for example, via metal traces of contact metal pillars CNT and metal layer M1.

[0065] In reality, the drain region D is usually affected by avalanche phenomena. It is assumed that the maximum absolute potential is usually applied to the drain D, which is positive for N-type transistors and negative for P-type transistors, while a lower absolute potential is usually applied to the source.

[0066] Therefore, the field effect generated at the potential of the drain D by the field plate PL at the PN junction between the drain and the substrate allows for enhanced breakdown voltage of the PN junction, that is, increased avalanche voltage of transistor 200.

[0067] The effect of increasing the avalanche voltage of transistor 200 by biasing a field plate PL to a voltage with the same sign as the voltage of the drain region D is obtained through the field effect in the PN junction and is independent of the presence of a lightly doped conductive region LDD2 under the field plate PL.

[0068] In this case, as previously mentioned and below regarding Figure 8 As described, the presence of a field plate PL results in the generation of a lightly doped conductive region LDD2 under the field plate PL through a self-aligned implantation step.

[0069] Furthermore, the presence of a lightly doped conductive region LDD2 under the field plate PL further allows for an independent increase in the avalanche voltage of transistor 200.

[0070] Therefore, refer to Figure 3 .

[0071] Figure 3 It shows Figure 2 The diagram shows a portion of a cross-sectional view of transistor 200, illustrating the dopant concentrations in the substrate PSUB, specifically in the drain region D and lightly doped conductive regions LDD and LDD2 under the gate structure STG and the field plate FP. The dopant concentrations are schematically represented by contour lines of equal concentration N-type dopant (e.g., in the case of an N-type transistor), with the minimum concentration at the substrate PSUB and the maximum concentration at the drain D.

[0072] The results for the presence of a lightly doped conductive region LDD2 (specifically, a lightly doped conductive region LDD2 under the field plate FP) are as follows: Between the drain region D and the substrate PSUB, specifically at the edge of the shallow isolation region STI, the change in dopant concentration is spatially greater than... Figure 1 The smoother curve is more pronounced in the conventional transistor 100 shown.

[0073] In fact, the dopant concentration morphology around the drain regions D, LDD, and LDD2 is essentially the same on the side of the gate structure STG as it is on the side of the field plate FP. Therefore, in transistor 200, the variation of dopant concentration between the drain region D and the substrate PSUB is essentially the same in all directions of the volume.

[0074] Therefore, the junction PN between the drain region D and the substrate PSUB does not include a region with high dopant concentration, and the PN junction between the drain region D and the substrate PSUB can withstand higher voltages without avalanche.

[0075] Figure 4 A top view and cross-sectional view of a second example of a transistor 400 suitable for high voltages typically greater than 12V are shown, which can replace the previously mentioned transistors. Figure 2 The transistor 200 is described.

[0076] Transistor 400 and about Figure 2 The common elements of the described transistor 200 have the same reference numerals and will not be described in detail hereafter.

[0077] Specifically, the gate structure STG, source S and drain D conductive regions, and lightly doped conductive regions LDDs are located under the gate structure STG of transistor 400. Figure 2 The components of the transistor 200 described are identical.

[0078] In this alternative embodiment of transistor 400, the field plate FP has the same properties and composition as the first gate region RG1, and for this purpose, the first gate region RG1 is formed during the same manufacturing steps (see...). Figure 8 Therefore, the third conductive layer P1 of the field plate FP has the same composition (polysilicon) and the same (measurable) thickness as the first conductive layer P1 of the first gate region RG1; the third dielectric layer D1 of the field plate FP has the same composition (silicon oxide) and the same (measurable) thickness as the first dielectric layer D1 of the first gate region RG1. Typically, the thicknesses of the first conductive layer P1 and the first dielectric layer D1 are smaller than the thicknesses of the second conductive layer P2 and the second dielectric layer D2, respectively.

[0079] Similarly, the field plate FP can be advantageously electrically connected to the drain region D in order to enhance the breakdown voltage of the PN junction through the field effect, thereby increasing the avalanche voltage of the transistor 400.

[0080] In this framework, the field plate FP generates the same self-aligned mask effect as the first gate region RG1 for implanting lightly doped conductive regions LDDs, LDDs. In other words, when lightly doped conductive regions LDDs, LDDs are implanted under the gate structure STG, lightly doped conductive region LDD2 is not implanted under the field plate FP.

[0081] In this case, compared with implanting lightly doped conductive regions LDDs, the conductive regions S and D are implanted with a higher concentration and greater energy, making the first conductive layer P1 and the first dielectric layer D1 partially permeable to the implanted conductive regions S and D.

[0082] Therefore, when conductive regions S and D are implanted, a second lightly doped conductive region LDD2 is implanted in the substrate PSUB through the field plate FP. The dopant concentration of the second lightly doped conductive region LDD2 is less than that of conductive regions S and D, and the depth from the front FA into the substrate PSUB is less than the depth of conductive regions S and D.

[0083] Therefore, regarding Figure 2 The example described is similar, with lightly doped conductive regions LDD1 and LDD2 extending from the edge of the second gate region RG2brd under the gate structure STG on either side of the drain region D, and extending from the edge of the field plate FPbrd1 under the field plate FP, the drain region D being perpendicular to the edge of the field plate FPbrd1.

[0084] Similarly, the presence of a second lightly doped conductive region LDD2 under the field plate PL allows for an increase in the avalanche voltage of transistor 200.

[0085] Therefore, refer to Figure 5 .

[0086] Figure 5 It shows Figure 4 A partial cross-sectional view of transistor 400 shows the dopant concentration in the substrate PSUB, specifically in the drain region D and lightly doped conductive regions LDD and LDD2 below the gate structure STG and the field plate FP.

[0087] Regarding Figure 3 The dopant concentrations around the described drain regions D, LDD, and LDD2 are similar. The presence of a second lightly doped conductive region LDD2 under the field plate FP causes the PN junction between the drain region D and the substrate PSUB to exclude localization with high dopant concentrations. Therefore, the PN junction between the drain region D and the substrate PSUB can withstand higher voltages without avalanche phenomena.

[0088] Moreover, previously regarding Figures 2 to 5 The embodiments of transistors 200 and 400 described include the presence of a field plate FP located on the outer side of the drain conductive region D (in the first direction, i.e., along the length of the active region ACT). This is justified by the fact that avalanche phenomena typically occur on the drain D side of high-voltage transistors. However, in certain applications, it may be desirable to improve the breakdown voltage of the PN junction between the source S and the substrate PSUB. For this purpose, the field plate FP and the lightly doped conductive region LDD2 below the field plate can be fabricated perfectly symmetrically on the side of the source conductive region S to achieve the same effect.

[0089] Figure 6 As shown in the example about Figure 2The described embodiments of transistor 200, such as those concerning Figure 4 The described embodiments of transistor 400, and as per... Figure 1 The measurement results of the avalanche voltage BV between the drain region D and the substrate PSUB in the embodiment of the described conventional transistor 100.

[0090] The avalanche voltage BV of a conventional transistor 100 is between 12.46V and 12.5V. The avalanche voltage BV of a transistor 200 is between 13.22V and 13.36V. The avalanche voltage BV of a transistor 400 is between 13.05V and 13.18V.

[0091] In other words, compared to the conventional high-voltage transistor 100, the presence of a lightly doped conductive region LDD2 beneath the field plate PL increases the avalanche voltage of high-voltage transistors 200 and 400 by approximately 1V.

[0092] In addition to its inherent advantages, the avalanche voltage (BV) increase of approximately 1V is particularly beneficial for non-volatile memory technologies such as EEPROM.

[0093] Therefore, refer to Figure 7 .

[0094] Figure 7 A portion of the memory plane PM of an EEPROM-type memory is shown, specifically the memory word MWi,j belonging to row RGj and column COLi. The memory word MWi,j includes at least one byte OCToi, for example, 4 bytes, each byte containing eight memory cells CEL.

[0095] Each memory cell CEL includes an access transistor TA and a state transistor TE with a floating gate and a control gate. The access transistor TA and the state transistor TE are coupled in series between bit lines BL01 to BL71, which are respectively coupled to the drain of the access transistor TA, and a source line SL01, which is coupled to the source of the state transistor TE. The source line SL01 may be common for memory cells CEL belonging to one or more bytes OCT0i, or for all memory cells CEL in the memory plane PM.

[0096] The gates of the access transistors TA of all memory cells CEL in the same row RGj are coupled to word lines WLj dedicated to each row.

[0097] The control gate of the state transistor TE of the memory cell of the same memory word MWi,j is coupled to the control gate line CGi,j dedicated to the memory word MWi,j of column COLi and row RGj.

[0098] Access (decoding) to the control gate line CGi,j in the memory plane PM is accomplished by the control gate switching circuit CGSWi,j located in the region CGSW near the word memory MWi,j in the memory plane PM.

[0099] Each control gate switching circuit CGSWi,j may include an inverter circuit comprising a high-voltage PMOS transistor and a high-voltage NMOS transistor. The high-voltage PMOS transistor and the high-voltage NMOS transistor are advantageously related to... Figure 2 The described embodiments of the high-voltage transistor 200 or related Figure 4 An embodiment of the high-voltage transistor 400 described herein.

[0100] The PMOS transistors and NMOS transistors 200 / 400 of the control gate switching circuit CGSWi,j are controlled by control signals on their gates, which are transmitted on the common control line CLj and dedicated to each row RGj.

[0101] The drains of the complementary transistors 200 / 400 of the inverter in the corresponding switching circuit CGSWi,j are coupled to the common and dedicated bias lines Dpi, Dni of each column of COLi. The well bias lines Bn, Bp allow biasing of complementary wells containing both PMOS and NMOS transistors. The sources of the complementary transistors 200 / 400 of the inverter in the switching circuit CGSWi,j are coupled to the lines of the corresponding control gate CGi,j.

[0102] Therefore, the control line CLj of row RGj and the bias lines Dpi and Dni of column COLi allow selective bias to be transferred on the control gate line CGi,j of the memory word MWi,j belonging to column COLi and row RGj.

[0103] In the memory cell write operation CEL, the write voltage transmitted on the control gate line CGi,j is adapted to inject charge into the floating gate of the state transistor TE through the tunnel oxide thickness via the Fowler-Nordheim effect.

[0104] The write voltage transmitted on the bias lines Dpi and Dni is typically 15V, with the bias voltage of well Bn at 3V and the bias voltage of well Bp at 15V, so as not to exceed the avalanche voltage of transistors 200 / 400, which is typically close to 12V.

[0105] However, for a given current budget, an increase of approximately 1V in the avalanche voltage BV of the 200 / 400 transistors controlling the gate switching circuit CGSWi,j might allow for the use of higher write voltages in the memory. This could potentially allow for increased oxide tunnel thickness for better data retention or reduced write cycle time.

[0106] In fact, increasing the write voltage by 500mV may allow the tunnel oxide thickness to increase from 0.3nm to 0.4nm, thereby improving data retention by 10 times; or allow the duration of the write cycle to be divided by 2.

[0107] Alternatively, an avalanche voltage increase of approximately 1V may allow for a reduction in the power consumption budget of the high-voltage circuitry, which includes the decoder of the memory plane PM and the numerous narrow transistors in the control gate switching circuitry CGSWi,j.

[0108] about Figure 2 and Figure 4 Another advantage of the described transistors 200 and 400 is that the same transistors 200 / 400 have the following benefits: low current in the blocking state (typically "Ioff") of the transistor (conventionally, narrow-channel transistors (that is, across the width of the active region ACT)) and high avalanche voltage from conventional wide-channel transistors (that is, across the width of the active region ACT).

[0109] Figure 8 The illustration shows about Figure 2 and Figure 4 Examples of manufacturing methods 800 for the described transistors 200 and 400.

[0110] The method 800 includes: forming at least one transistor, specifically including: forming separate gate structures STG and field plates FP, 802 to 804 and 806 to 808, the separate gate structures STG and field plates FP being disposed on the front side of a semiconductor substrate; and forming an S / D doped conductive region 809, the S / D doped conductive region being located in the semiconductor substrate, the S / D doped conductive region being perpendicular to the edge of the gate structure RG2brd and perpendicular to the edge of the field plate FPbrd.

[0111] Method 800 includes: forming a dielectric volume of a shallow isolation trench (STI) 801, thereby specifically allowing the active region ACT of the transistors 200 / 400 to be defined.

[0112] Then, method 800 includes: forming a first dielectric layer D1 802 on the front side of the substrate, forming a first conductive layer P1 803 on the first dielectric layer D1, and then etching the first conductive layer P1 804 to define a first gate region RG1.

[0113] In relation to Figure 4 Within the framework of the described example of transistor 400, the etching 804 of the first conductive layer P1 is configured to also define the field plate FP. Therefore, the formation of the field plate FP is performed simultaneously with the formation steps 802, 803 and the etching step 804 of the first gate region RG1.

[0114] Etching 804 is configured to selectively etch the polysilicon faster than the silicon oxide of the first dielectric layer D1. In this case, etching 804 is typically calibrated to “over-etch” the first conductive layer P1, that is, to remove a thickness greater than the actual thickness of the first conductive layer P1 to avoid any residue of polysilicon. This over-etch removes a portion of the first dielectric layer D1 that is not under the gate and retains the remaining thickness of the first dielectric layer D1.

[0115] Then, method 800 includes forming lightly doped conductive regions LDD, LDD1, LDD2 implanted in the semiconductor substrate in a self-aligned manner on the first gate region RG1 and optionally on a field plate formed during steps 802, 803, and 804.

[0116] Injection 805 is achieved with a second concentration lower than the first concentration in step 809 and a second energy lower than the first energy in step 809.

[0117] Then, method 800 includes: forming a second dielectric layer D2 806 on the obtained structure, and then forming a second conductive layer P2 807 on the second dielectric layer D2.

[0118] Then, method 800 includes etching 808 the second conductive layer P2 to define a second gate region RG2. The etching 808 is configured such that the second gate region RG2 includes an inner portion RG2int on the first gate region and an outer portion RG2ext on the front side of the substrate that protrudes beyond the first gate region.

[0119] In relation to Figure 2 Within the framework of the described example of transistor 200, the etching 808 of the second conductive layer P2 is configured to also define the field plate FP. Therefore, the formation of the field plate FP is performed simultaneously with the formation steps 806, 807 and the etching step 808 of the second gate region RG2. During steps 806, 807 and 808, the active region covered by the (future) field plate FP includes the lightly doped conductive region LDD2 formed during implantation step 805.

[0120] The second dielectric layer D2 of 806 is formed by stacking it on the remaining thickness of the first dielectric layer D1 at the location where the remaining thickness of D1 exists. Therefore, in an absolute sense, regarding... Figure 2In the example of the described transistor 200, below the outer portion RG2ext of the second gate region RG2 and below the field plate FP, the second dielectric layer D2 comprises a stack of residues of a partially etched first dielectric layer D1 (e.g., its thickness changes from 22 nm to 16 nm after etching 804) and a second dielectric layer added in step 806 (e.g., its thickness is approximately 16 nm, for a total thickness of approximately 32 nm). This stack allows for ensuring the gate-source and gate-drain withstand voltages of the second dielectric layer D2 at a high voltage of approximately 12 V to 13 V.

[0121] Then, method 800 includes: forming a conductive region S / D 809, the formation of which includes: implanting a self-aligned dopant on a second gate region RG2 at a first concentration higher than the second concentration of step 805 and at a first energy greater than the second energy of step 805.

[0122] At the same time, regarding Figure 4 Within the framework of the described example of transistor 400, a lightly doped conductive region LDD2 of 809 is formed under the field plate FP during the implantation of the 809 conductive region S / D.

[0123] Therefore, at this step of method 800, regarding Figure 2 and Figure 4 In the context of the two examples of transistors 200 and 400 described, the lightly doped conductive regions LDD1 and LDD2 extend from the edge of the gate structure under the gate structure STG and from the edge of the field plate under the field plate FP on either side of the conductive region D.

[0124] Then, method 800 includes: forming an electrical connection 810, typically by means of a metal contact post CNT and a metal trace M1 connecting the field plate and the conductive area.

[0125] An integrated circuit can be summarized as including at least one transistor (200, 400) comprising a separate gate structure (STG) and a field plate (FP) disposed on the front side (FA) of a semiconductor substrate (PSUB), and a doped conductive region (D) located in the semiconductor substrate perpendicular to the edge of the gate structure (RG2brd) and perpendicular to the edge of the field plate (FPbrd1).

[0126] The at least one transistor (200, 400) may further include a lightly doped conductive region (LDD, LDD2) implanted in a semiconductor substrate, the lightly doped conductive region (LDD, LDD2) extending below the gate structure (STG) from the edge of the gate structure (RG2brd) and below the field plate (FP) from the edge of the field plate (FPbrd1) on either side of the conductive region (D).

[0127] The conductive region (D) may have a first dopant concentration and may extend from the front (FA) to a first depth in the substrate (PSUB), and the lightly doped conductive regions (LDD1, LDD2) may have a second dopant concentration lower than the first concentration and may extend from the front (FA) to a second depth in the substrate (PSUB) lower than the first depth.

[0128] The gate structure (STG) may include a first gate region (RG1) and a second gate region (RG2). The first gate region (RG1) includes a first conductive layer (P1) disposed on a first dielectric layer (D1) and located on the front side of a substrate (FA). The second gate region (RG2) includes a second conductive layer (P2) disposed on a second dielectric layer (D2). The second gate region (RG2) includes an inner portion (RG2int) on the first gate region (RG1) and an outer portion (RG2ext) protruding from the first gate region (RG1) on the front side of the substrate (FA). The conductive region (D) is perpendicularly positioned to the edge (RG2brd) of the outer portion of the second gate region (RG2ext).

[0129] The lightly doped conductive region (LDD) can extend below the outer portion of the second gate region (RG2ext).

[0130] The field plate (FP) may include a third conductive layer (P2) disposed on a third dielectric layer (D2) and may be located on the front side of the substrate (FA). The third conductive layer (P2) has the same composition and the same thickness as the second conductive layer (P2), and the third dielectric layer (D2) has the same composition and the same thickness as the second dielectric layer (D2) of the outer portion (RG2ext) of the second gate region (RG2).

[0131] The field plate (FP) may include a third conductive layer (P1) disposed on a third dielectric layer (D1) and may be located on the front side of the substrate (F1). The third conductive layer (P1) has the same composition and the same thickness as the first conductive layer (P1), and the third dielectric layer (D1) has the same composition and the same thickness as the first dielectric layer (D1).

[0132] The field plate (FP) can be electrically connected (CNT, M1) to the conductive area (D).

[0133] The edge of the field plate (FPbrd2), which is perpendicular to the conductive region (D) and opposite to the edge (FRbrd1), can be located above the dielectric volume of the shallow isolation trench (STI).

[0134] A method for manufacturing an integrated circuit can be summarized as including at least forming (800) a transistor, the forming (800) comprising: forming (802 to 804, 806 to 808) a separate gate structure (STG) and a field plate (FP) disposed on the front side of a semiconductor substrate; and forming (809) a doped conductive region (S / D) in the semiconductor substrate, the doped conductive region being perpendicular to the edge of the gate structure (RG2brd) and perpendicularly positioned to the edge of the field plate (FPbrd).

[0135] The at least one structure (800) of the transistor may further include: forming (805) a lightly doped conductive region (LDD) implanted in the semiconductor substrate, the lightly doped conductive region (LDD) extending below the gate structure (STG) from the edge of the gate structure and below the field plate (FP) from the edge of the field plate on either side of the conductive region (D).

[0136] Forming a (809) conductive region (S / D) may include: implanting a dopant at a first concentration and a first energy; forming a (805) lightly doped conductive region (LDD) may include: implanting a dopant at a second concentration lower than the first concentration and a second energy lower than the first energy.

[0137] Forming a gate structure may include: forming (802) a first dielectric layer (D1) on the front side of a substrate, forming (803) a first conductive layer (P1) on the first dielectric layer (D1), and etching (804) the first conductive layer (P1) to define a first gate region; forming (806) a second dielectric layer (D2), forming (807) a second conductive layer (P2) on the second dielectric layer (D2), and etching (808) the second conductive layer (P2) to define a second gate region, such that the second gate region includes an inner portion (RG2int) on the first gate region and an outer portion (RG2ext) protruding from the first gate region on the front side of the substrate; and forming (809) a conductive region (S / D) includes: implanting a self-aligned dopant into the second gate region (D2, P2).

[0138] Forming a (805) lightly doped conductive region (LDD) may include implanting a self-aligned dopant into a first gate region (D1, P1) prior to the step of forming a second gate region.

[0139] Forming a field plate (806 to 808) may include: forming (806) a third dielectric layer (D2) on the front side of a substrate, forming (807) a third conductive layer (P2) on the third dielectric layer, and simultaneously forming (806, 807) a second gate region (D2, P2) and etching (808) the second gate region (D2, P2) to define the field plate.

[0140] Forming a field plate (802 to 804) may include: forming a third dielectric layer (D1) on the front side of a substrate (802), forming a third conductive layer (P1) on the third dielectric layer (803), and etching the third conductive layer (P1) to define the field plate while forming the first gate region (D1, P1) (802, 803) and etching the first gate region (D1, P1) (804); forming a lightly doped conductive region (LDD2) (809) may include: implanting a dopant through the field plate during implantation of the conductive region (S / D) (809).

[0141] The method may also include forming an electrical connection (810) (CNT-M1) between the field plate and the conductive region.

[0142] The method may include: forming a dielectric volume of a shallow isolation trench (STI) (801) prior to forming a field plate, the formation of the field plate including: defining (GRV1, GRV2) of the field plate such that the edges of the field plate opposite to the edges perpendicular to the conductive regions are located above the dielectric volume of the shallow isolation trench (STI).

[0143] The various embodiments described above can be combined to provide other embodiments. If desired, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide other embodiments.

[0144] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and their full scope of equivalents. Therefore, the claims are not limited by this disclosure.

Claims

1. An integrated circuit, comprising: At least one transistor, including: Semiconductor substrate, with a front side; The gate structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer; A field plate, physically separate from the gate structure, is disposed on the front side of the semiconductor substrate, the field plate comprising a third dielectric layer and a third conductive layer; and The doped conductive region in the semiconductor substrate is laterally positioned relative to the edge of the gate structure facing the field plate, and also laterally positioned relative to the edge of the field plate facing the gate structure. The gate structure includes a first gate region and a second gate region. The first gate region includes a first conductive layer disposed on a first dielectric layer and located on the front side of the substrate. The second gate region includes a second conductive layer disposed on the second dielectric layer. The second gate region includes an inner portion on the first gate region and an outer portion protruding from the first gate region on the front side of the substrate. The doped conductive region is laterally positioned at the edge of the outer portion of the second gate region.

2. The integrated circuit of claim 1, wherein the at least one transistor further comprises a lightly doped conductive region implanted in the semiconductor substrate, the lightly doped conductive region extending on either side of the doped conductive region from an edge of the gate structure beneath the gate structure and from an edge of the field plate beneath the field plate.

3. The integrated circuit of claim 2, wherein the lightly doped conductive region extends beneath the outer portion of the second gate region.

4. The integrated circuit of claim 1, wherein the field plate includes the third conductive layer, the third conductive layer being disposed on the third dielectric layer and located on the front side of the substrate, the third conductive layer having the same composition and the same thickness as the second conductive layer, and the third dielectric layer having the same composition and the same thickness as the second dielectric layer of the outer portion of the second gate region.

5. The integrated circuit of claim 1, wherein the field plate includes a third conductive layer disposed on a third dielectric layer and located on the front side of the substrate, the third conductive layer having the same composition and the same thickness as the first conductive layer, and the third dielectric layer having the same composition and the same thickness as the first dielectric layer.

6. The integrated circuit of claim 1, wherein the edge of the field plate opposite to the lateral edge of the doped conductive region is located above the dielectric volume of the shallow isolation trench.

7. An integrated circuit, comprising: At least one transistor, including: Semiconductor substrate, with a front side; The gate structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer; A field plate, physically separate from the gate structure, is disposed on the front side of the semiconductor substrate, the field plate comprising a third dielectric layer and a third conductive layer; and The doped conductive region in the semiconductor substrate is laterally positioned relative to the edge of the gate structure facing the field plate, and also laterally positioned relative to the edge of the field plate facing the gate structure. The at least one transistor further includes a lightly doped conductive region implanted in the semiconductor substrate, the lightly doped conductive region extending on either side of the doped conductive region from an edge of the gate structure beneath the gate structure and from an edge of the field plate beneath the field plate, and... The doped conductive region has a first dopant concentration and extends from the front side into the substrate to a first depth, and the lightly doped conductive region has a second dopant concentration lower than the first dopant concentration and extends from the front side into the substrate to a second depth less than the first depth.

8. An integrated circuit, comprising: At least one transistor, including: Semiconductor substrate, with a front side; The gate structure includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer; A field plate, physically separate from the gate structure, is disposed on the front side of the semiconductor substrate, the field plate comprising a third dielectric layer and a third conductive layer; and The doped conductive region in the semiconductor substrate is laterally positioned relative to the edge of the gate structure facing the field plate, and also laterally positioned relative to the edge of the field plate facing the gate structure. The field plate is electrically connected to the doped conductive region.

9. A method for manufacturing an integrated circuit, comprising: Forming a transistor includes: A semiconductor substrate is formed, the semiconductor substrate having a front side; A gate structure is formed, the gate structure including a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer; A field plate is formed, the field plate being separate from the gate structure and disposed on the front side of the semiconductor substrate, the field plate including a third dielectric layer and a third conductive layer; and A doped conductive region is formed in the semiconductor substrate located between the gate structure and the field plate. The formation of the gate structure includes: The first dielectric layer is formed on the front side of the substrate; The first conductive layer is formed on the first dielectric layer; The first conductive layer is etched to define the first gate region; Form the second dielectric layer; The second conductive layer is formed on the second dielectric layer; The second conductive layer is etched to define a second gate region, the second gate region including an inner portion on the first gate region and an outer portion protruding from the first gate region on the front side of the substrate; and The doped conductive region includes implanting a plurality of self-aligned dopants into the second gate region.

10. The method of claim 9, wherein forming the transistor further comprises: A lightly doped conductive region is formed and implanted into the semiconductor substrate, extending on either side of the doped conductive region from the edge of the gate structure below the gate structure and from the edge of the field plate below the field plate.

11. The method of claim 10, wherein forming the lightly doped conductive region comprises: Before forming the second gate region, the plurality of self-aligned dopants are implanted on the first gate region.

12. The method of claim 9, wherein forming the field plate comprises: The third dielectric layer is formed on the front side of the substrate; The third conductive layer is formed on the third dielectric layer; The third conductive layer is etched to define the field plate; and The second gate region is etched.

13. The method of claim 10, wherein forming the field plate comprises: The third dielectric layer is formed on the front side of the substrate; The third conductive layer is formed on the third dielectric layer; The third conductive layer is etched to define the field plate; The first gate region is etched; The lightly doped conductive region is formed during implantation by injecting dopant through the field plate.

14. The method of claim 9, comprising: Before forming the field plate, a shallow isolation trench dielectric volume is formed, and forming the field plate includes: The field plate is defined such that the edge of the field plate is located above the dielectric volume of the shallow isolation trench.

15. A method for manufacturing an integrated circuit, comprising: Forming a transistor includes: A semiconductor substrate is formed, the semiconductor substrate having a front side; A gate structure is formed, the gate structure including a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer; A field plate is formed, the field plate being separate from the gate structure and disposed on the front side of the semiconductor substrate, the field plate including a third dielectric layer and a third conductive layer; and A doped conductive region is formed in the semiconductor substrate located between the gate structure and the field plate. The transistor also includes: A lightly doped conductive region is formed and implanted into the semiconductor substrate, extending on either side of the doped conductive region from the edge of the gate structure beneath the gate structure and from the edge of the field plate beneath the field plate. The formation of the doped conductive region includes: The dopant is injected at a first concentration and with a first energy; and Forming the lightly doped conductive region includes: The dopant is injected at a second concentration lower than the first concentration and at a second energy lower than the first energy.

16. A method for manufacturing an integrated circuit, comprising: Forming a transistor includes: A semiconductor substrate is formed, the semiconductor substrate having a front side; A gate structure is formed, the gate structure including a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer; A field plate is formed, the field plate being separate from the gate structure and disposed on the front side of the semiconductor substrate, the field plate including a third dielectric layer and a third conductive layer; and A doped conductive region is formed in the semiconductor substrate located between the gate structure and the field plate, and The method further includes forming an electrical connection between the field plate and the doped conductive region.

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