Semiconductor device, integrated circuit, and electronic device

Abstract

The application discloses a semiconductor device, an integrated circuit and an electronic device. The semiconductor device comprises an n-type semiconductor substrate, a drift layer, a semiconductor layer, a trench, a shielding structure, a source and a drain. The shielding structure is arranged on the drift layer and comprises a plurality of first shielding structures and a plurality of second shielding structures. The first shielding structures extend along a first direction, the second shielding structures extend along a second direction, the first direction intersects the second direction, and the first shielding structures and the second shielding structures are arranged in a grid shape. It can be considered that the first shielding structures and the second shielding structures form a plurality of grid areas, each grid area has shielding structures on the periphery, and the gate oxide layer in the trench in each grid area can be protected by the shielding structures from all directions. This is beneficial to better reduce the electric field concentration of the gate oxide layer, improve the breakdown voltage of the semiconductor device, and improve the reliability and device characteristics of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, integrated circuit, and electronic device. Background Technology

[0002] Compared to silicon, SiC material offers advantages such as a wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher electron saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) made from SiC exhibit higher breakdown voltage and lower on-state voltage drop compared to insulated-gate bipolar transistors (IGBTs) made from Si. Furthermore, the unipolar conductivity of SiC MOSFETs results in faster switching speeds, lower conduction losses, and lower switching losses compared to Si IGBTs. Therefore, SiC MOSFETs have already replaced Si IGBTs in some applications.

[0003] Compared to traditional planar gate MOSFETs, trench gate MOSFETs can reduce the cell size of the MOSFET, increasing the chip cell density and thus increasing the channel density and the resulting current carrying capacity. Trench gate MOSFETs can significantly reduce the on-resistance of the device. However, in trench gate MOSFETs, the gate oxide layer is prone to electric field concentration at the bottom and corners of the trench, which can lead to breakdown of the gate oxide layer below the rated voltage, severely affecting the blocking characteristics of the device. Therefore, providing a solution to reduce the electric field concentration of the gate oxide layer at the bottom and corners of the trench is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a semiconductor device, integrated circuit, and electronic device to improve the protection effect of the shielding structure on the gate oxide layer, reduce the electric field concentration of the gate oxide layer, increase the breakdown voltage of the semiconductor device, and improve the reliability and device characteristics of the semiconductor device.

[0005] In a first aspect, this application provides a semiconductor device comprising an n-type semiconductor substrate, a drift layer, a semiconductor layer, a trench, a shielding structure, a source electrode, and a drain electrode. The semiconductor substrate is disposed on the drain electrode surface, and the drift layer is disposed on the surface of the semiconductor substrate opposite to the drain electrode. The semiconductor layer is disposed on the side of the drift layer opposite to the semiconductor substrate, and the semiconductor layer includes a source region, which is an n-type semiconductor region, and the source region is exposed on the side of the semiconductor layer opposite to the drift layer. A source electrode is disposed on the side of the semiconductor layer opposite to the drift layer, and the source electrode is in contact with the source region. The opening of the trench is located on the surface of the semiconductor layer opposite to the drift layer. A gate electrode is disposed within the trench, and a gate oxide layer is disposed between the gate electrode and the surface of the trench. Furthermore, the gate insulating layer covers the opening of the trench and exposes the source region to maintain contact between the source region and the source electrode. In addition, the source electrode is also in contact with the gate insulating layer. The gate electrode is encapsulated by the gate oxide layer and the gate insulating layer, thereby isolating the gate electrode and the source electrode. A P-type shielding structure is disposed on the drift layer, and the shielding structure includes multiple first shielding structures and multiple second shielding structures. The first shielding structures extend along a first direction, and the second shielding structures extend along a second direction, with the first and second directions intersecting. The multiple first and second shielding structures are arranged in a grid pattern. It can be considered that the multiple first and second shielding structures form multiple grid regions, each with a shielding structure on its periphery. Therefore, the gate oxide layer in the trench within each grid region can be protected from all sides by the shielding structure, which helps to better reduce the electric field concentration of the gate oxide layer, improve the breakdown voltage of the semiconductor device, and thus enhance the reliability and characteristics of the semiconductor device.

[0006] In one specific technical solution, to achieve the grid-like arrangement of the first and second shielding structures, the first shielding structure can be strip-shaped, with multiple first shielding structures arranged in parallel and spaced apart by a first predetermined distance; similarly, the second shielding structure can be strip-shaped, with multiple second shielding structures arranged in parallel and spaced apart by a second predetermined distance. Thus, the first and second shielding structures interweave to form a grid-like structure.

[0007] The first and second preset distances can be the same or different, and this application does not impose any restrictions. Specifically, the first and second preset distances can be made equal, in which case the grid area of ​​the mesh structure formed by the first and second shielding structures is rhomboid or square, with a relatively regular shape.

[0008] When specifically configuring the first and second shielding structures, the overlapping area between the first and second shielding structures is the first shared structure. In other words, the first and second shielding structures can be considered as a single, integrated structure, and the first shared structure belongs to both the first and second shielding structures.

[0009] The aforementioned first and second shielding structures can be fabricated in a single process or in two separate processes. When the first and second shielding structures are fabricated in two separate processes, the depths of the first and second shielding structures can be different. In other words, the distance between the surface of the first shielding structure facing the semiconductor substrate and the semiconductor substrate can be different from the distance between the surface of the second shielding structure facing the semiconductor substrate and the semiconductor substrate.

[0010] However, the depth of the shielding structure must be greater than the depth of the trench; that is, the depths of both the first and second shielding structures must be greater than the depth of the trench. In other words, the distance between the surface of the shielding structure facing the semiconductor substrate and the semiconductor substrate is less than the distance between the surface of the trench facing the semiconductor substrate and the semiconductor substrate. In this technical solution, the shielding structure can better protect the gate oxide layer within the trench, thereby reducing the concentration of the electric field in the gate oxide layer.

[0011] Furthermore, when specifically configuring the aforementioned shielding structure, it can be symmetrically arranged around the periphery of the trench. This improves the symmetry of the semiconductor device and enhances its performance.

[0012] The aforementioned trenches may include multiple first trenches and multiple second trenches. The first trenches extend along a third direction, and the second trenches extend along a fourth direction, intersecting the third and fourth directions. The multiple first and second trenches are arranged in a grid pattern. This technical solution allows for a larger trench area in the semiconductor device, which is beneficial for increasing the channel area of ​​the semiconductor device, resulting in lower resistance and higher current, thus improving the performance of the semiconductor device.

[0013] Specifically, the aforementioned third direction can be parallel to the first direction, and the fourth direction can be parallel to the second direction. That is, the first trench is parallel to the first shielding structure, and the second trench is parallel to the second shielding structure. In this technical solution, the shielding structures can be symmetrically arranged around the periphery of the trenches, so that the protection effect is more symmetrical and uniform, and the electric field of the gate oxide layer of the trenches is more uniform.

[0014] When specifically configuring the aforementioned shielding structure and trenches, at least one first shielding structure can be provided between any two adjacent first trenches, and at least one second shielding structure can be provided between any two adjacent second trenches. This technical solution ensures that no two first trenches are directly adjacent to each other, and similarly, no two second trenches are directly adjacent to each other, thereby reducing the electric field concentration of the gate oxide layer in the trenches.

[0015] In a specific technical solution, the first trench and the first shielding structure can be arranged alternately, and the second trench and the second shielding structure can be arranged alternately.

[0016] The first and second directions intersect, specifically, the first and second directions can be perpendicular, thus ensuring that the first and second shielding structures are perpendicularly positioned. The resulting grid area formed by the first and second shielding structures is rectangular, with a relatively regular shape. Alternatively, the grid area formed by the first and second shielding structures can be square, resulting in better symmetry of the shielding structure, more uniform protection, and a more uniform electric field in the gate oxide layer within the trench.

[0017] The specific structure of the shielding structure is not limited. For example, the shielding structure can extend along the fifth direction, which is perpendicular to the first and second directions. In other words, the shielding structure is arranged in a straight line along the fifth direction. The fabrication process of the shielding structure in this scheme is relatively simple, which helps to simplify the fabrication process of semiconductor devices.

[0018] The aforementioned shielding structure may further include a first shielding portion and a second shielding portion. The first shielding portion extends along a fifth direction, which is perpendicular to both the first and second directions. The second shielding portion is located at the end of the first shielding portion facing the semiconductor substrate and extends parallel to the semiconductor substrate. In this embodiment, the second shielding portion is formed as a protruding edge of the first shielding portion. Thus, the first shielding portion can protect the gate oxide layer from all sides, and the second shielding portion can protect the gate oxide layer from the direction of the gate oxide layer towards the semiconductor substrate. This design allows the shielding structure to enclose the gate oxide layer, protecting it from all directions and reducing electric field concentration in the gate oxide layer.

[0019] The aforementioned semiconductor device may further include a first semiconductor region and a well region located in the semiconductor layer. Specifically, the first semiconductor region is a P-type semiconductor region, and the well region is also a P-type semiconductor region. The doping concentration of the first semiconductor region is greater than that of the shielding structure. The well region is in contact with the shielding structure, the source region, and the first semiconductor region, respectively. The first semiconductor region is also in contact with the source electrode, thereby connecting the shielding structure, the well region, the first semiconductor region, and the source electrode in sequence, thus achieving grounding of the shielding structure. The well region and the source region form a PN junction. The first semiconductor region is in contact with the source electrode, connecting the well region and the source region, short-circuiting the PN junction between the well region and the source region, and preventing the PN junction from turning on and conducting.

[0020] The specific location of the first semiconductor region is not limited when setting it. In one technical solution, the orthographic projection of the first semiconductor region onto the semiconductor substrate coincides with the orthographic projection of the overlapping area of ​​the first and second shielding structures onto the semiconductor substrate. In this embodiment, the first semiconductor region can also be in full contact with the source regions on its periphery, and since the periphery of the first semiconductor region is entirely composed of source regions, even if the mask shifts during the fabrication of the first semiconductor region, the first semiconductor region can still maintain contact with the source regions and the source electrode.

[0021] In another technical solution, the orthographic projection of the first semiconductor region onto the semiconductor substrate coincides with the orthographic projection of the shielding structure onto the semiconductor substrate. This solution can utilize a single masking process to fabricate the first semiconductor region and the shielding structure by adjusting the ion implantation power and parameters, thereby simplifying the semiconductor device fabrication process. Of course, in the technical solution of this application, the first semiconductor region can also be made to have sufficient contact with the surrounding source region, and since the periphery of the first semiconductor region is entirely composed of source regions, even if the mask position shifts during the fabrication of the first semiconductor region, the first semiconductor region can still maintain contact with the source region and the source electrode.

[0022] The doping concentration of the well region is lower than that of the first semiconductor region, thereby ensuring that the doping concentration of the p-type dopant in the well region is not too high, which ensures that the channel can be opened and thus increases the channel area.

[0023] The aforementioned semiconductor device further includes a current diffusion layer, which is an n-type semiconductor region. The doping concentration of this current diffusion layer is greater than that of the drift layer but less than that of the source region. The current diffusion layer is located adjacent to the drift layer and the semiconductor layer. The current diffusion layer has a certain thickness; specifically, the distance between the surface of the current diffusion layer facing the semiconductor substrate and the semiconductor substrate is less than the distance between the surface of the trench facing the semiconductor substrate and the semiconductor substrate, thus allowing the current diffusion layer to cover the bottom of the trench. In this embodiment, the current diffusion layer can reduce the diffusion current of the drift layer at its upper end.

[0024] Secondly, this application also provides a method for fabricating a semiconductor device. This method is used to fabricate the semiconductor device described in the first aspect. The method specifically includes the following steps: epitaxially growing an epitaxial layer on the surface of an n-type semiconductor substrate; implanting p-type dopant elements into the surface of the epitaxial layer to form a p-type well region; fabricating a first mask layer on the surface of the well region, exposing the region corresponding to the shielding structure, and implanting p-type dopant elements to form the shielding structure; removing the first mask layer and fabricating a second mask layer, exposing the region corresponding to the source region, and implanting n-type dopant elements to form the source region; removing the second mask layer and fabricating a third mask layer, exposing the region corresponding to the trench, and etching to form the trench; forming a gate oxide layer in the trench using a high-temperature oxidation process; depositing a gate electrode in the gate oxide layer; and sequentially fabricating a gate insulating layer, a source electrode, and a drain electrode. This completes the fabrication of the semiconductor device.

[0025] Thirdly, this application also provides another method for fabricating a semiconductor device, which can also be used to fabricate the semiconductor device described in the first aspect. This method specifically includes the following steps: epitaxially growing a first epitaxial layer on the surface of an n-type semiconductor substrate, the first epitaxial layer being an n-type semiconductor layer; fabricating a first mask layer on the surface of the first epitaxial layer, exposing the region corresponding to the shielding structure, and implanting p-type dopant elements to form the shielding structure; removing the first mask layer, epitaxially growing a second epitaxial layer on the surface of the first epitaxial layer, the second epitaxial layer being a p-type semiconductor layer; fabricating a second mask layer on the surface of the second epitaxial layer, exposing the region corresponding to the source region, and implanting n-type dopant elements to form the source region; removing the second mask layer, fabricating a third mask layer, exposing the region corresponding to the trench, and etching to form the trench; forming a gate oxide layer in the trench using a high-temperature oxidation process; depositing a gate electrode in the gate oxide layer; and sequentially fabricating a gate insulating layer, a source electrode, and a drain electrode. This completes the fabrication of the semiconductor device.

[0026] Fourthly, this application also provides an integrated circuit, which includes a circuit board and a semiconductor device as described in the first aspect, the semiconductor device being disposed on the circuit board. The shielding structure in the semiconductor device can protect the gate oxide layer from all sides, thereby reducing the electric field concentration of the gate oxide layer, increasing the breakdown voltage of the semiconductor device, and thus improving the reliability and characteristics of the semiconductor device, thereby improving the performance and lifespan of the integrated circuit.

[0027] Fifthly, this application also provides an electronic device comprising a housing and an integrated circuit as described in the fourth aspect, the integrated circuit being disposed within the housing. The integrated circuit of this electronic device exhibits superior performance and a longer lifespan, thereby contributing to improved performance and lifespan of the electronic device. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a semiconductor device structure in an embodiment of this application;

[0029] Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure at point AA in the middle;

[0030] Figure 3 for Figure 1 Another cross-sectional structural diagram at point AA;

[0031] Figure 4 for Figure 1 Another cross-sectional structural diagram at point AA;

[0032] Figure 5 for Figure 1 Another cross-sectional structural diagram at point AA;

[0033] Figure 6 for Figure 1 Another cross-sectional structural diagram at point AA;

[0034] Figure 7 for Figure 1 Another cross-sectional structural diagram at point AA;

[0035] Figure 8 This is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0036] Figure 9 This is a schematic diagram showing the orthographic projection relationship of the trench, shielding structure, first semiconductor region, and source region of a semiconductor device in an embodiment of this application onto a semiconductor substrate.

[0037] Figure 10 This is a schematic diagram showing the orthographic projection relationship of the trench, shielding structure, first semiconductor region, and source region of another semiconductor device in an embodiment of this application onto the semiconductor substrate.

[0038] Figure 11 This is a schematic diagram of another structure of the semiconductor device in the embodiments of this application;

[0039] Figure 12 This application provides a method for fabricating a semiconductor device.

[0040] Figure 13 This is another method for fabricating semiconductor devices in the embodiments of this application.

[0041] Explanation of reference numerals in the attached figures:

[0042] 1-Source; 2-Semiconductor layer;

[0043] 21 - Source region; 22 - First semiconductor region;

[0044] 23-Trap region; 3-Gate insulating layer;

[0045] 4-Trench; 41-Gate;

[0046] 42 - Gate oxide layer; 43 - First trench;

[0047] 44 - Second trench; 45 - Second shared structure;

[0048] 5-Drift layer; 6-Semiconductor substrate;

[0049] 7-Drain; 8-Shielding structure;

[0050] 81 - First shielding structure; 82 - Second shielding structure;

[0051] 83-First common structure; 84-First shielding part;

[0052] 85 - Second shielding section; 9 - Current diffusion layer. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, a further detailed description of this application will be provided below in conjunction with the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this application are illustrative based on the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0054] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following descriptions are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of illustrating the general principles of this application and are not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0055] To facilitate understanding of the semiconductor device, integrated circuit, and electronic device provided in this application embodiment, its application scenarios are first introduced below. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) widely used in analog and digital circuits. FETs can operate under very low current and voltage conditions, and their manufacturing process allows for the convenient integration of many FETs into a single unit. Therefore, FETs are widely used in large-scale integrated circuits. For example, they can be applied in switching power supplies, power amplifiers, electric vehicle power supplies, photovoltaic inverters, server power supplies, and rail transportation.

[0056] It should be noted that, in this application, layers and regions marked with 'n' represent electrons as the majority carriers, and layers and regions marked with 'p' represent holes as the majority carriers. Furthermore, a '+' after 'n' or 'p' indicates a higher doping concentration than layers or regions without '+'. 'n' or 'p' containing the same number of '+' signs indicate similar doping concentrations, but are not limited to the same doping concentration. Conversely, a '-' after 'n' or 'p' indicates a lower doping concentration than layers or regions without '+'. 'n' or 'p' containing the same number of '-' signs indicate similar doping concentrations, but are not limited to the same doping concentration.

[0057] Figure 1 This is a schematic diagram of a semiconductor device structure in an embodiment of this application, such as... Figure 1As shown, the semiconductor device includes a source 1, a semiconductor layer 2, a gate insulating layer 3, a trench 4, a drift layer 5 (n-), an n-type semiconductor substrate 6 (n+), and a drain 7. The semiconductor substrate 6 (n+) is disposed on the surface of the drain 7. The drift layer 5 (n-), an n-type semiconductor region, is disposed on the surface of the semiconductor substrate 6 (n+) away from the drain 7 and is mainly used to carry high voltage. The semiconductor layer 2 is disposed on the surface of the drift layer 5 (n-) away from the semiconductor substrate 6 (n+) and includes a source region 21 (n+), which is an n-type semiconductor region and is exposed on the side of the semiconductor layer 2 away from the drift layer 5 (n-). The opening of the trench 4 is located on the surface of the semiconductor layer 2 away from the drift layer 5 (n-). A gate 41 is disposed within the trench 4, and a gate oxide layer 42 is disposed between the gate 41 and the surface of the trench 4. Furthermore, the gate insulating layer 3 covers the opening of the trench 4 and exposes the source region 21 (n+), so that the gate 41 is enveloped by the gate oxide layer 42 and the gate insulating layer 3. The source 1 is disposed on the surface of the semiconductor layer 2 away from the drift layer 5 (n-) and is in contact with the source region 21 (n+) and the gate insulating layer 3. The gate 41 is enveloped by the gate oxide layer 42 and the gate insulating layer 3, thereby isolating the gate 41 and the source 1. In a specific embodiment, the semiconductor device can be a MOSFET, and the MOSFET can be turned on or off by applying a gate bias voltage to the gate 41 of the MOSFET. When the gate bias voltage is higher than the threshold voltage, the MOSFET is in the on state, and current is conducted through the channel of the MOSFET; when the gate bias voltage is lower than the threshold voltage, current stops conducting through the channel. For example, in an n-type MOSFET device, when the applied gate bias voltage is higher than the threshold voltage, a conductive n-type inversion layer is formed in the p-type channel region of the device. This n-type inversion layer connects the source 1 and drain 7 of the MOSFET, thereby turning on the device and allowing majority carriers to conduct. The aforementioned gate oxide layer 42 easily causes electric field concentration at the bottom and corners of the trench 4, leading to breakdown of the gate oxide layer 42 below the rated voltage, severely affecting the blocking characteristics of the semiconductor device.

[0058] Please continue to refer to this. Figure 1 The aforementioned semiconductor device also includes a p-type shielding structure 8(p) disposed on the drift layer 5(n-). This shielding structure 8(p) can reduce the electric field strength of the gate oxide layer 42, so that the semiconductor device will only break down when the voltage is higher than the rated voltage, thus giving the semiconductor device good blocking characteristics. This improves the reliability and device characteristics of the semiconductor device. Figure 2 It shows Figure 1 A cross-sectional structural diagram at point AA shows the projection relationship between trench 4 and shielding structure 8(p) onto the plane containing semiconductor substrate 6(n+). Please refer to... Figure 1and Figure 2 The shielding structure 8(p) includes multiple first shielding structures 81(p) and multiple second shielding structures 82(p). The first shielding structures 81(p) extend along a first direction A, and the second shielding structures 82(p) extend along a second direction B. Since the first direction A and the second direction B intersect, the multiple first shielding structures 81(p) and the multiple second shielding structures 82(p) can be arranged in a grid pattern. In this embodiment, the grid-like arrangement of the first shielding structures 81(p) and the second shielding structures 82(p) can form multiple grid regions. Each grid region is surrounded by the shielding structure 8(p), thus protecting the gate oxide layer 42 in the trench 4 within each grid region from all sides. This helps to better reduce the electric field concentration of the gate oxide layer 42, improve the breakdown voltage of the semiconductor device, and enhance the reliability and characteristics of the semiconductor device.

[0059] It is worth noting that, specifically when configuring the first shielding structure 81(p) and the second shielding structure 82(p), the overlapping area of ​​the first shielding structure 81(p) and the second shielding structure 82(p) is the first common structure 83. That is, the first shielding structure 81(p) and the second shielding structure 82(p) can be considered as a single structure, and the first common structure 83 belongs to both the first shielding structure 81(p) and the second shielding structure 82(p). In this embodiment, when actually fabricating the shielding structure 8(p), the first shielding structure 81(p) and the second shielding structure 82(p) can be formed in one process using a single mask, thus simplifying the fabrication process of the shielding structure 8(p).

[0060] The depth of the aforementioned shielding structure 8(p) is greater than the depth of the trench 4. Specifically, the distance between the surface of the shielding structure 8(p) facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+) is less than the distance between the surface of the trench 4 facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+). In other words, the depth of the shielding structure 8(p) is greater than the depth of the trench 4. In this embodiment, the shielding structure 8(p) can better protect the gate oxide layer 42 within the trench 4, thereby reducing the electric field concentration in the gate oxide layer 42.

[0061] When specifically configuring the shielding structure 8(p), there are no restrictions on the extension direction of the shielding structure 8(p) and the shape of the formed mesh. However, the shielding structure 8(p) can be symmetrically arranged on the periphery of the trench 4 to improve the symmetry of the semiconductor device.

[0062] Of course, in other embodiments, two masks can be used to form the first shielding structure 81(p) and the second shielding structure 82(p) through two processes. For example, a first mask is formed to form the first shielding structure 81(p); then the first mask is removed to form a second mask, which is used to form the second shielding structure 82(p). In this embodiment, the first common structure 83 can be prepared in either of the two processes. For example, if the first common structure 83 is formed using the first mask, then the second mask does not need to expose the area where the first common structure 83 is located; it only needs to form the second shielding structure 82(p) to remove the area of ​​the first common structure 83.

[0063] When fabricating the first shielding structure 81(p) and the second shielding structure 82(p) using two processes, the depths of the first shielding structure 81(p) and the second shielding structure 82(p) can be different. That is, the distance between the surface of the first shielding structure 81(p) facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+) can be different from the distance between the surface of the second shielding structure 82(p) facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+). In this case, the first common structure 83 only needs to have the same depth as either the first shielding structure 81(p) or the second shielding structure 82(p).

[0064] Please continue to refer to this. Figure 2 In one specific embodiment, the first shielding structure 81(p) is strip-shaped, and multiple first shielding structures 81(p) are arranged in parallel and spaced apart by a first predetermined distance a. Similarly, the second shielding structure 82(p) is also strip-shaped, and multiple second shielding structures 82(p) are arranged in parallel and spaced apart by a second predetermined distance b. Thus, the first shielding structures 81(p) and the second shielding structures 82(p) are staggered to form a mesh-like structure.

[0065] In specific embodiments, the first predetermined distance a and the second predetermined distance b can be the same or different, and this application does not impose any restrictions. In specific embodiments, the first predetermined distance a and the second predetermined distance b can be equal, in which case the grid area of ​​the mesh structure formed by the first shielding structure 81(p) and the second shielding structure 82(p) is rhomboid or square, with a relatively regular shape. Of course, the first predetermined distance a and the second predetermined distance b can also be different according to the specific structural requirements of the semiconductor device.

[0066] Please continue to refer to this. Figure 2In a specific embodiment, the first direction A is perpendicular to the second direction B, so the grid area formed by the first shielding structure 81(p) and the second shielding structure 82(p) is rectangular and has a relatively regular shape. Furthermore, when the first set distance a and the second set distance b are equal, the grid area formed by the first shielding structure 81(p) and the second shielding structure 82(p) is square. The shielding structure 8(p) has good symmetry, resulting in a more uniform protection effect and a more uniform electric field in the gate oxide layer 42 of the trench 4.

[0067] Figure 3 for Figure 1 Another cross-sectional view of section AA shows a different projection relationship between trench 4 and shielding structure 8(p) on the plane of semiconductor substrate 6(n+). Please refer to [reference needed]. Figure 3 In a specific embodiment, the first direction A and the second direction B may not be perpendicular, in which case the grid area formed by the first shielding structure 81(p) and the second shielding structure 82(p) is a parallelogram. When the first set distance a and the second set distance b are equal, the grid area formed by the first shielding structure 81(p) and the second shielding structure 82(p) is a rhombus.

[0068] Figure 4 for Figure 1 Another cross-sectional view of section AA shows a different projection relationship between trench 4 and shielding structure 8(p) on the plane of semiconductor substrate 6(n+). Please refer to [reference needed]. Figures 2 to 4 As shown in the specific embodiment, when fabricating the above-mentioned trench 4, multiple trenches 4 extend along the sixth direction C, that is, the trenches 4 are arranged in a strip shape and extend in the same direction. In a specific embodiment, multiple trenches 4 can also be arranged in parallel and spaced at a certain distance to improve the symmetry and uniformity of the semiconductor device.

[0069] The sixth direction C mentioned above can be parallel to either the first direction A or the second direction B, such as... Figure 2 and Figure 3 As shown; or, the sixth direction C can also be non-parallel to both the first direction A and the second direction B, such that the sixth direction C has a certain angle with both the first direction A and the second direction B, as shown. Figure 4 As shown. The angle between the sixth direction C and the first direction A and the second direction B can also be made the same to improve the symmetry of the semiconductor device.

[0070] Figure 5 for Figure 1 Another cross-sectional view of the structure at point AA shows a different projection relationship between the trench 4 and the shielding structure 8(p) on the plane of the semiconductor substrate 6(n+). Figure 5As shown, the aforementioned trench 4 may include multiple first trenches 43 and multiple second trenches 44. The first trenches 43 extend along a third direction D, and the second trenches 44 extend along a fourth direction E. The third direction D intersects with the fourth direction E, so the first trenches 43 and second trenches 44 are arranged in a grid pattern. In this scheme, the area of ​​the trenches 4 in the semiconductor device can be increased, which is beneficial to increasing the channel area of ​​the semiconductor device, thereby reducing the resistance and increasing the current, which is beneficial to improving the performance of the semiconductor device.

[0071] It is worth noting that, specifically when configuring the first trench 43 and the second trench 44, the overlapping area of ​​the first trench 43 and the second trench 44 is the second common structure 45. That is, the first trench 43 and the second trench 44 can be considered as a single structure, and the second common structure 45 belongs to both the first trench 43 and the second trench 44. In this embodiment, during the actual fabrication of the trenches, the first trench 43 and the second trench 44 can be formed using a single etching process, thus simplifying the fabrication process of the trench 4.

[0072] Of course, in other embodiments, the first trench 43 and the second trench 44 can also be formed using two etching processes. For example, a third mask is formed, and the first trench 43 is formed using the third mask; then the third mask is removed to form a fourth mask, and the second trench 44 is formed using the fourth mask. In this embodiment, the second common structure 45 can be prepared in either of the two processes. For example, if the second common structure 45 is formed during the first etching, then the second mask does not need to expose the area where the second common structure 45 is located; it only needs to be formed in the area of ​​the second trench 44 where the second common structure 45 is removed.

[0073] When fabricating the first trench 43 and the second trench 44 using two processes, the depths of the first trench 43 and the second trench 44 can be different. That is, the distance between the surface of the first trench 43 facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+) can be different from the distance between the surface of the trench 4 facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+). In this case, the second common structure 45 only needs to have the same depth as either the first trench 43 or the second trench 44.

[0074] Please continue to refer to this. Figure 5 In one specific embodiment, the first groove 43 is strip-shaped, and multiple first grooves 43 are arranged in parallel and spaced apart by a third predetermined distance c. Similarly, the second groove 44 is also strip-shaped, and multiple second grooves 44 are arranged in parallel and spaced apart by a fourth predetermined distance d. Thus, the first grooves 43 and second grooves 44 interweave to form a mesh structure.

[0075] In specific embodiments, the third predetermined distance c and the fourth predetermined distance d can be the same or different, and this application does not impose any restrictions. In specific embodiments, the third predetermined distance c and the fourth predetermined distance d can be equal, in which case the grid area of ​​the mesh structure formed by the first trench 43 and the second trench 44 is rhomboid or square, with a relatively regular shape. Of course, the third predetermined distance c and the fourth predetermined distance d can also be different according to the specific structural requirements of the semiconductor device.

[0076] Please continue to refer to this. Figure 5 In a specific embodiment, when the third direction D is perpendicular to the fourth direction E, the grid area formed by the first trench 43 and the second trench 44 is rectangular and has a relatively regular shape. Furthermore, when the third predetermined distance c and the fourth predetermined distance d are equal, the grid area formed by the first trench 43 and the second trench 44 is square. The trench 4 has good symmetry, resulting in a more uniform protection effect, and the electric field of the gate oxide layer 42 of the trench 4 is more uniform.

[0077] like Figure 5 As shown, in a specific embodiment, the first direction A is the same as the third direction D, and the second direction B is the same as the fourth direction E. That is, the extension direction of the first trench 43 is the same as the extension direction of the first shielding structure 81(p), and the first trench 43 is parallel to the first shielding structure 81(p); the extension direction of the second trench 44 is the same as the extension direction of the second shielding structure 82(p), and the second trench 44 is parallel to the second shielding structure 82(p). In this embodiment, the shielding structures can be symmetrically arranged around the periphery of the trenches to achieve a more symmetrical and uniform protection effect, and to make the electric field of the gate oxide layer 42 of the trench 4 more uniform.

[0078] In a specific embodiment, at least one first shielding structure 81(p) can be provided between any two adjacent first trenches 43, and at least one second shielding structure 82(p) can be provided between any two adjacent second trenches 44. Alternatively, in a specific embodiment, the first trenches 43 and the first shielding structures 81(p) can be arranged alternately, and the second trenches 44 and the second shielding structures 82(p) can be arranged alternately. This technical solution ensures that no two first trenches 43 are directly adjacent, and similarly, no two second trenches 44 are adjacent, thereby reducing the electric field concentration of the gate oxide layer 42 in the trenches 4.

[0079] In other embodiments, the third direction D and the first direction A may not be the same, and the fourth direction E and the second direction B may also not be the same. However, the first angle between the third direction D and the first direction A is not limited, nor is the second angle between the fourth direction E and the second direction B. Furthermore, the first angle and the second angle may be the same or different, and this application does not impose any restrictions on this. For example... Figure 6 and Figure 7 In the illustrated embodiment, the first included angle and the second included angle are the same. Wherein, Figure 6 The first and second included angles are the same and are 45°. Figure 7 The first and second included angles are the same and are 30°.

[0080] Please continue to refer to this. Figure 1 The aforementioned shielding structure 8(p) extends along the fifth direction F, which is perpendicular to the first direction A and the second direction B. In other words, the shielding structure 8(p) is a linear structure along the fifth direction F, extending directly towards the semiconductor substrate 6(n+). In this scheme, the fabrication process of the shielding structure 8(p) is relatively simple; it can be fabricated directly by ion implantation. In this embodiment, the aforementioned trench 4 can also be considered to extend along the fifth direction F. That is, both the trench 4 and the shielding structure 8(p) extend towards the semiconductor substrate 6(n+), which also simplifies the semiconductor device fabrication process.

[0081] Figure 8 This is a schematic diagram of another structure of the semiconductor device in an embodiment of this application, as shown below. Figure 8 As shown, in another embodiment, the shielding structure 8(p) includes a first shielding portion 84 and a second shielding portion 85. The first shielding portion 84 extends along a fifth direction F, which is perpendicular to the first direction A and the second direction B. That is, the first shielding portion 84 has a linear structure along the fifth direction F, extending directly toward the semiconductor substrate 6(n+). The second shielding portion 85 is located at the end of the first shielding portion 84 facing the semiconductor substrate 6(n+). Figure 8 In the shown state, the second shielding portion 85 is located at the bottom of the first shielding portion 84. The second shielding portion 85 extends in a direction parallel to the surface of the semiconductor substrate 6(n+), forming a protruding edge of the first shielding portion 84. The first shielding portion 84 and the second shielding portion 85 can be considered as a single shielding structure 8(p), in which case the shielding structure 8(p) bends at the bottom of the gate oxide layer 42 towards the direction where the gate oxide layer 42 is located. In this embodiment, the first shielding portion 84 can protect the gate oxide layer 42 from all sides, reducing the influence of the surrounding environment on the gate oxide layer 42 and reducing the electric field concentration of the gate oxide layer 42; the second shielding portion 85 can extend from the gate oxide layer 42 towards the semiconductor substrate 6(n+) in the direction ( Figure 8 The shielding structure 8(p) in this embodiment can form a wrapping structure around the gate oxide layer 42 to effectively shield the gate oxide layer 42 from interference, reduce the electric field concentration of the gate oxide layer 42, and improve the reliability and lifespan of the semiconductor device.

[0082] In a specific technical solution, when both sides of the first shielding portion 84 have grooves 4, the second shielding portion 85 can be symmetrically arranged on both sides of the first shielding portion 84 to protect the gate oxide layer 42 on both sides. Alternatively, depending on actual product requirements, both sides of the first shielding portion 84 can have second shielding portions, but the second shielding portions 85 on both sides can be asymmetrically arranged. For example, if the distance between the grooves 4 on both sides of the first shielding portion 84 and the first shielding portion 84 is different, the second shielding portion 85 on the side closer to the groove 4 and the first shielding portion 84 will have a shorter extension direction, and the second shielding portion 85 on the side farther from the groove 4 and the first shielding portion 84 will have a longer extension direction. When the first shielding portion 84 has a groove 4 on only one side, the second shielding portion 85 can be provided only on the side of the first shielding portion 84 facing the groove 4.

[0083] Please continue to refer to this. Figure 8 In one embodiment, the semiconductor device includes a first semiconductor region 22 (P+) and a well region 23 (p), which are located in semiconductor layer 2. Specifically, the first semiconductor region 22 (P+) is a p-type semiconductor region, and the well region 23 (p) is also a p-type semiconductor region. The doping concentration of the first semiconductor region 22 (P+) is greater than the doping concentration of the shielding structure 8 (p). The well region 23 (p) is in contact with the shielding structure 8 (p), the source region 21 (n+), and the first semiconductor region 22 (P+), respectively. The first semiconductor region 22 (P+) is also in contact with the source electrode 1, thereby connecting the shielding structure 8 (p), the well region 23 (p), the first semiconductor region, and the source electrode 1 in sequence, thus grounding the shielding structure 8 (p). The well region 23(p) and the source region 21(n+) form a PN junction. The first semiconductor is in contact with the source 1. Then the first semiconductor region 22(P+) connects the well region 23(p) and the source region 21(n+), making the PN junction of the well region 23(p) and the source region 21(n+) short-circuited, thus preventing the PN junction from being turned on and conducting.

[0084] Please refer to Figure 8 In a specific embodiment, the first semiconductor region 22 (P+) and the source region 21 (n+) can be disposed on the same layer, and the first semiconductor region 22 (P+) and the source region 21 (n+) can be disposed alternately in sequence, and the well region 23 (p) can be disposed on the side of the first semiconductor region 22 (P+) and the source region 21 (n+) facing the drift region. Figure 9 This is a partial top view of a semiconductor device in an embodiment of this application, showing the orthographic projection relationship of the trench 4, shielding structure 8(p), first semiconductor region 22 (P+), and source region 21 (n+) onto the semiconductor substrate 6 (n+). Figure 8 and Figure 9As shown, when the first semiconductor region 22(P+) is specifically configured, the orthographic projection of the first semiconductor region 22(P+) onto the semiconductor substrate 6(n+) coincides with the orthographic projection of the overlapping area of ​​the first shielding structure 81(p) and the second shielding structure 82(p) onto the semiconductor substrate 6(n+). This overlapping area can be understood as the common area in the above embodiment. In this embodiment, the first semiconductor region 22(P+) and the peripheral source region 21(n+) can be in full contact, and the periphery of the first semiconductor region 22(P+) is all the source region 21(n+). Therefore, even if the mask is shifted during the fabrication of the first semiconductor region 22(P+), the first semiconductor region 22(P+) can still maintain contact with the source region 21(n+) and the source electrode 1.

[0085] Figure 10 This is another partial top view of the semiconductor device in an embodiment of this application, showing the orthographic projection relationship of the trench 4, shielding structure 8(p), first semiconductor region 22 (P+), and source region 21 (n+) onto the semiconductor substrate 6 (n+). Figure 10 As shown, when specifically configuring the first semiconductor region 22(P+), the orthographic projection of the first semiconductor region 22(P+) onto the semiconductor substrate 6(n+) can also be made to coincide with the orthographic projection of the shielding structure 8(p) onto the semiconductor substrate 6(n+). In other words, the first semiconductor region 22(P+) and the shielding structure 8(p) have the same shape. This scheme can utilize a single masking process to fabricate the first semiconductor region 22(P+) and the shielding structure 8(p) by adjusting the ion implantation power and parameters, thereby simplifying the semiconductor device fabrication process.

[0086] Of course, in other embodiments, the first semiconductor region 22 (P+) may also be independent of the shielding structure 8 (p), as long as it can make contact with each part. This application does not impose any restrictions on this.

[0087] The doping concentration of the well region 23(p) is lower than that of the first semiconductor region 22(P+). In this embodiment, the doping concentration of the p-type dopant in the well region 23(p) can be ensured to be not too high, thus ensuring that the channel is open and increasing the channel area.

[0088] In a specific embodiment, the doping concentration of the well region 23(p) is less than the doping concentration of the shielding structure 8(p). Specifically, the doping concentration of the shielding structure 8(p) can be 10 to 100 times that of the well region 23(p) to improve the shielding performance of the shielding structure.

[0089] Figure 11 This is a schematic diagram of another structure of the semiconductor device in an embodiment of this application, as shown below. Figure 11As shown, in another embodiment, the semiconductor device further includes a current diffusion layer 9(n), which is an n-type semiconductor region. The doping concentration of the current diffusion layer 9(n) is greater than that of the drift layer 5(n-) and less than that of the source region 21(n+). The current diffusion layer 9(n) is located on the drift layer 5(n-) and adjacent to the semiconductor layer 2. The current diffusion layer 9(n) has a certain thickness. Specifically, the distance between the surface of the current diffusion layer 9(n) facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+) is less than the distance between the surface of the trench 4 facing the semiconductor substrate 6(n+) and the semiconductor substrate 6(n+), so that the current diffusion layer 9(n) can cover the bottom of the trench 4. In this embodiment, the current diffusion layer 9(n) can reduce the diffusion current of the drift layer 5(n-) at the upper end.

[0090] This application also provides two methods for fabricating the semiconductor devices described in the above embodiments. Figure 12 This application provides a method for fabricating a semiconductor device, which specifically includes the following steps:

[0091] Step S101: An epitaxial layer is grown on the surface of an n-type semiconductor substrate 6(n+);

[0092] Specifically, the aforementioned semiconductor substrate can be a silicon carbide (SiC) substrate.

[0093] Step S102: Implant p-type dopant elements on the surface of the epitaxial layer to form a p-type well region;

[0094] Step S103: Prepare a first mask layer on the surface of the well region. The first mask layer exposes the region corresponding to the shielding structure 8(p). P-type dopant elements are implanted to form the shielding structure 8(p).

[0095] The material of the first mask layer is not limited; for example, it can be any one of silicon dioxide, polysilicon layer, nitride layer, or silicon nitride. A first opening in the first mask layer is formed using a dry etching process or a wet etching process. This first opening corresponds to the region where the shielding structure is located. Subsequently, p-type dopant elements can be implanted via ion implantation to form the shielding structure.

[0096] Step S104: Remove the first mask layer and prepare the second mask layer. The second mask layer exposes the region corresponding to the source region 21(n+). Implant n-type doped elements to form the source region 21(n+).

[0097] The material of the second mask layer is not limited; for example, it can be any one of silicon dioxide, polysilicon layer, nitride layer, or silicon nitride. A second opening in the second mask layer is formed using a dry etching process or a wet etching process. This second opening corresponds to the region where the source region is located. Subsequently, n-type dopant elements can be implanted via ion implantation to form the source region.

[0098] Step S105: Remove the second mask layer and prepare the third mask layer. The third mask layer exposes the area corresponding to the trench 4, and the trench 4 is formed by etching.

[0099] After removing the second mask layer, ion-activated annealing and surface cleaning can be performed to facilitate the fabrication of the third mask layer. The material of the third mask layer is not limited; for example, it can be any of silicon dioxide, a polysilicon layer, a nitride layer, or silicon nitride. A third opening in the third mask layer, corresponding to the area where the trench is located, is formed using either a dry etching process or a wet etching process. The trench can then be formed using a dry etching process.

[0100] Step S106: A gate oxide layer 42 is formed in the trench 4 using a high-temperature oxidation process;

[0101] Step S107: Deposit a gate 41 within the gate oxide layer 42;

[0102] Step S108: Sequentially prepare the gate insulating layer 3, the source electrode 1, and the drain electrode 7.

[0103] Figure 13 This application provides another method for fabricating a semiconductor device, which includes the following steps:

[0104] Step S201: An epitaxial layer is grown on the surface of an n-type semiconductor substrate 6(n+), wherein the first epitaxial layer is an n-type semiconductor layer 2;

[0105] Specifically, the aforementioned semiconductor substrate can be a silicon carbide (SiC) substrate.

[0106] Step S202: Prepare a first mask layer on the surface of the first epitaxial layer. The first mask layer exposes the region corresponding to the shielding structure 8(p). P-type dopant elements are implanted to form the shielding structure 8(p).

[0107] The material of the first mask layer is not limited; for example, it can be any one of silicon dioxide, polysilicon layer, nitride layer, or silicon nitride. A first opening in the first mask layer is formed using a dry etching process or a wet etching process. This first opening corresponds to the region where the shielding structure is located. Subsequently, p-type dopant elements can be implanted via ion implantation to form the shielding structure.

[0108] Step S203: Remove the first mask layer and grow a second epitaxial layer on the surface of the first epitaxial layer. The second epitaxial layer is a p-type semiconductor layer 2.

[0109] Step S204: Prepare a second mask layer on the surface of the second epitaxial layer. The second mask layer exposes the region corresponding to the source region 21(n+). Implant n-type doped elements to form the source region 21(n+).

[0110] The material of the second mask layer is not limited; for example, it can be any one of silicon dioxide, polysilicon layer, nitride layer, or silicon nitride. A second opening in the second mask layer is formed using a dry etching process or a wet etching process. This second opening corresponds to the region where the source region is located. Subsequently, n-type dopant elements can be implanted via ion implantation to form the source region.

[0111] Step S205: Remove the second mask layer and prepare the third mask layer. The third mask layer exposes the area corresponding to the trench 4, and the trench 4 is formed by etching.

[0112] After removing the second mask layer, ion-activated annealing and surface cleaning can be performed to facilitate the fabrication of the third mask layer. The material of the third mask layer is not limited; for example, it can be any of silicon dioxide, a polysilicon layer, a nitride layer, or silicon nitride. A third opening in the third mask layer, corresponding to the area where the trench is located, is formed using either a dry etching process or a wet etching process. The trench can then be formed using a dry etching process.

[0113] Step S206: A gate oxide layer 42 is formed in the trench 4 using a high-temperature oxidation process;

[0114] Step S207: Deposit gate 41 within gate oxide layer 42;

[0115] Step S208: Sequentially prepare the gate insulating layer 3, source 1, and drain 7.

[0116] Based on the same inventive concept, this application also provides an integrated circuit, which includes a circuit board and a semiconductor device as described in any of the above embodiments. The semiconductor device is disposed on the circuit board, and the shielding structure 8(p) in the semiconductor device can protect the gate oxide layer 42 from all sides to reduce the electric field concentration of the gate oxide layer 42, improve the breakdown voltage of the semiconductor device, and thus improve the reliability and device characteristics of the semiconductor device, thereby improving the performance and lifespan of the integrated circuit.

[0117] Based on the same inventive concept, this application also provides an electronic device, which includes a housing and the aforementioned integrated circuit, with the integrated circuit disposed in the housing. Specifically, the integrated circuit may be disposed inside or on the surface of the housing, and this application does not impose any limitations on this. The integrated circuit of this electronic device has better performance and a longer service life, thereby contributing to improved performance and lifespan of the electronic device.

[0118] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: n-type semiconductor substrate; A drift layer is disposed on the surface of the semiconductor substrate; A semiconductor layer is disposed on the surface of the drift layer away from the semiconductor substrate, and includes a source region, which is an n-type semiconductor region, and the source region is exposed on the side of the semiconductor layer away from the drift layer. A trench, wherein the opening of the trench is located on the surface of the semiconductor layer away from the drift layer, a gate is disposed in the trench, a gate oxide layer is disposed between the gate and the surface of the trench, and a gate insulating layer covers the opening of the trench and exposes the source region; A p-type shielding structure is disposed on the drift layer, and the shielding structure includes a plurality of first shielding structures and a plurality of second shielding structures. The first shielding structures extend along a first direction, and the second shielding structures extend along a second direction. The first direction and the second direction intersect, and the plurality of first shielding structures and the plurality of second shielding structures are arranged in a grid pattern. The source electrode is disposed on the side of the semiconductor layer away from the drift layer and is in contact with the source region and the gate insulating layer; The drain electrode is located on the side of the semiconductor substrate away from the drift layer. The trench includes a plurality of first trenches and a plurality of second trenches, the first trenches extending along a third direction, the second trenches extending along a fourth direction, the third direction and the fourth direction intersecting, and the plurality of first trenches and the plurality of second trenches being arranged in a grid pattern; At least one first shielding structure is provided between any two adjacent first trenches, and at least one second shielding structure is provided between any two adjacent second trenches.

2. The semiconductor device as claimed in claim 1, characterized in that, The first shielding structure is strip-shaped, and multiple first shielding structures are arranged in parallel and spaced apart by a first predetermined distance; the second shielding structure is strip-shaped, and multiple second shielding structures are arranged in parallel and spaced apart by a second predetermined distance.

3. The semiconductor device as described in claim 1, characterized in that, The first direction is the same as the third direction, and the second direction is the same as the fourth direction.

4. The semiconductor device as claimed in claim 1, characterized in that, The first direction is perpendicular to the second direction.

5. The semiconductor device as claimed in claim 1, characterized in that, The shielding structure extends along a fifth direction, which is perpendicular to the first and second directions.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The shielding structure includes a first shielding portion and a second shielding portion. The first shielding portion extends along a fifth direction, which is perpendicular to the first direction and the second direction. The second shielding portion is located at the end of the first shielding portion facing the semiconductor substrate, and the second shielding portion extends along a direction parallel to the surface of the semiconductor substrate, forming a convex edge of the first shielding portion.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a first semiconductor region and a well region located in the semiconductor layer, wherein the first semiconductor region is a p-type semiconductor region and the well region is also a p-type semiconductor region; the well region is in contact with the shielding structure, the source region and the first semiconductor region respectively, and the first semiconductor region is also in contact with the source electrode; the doping concentration of the first semiconductor region is greater than the doping concentration of the shielding structure.

8. The semiconductor device as claimed in claim 7, characterized in that, The orthographic projection of the first semiconductor region onto the semiconductor substrate coincides with the orthographic projection of the overlapping area of ​​the first shielding structure and the second shielding structure onto the semiconductor substrate.

9. The semiconductor device as claimed in claim 7, characterized in that, The orthographic projection of the first semiconductor region onto the semiconductor substrate coincides with the orthographic projection of the shielding structure onto the semiconductor substrate.

10. The semiconductor device as claimed in claim 7, characterized in that, The doping concentration of the well region is less than that of the first semiconductor region.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a current diffusion layer, which is an n-type semiconductor region. The current diffusion layer is located in the drift layer and adjacent to the semiconductor layer. The distance between the surface of the current diffusion layer facing the semiconductor substrate and the semiconductor substrate is less than the distance between the surface of the trench facing the semiconductor substrate and the semiconductor substrate.

12. The semiconductor device according to any one of claims 1 to 4, characterized in that, The distance between the surface of the shielding structure facing the semiconductor substrate and the semiconductor substrate is less than the distance between the surface of the trench facing the semiconductor substrate and the semiconductor substrate.

13. The semiconductor device according to any one of claims 1 to 4, characterized in that, The distance between the surface of the first shielding structure facing the semiconductor substrate and the semiconductor substrate is different from the distance between the surface of the second shielding structure facing the semiconductor substrate and the semiconductor substrate.

14. The semiconductor device according to any one of claims 1 to 4, characterized in that, The shielding structure is symmetrically arranged on the periphery of the trench.

15. An integrated circuit, characterized in that, Includes a circuit board and a semiconductor device disposed on the circuit board as described in any one of claims 1-14.

16. An electronic device, characterized in that, It includes a housing and an integrated circuit as described in claim 15, wherein the integrated circuit is disposed in the housing.

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