High-efficiency heterojunction solar cell and manufacturing method thereof

Abstract

The application discloses a kind of high-efficiency heterojunction solar cells and its manufacturing method, the battery includes: N-type silicon wafer, first intrinsic amorphous silicon layer, N-type doped layer and transparent conductive layer, metal grid line layer are sequentially arranged in the front of silicon wafer, second intrinsic amorphous silicon layer, P-type doped layer and transparent conductive layer, metal grid line layer are sequentially arranged in the back of silicon wafer.The N-type doped layer or / and P-type doped layer is multilayer composite structure, that is, including seed layer, microcrystalline silicon oxide layer and microcrystalline silicon layer multilayer composite structure;And specifically disclosed the manufacturing method of multilayer composite structure N-type doped layer and P-type doped layer.This multilayer composite structure has greater optical band gap to bring the short-circuit current of cell to be greatly promoted while the seed layer at the interface with intrinsic passivation layer improves thin film growth quality and passivation effect, the N-type microcrystalline silicon layer at the interface with TCO film forms good contact, so that the conversion efficiency of cell is obviously improved.

Description

Technical Field

[0001] This invention relates to the field of crystalline silicon solar cells, and more particularly to a high-efficiency heterojunction solar cell and its fabrication method. Background Technology

[0002] Heterojunction solar cells have simple manufacturing processes and low temperatures. They also offer advantages such as high power generation, high stability, no degradation, and low cost. With continuous technological advancements and policy support in the industry, heterojunction solar cells are showing their cost-effectiveness advantage and may replace crystalline silicon solar cells as the next generation of mainstream photovoltaic cells.

[0003] Currently, conventional heterojunction solar cells use N-type monocrystalline silicon wafers as substrates, with phosphorus-doped amorphous silicon N-layers serving as window layers on the light-receiving surface, resulting in higher conversion efficiency. To further improve the efficiency of heterojunction cells, existing technologies incorporate carbon dioxide into the amorphous silicon N-layers used as window layers to form N-type silicon-oxygen thin films with wider band gaps, thereby significantly increasing the short-circuit current. However, the addition of carbon dioxide increases the defect state density of the material, reduces conductivity, and consequently leads to a significant decrease in the cell fill factor. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a high-efficiency heterojunction solar cell and its fabrication method. By employing a multilayer composite structure with N-type doped layers and / or P-type doped layers, the effects of short-circuit current, open-circuit voltage, and fill factor can be simultaneously improved, resulting in a significant increase in cell efficiency.

[0005] To achieve the above objectives, the present invention provides a high-efficiency heterojunction solar cell, comprising: an N-type silicon wafer, wherein a first intrinsic amorphous silicon layer, an N-type doped layer, a front transparent conductive layer, and a front metal grid layer are sequentially disposed on the front side of the silicon wafer; and a second intrinsic amorphous silicon layer, a P-type doped layer, a back transparent conductive layer, and a back metal grid layer are sequentially disposed on the back side of the silicon wafer; characterized in that the N-type doped layer and / or the P-type doped layer is a multilayer composite structure; the N-type doped layer of the multilayer composite structure includes an N-face seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer; the P-type doped layer of the multilayer composite structure includes a P-face seed layer, a P-type microcrystalline silicon oxide layer, and a P-type microcrystalline silicon layer.

[0006] Furthermore, the thickness of the N-face seed layer is 1-4 nm; the thickness of the N-type microcrystalline silicon oxide layer is 4-8 nm; and the thickness of the N-type microcrystalline silicon layer is 1-4 nm.

[0007] Furthermore, the thickness of the P-side seed layer is 1-4 nm; the thickness of the P-type microcrystalline silicon oxide layer is 2-6 nm; and the thickness of the P-type microcrystalline silicon layer is 8-20 nm.

[0008] This invention also provides a method for fabricating a high-efficiency heterojunction solar cell, comprising the following steps:

[0009] We provide texturized and cleaned N-type silicon wafers;

[0010] A second intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer using PECVD.

[0011] A first intrinsic amorphous silicon layer is deposited on the front side of the silicon wafer by PECVD.

[0012] An N-type doped layer is formed on the first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD deposition of an N-type doped layer or by sequentially depositing an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer.

[0013] A multilayer composite layer structure P-type doped layer is formed on the second intrinsic amorphous silicon layer on the back side of the silicon wafer by PECVD deposition of a P-type doped layer or by sequentially depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer.

[0014] Transparent conductive layers were deposited on the N-type doped layer on the front side and the P-type doped layer on the back side of the silicon wafer by PVD magnetron sputtering.

[0015] Metal grid electrodes are fabricated on the transparent conductive layers on the front and back sides of the silicon wafer, respectively.

[0016] This invention also provides a back-contact heterojunction solar cell (HBC) comprising an N-type monocrystalline silicon wafer, wherein a pyramidal textured surface, an intrinsic amorphous silicon layer, and an anti-reflection layer are sequentially disposed on the front side of the silicon wafer. An intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer are sequentially disposed on the surface of the P-region on the back side of the silicon wafer. An intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer are sequentially disposed on the surface of the N-region on the back side of the silicon wafer. The N-type amorphous silicon layer is replaced by an N-type doped layer of the aforementioned multilayer composite structure, or / and the P-type amorphous silicon layer is replaced by a P-type doped layer of the multilayer composite structure.

[0017] The beneficial effects of the high-efficiency heterojunction solar cell and its fabrication method provided by this invention are as follows:

[0018] (1) Forming an undoped seed layer at the bottom of the N-type doped layer and / or P-type doped layer is beneficial to improving the quality of subsequent thin film growth, while reducing the passivation effect caused by the diffusion of doped impurities into the intrinsic passivation layer.

[0019] (2) The second layer is formed by introducing carbon dioxide doping to form an N-type microcrystalline silicon oxide layer or / and a P-type microcrystalline silicon oxide layer, which has a larger optical band gap, thereby increasing the absorption of light by the battery; it can bring greater band bending at the PN junction interface, thereby increasing the open circuit voltage of the battery.

[0020] (3) No carbon dioxide doping is performed on the third layer of the N-type doped layer or / and the P-type doped layer, which is beneficial to maintain good electrical contact with the subsequent TCO film and reduce the series resistance.

[0021] In summary, the high-efficiency heterojunction solar cell and its fabrication method provided by this invention employ a multi-layer composite structure for its N-type doped layer and / or P-type doped layer, namely, an N-face seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer composite layer, or a P-face seed layer, a P-type microcrystalline silicon oxide layer, and a P-type microcrystalline silicon oxide layer. The larger optical bandgap significantly increases the short-circuit current of the cell. Simultaneously, the seed layer at the interface with the intrinsic passivation layer improves the thin film growth quality and passivation effect. Furthermore, the N-type microcrystalline silicon layer and / or P-type microcrystalline silicon layer at the interface with the TCO thin film form good contact, resulting in a significant improvement in cell conversion efficiency. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0023] Figure 1 This is a schematic diagram of the structure of Example 1 of the high-efficiency heterojunction solar cell provided by the present invention.

[0024] Figure 2 This is a schematic diagram of the structure of Example 2 of the high-efficiency heterojunction solar cell provided by the present invention.

[0025] Figure 3 This is a schematic diagram of the structure of Example 3 of the high-efficiency heterojunction solar cell provided by the present invention.

[0026] Figure 4 A flowchart illustrating the fabrication method of the high-efficiency heterojunction solar cell provided by this invention.

[0027] Explanation of reference numerals: N-type silicon wafer 10, first intrinsic amorphous silicon layer 20, N-type doped layer 30, front transparent conductive layer 60-1, front metal gate layer 70-1, second intrinsic amorphous silicon layer 40, P-type doped layer 50, back transparent conductive layer 60-2, back metal gate layer 70-2, N-side seed layer 31, N-type microcrystalline silicon oxide layer 32, N-type microcrystalline silicon layer 33, P-side seed layer 51, P-type microcrystalline silicon oxide layer 52, P-type microcrystalline silicon layer 53. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] like Figure 1-3 As shown, the present invention provides a high-efficiency heterojunction solar cell, comprising: an N-type silicon wafer 10, wherein a first intrinsic amorphous silicon layer 20, an N-type doped layer 30, a front transparent conductive layer 60-1, and a front metal grid layer 70-1 are sequentially disposed on the front side of the silicon wafer 10; a second intrinsic amorphous silicon layer 40, a P-type doped layer 50, a back transparent conductive layer 60-2, and a back metal grid layer 70-2 are sequentially disposed on the back side of the silicon wafer 10; the N-type doped layer 30 and / or the P-type doped layer 50 are multilayer composite structures, wherein the N-type doped layer of the multilayer composite structure includes an N-face seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer; the P-type doped layer 50 of the multilayer composite structure includes a P-face seed layer 51, a P-type microcrystalline silicon oxide layer 52, and a P-type microcrystalline silicon layer 53.

[0030] The N-type silicon wafer is either a monocrystalline silicon wafer or a polycrystalline silicon wafer.

[0031] The thickness of the N-face seed layer 31 is 1-4 nm; the thickness of the N-type microcrystalline silicon oxide layer 32 is 4-8 nm; and the thickness of the N-type microcrystalline silicon layer 33 is 1-4 nm.

[0032] The thickness of the P-face seed layer 51 is 1-4 nm; the thickness of the P-type microcrystalline silicon oxide layer 52 is 2-6 nm; and the thickness of the P-type microcrystalline silicon layer 53 is 8-20 nm.

[0033] like Figure 4 As shown, the method for fabricating the high-efficiency heterojunction solar cell includes the following steps:

[0034] S01 provides texturized and cleaned N-type silicon wafers;

[0035] S02, a second intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer by PECVD;

[0036] S03, depositing the first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD;

[0037] S04, an N-type doped layer is deposited on the first intrinsic amorphous silicon layer on the front side of the silicon wafer by PECVD, or by sequentially depositing an N-face seed layer, an N-type microcrystalline silicon oxide layer and an N-type microcrystalline silicon layer to form a multi-layer composite structure N-type doped layer.

[0038] S05, a multi-layer composite structure P-type doped layer is formed by depositing a P-type doped layer on the second intrinsic amorphous silicon layer on the back side of the silicon wafer through PECVD or by sequentially depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer and a P-type microcrystalline silicon layer.

[0039] S06, transparent conductive layers are deposited on the N-type doped layer on the front side and the P-type doped layer on the back side of the silicon wafer by PVD magnetron sputtering;

[0040] S07, metal gate electrodes are fabricated on the transparent conductive layers on the front and back sides of the silicon wafer, respectively;

[0041] The process of depositing the N-face seed layer in step S04 and the process of depositing the P-face seed in step S05 involves introducing a mixed gas of silane and hydrogen, with a reaction gas pressure of 100-300 Pa.

[0042] The process of depositing the N-type microcrystalline silicon oxide layer in step S04 involves introducing a mixed gas of silane, phosphine, hydrogen, and carbon dioxide. The reaction gas pressure is 150-400 Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%.

[0043] In step S04, the process of depositing the N-type microcrystalline silicon layer involves introducing a mixed gas of silane, phosphine, and hydrogen. The reaction gas pressure is 150-400 Pa, and the ratio of phosphine to silane is 1%-10%.

[0044] In step S04, the preset film-forming temperature for PECVD is 150-250℃.

[0045] The process of depositing the P-type microcrystalline silicon oxide layer in step S05 involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane, diborane, hydrogen, and carbon dioxide. The reaction gas pressure is 150-400 Pa, the ratio of diborane to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%.

[0046] The process of depositing the P-type microcrystalline silicon layer in step S05 involves first setting the PECVD film formation temperature to 150-250℃, then introducing a mixed gas of silane, diborane, and hydrogen, with a reaction gas pressure of 150-400 Pa and a diborane to silane ratio of 1%-10%.

[0047] A back-contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, with a pyramidal textured surface, an intrinsic amorphous silicon layer, and an anti-reflection layer sequentially disposed on the front side of the silicon wafer. An intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer sequentially disposed on the P-region surface of the back side of the silicon wafer. An intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer sequentially disposed on the N-region surface of the back side of the silicon wafer. The N-type amorphous silicon layer is replaced by an N-type doped layer of the aforementioned multilayer composite structure, and / or the P-type amorphous silicon layer is replaced by a P-type doped layer of the aforementioned multilayer composite structure.

[0048] Example 1

[0049] like Figure 1As shown, a high-efficiency heterojunction solar cell includes: an N-type silicon wafer 10, with a first intrinsic amorphous silicon layer 20, an N-type doped layer 30, a front transparent conductive layer 60-1, and a front metal grid layer 70-1 sequentially disposed on the front side of the silicon wafer 10; and a second intrinsic amorphous silicon layer 40, a P-type doped layer 50, a back transparent conductive layer 60-2, and a back metal grid layer 70-2 sequentially disposed on the back side of the silicon wafer 10; both the N-type doped layer 30 and the P-type doped layer 50 are multilayer composite structures, wherein the N-type doped layer of the multilayer composite structure includes an N-face seed layer 31, an N-type microcrystalline silicon oxide layer 32, and an N-type microcrystalline silicon layer 33; and the P-type doped layer 50 of the multilayer composite structure includes a P-face seed layer 51, a P-type microcrystalline silicon oxide layer 52, and a P-type microcrystalline silicon layer 53.

[0050] The specific process for fabricating the high-efficiency heterojunction solar cell is as follows:

[0051] S01 provides an N-type silicon wafer that has been texturized and cleaned; the specific process involves forming a pyramidal textured surface on the surface of the N-type silicon wafer through a texturing and cleaning method, while maintaining cleanliness; the N-type silicon wafer is a monocrystalline silicon wafer.

[0052] S02, a second intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer of S01 by PECVD; the specific process is to introduce silane and hydrogen into the reaction chamber; the preset film formation temperature is 150-250℃; the reaction gas pressure is 30-150Pa; the deposition thickness is 5-10nm.

[0053] S03, depositing the first intrinsic amorphous silicon layer on the front side of the silicon wafer of S02 by PECVD; the specific process is to introduce silane and hydrogen into the reaction chamber; the preset film formation temperature is 150-250℃; the reaction gas pressure is 30-150Pa; the deposition thickness is 4-7nm.

[0054] S04, on the first intrinsic amorphous silicon layer on the front side of the silicon wafer S03, an N-face seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer are sequentially deposited by PECVD to form a multilayer composite N-type doped layer; the specific process is as follows: the preset film deposition temperature is 150-250℃; a mixture of silane and hydrogen gas is first introduced into the reaction chamber at a pressure of 100-300 Pa to deposit the first layer as a seed layer with a thickness of 1-4 nm; then a mixture of silane, phosphine, hydrogen, and carbon dioxide is introduced into the reaction chamber. A mixture of phosphine and hydrogen gas, with a phosphine to silane ratio of 1%-10% and a carbon dioxide to silane ratio of 50%-100%, is deposited at a reaction gas pressure of 150-400 Pa. A second layer, N-type microcrystalline silicon oxide, with a thickness of 4-8 nm, is deposited. Finally, a mixture of silane, phosphine, and hydrogen gas, with a phosphine to silane ratio of 1%-10% and a reaction gas pressure of 150-400 Pa, is introduced into the reaction chamber to deposit a third layer, N-type microcrystalline silicon, with a thickness of 1-4 nm. The deposition power density is 0.03-0.3 W / cm². 2 .

[0055] In step S05, a multilayer composite P-type doped layer is formed by depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer, and a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of the silicon wafer in step S04 using PECVD. Specifically, the film deposition temperature is preset to 150-250℃; a mixture of silane and hydrogen is first introduced into the reaction chamber at a pressure of 100-300 Pa to deposit the first layer as a P-face seed layer with a thickness of 1-4 nm; then a mixture of silane, diborane, hydrogen, and carbon dioxide is introduced into the reaction chamber. The reaction chamber contains a mixture of silane, diborane, and hydrogen, with a diborane to silane ratio of 1%-10% and a carbon dioxide to silane ratio of 50%-100%. The reaction gas pressure is 150-400 Pa. A second layer, a P-type microcrystalline silicon oxide layer with a thickness of 2-6 nm, is deposited. Finally, a mixture of silane, diborane, and hydrogen is introduced into the reaction chamber, with a diborane to silane ratio of 1%-10% and a reaction gas pressure of 150-400 Pa. A third layer, a P-type microcrystalline silicon layer with a thickness of 8-20 nm, is deposited. The deposition power density is 0.05-0.4 W / cm³. 2 .

[0056] S06, an ITO transparent conductive layer is deposited on the N-type doped layer on the front side and the P-type doped layer on the back side of the silicon wafer of S05 by PVD magnetron sputtering; the deposition thickness is 90-110nm.

[0057] S07, silver grid electrodes are fabricated on the transparent conductive layers on the front and back sides of the silicon wafer of S06 by screen printing.

[0058] Example 2

[0059] like Figure 2As shown, a high-efficiency heterojunction solar cell includes: an N-type silicon wafer 10, a first intrinsic amorphous silicon layer 20, an N-type doped layer 30, a front transparent conductive layer 60-1, and a front metal grid layer 70 sequentially disposed on the front side of the silicon wafer 10; a second intrinsic amorphous silicon layer 40, a P-type doped layer 50, a back transparent conductive layer 60-2, and a back metal grid layer 70-2 sequentially disposed on the back side of the silicon wafer 10; the N-type doped layer 30 is a multilayer composite structure, the multilayer composite N-type doped layer including an N-face seed layer 31, an N-type microcrystalline silicon oxide layer 32, and an N-type microcrystalline silicon layer 33.

[0060] The specific process for fabricating the high-efficiency heterojunction solar cell differs from that in Example 1 only in the following aspects:

[0061] S05 involves depositing a P-type doped layer on the second intrinsic amorphous silicon layer on the back side of the silicon wafer of S04 using PECVD. The specific process involves introducing diborane, silane, and hydrogen into the reaction chamber. The preset film formation temperature is 150-250℃, the reaction gas pressure is 30-150Pa, and the deposition thickness is 6-14nm.

[0062] Example 3

[0063] like Figure 3 As shown, a high-efficiency heterojunction solar cell includes: an N-type silicon wafer 10, a first intrinsic amorphous silicon layer 20, an N-type doped layer 30, a front transparent conductive layer 60-1, and a front metal grid layer 70 sequentially disposed on the front side of the silicon wafer 10; a second intrinsic amorphous silicon layer 40, a P-type doped layer 50, a back transparent conductive layer 60-2, and a back metal grid layer 70-2 sequentially disposed on the back side of the silicon wafer 10; the P-type doped layer 50 is a multilayer composite structure, which includes a P-side seed layer 51, a P-type microcrystalline silicon oxide layer 52, and a P-type microcrystalline silicon layer 53.

[0064] The specific process for fabricating the high-efficiency heterojunction solar cell differs from that in Example 1 only in the following aspects:

[0065] S04 involves depositing an N-type doped layer on the first intrinsic amorphous silicon layer on the front side of the S03 silicon wafer using PECVD. The specific process involves introducing phosphine, silane, and hydrogen into the reaction chamber. The preset film formation temperature is 150-250℃, the reaction gas pressure is 30-150Pa, and the deposition thickness is 4-7nm.

[0066] Example 4

[0067] A back-contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, with a pyramidal textured surface, an intrinsic amorphous silicon layer, and an anti-reflection layer sequentially disposed on the front side of the silicon wafer. An intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer sequentially disposed on the P-region surface of the back side of the silicon wafer. An intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer sequentially disposed on the N-region surface of the back side of the silicon wafer. The N-type amorphous silicon layer and the P-type amorphous silicon layer are respectively replaced by the multilayer composite layer structure described in Example 1, with an N-type doped layer and a P-type doped layer, and are fabricated using the same method.

[0068] Example 5

[0069] A back-contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, with a pyramidal textured surface, an intrinsic amorphous silicon layer, and an anti-reflection layer sequentially disposed on the front side of the silicon wafer. On the back side of the silicon wafer, on the surface of the P-region, are an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer. On the back side of the silicon wafer, on the surface of the N-region, are an intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer. Only the N-type amorphous silicon layer is replaced by an N-type doped layer of the multilayer composite layer structure described in Example 1, and is fabricated using the same method.

[0070] Example 6

[0071] A back-contact heterojunction solar cell (HBC) comprises an N-type monocrystalline silicon wafer, with a pyramidal textured surface, an intrinsic amorphous silicon layer, and an anti-reflection layer sequentially disposed on the front side of the silicon wafer. On the back side of the silicon wafer, on the surface of the P-region, are an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer. On the back side of the silicon wafer, on the surface of the N-region, are an intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal grid layer. Only the P-type amorphous silicon layer is replaced by a P-type doped layer of the multilayer composite layer structure described in Example 1, and is prepared using the same fabrication method.

[0072] Table 1 lists a comparison of the efficiency of the heterojunction solar cell provided by this invention and conventional heterojunction solar cells. The results show that the heterojunction solar cell provided by this invention exhibits superior electrical performance, as detailed below:

[0073]

[0074] In summary, the high-efficiency heterojunction solar cell and its fabrication method provided by this invention employ a multilayer composite structure for the N-type doped layer and / or P-type doped layer, namely, an N-face seed layer, an N-type microcrystalline silicon oxide layer, and a composite layer of N-type microcrystalline silicon oxide, or a P-face seed layer, a P-type microcrystalline silicon oxide layer, and a P-type microcrystalline silicon oxide layer. The larger optical bandgap significantly improves the short-circuit current of the cell. Simultaneously, the seed layer at the interface with the intrinsic passivation layer enhances the film growth quality and passivation effect, while the N-type microcrystalline silicon layer at the interface with the TCO film forms good contact, resulting in a significant improvement in cell conversion efficiency. Furthermore, this multilayer composite structure of N-type doped layer and / or P-type doped layer is also suitable for back-contact heterojunction solar cells (HBCs) and can be used to replace the existing N-type amorphous silicon layer or P-type amorphous silicon layer and its fabrication process in HBC cells.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-efficiency heterojunction solar cell, characterized in that: The high-efficiency heterojunction solar cell comprises: an N-type silicon wafer, wherein a first intrinsic amorphous silicon layer, an N-type doped layer, a front transparent conductive layer, and a front metal grid layer are sequentially disposed on the front side of the silicon wafer; a second intrinsic amorphous silicon layer, a P-type doped layer, a back transparent conductive layer, and a back metal grid layer are sequentially disposed on the back side of the silicon wafer; the N-type doped layer and / or the P-type doped layer are multilayer composite layer structures; the N-type doped layer of the multilayer composite layer structure includes an N-face seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer; the P-type doped layer of the multilayer composite layer structure includes a P-face seed layer, a P-type microcrystalline silicon oxide layer, and a P-type microcrystalline silicon layer; the thickness of the P-face seed layer is 1-4 nm; the thickness of the P-type microcrystalline silicon oxide layer is 2-6 nm; the thickness of the P-type microcrystalline silicon layer is 8-20 nm; the N-type microcrystalline silicon oxide layer and / or the P-type microcrystalline silicon oxide layer are formed by introducing carbon dioxide doping.

2. The high-efficiency heterojunction solar cell according to claim 1, further characterized in that: The thickness of the N-face seed layer is 1-4 nm; the thickness of the N-type microcrystalline silicon oxide layer is 4-8 nm; and the thickness of the N-type microcrystalline silicon layer is 1-4 nm.

3. The method for fabricating a high-efficiency heterojunction solar cell according to any one of claims 1-2, characterized in that: Includes the following steps: We provide texturized and cleaned N-type silicon wafers; A second intrinsic amorphous silicon layer is deposited on the back side of the silicon wafer by PECVD. A first intrinsic amorphous silicon layer is deposited on the front side of the silicon wafer by PECVD. On the first intrinsic amorphous silicon layer on the front side of the silicon wafer, an N-face seed layer, an N-type microcrystalline silicon oxide layer, and an N-type microcrystalline silicon layer are sequentially deposited by PECVD to form a multilayer composite layer structure N-type doped layer. A multilayer composite layer structure P-type doped layer is formed by sequentially depositing a P-face seed layer, a P-type microcrystalline silicon oxide layer, and a P-type microcrystalline silicon layer on the second intrinsic amorphous silicon layer on the back side of a silicon wafer via PECVD. Transparent conductive layers were deposited on the N-type doped layer on the front side and the P-type doped layer on the back side of the silicon wafer by PVD magnetron sputtering. Metal grid electrodes are fabricated on the transparent conductive layers on the front and back sides of the silicon wafer, respectively.

4. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, further characterized in that: The process of depositing the N-side seed layer and the P-side seed layer involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane and hydrogen at a reaction gas pressure of 100-300Pa.

5. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, further characterized in that: The process of depositing the N-type microcrystalline silicon oxide layer involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane, phosphine, hydrogen, and carbon dioxide. The reaction gas pressure is 150-400 Pa, the ratio of phosphine to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%.

6. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, further characterized in that: The process of depositing the N-type microcrystalline silicon layer involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane, phosphine, and hydrogen. The reaction gas pressure is 150-400 Pa, and the ratio of phosphine to silane is 1%-10%.

7. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, further characterized in that: The process of depositing the P-type microcrystalline silicon oxide layer involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane, diborane, hydrogen, and carbon dioxide. The reaction gas pressure is 150-400 Pa, the ratio of diborane to silane is 1%-10%, and the ratio of carbon dioxide to silane is 50%-100%.

8. The method for fabricating a high-efficiency heterojunction solar cell according to claim 3, further characterized in that: The process of depositing the P-type microcrystalline silicon layer involves first setting the PECVD film formation temperature to 150-250℃, and then introducing a mixed gas of silane, diborane, and hydrogen. The reaction gas pressure is 150-400 Pa, and the ratio of diborane to silane is 1%-10%.

9. A back-contact heterojunction solar cell (HBC) comprising an N-type monocrystalline silicon wafer, wherein a pyramidal textured surface, an intrinsic amorphous silicon layer, and an anti-reflection layer are sequentially disposed on the front side of the silicon wafer; an intrinsic amorphous silicon layer, a P-type doped layer of the multilayer composite structure as described in any one of claims 1 or 2, a transparent conductive film layer, and a metal grid layer are sequentially disposed on the surface of the N-region of the back side of the silicon wafer; and an intrinsic amorphous silicon layer, an N-type doped layer of the multilayer composite structure as described in any one of claims 1 or 2, a transparent conductive film layer, and a metal grid layer are sequentially disposed on the surface of the N-region of the back side of the silicon wafer.

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