Power transistor drive circuit for switching power supplies

Abstract

The application discloses a power tube driving circuit for a switching power supply, comprising: a fixed slope driving circuit for generating a gate driving signal for driving a power tube according to a pulse width modulation signal and a dead zone control signal; and a variable slope control circuit for judging whether the power tube is in a Miller platform by detecting a feedback signal of the gate driving signal, and adjusting the slope of the gate driving signal according to the judgment result, wherein the gate driving signal has a first slope and a second slope related to time when the power tube is turned on, and the second slope is increased relative to the first slope, so that the driving slope of the gate driving signal is adaptively adjusted according to the load current of the power tube during the power tube turning-on process, and the EMI performance of the circuit is considered while high-efficiency driving is realized.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and more specifically, to a power transistor drive circuit for a switching power supply. Background Technology

[0002] With the gradual maturation of switching power supply technology, EMI (Electromagnetic Interference) performance has become an unavoidable and one of the most difficult problems to solve in power supply systems.

[0003] Switching power supplies control the entire energy transfer process by controlling the turn-on and turn-off times of the power transistors through feedback, achieving high-efficiency, wide-range voltage conversion. The design of the drive circuit is related to the turn-on and turn-off delays of the power transistors, as well as the current and voltage stress on the power transistors. Long drive delays will lead to significant switching losses, affecting the transmission efficiency of the switching power supply system and introducing control errors. Furthermore, the large dv / dt and di / dt generated when the drive circuit turns the power transistors on or off will not only cause significant EMI noise interference, severely impacting the reliability of the chip, but also pose a significant challenge to the voltage withstand and overcurrent capabilities of the power transistors.

[0004] Traditional fixed-slope drive circuits generate high EMI interference during the rapid turn-on and turn-off of power transistors, while slowing down the turn-on and turn-off speeds results in efficiency loss, making them unsuitable for high-efficiency applications. Therefore, fixed-slope drive solutions cannot resolve the trade-off between efficiency loss caused by drive delay and EMI interference. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a power transistor drive circuit for switching power supplies that achieves high-efficiency driving without affecting the EMI performance of the switching power supply.

[0006] According to an embodiment of the present invention, a power transistor driving circuit for a switching power supply is provided, comprising: a fixed slope driving circuit for generating a gate driving signal for driving the power transistor based on a pulse width modulation signal and a dead-time control signal; and a variable slope control circuit for determining whether the power transistor is at a Miller plateau by detecting a feedback signal of the gate driving signal, and adjusting the slope of the gate driving signal according to the determination result, wherein when the power transistor is turned on, the gate driving signal has a time-related first slope and a second slope, and the second slope is increased relative to the first slope.

[0007] Optionally, when the power transistor is turned off, the gate drive signal has a time-dependent third slope, a fourth slope, and a fifth slope, wherein the fourth slope is decreasing relative to the third slope, and the fifth slope is increasing relative to the fourth slope.

[0008] Optionally, the fixed slope driving circuit includes: a logic gate module for obtaining a logic signal based on the pulse width modulation signal and the dead time control signal; a level conversion module for boosting the logic signal from the low power rail voltage domain to the high power rail voltage domain; a first logic control module for generating a switch signal, an on indication signal, and an off indication signal based on the boosted logic signal; and a first delay driving module for generating the gate drive signal based on the switch signal.

[0009] Optionally, the variable slope control circuit includes: a first slope control circuit, used to determine whether the power transistor is at a Miller plateau by detecting the feedback signal of the gate drive signal, and to generate an upward slope control signal based on the determination result and the turn-on indication signal; a second slope control circuit, used to compare the feedback signal of the gate drive signal with a set window voltage, and to generate a downward slope control signal based on the comparison result and the turn-off indication signal; and a charging / discharging circuit, used to adjust the slope of the gate drive signal according to the feedback of the upward slope control signal or the downward slope control signal.

[0010] Optionally, the first slope control circuit includes: a Miller plateau detection module, used to compare the feedback signal of the gate drive signal with a set threshold, and determine whether the power transistor is at the Miller plateau based on the comparison result; a second logic control module, used to receive the determination result and the on indication signal, and provide a first output signal based on the determination result and the on indication signal; and a second delay drive module, used to generate the pull-up slope control signal based on the first output signal.

[0011] Optionally, the second slope control circuit includes: a window comparator for comparing the feedback signal of the gate drive signal with the upper window voltage and the lower window voltage to obtain a comparison result; a third logic control module for receiving the comparison result, the turn-off indication signal, and the pull-up slope control signal, and providing a second output signal based on these three signals; and a third delay drive module for generating the pull-down slope control signal based on the second output signal.

[0012] Optionally, the first delay driving module, the second delay driving module, and the third delay driving module are all composed of several inverters connected in series.

[0013] Optionally, the Miller platform detection module includes: a first transistor, a sensing resistor, and a replica transistor of the same type as the power transistor, which are sequentially connected between the high power rail voltage domains. The control terminals of the first transistor and the replica transistor receive feedback signals from the gate drive signal, and the common node of the sensing resistor and the replica transistor is used to output the comparison result.

[0014] Optionally, the detection resistor is used to provide the set threshold.

[0015] Optionally, the detection resistor can be implemented using a reference current source.

[0016] Optionally, the logic gate module is implemented using NAND gates, and the NAND gates operate within the low power rail voltage domain.

[0017] Optionally, the charging and discharging circuit includes: a pull-up transistor and a pull-down transistor connected sequentially between the high power rail voltage domains, wherein the common node of the pull-up transistor and the pull-down transistor is connected to the gate drive signal, wherein the control terminal of the pull-up transistor receives the pull-up slope control signal, and the control terminal of the pull-down transistor receives the pull-down slope control signal.

[0018] Optionally, the window comparator is implemented using a Schmitt trigger with different thresholds.

[0019] The power transistor drive circuit of this invention uses a variable slope control circuit to detect changes in the gate drive signal of the power transistor. This enables adaptive adjustment of the drive slope of the gate drive signal according to the load current of the power transistor during the power transistor's turn-on and turn-off processes. This reduces circuit losses without introducing additional EMI noise interference, achieving high-efficiency drive while also considering the circuit's EMI performance. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 This is a schematic circuit diagram of an existing power transistor drive circuit used in switching power supplies.

[0022] Figure 2 The waveform diagram of the existing power transistor drive circuit is shown.

[0023] Figure 3 A schematic structural diagram of a power transistor drive circuit for a switching power supply provided by the present invention;

[0024] Figure 4A schematic structural diagram of a fixed-slope driving circuit and a variable-slope control circuit in a power transistor driving circuit for a switching power supply provided by the present invention.

[0025] Figure 5 A schematic circuit diagram of a power transistor drive circuit for a switching power supply provided by the present invention.

[0026] Figure 6 The waveform diagram of the power transistor drive circuit for a switching power supply provided by the present invention. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0028] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0029] This invention can be presented in various forms, some of which will be described below.

[0030] Figure 1 This section provides a schematic circuit diagram of an existing power transistor drive circuit for switching power supplies, using an example of a drive circuit applied to a Buck converter. Figure 1 As shown, the switching power supply 100 includes transistor M NH (Also known as a high-side transistor), transistor M NL (Also known as a low-side transistor), inductor Lo, load capacitance C LOAD Load resistance R LOAD The control circuit 101 and the drive circuits HDRV and LDRV.

[0031] Among them, the high-side transistor M NH and low-side transistor M NL The circuit is connected sequentially between the input voltage Vin and ground GND, with their common terminal forming a switching node SW. The first terminal of the inductor Lo is connected to the switching node SW, and the second terminal is connected to the output voltage Vo. The load capacitor C... LOAD and load resistance R LOAD It is connected between the output voltage Vo and ground GND.

[0032] Control circuit 101 adjusts the high and low level pulse widths of the PWM (Pulse Width Modulation) signal by the difference between the feedback output voltage Vo information and the preset value. The PWM signal passes through the upper and lower transistor drive circuits HDRV and LDRV to generate signals for driving the high-side transistor M. NH gate drive signal V HDRV and drive low-side transistor M NL gate drive signal V LDRV To control the high-side transistor M NH and low-side transistor M NL The opening or closing of the switch allows energy to be transferred through Vin to the switching node SW and then to the output terminal to maintain the stability of the output voltage Vo.

[0033] Although NMOS power transistors require bootstrap capacitors, they offer higher drive efficiency and smaller device size than PMOS power transistors, and are therefore often used as power switches in switching power supply systems. The following combines... Figure 2 Taking the HDRV driver circuit as an example, the operation of the existing driver circuit is explained. When the system is working normally, the high-side transistor M is required when the PWM signal generated by the control circuit 101 goes high. NH Enabled to ensure high-side transistor M NH and low-side transistor M NL There will be no through-flow between them, resulting in a large current, and a high-side transistor M is still needed. NH and low-side transistor M NL Set a dead time between them to ensure that the low-side transistor M NL After being turned off, the high-side transistor M NH Only then can it be activated.

[0034] Figure 2 The t0-t1 time period is the high-side transistor M NH and low-side transistor M NL Dead time between t1 and t2, during the time interval M on the upper tube NH Gate-source voltage V GS,H (i.e. V) HDRV -V SW The voltage gradually increases, at which point the gate-source voltage V... GS,H High-side transistor M not reached NH Turn-on threshold voltage V THN High-side transistor M NH When in the off state, the drain-source current I DS,H The current is 0, and the current generated by the pre-stage driver inverter circuit supplies the high-side transistor M. NH The gate-source capacitance Cgs is charged. At time t2, the high-side transistor M... NHGate-source voltage V GS,H The rise exceeds the activation threshold V THN High-side transistor M NH Drain-source current I DS,H With gate-source voltage V GS,H The gate-source voltage V gradually increases as it rises, until it reaches t3. GS,H The Miller plateau voltage Vmiller is reached, and the drain-source current I... DS,H I required to reach the load DSO During the time period t3-t4, the gate-source voltage V GS,H Maintaining the Miller plateau voltage, the voltage V at the switching node SW The current begins to rise, and at this point, due to di / dt and dv / dt, a drain-source current I will be generated. DS,H The spikes generated create EMI noise. At time t4, the switching node voltage V... SW The rise action is completed when the input voltage Vin is reached, and the gate-source voltage V GS,H Exiting the Miller platform, due to dv / dt, the switching node voltage V SW Voltage spikes are generated. During the time interval t4-t5, the gate-source voltage V... GS,H The voltage continues to rise, at which point the switching node voltage V... SW and drain-source current I DS,H It remains essentially unchanged until the gate-source voltage V GS,H Once the power rail BST-SW voltage is reached, the entire process of driving the upper transistor to turn on is complete, after which the high-side transistor M is driven. NH The process of closing is similar to that of opening, and will not be described in detail here.

[0035] Existing power transistor driving technologies generally employ a totem-pole structure, which uses an upper driver transistor and a lower driver transistor connected between the power rail voltage domains BST-SW to drive the power transistor. At the instant the upper driver transistor turns on, it uses its maximum current capability to drive the power transistor (e.g., the high-side transistor M). NH The gate capacitance (including gate-source capacitance and gate-drain capacitance) of the power transistor is charged, causing the power transistor to turn on rapidly. During the power transistor's turn-on process, the slope of its drain-source current rise is very large, i.e., di / dt is very large. A large di / dt will lead to a deterioration in the EMI performance of the switching power supply. On the other hand, slowing down the turn-on and turn-off time of the power transistor will increase the switching losses of the power transistor and reduce the efficiency of the switching power supply. Therefore, there is still a lot of room for improvement in the existing power transistor driving technology.

[0036] Figure 3This is a schematic structural diagram of the power transistor drive circuit for a switching power supply provided by the present invention. The power transistor drive circuit for a switching power supply provided by the present invention uses a PWM signal and a dead-time control signal Death to control the power transistor's on / off state. When both the PWM signal and the dead-time control signal Death are high, the power transistor is turned on (i.e., the power transistor is conducting); when the PWM signal is low, the power transistor is turned off (i.e., the power transistor is cut off). Figure 3 As shown, the power transistor drive circuit includes a fixed-slope drive circuit 200 and a variable-slope control circuit 300. The fixed-slope drive circuit 200 is used to generate a drive signal for the power transistor M based on the PWM signal and the dead-time control signal Death. NH gate drive signal V HDRV The variable slope control circuit 300 is used to detect the feedback signal V of the gate drive signal. HDRV_FB To determine whether the power transistor is at the Miller plateau, and to adaptively adjust the gate drive signal V based on the determination result. HDRV The slope. Furthermore, the power transistor drive circuit of the present invention utilizes a replica transistor to detect the Miller plateau voltage of the power transistor, and designs a suitable intervention threshold using a resistor to achieve the driving of the power transistor M... NH The process involves adaptive variable slope pull-up, while during the power transistor turn-off process, the gate drive signal V is detected. HDRV The threshold of the feedback signal is used to achieve variable slope pull-down, thereby completing the entire variable slope drive to turn on and off the power transistor. This improves the system's energy transfer efficiency while reducing the EMI noise interference. At the same time, the variable slope drive scheme can also ensure that the high-side and low-side power transistors will not be coupled to turn on during the turn-on or turn-off process, avoiding the generation of large current.

[0037] Furthermore, in turning the power transistor M on and off... NH During the process, the gate drive signal V HDRV It has multiple slopes that are time-dependent. When the power transistor M is turned on... NH At that time, the gate drive signal V HDRV It has a first slope and a second slope, with the second slope being larger than the first slope, thus enabling the power transistor M to be quickly turned on after it crosses the Miller plateau voltage. NH This reduces transmission loss. When the power transistor M is turned off... NH At that time, the gate drive signal V HDRV It has a third slope, a fourth slope and a fifth slope, and the fourth slope is reduced relative to the third slope and the fifth slope, thereby reducing EMI noise interference caused by current spikes when the power transistor is near the Miller plateau, and shortening the drive delay and improving efficiency after crossing the Miller plateau.

[0038] Please see Figure 4The fixed-slope driving circuit 200 includes: a logic gate module 201, a level shifting module 202, a first logic control module 203, and a first delay driving module 204. The logic gate module 201 is used to obtain a logic signal based on the PWM signal and the dead-time control signal Death, wherein the logic gate module 201 is used to obtain the logic signal based on the NAND logic between the PWM signal and the dead-time control signal Death. The level shifting module 202 is used to boost the logic signal in the low power rail voltage domain to the high power rail voltage domain, wherein the low power rail voltage domain is from the low power supply voltage VDDD to ground level GNDD, and the high power rail voltage domain is from the bootstrap voltage BST to the switching node SW. The first logic control module 203 is used to generate a switching signal S0, an on indication signal S1, and an off indication signal S2 based on the boosted logic signal. The first delay driving module 204 is used to generate a driving signal for the power transistor M based on the switching signal S0. NH gate drive signal V HDRV .

[0039] The variable slope control circuit 300 includes: a first slope control circuit 301, a second slope control circuit 302, and a charging / discharging circuit 303. The first slope control circuit 301 is used to detect the feedback signal V of the gate drive signal. HDRV_FB Determine the power transistor M NH Whether it is at the Miller plateau, and based on the judgment result and the enable indication signal S1, generate the pull-up slope control signal Fast_up. The second slope control circuit 302 is used to convert the feedback signal V of the gate drive signal into a value. HDRV_FB The voltage is compared with a set window voltage, and a pull-down slope control signal Fast_down is generated based on the comparison result and the shutdown indication signal S2. The charging / discharging circuit 303 is used to increase the power transistor M based on the pull-up slope control signal Fast_up or the pull-down slope control signal Fast_down. NH The gate capacitor charging current or discharging current can be adjusted in the power transistor M. NH Adaptive adjustment of the gate drive signal V during the turn-on and turn-off process HDRV The slope.

[0040] Furthermore, the first slope control circuit 301 includes a Miller plateau detection module 311, a second logic control module 312, and a second delay drive module 313. The Miller plateau detection module 311 is used to detect the feedback signal V of the gate drive signal. HDRV_FB The value is compared with a set threshold, and the power transistor M is determined based on the comparison result. NHWhether it is on the Miller platform. The second logic control module 312 receives the judgment result and the on indication signal S1, and obtains a first output signal based on the two. The second delay drive module 313 is used to obtain the pull-up slope control signal Fast_up based on the first output signal.

[0041] Furthermore, the second slope control circuit 302 includes a window comparator 321, a third logic control module 322, and a third delay drive module 323. The window comparator 321 is used to convert the feedback signal V of the gate drive signal into a window comparator. HDRV_FB The comparison is performed with the upper limit voltage VTH1 and the lower limit voltage VTH2 of the window to obtain a comparison result. The third logic control module 322 receives the comparison result, the shutdown indication signal S2, and the pull-up slope control signal Fast_up, and provides a second output signal based on these three signals. The third delay drive module 323 is used to generate the pull-down slope control signal Fast_down based on the second output signal.

[0042] Figure 5 A schematic circuit diagram of a power transistor drive circuit for a switching power supply provided by the present invention. (See diagram below.) Figure 5 As shown, the logic gate module 201 is implemented, for example, through a NAND gate circuit. The first input terminal of the NAND gate is used to receive the PWM signal, the second input terminal is used to receive the dead-time control signal Death, and the output terminal is used to output the logic signal. The first delay drive module 204 is implemented, for example, through a drive chain composed of several cascaded inverters. Specifically, the upper drive transistor M... P1 and the lower drive transistor M N1 The first-stage inverter and the upper drive transistor M are constructed P2 and the lower drive transistor M N2 The second-stage inverter and the upper drive transistor M are constructed. P3 and the lower drive transistor M N3 This forms the third stage inverter. The upper drive transistor M... P1 and the lower drive transistor M N1 The gate of the first-stage inverter is connected to the output of the first logic control module 203, and the upper driving transistor M P3 and the lower drive transistor M N3 The drain of the inverter is used as the output terminal of the third-stage inverter to output the gate drive signal V. HDRV This three-stage drive chain provides sufficient driving capability, meaning it can supply a sufficiently large current to the power transistor M. NH The gate capacitor charging and discharging path ensures driving speed and efficiency.

[0043] Furthermore, the Miller platform detection 311 includes transistor M. PMDetection resistor Rc and replica transistor M NH,copy Transistor M PM Detection resistor Rc and replica transistor M NH,copy Transistor M is sequentially connected between the high power rail voltage domains BST-SW. PM and replicating transistor M NH,copy The control terminal and the inverted signal V of the gate drive signal HDRV_FB Connection, detection resistor Rc and the replicated transistor M NH,copy The common node is used to output the comparison result. Among them, the replicated transistor M... NH,copy With power transistor M NH Under the same state and type, it is used to replicate power transistor M. NH The process of the gate-source voltage being at the Miller plateau during power-on is thus obtained for power transistor M. NH The Miller plateau voltage increases with the increase of load current. A threshold is set by the sensing resistor Rc. When the Miller plateau voltage rises to the threshold, the Miller plateau detection module 311 provides the detection result to the subsequent stage.

[0044] Furthermore, without considering the static power consumption of the bootstrap voltage BST, the sensing resistor Rc can be replaced by a pull-up load with a reference current, which can achieve a more accurate sensing effect.

[0045] Furthermore, the second delay drive module 313 is implemented through a two-stage drive chain consisting of several cascaded inverters. Specifically, the upper drive transistor M... P5 and the lower drive transistor M N5 The first-stage inverter and the upper drive transistor M are constructed P6 and the lower drive transistor M N6 This forms the second-stage inverter. The upper driving transistor M... P5 and the lower drive transistor M N5 The gate of the first-stage inverter is connected to the output of the second logic control module 312, and the upper driving transistor M P6 and the lower drive transistor M N6 The drain of the inverter is used as the output terminal of the second-stage inverter to output the pull-up slope control signal Fast_up.

[0046] Furthermore, the window comparator 321 is implemented, for example, by Schmitt triggers 3211 and 3212 with different thresholds, the inputs of which are used to receive the feedback signal V of the gate drive signal. HDRV_FB The output terminal is connected to the third logic control module 322, and the Schmitt trigger 3211 is used to convert the feedback signal V of the gate drive signal. HDRV_FBThe Schmitt trigger 3212 compares the gate drive signal with the upper limit voltage VTH1, and then converts the feedback signal V of the gate drive signal into a signal that is equal to the upper limit voltage VTH1 of the window. HDRV_FB It is compared with the lower limit voltage VTH2 of the window, and the upper limit voltage VTH1 of the window is greater than the lower limit voltage VTH2 of the window.

[0047] Furthermore, the third delay drive module 323 includes a two-stage drive chain, specifically including the upper drive transistor M. P7 and the lower drive transistor M N7 The first-stage inverter and the upper drive transistor M are constructed P8 and the lower drive transistor M N8 This forms the second-stage inverter. The upper driving transistor M... P7 and the lower drive transistor M N7 The gate of the first-stage inverter is connected to the output of the third logic control module 322, and the upper driving transistor M is used as the input terminal of the first-stage inverter. P8 and the lower drive transistor M N8 The drain of the inverter serves as the output of the second-stage inverter, used to output the pull-down slope control signal Fast_down.

[0048] Furthermore, the charging / discharging circuit 303 includes an upper driving transistor M. P4 and the lower drive transistor M N4 upper drive transistor M P4 and the lower drive transistor M N4 Connected sequentially between the high power rail voltage domains BST-SW, their common node is connected to the gate drive signal V. HDRV Connection, upper drive transistor M P4 The gate of the lower drive transistor M is connected to the pull-up slope control signal Fast_up. N4 The gate of the transistor is connected to the pull-down slope control signal Fast_down. Furthermore, the pull-up slope control signal Fast_up is active low; when Fast_up toggles to low, the upper drive transistor M... P4 Turning on the transistor increases the power of the transistor M. NH The charging current of the gate capacitor increases the power transistor M NH The pull-down slope control signal Fast_down is active high. When the pull-down slope control signal Fast_down toggles to high, the drive transistor M is activated. N4 Turning on the transistor increases the power of the transistor M. NH The discharge current of the gate capacitor increases the power transistor M NH The shut-off slope.

[0049] During operation, when the PWM signal flips to a high level and the dead-time control signal Death flips to a high level, the switching signal S0 and the on-indication signal S1 output by the first logic control module 203 flip to a high level, and the off-indication signal S2 flips to a low level. The existence of dead time ensures that under normal logic control, only one of the high-side transistor and the low-side transistor of the switching power supply can be turned on at any given time, and also includes auxiliary control to ensure that the high-side transistor can be turned on and off normally. The first delay drive module 204 converts the high-level switching signal S0 into a gate drive signal V. HDRV To drive the power transistor M NH At this time, the load current is low, the switching node voltage SW is low, and the inductor current of the switching power supply is mainly provided by the freewheeling current of the low-side transistor. The power transistor M... NH The Miller plateau voltage is less than the threshold set by the sensing resistor Rc, therefore both the pull-up slope control signal Fast_up and the pull-down slope control signal Fast_down are invalid, and the gate drive signal V... HDRV The slope is relatively small to minimize spikes caused by sudden current changes, thereby avoiding EMI noise interference. As the load current gradually increases, the switching node voltage SW gradually moves away from the low position, and the inductor current is mainly provided by the high-side transistor of the switching power supply. When the reverse recovery current of the down-side freewheeling diode has decreased to zero, the power transistor M... NH When the Miller plateau voltage rises to the threshold set by the sensing resistor Rc, the pull-up slope control signal Fast_up flips to low, and the drive transistor M... P4 Turn on, increase the gate drive signal V HDRV The rising slope reduces transmission loss, and the overall goal is to adaptively change the drive slope according to the load current.

[0050] When the PWM signal toggles to low, the pull-down slope control signal Fast_down toggles to high, driving transistor M... N4 Turn on, increase the power transistor M NH The gate capacitor discharge current, when the feedback signal V of the gate drive signal... HDRV_FB When the voltage drops to the upper limit of the window voltage VTH1, it characterizes the power transistor M. NH Approaching the Miller plateau, to avoid significant EMI noise interference from current spikes, the pull-down slope control signal Fast_down toggles to a low level, turning off the lower drive transistor M. N4 gate drive signal V HDRV Switch to a smaller slope. When the feedback signal V of the gate drive signal... HDRV_FB When the voltage drops to the lower limit of the window voltage VTH2, it characterizes the power transistor M. NH After crossing the Miller plateau, the pull-down slope control signal Fast_down flips to high again, turning on the lower drive transistor M.N4 Increase the power transistor M NH The gate capacitor discharge current completes the entire driving process. Thus, the pull-up slope control circuit 301 and the pull-down slope control circuit 302 detect the power transistor M. NH The change in gate voltage is realized in the power transistor M NH Controlling the gate charging / discharging current during turn-on and turn-off also enables control of the drain current slope (di / dt) of the power transistor MNH, improving EMI performance without adding extra losses.

[0051] Figure 6 The diagram shows the operating waveforms of the power transistor drive circuit for a switching power supply provided by this invention. Figure 6 In the middle, V SW I represents the switching node voltage in a switching power supply. DS,H Indicates power transistor M NH Drain current, V HDRV -V SW Indicates power transistor M NH The Miller plateau voltage is defined by PWM, which represents the received pulse width modulation signal. Fast_up represents the pull-up slope control signal, which is active low. Fast_down represents the pull-down slope control signal, which is active high. The t0-t3 time period is the same as the existing control scheme and will not be described further. During the t3-t5 time period, the power transistor M... NH At the Miller plateau, at time t4, the pull-up slope control signal Fast_up toggles to a low level, causing the upper drive transistor M... P4 Turn on, increase the power transistor M NH The charging current of the gate capacitor causes the gate drive signal V to... HDRV The driving slope increases, thereby shortening the power transistor M. NH The time spent on the Miller plateau, while shortening the V of the t5-t6 time period. GS,H The time required to reach the high power rail voltage domain is reduced, thereby shortening the drive delay. This is achieved in power transistor M... NH During the turn-off process, the slope control signal Fast_down flips to a high level during the time interval t7-t9, causing the lower drive transistor M to... N4 Turn on, increase the power transistor M NH The discharge current of the gate capacitor increases the gate drive signal V. HDRV The drive slope. During the time period t9-t11, the power transistor M... NH Once back at the Miller plateau, a significant current spike will generate EMI noise interference to the system. The pull-down slope control circuit 302 toggles the pull-down slope control signal Fast_down to a low level, causing the lower drive transistor M...N4 Turning off reduces EMI noise generation; after time t11, power transistor M... NH Crossing the Miller plateau, the pull-down slope control circuit 302 flips the pull-down slope control signal Fast_down to a high level, further increasing the gate drive signal V. HDRV The decreasing slope shortens the power transistor M NH Current and gate-source voltage V GS,H The time it takes for the voltage to drop to zero reduces drive delay and avoids significant EMI noise interference. Simultaneously, by keeping the pull-down slope control signal Fast_down high during the low-side power transistor's turn-on process, it prevents the gate-source voltage Vo of the high-side transistor from being affected by the gate-source capacitance of the high-side transistor during low-side transistor turn-on. GS,H Coupling lifts the high-side transistor, thus turning it on and preventing the risk of through-through between the upper and lower transistors.

[0052] The switching losses caused by the power transistor drive circuit in this embodiment of the invention are mainly due to Figure 6 The time periods t2-t4 and t7-t9, which are the drain current rise time and Miller plateau time periods, can be expressed as follows:

[0053]

[0054] Since the generation of EMI noise is positively correlated with current spikes, after adopting the power transistor drive circuit of this embodiment, under the same load conditions, the rise time of the drain current remains unchanged during the process of driving the power transistor to turn on. However, the time spent on the Miller plateau is shortened due to the increase in the drive slope. During the process of driving the power transistor to turn off, both the time spent on the Miller plateau and the current drop time are shortened due to the variable slope drive. At the same time, the increase in the slope of the gate drive signal in this embodiment avoids the time when current spikes are generated, so it will not bring additional EMI noise interference. It achieves high-efficiency drive while taking into account the EMI performance of the circuit.

[0055] It should be noted that although the above embodiments use the high-side transistor in a switching power supply as an example, the power transistor driving circuit of this invention is also applicable to the low-side transistor in a switching power supply. The power rail and Miller plateau voltage detection transistor used for driving the low-side transistor need to be connected to the low-side transistor M. NL Correspondingly, the power transistor drive circuit of this embodiment is applicable to various synchronous rectification architectures integrated on-chip, including Buck, Boost, and Buck-Boost power transistors.

[0056] In summary, the power transistor drive circuit of this embodiment uses a variable slope control circuit to detect changes in the gate drive signal of the power transistor. This enables adaptive adjustment of the drive slope of the gate drive signal according to the load current of the power transistor during the power transistor's turn-on and turn-off processes. This reduces circuit losses without introducing additional EMI noise interference, achieving high-efficiency drive while also considering the circuit's EMI performance.

[0057] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0058] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A power transistor drive circuit for a switching power supply, comprising: A fixed slope drive circuit is used to generate a gate drive signal for driving the power transistor based on the pulse width modulation signal and the dead time control signal. as well as A variable slope control circuit is used to determine whether the power transistor is at a Miller plateau by detecting the feedback signal of the gate drive signal, and to adjust the slope of the gate drive signal according to the determination result. Specifically, when the power transistor is turned on, the gate drive signal has a first slope and a second slope that are time-related, and the second slope is increasing relative to the first slope. The fixed slope driving circuit includes: The logic gate module is used to obtain a logic signal based on the pulse width modulation signal and the dead-time control signal; A level shifting module is used to boost the logic signal that is in the low power rail voltage domain to the high power rail voltage domain. The first logic control module is used to generate a switch signal, an on indication signal, and an off indication signal based on the enhanced logic signal; and The first delay driving module is used to generate the gate driving signal based on the switching signal.

2. The power transistor drive circuit according to claim 1, wherein, When the power transistor is turned off, the gate drive signal has a time-dependent third slope, a fourth slope, and a fifth slope, wherein the fourth slope is decreasing relative to the third slope, and the fifth slope is increasing relative to the fourth slope.

3. The power transistor drive circuit according to claim 2, wherein, The slope control circuit includes: The first slope control circuit is used to determine whether the power transistor is at the Miller plateau by detecting the feedback signal of the gate drive signal, and to generate a pull-up slope control signal based on the determination result and the turn-on indication signal. The second slope control circuit is used to compare the feedback signal of the gate drive signal with a set window voltage, and generate a pull-down slope control signal based on the comparison result and the turn-off indication signal; and A charging and discharging circuit is used to adjust the slope of the gate drive signal based on the pull-up slope control signal or the pull-down slope control signal.

4. The power transistor drive circuit according to claim 3, wherein, The first slope control circuit includes: The Miller platform detection module is used to compare the feedback signal of the gate drive signal with a set threshold, and determine whether the power transistor is on the Miller platform based on the comparison result; The second logic control module receives the judgment result and the activation indication signal, and provides a first output signal based on the judgment result and the activation indication signal; and The second delay driving module is used to generate the pull-up slope control signal based on the first output signal.

5. The power transistor drive circuit according to claim 4, wherein, The second slope control circuit includes: A window comparator is used to compare the feedback signal of the gate drive signal with the upper limit voltage and the lower limit voltage of the window to obtain a comparison result; The third logic control module receives the comparison result, the shutdown indication signal, and the pull-up slope control signal, and provides a second output signal based on these three signals; and The third delay drive module is used to generate the pull-down slope control signal based on the second output signal.

6. The power transistor drive circuit according to claim 5, wherein, The first delay driver module, the second delay driver module, and the third delay driver module are all composed of several inverters connected in series.

7. The power transistor drive circuit according to claim 4, wherein, The Miller platform detection module includes: A first transistor, a sense resistor, and a replica transistor of the same type as the power transistor are sequentially connected between the high power rail voltage domains. The control terminals of the first transistor and the replica transistor receive feedback signals from the gate drive signal, and the common node of the detection resistor and the replica transistor is used to output the comparison result.

8. The power transistor drive circuit according to claim 7, wherein, The detection resistor is used to provide the set threshold.

9. The power transistor drive circuit according to claim 8, wherein, The detection resistor can be implemented using a reference current source.

10. The power transistor drive circuit according to claim 1, wherein, The logic gate module is implemented using NAND gates, and the NAND gates operate within the low power rail voltage domain.

11. The power transistor drive circuit according to claim 3, wherein, The charging and discharging circuit includes: A pull-up transistor and a pull-down transistor are sequentially connected between the high power rail voltage domains, and the common node of the pull-up transistor and the pull-down transistor is connected to the gate drive signal. The control terminal of the pull-up transistor receives the pull-up slope control signal, and the control terminal of the pull-down transistor receives the pull-down slope control signal.

12. The power transistor drive circuit according to claim 5, wherein, The window comparator is implemented using Schmitt triggers with different thresholds.

Images