Ultrasonic transducer excitation circuit and ultrasonic treatment device

Abstract

This invention provides an ultrasonic transducer excitation circuit and an ultrasonic therapy device. The ultrasonic transducer excitation circuit includes a clock signal generation circuit, a full-bridge dead-time control circuit, and a full-bridge power amplifier circuit. The clock signal generation circuit outputs two excitation clock signals with a 180° phase difference from each other at its first and second signal output terminals. The full-bridge dead-time control circuit includes a first OR gate, a first AND gate, a second OR gate, and a second AND gate. The first OR gate controls the first half-bridge circuit of the full-bridge power amplifier circuit, the first AND gate controls the NMOS transistors in the first half-bridge circuit, the second OR gate controls the PMOS transistors in the second half-bridge circuit, and the second AND gate controls the NMOS transistors in the second half-bridge circuit. Applying this ultrasonic transducer excitation circuit avoids the drawback of simultaneous conduction of PMOS and NMOS transistors and prevents excessively long dead times, thus improving output efficiency.

Description

Technical Field

[0001] This invention relates to the field of ultrasonic therapy equipment technology, specifically to an ultrasonic transducer excitation circuit, and also to an ultrasonic therapy device using the ultrasonic transducer excitation circuit. Background Technology

[0002] Ultrasonic therapy devices treat the human body primarily by using high-voltage pulse signals inside the device to excite an ultrasonic transducer. The transducer's piezoelectric effect converts the electrical signal into a mechanical wave, which is then propagated to the human tissue through a coupling process. This allows the three major effects of ultrasonic energy to be applied to the human tissue, achieving the therapeutic purpose.

[0003] Ultrasonic transducers are typically excited using a half-bridge or single MOS transistor. Half-bridge excitation is further divided into high-voltage direct excitation and low-voltage resonant excitation. High-voltage direct excitation uses a pair of PMOS and NMOS transistors. The PMOS transistor is directly connected to a high voltage for charging, while the NMOS transistor is connected to a low voltage or ground for discharging. The two transistors are driven by an in-phase signal to excite the ultrasonic transducer. Low-voltage resonant excitation is mainly achieved using two NMOS transistors. Inverted dual-path excitation signal outputs are used to turn on both NMOS transistors, resulting in a low-voltage square wave output. Then, through LC resonance, the excitation signal is boosted into a high-voltage pulse.

[0004] Half-bridge drive circuits use dual-transistor drive, with one MOSFET responsible for charging and the other for discharging. This ensures both driving efficiency and a higher safety factor. Even if one MOSFET fails, the other will remain off in the idle state, preventing further circuit damage. The drawback is that the drive signals of both MOSFETs can simultaneously conduct during transitions, easily burning them out. For low-voltage resonant excitation, mature low-side drive chips are available. These chips introduce a nanosecond delay between the drive signals of the two MOSFETs to prevent simultaneous conduction and ensure excitation safety. However, this method is limited by chip manufacturing processes, restricting the input voltage. Therefore, LC resonance is used to increase the amplitude of the drive signal. LC resonant circuits have a high Q value; when the transducer contacts the human body, its impedance changes, and the resonant frequency changes accordingly. Changing the excitation frequency reduces the amplitude of the LC resonant waveform, resulting in lower output ultrasonic energy. For high-voltage direct excitation, a common approach is to connect a PMOS transistor to a positive high voltage and an NMOS transistor to a negative voltage or ground to achieve a square wave output. This scheme produces a consistent amplitude excitation waveform that doesn't change with frequency variations. However, current chip manufacturing processes lack drive control chips capable of excitation voltages exceeding several hundred volts. Therefore, capacitor-blocked DC or transformer-transmitted methods are used to separately conduct the PMOS and NMOS transistors to achieve the square wave output. This circuit is relatively simple and offers good amplitude consistency. However, due to the lack of a specific drive chip, an FPGA is typically used to implement dual-channel excitation signal output and dead-time control. Since the minimum dead time is the FPGA's clock pulse width, typically ranging from several hundred to tens of nanoseconds, an excessively long dead time can cause waveform distortion and reduce output efficiency. This solution is costly and its performance is not ideal.

[0005] Meanwhile, the half-bridge drive circuit can only drive the transducer with a waveform that does not exceed the positive high voltage amplitude. For transducers that require higher voltage drive, there is no other way but to increase the positive high voltage amplitude. However, increasing the voltage amplitude will affect the performance of the MOSFET and reduce its lifespan. Summary of the Invention

[0006] The primary objective of this invention is to provide an ultrasonic transducer excitation circuit that avoids the drawback of simultaneous conduction of PMOS and NMOS transistors, ensures the service life of the MOS transistors, and prevents excessively long dead time, thereby improving output efficiency.

[0007] The second objective of this invention is to provide an ultrasound therapy device that avoids the drawbacks of simultaneous conduction of PMOS and NMOS transistors, ensures the service life of MOS transistors, avoids excessively long dead time, and improves output efficiency.

[0008] To achieve the aforementioned first objective, the ultrasonic transducer excitation circuit provided by the present invention includes a clock signal generation circuit, a full-bridge dead-time control circuit, and a full-bridge power amplifier circuit. The clock signal generation circuit is provided with a first signal output terminal and a second signal output terminal, which output two excitation clock signals with a phase difference of 180°. The full-bridge dead-time control circuit includes a first OR gate circuit, a first RC filter circuit, a first AND gate circuit, a second RC filter circuit, a second OR gate circuit, a third RC filter circuit, a second AND gate circuit, and a fourth RC filter circuit. The first input terminal of the first OR gate circuit is electrically connected to the first signal output terminal, and the second input terminal of the first OR gate circuit is electrically connected to the first signal output terminal through the first RC filter circuit. The first input terminal of the first AND gate circuit is electrically connected to the first signal output terminal, and the second input terminal of the first AND gate circuit is electrically connected to the first signal output terminal. The input terminal is electrically connected to the first signal output terminal through a second RC filter circuit. The first input terminal of the second OR gate circuit is electrically connected to the second signal output terminal. The second input terminal of the second OR gate circuit is electrically connected to the first signal output terminal through a third RC filter circuit. The first input terminal of the second AND gate circuit is electrically connected to the second signal output terminal. The second input terminal of the second AND gate circuit is electrically connected to the first signal output terminal through a fourth RC filter circuit. The full-bridge power amplifier circuit includes a first half-bridge circuit and a second half-bridge circuit. The gate of the PMOS transistor in the first half-bridge circuit is electrically connected to the output terminal of the first OR gate circuit. The gate of the NMOS transistor in the first half-bridge circuit is electrically connected to the output terminal of the first AND gate circuit. The gate of the PMOS transistor in the second half-bridge circuit is electrically connected to the output terminal of the second OR gate circuit. The gate of the NMOS transistor in the second half-bridge circuit is electrically connected to the output terminal of the second AND gate circuit.

[0009] As can be seen from the above scheme, the full-bridge dead-time control circuit of the ultrasonic transducer excitation circuit of the present invention uses logic gate circuits for dead-time control, and performs delay processing on the clock signal edge to achieve edge staggering of the excitation signals of PMOS and NMOS transistors. This effectively avoids the drawback of simultaneous conduction of PMOS and NMOS transistors, ensures the service life of MOS transistors, reduces the heat generation of field-effect transistors, and uses logic gate circuits, resulting in lower cost. In addition, filtering is performed through an RC filter circuit to smooth out signal edge transitions and change the time delay from transition to the threshold, typically a few nanoseconds, which can avoid excessively long dead time, reduce distortion, and improve output efficiency.

[0010] In a further embodiment, the first RC filter circuit includes a first resistor and a first capacitor. The first end of the first resistor is electrically connected to the first signal output terminal, the second end of the first resistor is electrically connected to the second input terminal of the first OR gate circuit, the first end of the first capacitor is electrically connected to the second end of the first resistor, and the second end of the first capacitor is grounded.

[0011] Therefore, it can be seen that by setting the first resistor and the first capacitor, the first RC filter circuit can slow down the signal edge transitions, thereby controlling the dead time.

[0012] In a further embodiment, the second RC filter circuit includes a second resistor and a second capacitor. The first end of the second resistor is electrically connected to the first signal output terminal, the second end of the second resistor is electrically connected to the second input terminal of the first AND gate circuit, the first end of the second capacitor is electrically connected to the second end of the second resistor, and the second end of the second capacitor is grounded.

[0013] Therefore, it can be seen that by setting a second resistor and a second capacitor, the second RC filter circuit can slow down the signal edge transitions, thereby controlling the dead time.

[0014] In a further embodiment, the third RC filter circuit includes a third resistor and a third capacitor. The first end of the third resistor is electrically connected to the second signal output terminal, the second end of the third resistor is electrically connected to the second input terminal of the second OR gate circuit, the first end of the third capacitor is electrically connected to the second end of the third resistor, and the second end of the third capacitor is grounded.

[0015] Therefore, it can be seen that by setting the third resistor and the third capacitor, the third RC filter circuit can slow down the signal edge transitions, thereby controlling the dead time.

[0016] In a further embodiment, the fourth RC filter circuit includes a fourth resistor and a fourth capacitor. The first end of the fourth resistor is electrically connected to the second signal output terminal, the second end of the fourth resistor is electrically connected to the second input terminal of the second AND gate circuit, the first end of the fourth capacitor is electrically connected to the second end of the fourth resistor, and the second end of the fourth capacitor is grounded.

[0017] It can be seen that by setting a fourth resistor and a fourth capacitor, the fourth RC filter circuit can slow down the signal edge transitions, thereby controlling the dead time.

[0018] In a further embodiment, the clock signal generation circuit includes a main control circuit, a clock generator, and a tri-state gate circuit. Both the clock generator and the tri-state gate circuit are electrically connected to the main control circuit, and the output terminal of the clock generator is electrically connected to the input terminal of the tri-state gate circuit.

[0019] As can be seen, the main control circuit controls the clock generator to generate two excitation clock signals of corresponding frequencies, while the three-state gate circuit controls the signal to turn on and off, realizing the first level of control and protection, and preventing the clock signal from flowing uncontrollably to the excitation circuit at the back end.

[0020] In a further design, a capacitor is connected in series with the gates of both the PMOS and NMOS transistors in the full-bridge power amplifier circuit.

[0021] Therefore, it can be seen that both the gate of the PMOS transistor and the gate of the NMOS transistor in the full-bridge power amplifier circuit are connected in series with a capacitor, which can further filter the drive signal and ensure the stability of the drive signal.

[0022] To achieve the second objective of the present invention, the ultrasonic therapy device provided by the present invention is provided with an ultrasonic transducer excitation circuit and a transducer circuit, wherein the ultrasonic transducer excitation circuit and the transducer circuit are electrically connected; the ultrasonic transducer excitation circuit adopts the ultrasonic transducer excitation circuit described above.

[0023] In a further embodiment, the transducer circuit includes a first inductor, a second inductor, a first matching capacitor, a second matching capacitor, and a transducer. The first end of the first inductor is electrically connected to the output end of the first half-bridge circuit, the second end of the first inductor is electrically connected to the first end of the transducer, the second end of the transducer is electrically connected to the first end of the second inductor, and the second end of the second inductor is electrically connected to the output end of the second half-bridge circuit. Both the first matching capacitor and the second matching capacitor are connected in parallel with the transducer.

[0024] Therefore, the first inductor, the second inductor, the first matching capacitor, and the second matching capacitor are set up to form an impedance matching circuit, which is used to perform impedance matching with the transducer. Attached Figure Description

[0025] Figure 1 This is a circuit block diagram of an embodiment of the ultrasonic therapy device of the present invention.

[0026] Figure 2 This is a circuit diagram of the tri-state gate circuit and the full-bridge dead zone control circuit in the embodiment of the ultrasonic therapy device of the present invention.

[0027] Figure 3 This is a circuit diagram of the full-bridge power amplifier circuit and transducer circuit in an embodiment of the ultrasonic therapy device of the present invention.

[0028] Figure 4 This is a waveform diagram of the excitation signal in an embodiment of the ultrasonic therapy device of the present invention.

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0030] Example of ultrasound therapy equipment:

[0031] like Figure 1 As shown in this embodiment, the ultrasonic therapy device is equipped with an ultrasonic transducer excitation circuit and a transducer circuit 4, and the ultrasonic transducer excitation circuit and the transducer circuit 4 are electrically connected.

[0032] In this embodiment, the ultrasonic transducer excitation circuit includes a clock signal generation circuit 1, a full-bridge dead-time control circuit 2, and a full-bridge power amplifier circuit 3.

[0033] The clock signal generation circuit 1 includes a main control circuit 11, a clock generator 12, and a tri-state gate circuit 13. Both the clock generator 12 and the tri-state gate circuit 13 are electrically connected to the main control circuit 11, and the output terminal of the clock generator 12 is electrically connected to the input terminal of the tri-state gate circuit 13. Preferably, the tri-state gate circuit 13 uses a SN74LVC1G19DBVR tri-state gate chip. See [link / reference] Figure 2 The tri-state gate circuit 13 is electrically connected to the output terminal of the clock generator 12 via the CLK terminal, and is also electrically connected to the main control circuit 11 via the WINDOW terminal. The tri-state gate circuit 13 is further provided with a first signal output terminal PWM-A and a second signal output terminal PWM-B. The main control circuit 11 sends a control signal to the clock generator 12 to generate a clock signal. The main control circuit 11 sends a duty cycle control signal to the tri-state gate circuit 13 via the WINDOW terminal. When the duty cycle control signal is low, the first signal output terminal PWM-A and the second signal output terminal PWM-B output two excitation clock signals with a phase difference of 180°. When the duty cycle control signal is high, the first signal output terminal PWM-A and the second signal output terminal PWM-B output a high level.

[0034] In this embodiment, the full-bridge dead-time control circuit 2 includes a first OR gate circuit U1, a first RC filter circuit 21, a first AND gate circuit U2, a second RC filter circuit 22, a second OR gate circuit U3, a third RC filter circuit 23, a second AND gate circuit U4, and a fourth RC filter circuit 24. The first input terminal of the first OR gate circuit U1 is electrically connected to the first signal output terminal PWM-A, and the second input terminal of the first OR gate circuit U1 is electrically connected to the first signal output terminal PWM-A through the first RC filter circuit 21. The first input terminal of the first AND gate circuit U2 is connected to the first signal output terminal PWM-A. -A is electrically connected. The second input terminal of the first AND gate circuit U2 is electrically connected to the first signal output terminal PWM-A through the second RC filter circuit 22. The first input terminal of the second OR gate circuit U3 is electrically connected to the second signal output terminal PWM-B. The second input terminal of the second OR gate circuit U3 is electrically connected to the first signal output terminal PWM-A through the third RC filter circuit 23. The first input terminal of the second AND gate circuit U4 is electrically connected to the second signal output terminal PWM-B. The second input terminal of the second AND gate circuit U4 is electrically connected to the first signal output terminal PWM-A through the fourth RC filter circuit 24.

[0035] In this embodiment, the first RC filter circuit 21 includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is electrically connected to the first signal output terminal PWM-A, the second end of the first resistor R1 is electrically connected to the second input terminal of the first OR gate circuit U1, the first end of the first capacitor C1 is electrically connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is grounded. The second RC filter circuit 22 includes a second resistor R2 and a second capacitor C2. The first end of the second resistor R2 is electrically connected to the first signal output terminal PWM-A, the second end of the second resistor R2 is electrically connected to the second input terminal of the first AND gate circuit U2, the first end of the second capacitor C2 is electrically connected to the second end of the second resistor R2, and the second end of the second capacitor C2 is grounded. The third RC filter circuit 23 includes a third resistor R3 and a third capacitor C3. The first end of the third resistor R3 is electrically connected to the second signal output terminal PWM-B, the second end of the third resistor R3 is electrically connected to the second input terminal of the second OR gate circuit U3, the first end of the third capacitor C3 is electrically connected to the second end of the third resistor R3, and the second end of the third capacitor C3 is grounded. The fourth RC filter circuit 24 includes a fourth resistor R4 and a fourth capacitor C4. The first end of the fourth resistor R4 is electrically connected to the second signal output terminal PWM-B, the second end of the fourth resistor R4 is electrically connected to the second input terminal of the second AND gate circuit U4, the first end of the fourth capacitor C4 is electrically connected to the second end of the fourth resistor R4, and the second end of the fourth capacitor C4 is grounded.

[0036] See Figure 3 In this embodiment, the full-bridge power amplifier circuit 3 includes a first half-bridge circuit 31 and a second half-bridge circuit 32. The first half-bridge circuit 31 includes a PMOS transistor Q1 and an NMOS transistor Q2. The drain of the PMOS transistor Q1 is electrically connected to the power supply terminal VCC-HV. The gate of the PMOS transistor Q1 is electrically connected to the output terminal of the first OR gate circuit U1 through a capacitor C5. The source of the PMOS transistor Q1 is electrically connected to the output terminal of the first half-bridge circuit 31. The drain of the NMOS transistor Q2 is electrically connected to the output terminal of the first half-bridge circuit 31. The gate of the NMOS transistor Q2 is electrically connected to the output terminal of the first AND gate circuit U2 through a capacitor C6. The source of the NMOS transistor Q2 is grounded. The second half-bridge circuit 32 includes a PMOS transistor Q3 and an NMOS transistor Q4. The drain of the PMOS transistor Q3 is electrically connected to the power supply terminal VCC-HV. The gate of the PMOS transistor Q3 is electrically connected to the output terminal of the second OR gate circuit U3 through a capacitor C7. The source of the PMOS transistor Q3 is electrically connected to the output terminal of the second half-bridge circuit 32. The drain of the NMOS transistor Q4 is electrically connected to the output terminal of the second half-bridge circuit 32. The gate of the NMOS transistor Q4 is electrically connected to the output terminal of the second AND gate circuit U4 through a capacitor C8. The source of the NMOS transistor Q4 is grounded.

[0037] In this embodiment, the transducer circuit 4 includes a first inductor L1, a second inductor L2, a first matching capacitor C9, a second matching capacitor C10, and a transducer Y1. The first end of the first inductor L1 is electrically connected to the output end of the first half-bridge circuit 31, the second end of the first inductor L1 is electrically connected to the first end of the transducer Y1, the second end of the transducer Y1 is electrically connected to the first end of the second inductor L2, the second end of the second inductor L2 is electrically connected to the output end of the second half-bridge circuit 32, and the first matching capacitor C9 and the second matching capacitor C10 are both connected in parallel with the transducer Y1.

[0038] See Figure 4 In this embodiment of the ultrasound therapy device, during operation, the main control circuit 11 controls the clock generator 12 to generate a clock signal of a corresponding frequency. The clock signal is input to the tri-state gate circuit 13 through the terminal CLK. The first signal output terminal PWM-A and the second signal output terminal PWM-B of the tri-state gate circuit 13 output two excitation clock signals with a phase difference of 180°. The excitation clock signal of the first signal output terminal PWM-A is respectively sent to the first OR gate circuit U1 and the first AND gate circuit U2. The excitation clock signal of the second signal output terminal PWM-B is respectively sent to the second OR gate circuit U3 and the second AND gate circuit U4.

[0039] The first OR gate U1 controls the PMOS transistor Q1 of the first half-bridge circuit 31. The first input terminal of the first OR gate U1 receives the PWM-A signal, and the second input terminal receives the filtered and delayed PWM-A signal. This signal is filtered by the first RC filter circuit 21, which smooths out the signal edge transitions and changes the time delay before the transition reaches the threshold, typically by several nanoseconds. The output of the first OR gate U1 can only be converted to logic 0 when both the first and second input signals drop below the logic 0 level transition threshold. Conversely, the output of the first OR gate U1 becomes logic 1 when either the first or second input signal rises above the logic 1 level transition threshold, thus achieving a falling edge delay while maintaining the rising edge of the PWM-A signal.

[0040] The first AND gate U2 controls the NMOS transistor Q2 of the first half-bridge circuit 31. The input of the first AND gate U2 is a PWM-A signal, and the second input is a filtered and delayed PWM-A signal processed by the second RC filter circuit 22. The output of the first AND gate U2 becomes logic 1 only when both the first and second input signals rise above the logic 1 level threshold. Conversely, the output of the first AND gate U2 becomes logic 0 only if either the first or second input signal becomes logic 0, thus delaying the rising edge of the PWM-A signal while keeping the falling edge unchanged.

[0041] The second OR gate circuit U3 works in the same way as the first OR gate circuit U1, and the second AND gate circuit U4 works in the same way as the first AND gate circuit U2, realizing different signal delays at the upper and lower transition edges, which will not be elaborated here.

[0042] Depend on Figure 4 As can be seen, due to the delay processing of the corresponding signal edge, the turn-on signal of the PMOS transistor falls completely within the turn-off signal of the NMOS transistor, and at the same time, the turn-on signal of the NMOS transistor also falls completely within the turn-off signal of the PMOS transistor. This ensures the dead time, avoids the simultaneous conduction of the two transistors, and also realizes that one CLK signal can drive four MOS transistors, so that the signals can be kept synchronized and the stability of control can be improved.

[0043] As described above, the full-bridge dead-time control circuit 2 of the ultrasonic transducer excitation circuit of this invention uses logic gate circuits for dead-time control, delaying the clock signal edges to achieve edge staggering of the excitation signals of PMOS and NMOS transistors. This effectively avoids the drawback of simultaneous conduction of PMOS and NMOS transistors, ensuring the service life of the MOS transistors, reducing the heat generation of the field-effect transistors, and using logic gate circuits, resulting in lower cost. Furthermore, RC filter circuits are used to smooth signal edge transitions, changing the time delay from transition to the threshold, typically a few nanoseconds, which avoids excessively long dead times, reduces distortion, and improves output efficiency.

[0044] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept also fall within the protection scope of the present invention.

Claims

1. An ultrasonic transducer excitation circuit, characterized in that: This includes a clock signal generation circuit, a full-bridge dead-time control circuit, and a full-bridge power amplifier circuit; The clock signal generation circuit is provided with a first signal output terminal and a second signal output terminal, and the first signal output terminal and the second signal output terminal output two excitation clock signals with a phase difference of 180°. The full-bridge dead-time control circuit includes a first OR gate, a first RC filter circuit, a first AND gate, a second RC filter circuit, a second OR gate, a third RC filter circuit, a second AND gate, and a fourth RC filter circuit. The first input terminal of the first OR gate is electrically connected to the first signal output terminal, and the second input terminal of the first OR gate is electrically connected to the first signal output terminal through the first RC filter circuit. The first input terminal of the first AND gate is electrically connected to the first signal output terminal, and the second input terminal of the first AND gate is electrically connected to the first signal output terminal through the second RC filter circuit. The first input terminal of the second OR gate is electrically connected to the second signal output terminal, and the second input terminal of the second OR gate is electrically connected to the first signal output terminal through the third RC filter circuit. The first input terminal of the second AND gate is electrically connected to the second signal output terminal, and the second input terminal of the second AND gate is electrically connected to the first signal output terminal through the fourth RC filter circuit. The full-bridge power amplifier circuit includes a first half-bridge circuit and a second half-bridge circuit. The gate of the PMOS transistor in the first half-bridge circuit is electrically connected to the output terminal of the first OR gate circuit, and the gate of the NMOS transistor in the first half-bridge circuit is electrically connected to the output terminal of the first AND gate circuit. The gate of the PMOS transistor in the second half-bridge circuit is electrically connected to the output terminal of the second OR gate circuit, and the gate of the NMOS transistor in the second half-bridge circuit is electrically connected to the output terminal of the second AND gate circuit.

2. The ultrasonic transducer excitation circuit according to claim 1, characterized in that: The first RC filter circuit includes a first resistor and a first capacitor. The first end of the first resistor is electrically connected to the first signal output terminal, the second end of the first resistor is electrically connected to the second input terminal of the first OR gate circuit, the first end of the first capacitor is electrically connected to the second end of the first resistor, and the second end of the first capacitor is grounded.

3. The ultrasonic transducer excitation circuit according to claim 1, characterized in that: The second RC filter circuit includes a second resistor and a second capacitor. The first end of the second resistor is electrically connected to the first signal output terminal, the second end of the second resistor is electrically connected to the second input terminal of the first AND gate circuit, the first end of the second capacitor is electrically connected to the second end of the second resistor, and the second end of the second capacitor is grounded.

4. The ultrasonic transducer excitation circuit according to claim 1, characterized in that: The third RC filter circuit includes a third resistor and a third capacitor. The first end of the third resistor is electrically connected to the second signal output terminal, the second end of the third resistor is electrically connected to the second input terminal of the second OR gate circuit, the first end of the third capacitor is electrically connected to the second end of the third resistor, and the second end of the third capacitor is grounded.

5. The ultrasonic transducer excitation circuit according to claim 1, characterized in that: The fourth RC filter circuit includes a fourth resistor and a fourth capacitor. The first end of the fourth resistor is electrically connected to the second signal output terminal, the second end of the fourth resistor is electrically connected to the second input terminal of the second AND gate circuit, the first end of the fourth capacitor is electrically connected to the second end of the fourth resistor, and the second end of the fourth capacitor is grounded.

6. The ultrasonic transducer excitation circuit according to any one of claims 1 to 5, characterized in that: The clock signal generation circuit includes a main control circuit, a clock generator, and a tri-state gate circuit. The clock generator and the tri-state gate circuit are both electrically connected to the main control circuit, and the output terminal of the clock generator is electrically connected to the input terminal of the tri-state gate circuit.

7. The ultrasonic transducer excitation circuit according to any one of claims 1 to 5, characterized in that: In the full-bridge power amplifier circuit, a capacitor is connected in series with the gate of both the PMOS transistor and the gate of the NMOS transistor.

8. An ultrasonic therapy device, comprising an ultrasonic transducer excitation circuit and a transducer circuit, wherein the ultrasonic transducer excitation circuit is electrically connected to the transducer circuit; characterized in that: The ultrasonic transducer excitation circuit adopts the ultrasonic transducer excitation circuit according to any one of claims 1 to 7.

9. The ultrasound therapy device according to claim 8, characterized in that: The transducer circuit includes a first inductor, a second inductor, a first matching capacitor, a second matching capacitor, and a transducer. The first end of the first inductor is electrically connected to the output end of the first half-bridge circuit, the second end of the first inductor is electrically connected to the first end of the transducer, the second end of the transducer is electrically connected to the first end of the second inductor, and the second end of the second inductor is electrically connected to the output end of the second half-bridge circuit. The first matching capacitor and the second matching capacitor are both connected in parallel with the transducer.

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