Zvs adaptive dead-time control method and circuit, computer device and storage medium

Abstract

The application discloses a ZVS adaptive dead-time control method and circuit, computer equipment and a storage medium, and the method comprises the following steps: obtaining an off signal of a driving signal of a first power tube, recording a time point t1 corresponding to a starting point of the off signal; detecting a voltage signal of a connection node of the first power tube and a second power tube, judging whether the second power tube generates a ZVS signal according to the currently detected voltage signal, and if yes, recording a time point t2 corresponding to the generation of the ZVS signal; and adjusting a dead-time of a next period according to the time point t1 and the time point t2. The optimal dead-time of the power device is calculated, and the dead-time is updated in real time, so that the dynamic adjustment of the dead-time is realized. Through the dynamic dead-time adjustment, the problem of low efficiency of the traditional fixed dead-time is solved, and the problem of the influence of the device tolerance and the system parasitic parameter tolerance on the dead-time is solved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method, circuit, computer device, and storage medium for dead-zone control of power circuit ZVS conduction. Background Technology

[0002] In the field of power electronics, ZVS (Zero Voltage Switching) turn-on of power devices is widely used due to its advantages of reducing turn-on losses and improving system efficiency. In LLC topologies, phase-shifted full-bridge topologies, synchronous BOOST topologies, and synchronous BUCK topologies, ZVS turn-on can be achieved through resonance between the system's inductance and the device's junction capacitance. The essence of ZVS turn-on is that after the corresponding power device is turned off, the current flowing through the inductor through the junction capacitance of the power device charges and discharges, causing the voltage across the power device to drop to zero. At this point, the power device is turned on, achieving ZVS turn-on. The charging and discharging of the junction capacitance depends on the current in the inductor and the charging and discharging time of the junction capacitance.

[0003] The charging and discharging time is controlled by the dead time of the complementary conducting power devices. Traditionally, the dead time is set by the control system to a fixed time, or calculated theoretically based on the output voltage and system parameters, thus achieving ZVS (Zero-Voltage-Time) for the power devices. However, since the inductor current varies under different operating conditions, the charging current for the junction capacitance also varies. Furthermore, due to the piezoelectric effect of the power device's output capacitance, control methods using a fixed dead time or based on theoretical calculations of the capacitor charging current have certain deviations and do not consider system tolerance issues. Dead time control cannot achieve very high accuracy, especially with the rise of wide-bandgap devices in recent years, where reverse overconduction causes greater losses and affects system gain. Summary of the Invention

[0004] To address the aforementioned problems, the main objective of this invention is to provide a ZVS adaptive dead-time control method, circuit, computer device, and storage medium to achieve accurate control of the ZVS dead-time, thereby resolving efficiency and gain issues caused by inaccurate ZVS.

[0005] The technical solution provided by this invention to solve the above-mentioned technical problems is as follows:

[0006] Firstly, a control method for ZVS adaptive dead time is provided, applied to a power loop circuit implementing ZVS, wherein the power loop circuit includes a first power transistor and a second power transistor connected in series, and the drive signals of the first power transistor and the second power transistor are complementary; the control method includes:

[0007] Obtain the turn-off signal of the drive signal of the first power transistor, and record the time point t1 corresponding to the start point of the turn-off signal;

[0008] Detect the voltage signal at the connection node between the first power transistor and the second power transistor. Based on the currently detected voltage signal, determine whether the second power transistor generates a ZVS signal. If so, record the time point t2 corresponding to the generation of the ZVS signal.

[0009] Adjust the dead time of the next cycle based on time points t1 and t2.

[0010] Preferably, the dead time of the next cycle is adjusted according to time points t1 and t2, specifically including:

[0011] The first time difference T1 is generated by subtracting time point t2 from time point t1, and it is determined whether the first time difference T1 is less than the set dead time Td.

[0012] If not, then adjust the dead time Td of the next cycle to Td = Tdmax, where Tdmax is the dead time that can achieve ZVS under all operating conditions;

[0013] If yes, then determine whether the power loop circuit has over-conducted. If yes, record the time point t3 corresponding to the over-conducting event, and adjust the dead time Td of the next cycle according to the time points t1 and t3. If no, adjust the dead time Td of the next cycle to Td = t2 - t1 + Tmin, where Tmin is the set delay time, and Tmin is the adjustable time of the ZVS conduction point and the time difference between the reverse over-conduction point of the realized power device. Tmin is not less than the minimum time that the controller can process.

[0014] Preferably, when it is determined that the power loop circuit has over-conduction, the dead time Td of the next cycle is adjusted to Td = t3 - t1.

[0015] Preferably, determining whether the second power transistor has achieved ZVS conduction based on the currently detected voltage signal specifically includes:

[0016] Determine whether the voltage signal is less than a set first threshold. If so, determine that a ZVS signal is generated.

[0017] Preferably, determining whether the power circuit has experienced over-conduction specifically includes:

[0018] Determine whether the currently detected voltage signal is less than the second threshold. If so, determine that overconduction has occurred.

[0019] Secondly, a control circuit for ZVS adaptive dead time is provided, which is applied to a power loop circuit for implementing ZVS. The power loop circuit includes a first power transistor and a second power transistor connected in series, and the drive signals of the first power transistor and the second power transistor are complementary. It includes a detection and comparison circuit and a controller. The input terminal of the detection and comparison circuit is used to connect to the connection node of the first power transistor and the second power transistor, and the output terminal is connected to the input terminal of the controller. The output terminal of the controller is used to connect to the control terminal of the first power transistor and the control terminal of the second power transistor, respectively.

[0020] The controller is used to acquire the turn-off signal of the drive signal of the first power transistor and record the time point t1 corresponding to the start point of the turn-off signal.

[0021] The detection and comparison circuit is used to detect the voltage signal at the connection node between the first power transistor and the second power transistor, and to determine whether the second power transistor generates a ZVS signal based on the currently detected voltage signal.

[0022] The controller is also used to record the time point t2 corresponding to the generation of the ZVS signal when the detection and comparison circuit determines that the second power transistor generates a ZVS signal, and adjust the dead time of the next cycle according to the time point t1 and the time point t2.

[0023] Preferably, the controller adjusts the dead time of the next cycle according to time points t1 and t2, specifically including:

[0024] The first time difference T1 is generated by subtracting time point t2 from time point t1, and it is determined whether the first time difference T1 is less than the set dead time Td.

[0025] If not, then adjust the dead time Td of the next cycle to Td = Tdmax, where Tdmax is the dead time that can achieve ZVS under all operating conditions;

[0026] If so, the detection and comparison circuit determines whether the power loop circuit has been over-conducted;

[0027] When the detection and comparison circuit determines that the power loop circuit has over-conducted, the controller records the time point t3 corresponding to the over-conducting time, and adjusts the dead time Td of the next cycle according to the time point t1 and the time point t3.

[0028] When the detection and comparison circuit determines that the power loop circuit has not been over-conducted, the controller adjusts the dead time Td of the next cycle to Td = t2 - t1 + Tmin, where Tmin is the set delay time.

[0029] Preferably, the controller's input terminals include a first input terminal and a second input terminal; the detection and comparison circuit includes a voltage acquisition circuit, a first comparator, and a second comparator; the input terminal of the voltage acquisition circuit is connected to the connection node of the first power transistor and the second power transistor, and its output terminal is connected to the first input terminal of the first comparator and the first input terminal of the second comparator, respectively; the second input terminal of the first comparator is used to input a first threshold, and the second input terminal of the second comparator is used to input a second threshold; the output terminal of the first comparator is connected to the first input terminal of the controller, and the output terminal of the second comparator is connected to the second input terminal of the controller.

[0030] The detection and comparison circuit determines whether the second power transistor generates a ZVS signal based on the currently detected voltage signal, specifically including:

[0031] The first comparator compares the currently detected voltage signal with a first threshold. When the voltage signal is less than the first threshold, it outputs a result signal that generates a ZVS signal to the comparator.

[0032] The detection and comparison circuit determines whether the power loop circuit has experienced over-conduction, specifically including:

[0033] The second comparator compares the currently detected voltage signal with a first threshold. When the voltage signal is less than a second threshold, it outputs an overconduction result signal to the comparator.

[0034] Thirdly, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0035] Fourthly, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the method described above.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention records the time point t2 corresponding to the ZVS turn-on and the time point t1 of the turn-off signal of the first power transistor, and adjusts the dead time of the next cycle according to the time point t2 and the time point t1, thereby realizing the dynamic adjustment of the time required to realize ZVS in real-time operation, satisfying the optimal dead time control, and realizing the high efficiency and best performance of the system. Attached Figure Description

[0037] Figure 1 This is a flowchart of the ZVS adaptive dead zone control method described in this invention.

[0038] Figure 2This is a block diagram of the ZVS adaptive dead zone control circuit described in this invention.

[0039] Figure 3 This is a timing diagram illustrating the control method using the ZVS adaptive dead zone described in this invention. Detailed Implementation

[0040] It should be understood that the specific embodiments described herein are merely illustrative of the invention, and the specific implementation of the invention is not limited thereto. The described embodiments are only a part of the embodiments of the invention, and not all of them. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Based on the described embodiments of the invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the invention.

[0041] like Figure 1 The diagram shows a flowchart of the ZVS adaptive dead-time control method described in this embodiment. This embodiment provides a ZVS adaptive dead-time control method applied to a power loop circuit implementing ZVS. The power loop circuit includes a first power transistor and a second power transistor connected in series, with complementary drive signals for the first and second power transistors. The control method includes the following steps:

[0042] S200. Obtain the turn-off signal of the drive signal of the first power transistor, and record the time point t1 corresponding to the start point of the turn-off signal.

[0043] S300. Detect the voltage signal at the connection node between the first power transistor and the second power transistor. Based on the currently detected voltage signal, determine whether the second power transistor generates a ZVS signal. If yes, record the time point t2 corresponding to the generation of the ZVS signal and execute step S400. If no, execute step S500. Step S300 specifically includes the following steps:

[0044] S301. Determine whether the voltage signal is less than the set first threshold. If yes, determine that a ZVS signal is generated and execute step S400. If no, execute step S500.

[0045] S400. Adjust the dead time of the next cycle based on time points t1 and t2. Step S400 specifically includes the following steps:

[0046] S401. Calculate the difference between time point t2 and time point t1 to generate a first time difference T1. Determine whether the first time difference T1 is less than the set dead time Td. If yes, proceed to step S402. If no, proceed to step S500.

[0047] S402. Determine whether the power loop circuit has been over-conducted. If yes, proceed to step S4021; otherwise, proceed to step S4022.

[0048] S4021 records the time point t3 corresponding to the time when conduction occurred, and adjusts the dead time Td of the next cycle according to the time points t1 and t3;

[0049] S4022. Adjust the dead time Td of the next cycle to Td = t2 - t1 + Tmin, where Tmin is the set delay time, Tmin is the adjustable time of the ZVS turn-on point and the time difference between the reverse turn-on point of the realized power device, and Tmin is not less than the minimum time that the controller can process.

[0050] S500. Adjust the dead time Td of the next cycle to Td = Tdmax, where Tdmax is the dead time that can achieve ZVS under all operating conditions.

[0051] This embodiment records the time point t2 corresponding to the ZVS turn-on and the time point t1 of the first power transistor turn-off signal, and adjusts the dead time of the next cycle according to the time points t2 and t1. This enables dynamic adjustment of the time required to achieve ZVS in real-time operation, meets the optimal dead time control, and achieves high system efficiency and optimal performance.

[0052] Specifically, during startup, the dead time Td of the first and second power transistors is set. The initial value of the dead time Td is Tdmax, which is the dead time that enables ZVS under all operating conditions. Tdmax is set to be no less than the minimum time that the system can achieve ZVS under the minimum output voltage. After adjusting the dead time of the next cycle, the acquired values ​​are cleared to zero. These acquired values ​​include the time points and voltage signals.

[0053] In another embodiment, such as Figure 2 As shown, a control circuit for ZVS adaptive dead time is provided, which is applied to the power loop circuit for implementing ZVS. The power loop circuit includes a first power transistor and a second power transistor connected in series, and the drive signals of the first power transistor and the second power transistor are complementary. It includes a detection and comparison circuit and a controller. The input terminal of the detection and comparison circuit is used to connect to the connection node of the first power transistor and the second power transistor, and the output terminal is connected to the input terminal of the controller. The output terminal of the controller is used to connect to the control terminal of the first power transistor and the control terminal of the second power transistor respectively.

[0054] The controller is used to acquire the turn-off signal of the drive signal of the first power transistor and record the time point t1 corresponding to the start point of the turn-off signal.

[0055] The detection and comparison circuit is used to detect the voltage signal at the connection node between the first power transistor and the second power transistor, and to determine whether the second power transistor generates a ZVS signal based on the currently detected voltage signal.

[0056] The controller is also used to record the time point t2 corresponding to the ZVS conduction when the detection and comparison circuit determines that the second power transistor has achieved ZVS conduction, and adjust the dead time of the next cycle according to the time point t1 and the time point t2.

[0057] Specifically, as one embodiment of the detection and comparison circuit, the controller's input terminals include a first input terminal and a second input terminal; the detection and comparison circuit includes a voltage acquisition circuit, a first comparator, and a second comparator; the input terminal of the voltage acquisition circuit is used to connect to the connection node of the first power transistor and the second power transistor, and its output terminal is connected to the first input terminal of the first comparator and the first input terminal of the second comparator, respectively; the second input terminal of the first comparator is used to connect to a first threshold, and the second input terminal of the second comparator is used to connect to a second threshold; the output terminal of the first comparator is connected to the first input terminal of the controller, and the output terminal of the second comparator is connected to the second input terminal of the controller.

[0058] Specifically, the power loop circuit described in this embodiment includes at least two complementary turn-on power transistors, applied to ZVS turn-on control of power devices. The first and second power transistors can be, but are not limited to, MOSFETs. The power loop circuit described in this embodiment can be, but is not limited to, power loop circuits in LLC topology, phase-shifted full-bridge topology, synchronous BOOST topology, and synchronous BUCK topology. The connection node of the first and second power transistors is the node where the source of the first power transistor and the drain of the second power transistor are connected. The voltage acquisition circuit includes a low-voltage control voltage source Vcc, a first voltage divider resistor and a second voltage divider resistor, and a diode; control signals 1 and 2 generated by the controller are used to generate drive signals 1 and 2, respectively, to drive the first and second power transistors.

[0059] Next, combined Figure 1 and Figure 2 The principle of the control method described in this embodiment will be explained as follows:

[0060] 1. When the controller starts, the internal time base controller is started, and the dead time Td is set. The initial value of Td is Tdmax. Tdmax is the dead time that can achieve ZVS under all operating conditions. Tdmax is set to be no less than the minimum time that the system can achieve ZVS under the minimum output voltage.

[0061] 2. The controller obtains the moment when the control signal 1 corresponding to the first power transistor is turned off. The controller generates the corresponding time point t1 through the time base, which is used as the starting point for the junction capacitance discharge of the second power transistor that is about to be turned on, and also the starting point of the dead time.

[0062] 3. When the first power transistor is turned off as described in step 2, its junction capacitance is charged by the loop current. This loop current originates from the inductor resonating with the junction capacitance. Specifically, in the LLC topology, this current value is the resonant inductor current. The voltage VDS across the second power transistor begins to decrease. The voltage acquisition circuit acquires the voltage signal at the connection node between the first and second power transistors. The first comparator compares this voltage signal with a set first threshold. When the voltage signal at the connection node is less than the set first threshold, the first comparator outputs a flip signal and transmits it to the controller. The controller captures this signal and can accurately determine the ZVS (Zero-Voltage Switching) time point t2. The ZVS signal will definitely be generated, but it may not necessarily reflect the time when VDS reaches the ZVS turn-on. It could also be that the complementary power device turns on, forcing VDS to drop to the ZVS turn-on point. Specifically, when the voltage signal is less than the first threshold, the first comparator outputs a flip signal.

[0063] Therefore, to distinguish whether the signal is generated by ZVS or caused by the complementary transistor being turned on, the following steps are performed for judgment:

[0064] 4. When the difference between t2 and t1 (the first time difference T1) is greater than or equal to the set dead time Td, it cannot be determined whether ZVS has been truly achieved. In this case, the dead time of the next cycle is adjusted to Tdmax, i.e., Td = Tdmax. At the same time, the acquired value is cleared to zero, and the next cycle begins.

[0065] 5. When t2-t1 is less than the set dead time Td, it indicates that the time point corresponding to the ZVS signal has occurred within this dead time. At this time, the controller obtains the signal output by the second comparator, which compares the currently detected voltage signal with the second threshold. When the voltage signal is less than the second threshold, it indicates that the power circuit has been over-conducted. The controller obtains the time point t3 corresponding to the flip signal of the second comparator. The time point t3 represents the time point when the reverse diode of the second power transistor just turns on. Then, the dead time of the next cycle is adjusted to t3-t1, i.e., Td = t3-t1. The controller value is cleared. Specifically, when the voltage signal is less than the second threshold, the output signal of the second comparator flips from low level to high level, and the second threshold is less than the first threshold. When the controller does not obtain the flip signal of the second comparator and the corresponding time point t3, the dead time of the next cycle is adjusted to t2-t1+Tmin, i.e., Td = t2-t1+Tmin, and the controller value is cleared.

[0066] In another embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the control method described above.

[0067] In another embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0068] It should be noted that for details not disclosed in the computer storage medium in the embodiments of the present invention, please refer to the details disclosed in the ZVS control method of the circuit in the embodiments of the present invention, which will not be repeated here.

[0069] The above description of the embodiments is only for the purpose of helping to understand the inventive concept of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made without departing from the principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A control method for ZVS adaptive dead time, applied to a power loop circuit implementing ZVS, wherein the power loop circuit includes a first power transistor and a second power transistor connected in series, and the drive signals of the first power transistor and the second power transistor are complementary; characterized in that, The control method includes: Obtain the turn-off signal of the drive signal of the first power transistor, and record the time point t1 corresponding to the start point of the turn-off signal; Detect the voltage signal at the connection node between the first power transistor and the second power transistor. Based on the currently detected voltage signal, determine whether the second power transistor generates a ZVS signal. If so, record the time point t2 corresponding to the generation of the ZVS signal. Adjust the dead time of the next cycle based on time points t1 and t2; Adjusting the dead time for the next cycle based on time points t1 and t2, specifically including: The first time difference T1 is generated by subtracting time point t2 from time point t1, and it is determined whether the first time difference T1 is less than the set dead time Td. If not, then adjust the dead time Td of the next cycle to Td=Tdmax, where Tdmax is the dead time that can achieve ZVS under all operating conditions; If yes, then determine whether the power loop circuit has over-conducted. If yes, record the time point t3 corresponding to the over-conducting event, and adjust the dead time Td of the next cycle according to the time points t1 and t3, where Td = t3 - t1. If no, then adjust the dead time Td of the next cycle to Td = t2 - t1 + Tmin, where Tmin is the set delay time and Tmin is the adjustable time of the ZVS conduction point and the time difference between the reverse over-conduction point of the realized power device.

2. The ZVS adaptive dead-zone control method according to claim 1, characterized in that, Determining whether the second power transistor generates a ZVS signal based on the currently detected voltage signal specifically includes: Determine whether the voltage signal is less than a set first threshold. If so, determine that a ZVS signal is generated.

3. The ZVS adaptive dead-zone control method according to claim 1, characterized in that, Determining whether the power circuit has experienced over-conduction specifically includes: Determine whether the currently detected voltage signal is less than the second threshold. If so, determine that overconduction has occurred.

4. A control circuit for ZVS adaptive dead time, applied to a power loop circuit for implementing ZVS, wherein the power loop circuit includes a first power transistor and a second power transistor connected in series, and the drive signals of the first power transistor and the second power transistor are complementary; characterized in that, The control circuit includes a detection and comparison circuit and a controller. The input terminal of the detection and comparison circuit is connected to the connection node of the first power transistor and the second power transistor, and the output terminal is connected to the input terminal of the controller. The output terminal of the controller is connected to the control terminal of the first power transistor and the control terminal of the second power transistor, respectively. The controller is used to acquire the turn-off signal of the drive signal of the first power transistor and record the time point t1 corresponding to the start point of the turn-off signal. The detection and comparison circuit is used to detect the voltage signal at the connection node between the first power transistor and the second power transistor, and to determine whether the second power transistor generates a ZVS signal based on the currently detected voltage signal. The controller is also used to record the time point t2 corresponding to the generation of the ZVS signal when the detection and comparison circuit determines that the second power transistor generates a ZVS signal, and adjust the dead time of the next cycle according to the time point t1 and the time point t2. The controller adjusts the dead time of the next cycle based on time points t1 and t2, specifically including: The first time difference T1 is generated by subtracting time point t2 from time point t1, and it is determined whether the first time difference T1 is less than the set dead time Td. If not, then adjust the dead time Td of the next cycle to Td=Tdmax, where Tdmax is the dead time that can achieve ZVS under all operating conditions; If so, the detection and comparison circuit determines whether the power loop circuit has been over-conducted; When the detection and comparison circuit determines that the power loop circuit has over-conducted, the controller records the time point t3 corresponding to the over-conducting time, and adjusts the dead time Td of the next cycle according to the time point t1 and the time point t3, where Td = t3 - t1. When the detection and comparison circuit determines that the power loop circuit has not been over-conducted, the controller adjusts the dead time Td of the next cycle to Td=t2-t1+Tmin, where Tmin is the set delay time and Tmin is the adjustable time of the ZVS conduction point and the time difference between the reverse over-conduction point of the realized power device.

5. The control circuit for ZVS adaptive dead time according to claim 4, characterized in that, The controller includes a first input terminal and a second input terminal; the detection and comparison circuit includes a voltage acquisition circuit, a first comparator, and a second comparator; the input terminal of the voltage acquisition circuit is connected to the connection node of the first power transistor and the second power transistor, and the output terminal is connected to the first input terminal of the first comparator and the first input terminal of the second comparator, respectively; the second input terminal of the first comparator is used to input a first threshold, and the second input terminal of the second comparator is used to input a second threshold; the output terminal of the first comparator is connected to the first input terminal of the controller, and the output terminal of the second comparator is connected to the second input terminal of the controller. The detection and comparison circuit determines whether the second power transistor generates a ZVS signal based on the currently detected voltage signal, specifically including: The first comparator compares the currently detected voltage signal with a first threshold. When the voltage signal is less than the first threshold, it outputs a result signal that generates a ZVS signal to the comparator. The detection and comparison circuit determines whether the power loop circuit has experienced over-conduction, specifically including: The second comparator compares the currently detected voltage signal with a first threshold. When the voltage signal is less than a second threshold, it outputs an overconduction result signal to the comparator.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1-3.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-3.

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