Circuit and method for automatically calculating rotor speed

Abstract

The application provides a circuit and method for automatically calculating rotor speed, comprising: an edge generation module receiving U, V, W three-phase Hall signals and generating edge response signals of each phase Hall signal; a counting module connected to the output end of the edge generation module, counting the time difference between each adjacent two times of each phase Hall signal based on the output signal of the edge generation module to obtain each phase counting value and output the current counting value, and generating a trigger signal when any phase Hall signal jumps; and a division module connected to the output end of the counting module, dividing the angle difference between adjacent two times of the Hall signal by the current counting value to obtain the motor speed. The application has the advantages of accurate speed calculation, convenient and simple operation, less development time, less CPU resource occupation and wide application scenarios.

Description

Technical Field

[0001] This invention relates to the field of motor control, and in particular to a circuit and method for automatically calculating rotor speed. Background Technology

[0002] Most existing technologies use software to calculate the rotor speed of the motor, including the following steps:

[0003] Step 1: Install Hall effect sensors in the motor to provide feedback on the position information of the motor rotor;

[0004] Step 2: Compensate for Hall bias;

[0005] Step 3: Obtain the time difference between two consecutive transitions of the Hall signal;

[0006] Step 4: Filter the time obtained in Step 3;

[0007] Step 5: Calculate the rotor speed based on the rotor's angle change and the filtered time.

[0008] The above method heavily relies on rotor position information. Any deviation will result in inaccurate rotor speed calculations. However, Hall sensors often have mechanical deviations during installation, causing errors in rotor position angle estimation and consequently, inaccurate calculations. Therefore, Hall error compensation is necessary. Most compensation methods employ software compensation, requiring numerous algorithms such as zero-order Taylor algorithms and Fourier decoupling transforms, making implementation complex and difficult. Since external factors such as air and ground roughness can affect motor operation, after obtaining the time difference between two adjacent Hall signal transitions, RC filtering or averaging filtering is needed to eliminate random errors, requiring a high level of knowledge from software engineers.

[0009] In addition, the software takes a long time to calculate the rotor speed, which is not ideal for functions that require strict time control (such as FOC (Field Oriented Control) mode); moreover, the complex software program will occupy the CPU for a long time, which is not conducive to other safety controls.

[0010] Therefore, overcoming the above problems has become one of the urgent issues to be addressed by those skilled in the art. Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a circuit and method for automatically calculating rotor speed, which solves the problems of the prior art's method of calculating rotor speed, which heavily relies on rotor position information, is cumbersome and complicated to operate, has a long calculation time, is not friendly to functions that require strict time control, and occupies a long CPU time.

[0012] To achieve the above and other related objectives, the present invention provides a circuit for automatically calculating rotor speed, the circuit for automatically calculating rotor speed comprising at least:

[0013] The edge generation module receives the three-phase Hall signals U, V, and W, and generates the edge response signals of each phase Hall signal respectively.

[0014] The counting module, connected to the output of the edge generation module, counts the time difference between two adjacent transitions of each phase Hall signal based on the output signal of the edge generation module to obtain the count value of each phase, outputs the current count value, and generates a trigger signal when any phase Hall signal transitions.

[0015] The division module, connected to the output of the counting module, divides the angle difference between two adjacent transitions of the Hall signal by the current count value to obtain the motor speed.

[0016] Optionally, the counting module includes a first counting unit, a second counting unit, a third counting unit, a selection unit, an OR logic unit, and a flip-flop;

[0017] The first counting unit, the second counting unit, and the third counting unit receive a counting trigger signal and a corresponding edge response signal, and count the time difference between two adjacent transitions of each phase Hall signal to obtain the count value of each phase.

[0018] The selection unit is connected to the output terminals of the first counting unit, the second counting unit, and the third counting unit, and receives each edge response signal; when two or more Hall signals change simultaneously, the corresponding count value of the Hall signal is output as the current count value according to the priority order of U, V, W; when each Hall signal changes separately, the count value corresponding to the change is output as the current count value.

[0019] The OR logic unit receives each edge response signal and performs an OR logic operation;

[0020] The trigger is connected to the output terminal of the OR logic unit, and outputs the trigger signal when the output signal of the OR logic unit is valid.

[0021] Optionally, the first counting unit, the second counting unit, or the third counting unit includes a first selector, a second selector, a first D flip-flop, and an adder;

[0022] The first input terminal of the first selector is connected to the output terminal of the first D flip-flop, the second input terminal is connected to the output terminal of the adder, and the control terminal is connected to the counting trigger signal.

[0023] The first input terminal of the second selector is connected to the output terminal of the first selector, the second input terminal is connected to a low-level signal, and the control terminal is connected to the edge response signal of the corresponding phase Hall signal.

[0024] The data input terminal of the first D flip-flop is connected to the output terminal of the second selector;

[0025] The input terminals of the adder are respectively connected to the output terminal of the first D flip-flop and a high-level signal. When the output signal of the first D flip-flop is valid, an increment operation is performed, and the corresponding phase count value is output.

[0026] When the control signal of each selector is valid, the signal output of the second input terminal is selected; when the control signal is invalid, the signal output of the first input terminal is selected.

[0027] Alternatively, the selection unit may include a third selector, a fourth selector, and a fifth selector;

[0028] The first input terminal of the third selector is connected to a low-level signal, the second input terminal is connected to the output terminal of the first counting unit, and the control terminal is connected to the edge response signal of the W-phase Hall signal.

[0029] The first input terminal of the fourth selector is connected to the output terminal of the third selector, the second input terminal is connected to the output terminal of the second counting unit, and the control terminal is connected to the edge response signal of the V-phase Hall signal.

[0030] The first input terminal of the fifth selector is connected to the output terminal of the fourth selector, the second input terminal is connected to the output terminal of the third counting unit, and the control terminal is connected to the edge response signal of the U-phase Hall signal.

[0031] When the control signal of each selector is valid, the signal output of the second input terminal is selected; when the control signal is invalid, the signal output of the first input terminal is selected.

[0032] Alternatively, the counting module further includes a filtering unit; the filtering unit is connected to the output of the selection unit and the OR logic unit, and receives the upper limit value and the lower limit value of the count, and outputs the current count value when any phase Hall signal changes and the current count value is between the upper limit value and the lower limit value of the count.

[0033] Alternatively, the filtering unit includes a first comparator, a second comparator, an AND gate, a sixth selector, and a second D flip-flop;

[0034] The input of the first comparator is connected to the output of the selection unit and the lower limit of the filter, respectively, and outputs the first comparison result;

[0035] The input of the second comparator is connected to the output of the selection unit and the upper limit of the filter, respectively, and outputs the second comparison result;

[0036] The input terminals of the AND logic gate are respectively connected to the first comparator, the second comparator, and the output terminal of the OR logic unit. When the current count value is greater than or equal to the lower limit of the filter and less than or equal to the upper limit of the filter, and any phase Hall signal changes, an effective filter control signal is output.

[0037] The first input terminal of the sixth selector is connected to the output terminal of the second D flip-flop, the second input terminal is connected to the output terminal of the selection unit, and the control terminal is connected to the output terminal of the AND logic gate; when the filter control signal is valid, the output signal of the selection unit is selected for output; when the filter control signal is invalid, the output signal of the second D flip-flop is selected for output.

[0038] The data input terminal of the second D flip-flop is connected to the output terminal of the sixth selector, and outputs the filtered current count value.

[0039] Alternatively, the lower filter limit and the upper filter limit are provided by registers.

[0040] Optionally, the angle difference between two adjacent transitions of the Hall signal is 180°.

[0041] To achieve the above and other related objectives, the present invention also provides a method for automatically calculating rotor speed, the method comprising at least:

[0042] 1) Generate the edge response signals of the three-phase Hall signals U, V, and W respectively;

[0043] 2) Based on the edge response signals of each phase Hall signal, count the time difference between two adjacent transitions of each phase Hall signal to obtain the count value of each phase, and output the current count value;

[0044] 3) Divide the angle difference between two consecutive Hall signal transitions by the current count value to calculate the motor speed.

[0045] Optionally, in step 1), the edge response signal includes a rising edge response signal and a falling edge response signal.

[0046] Optionally, in step 2), the time difference between two adjacent transitions of each phase Hall signal is counted; when two or more phase Hall signals transition simultaneously, the corresponding count value of the phase Hall signal is output as the current count value according to the priority order of U, V, W; when each phase Hall signal transitions separately, the count value corresponding to the transition is output as the current count value.

[0047] Alternatively, step 2) may also include the step of filtering the current count value and then outputting it.

[0048] Alternatively, the filtering method includes: outputting the current count value when any phase Hall signal changes and the current count value is between the upper and lower count limits, otherwise filtering it out.

[0049] As described above, the circuit and method for automatically calculating rotor speed of the present invention have the following beneficial effects:

[0050] The circuit and method for automatically calculating rotor speed of the present invention are based on hardware circuitry using the jump of the same phase Hall signal to calculate the rotational speed, and use register writing to filter the time difference; it does not rely on rotor position information, and the rotational speed calculation is accurate; it is convenient and simple to operate, does not require high technical personnel skills, and can reduce development time; it does not require complex software programs, and has low CPU resource consumption; it has a wide range of applications, and is suitable for ideal conditions, Hall deviation conditions, and phase loss conditions. Attached Figure Description

[0051] Figure 1 This diagram illustrates the relationship between the rotor angle and the three-phase Hall signal under ideal conditions.

[0052] Figure 2 This diagram illustrates the relationship between rotor angle and three-phase Hall signals in the presence of Hall bias.

[0053] Figure 3 This diagram illustrates the relationship between the rotor angle and the three-phase Hall signals in the case of phase loss.

[0054] Figure 4 The diagram shown is a schematic representation of the circuit for automatically calculating the rotor speed according to the present invention.

[0055] Figure 5 The diagram shown is a structural schematic of the counting module of the present invention.

[0056] Figure 6 The diagram shown is a structural schematic of the first counting unit of the present invention.

[0057] Component designation explanation

[0058] 1. Circuit for automatically calculating rotor speed

[0059] 11 Edge Generation Module

[0060] 12 Counting Modules

[0061] 121 First Counting Unit

[0062] 12a First Selector

[0063] 12b Second Selector

[0064] 12c First D Flip-Flop

[0065] 12d adder

[0066] 122 Second counting unit

[0067] 123 Third counting unit

[0068] 124 Selection Unit

[0069] 12e Third Selector

[0070] 12f Fourth Selector

[0071] 12g Fifth Selector

[0072] 125 OR logic unit

[0073] 126 triggers

[0074] 127 Filtering Unit

[0075] 12h First comparator

[0076] 12i Second Comparator

[0077] 12j AND logic gate

[0078] 12k Sixth Selector

[0079] 12L Second D Flip-Flop

[0080] 13 Division Module

[0081] 14 Central Processing Unit Detailed Implementation

[0082] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0083] Please see Figures 1-6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0084] Three Hall effect sensors are evenly arranged at 120° electrical angles on an integrated circuit board at the end of the motor to provide feedback on the rotor's position. Each Hall sensor generates a 0 or 1 logic level based on the polarity of its corresponding magnetic pole piece. As the motor rotates, the three-phase Hall signals {U, V, W} change periodically in the sequence 5, 4, 6, 2, 3, 1. Theoretically, the angle difference between any two adjacent Hall signals is 60°. Figure 1 As shown, PHU is the U-phase Hall signal, PHV is the V-phase Hall signal, and PHW is the W-phase Hall signal. However, due to Hall bias, the Hall signals may lead or lag, causing the angle difference between adjacent Hall signals to be greater than 60° or less than 60°, such as... Figure 2 As shown, the V-phase Hall signal PHV lags behind, while the W-phase Hall signal PHW leads; therefore, calculating the rotor speed using the angle and time difference between two adjacent Hall signal transitions is inaccurate. Furthermore, in the case of phase loss, such as... Figure 3 As shown, the W-phase Hall signal PHW drops phase, and the angle difference between two adjacent Hall signals is no longer 60°, but becomes 120°, 60°, 120°. At this time, the calculated rotor speed is also incorrect and cannot be used.

[0085] However, regardless of the Hall deviation between the three Hall sensors, the angle difference between two adjacent transitions of the same Hall signal is fixed, such as... Figure 1 and Figure 2 As shown, regardless of whether it's an ideal situation or a leading or lagging situation, the angle difference between two adjacent transitions of the U-phase Hall signal PHU is 180°, and the same applies to the V-phase Hall signal and the W-phase Hall signal PHW. However, in the case of phase loss, except for the phase-loss W-phase Hall signal PHW, the angle difference between two adjacent transitions of the other two phases is also 180°.

[0086] This invention calculates the rotor speed based on the angle and time difference between two adjacent transitions of the same Hall signal, thus obtaining an accurate rotor speed. This avoids the complex procedure of compensating for Hall bias and is simple and convenient to operate. The specific solution is as follows:

[0087] Example 1

[0088] like Figure 4 As shown, this embodiment provides a circuit 1 for automatically calculating rotor speed. The circuit 1 for automatically calculating rotor speed includes:

[0089] Edge generation module 11, counting module 12 and division module 13.

[0090] like Figure 4 As shown, the edge generation module 11 receives the three-phase Hall signals U, V, and W, and generates the edge response signals of each phase Hall signal respectively.

[0091] Specifically, the edge generation module 11 receives the U-phase Hall signal PHU, the V-phase Hall signal PHV, and the W-phase Hall signal PHW. The edge generation module 11 responds to the rising and falling edges of the W-phase Hall signal PHW and generates a first edge response signal Wchg; it responds to the rising and falling edges of the V-phase Hall signal PHV and generates a second edge response signal Vchg; and it responds to the rising and falling edges of the U-phase Hall signal PHU and generates a third edge response signal Uchg. Any circuit structure capable of achieving dual-edge (rising and falling edge) detection is applicable to this invention, and will not be elaborated upon here. As an example, when the Hall signal changes, a corresponding pulse signal is generated as the edge response signal.

[0092] like Figure 4 As shown, the counting module 12 is connected to the output terminal of the edge generation module 11. Based on the output signal of the edge generation module 11, it counts the time difference between two adjacent transitions of each phase Hall signal to obtain the count value of each phase and outputs the current count value; and generates a trigger signal DivTrig when any phase Hall signal transitions.

[0093] Specifically, such as Figure 5 As shown, in this embodiment, the counting module 12 includes a first counting unit 121, a second counting unit 122, a third counting unit 123, a selection unit 124, an or logic unit 125, and a flip-flop 126.

[0094] More specifically, such as Figure 5 As shown, the first counting unit 121, the second counting unit 122, and the third counting unit 123 receive a counting trigger signal Cnt_trig and a corresponding edge response signal, and count the time difference between two adjacent transitions of each phase Hall signal; wherein, the first counting unit 121 receives a first edge response signal Wchg and the counting trigger signal Cnt_trig, and counts the time difference between two adjacent transitions of the W-phase Hall signal PHW; the second counting unit 122 receives a second edge response signal Vchg and the counting trigger signal Cnt_trig, and counts the time difference between two adjacent transitions of the V-phase Hall signal PHV; the third counting unit 123 receives a third edge response signal Uchg and the counting trigger signal Cnt_trig, and counts the time difference between two adjacent transitions of the U-phase Hall signal PHU. As an example, Figure 6As shown, the first counting unit 121 includes a first selector 12a, a second selector 12b, a first D flip-flop 12c, and an adder 12d. The first input terminal of the first selector 12a is connected to the output terminal of the first D flip-flop 12c, the second input terminal is connected to the output terminal of the adder 12d, and the control terminal is connected to the counting trigger signal Cnt_trig. The first input terminal of the second selector 12b is connected to the output terminal of the first selector 12a, the second input terminal is connected to the low-level signal "0", and the control terminal is connected to the first edge response signal Wchg. The data input terminal D of the first D flip-flop 12c is connected to the output terminal of the second selector 12b. The input terminals of the adder 12d are respectively connected to the output terminal of the first D flip-flop 12c and the high-level signal "1". When the output signal of the first D flip-flop 12c is valid, an increment operation is performed, and the W-phase count value W_Cnt is output. When the control signal of each selector is valid, the signal output of the second input terminal is selected; when the control signal is invalid, the signal output of the first input terminal is selected. The second counting unit 122 and the third counting unit 123 have the same structure as the first counting unit 121. The difference is that the control terminal of the second selector 12b in the second counting unit 122 receives the second edge response signal Vchg and finally outputs the V-phase count value V_Cnt; the control terminal of the second selector 12b in the third counting unit 123 receives the third edge response signal Uchg and finally outputs the U-phase count value U_Cnt. The specific structure will not be described in detail here.

[0095] It should be noted that any circuit structure capable of counting the time difference between two adjacent transitions of the Hall signal is applicable to the present invention; furthermore, the structures of the first counting unit 121, the second counting unit 122, and the third counting unit 123 may also be different, and are not limited to this embodiment.

[0096] More specifically, such as Figure 5As shown, the selection unit 124 is connected to the output terminals of the first counting unit 121, the second counting unit 122 and the third counting unit 123, and receives each edge response signal; when two or more Hall signals change simultaneously, the corresponding count value of the Hall signal is output as the current count value UVW_Cnt according to the priority order of U, V, W (U phase has the highest priority, followed by V phase, and finally W phase); when each Hall signal changes separately, the count value corresponding to the change is output as the current count value UVW_Cnt. As an example, the selection unit 124 includes a third selector 12e, a fourth selector 12f, and a fifth selector 12g. The first input terminal of the third selector 12e is connected to a low-level signal "0", the second input terminal is connected to the W-phase count value W_Cnt output by the first counting unit 121, and the control terminal is connected to the first edge response signal Wchg. The first input terminal of the fourth selector 12f is connected to the output terminal of the third selector 12e, the second input terminal is connected to the V-phase count value V_Cnt output by the second counting unit 122, and the control terminal is connected to the second edge response signal Vchg. The first input terminal of the fifth selector 12g is connected to the output terminal of the fourth selector 12f, the second input terminal is connected to the U-phase count value U_Cnt output by the third counting unit 123, and the control terminal is connected to the third edge response signal Uchg, ultimately outputting the current count value UVW_Cnt. When the control signal of each selector is valid, the signal output of the second input terminal is selected; when the control signal is invalid, the signal output of the first input terminal is selected.

[0097] It should be noted that any circuit structure capable of achieving the above functions is applicable to the selection unit of this invention, and is not limited to this embodiment. Under normal operating conditions, the three-phase Hall signals U, V, and W alternately and periodically change, and the count values ​​corresponding to each phase Hall signal are output sequentially according to the changing order; in the case of one phase loss, the count values ​​corresponding to the Hall signals of the phases that have not been lost are output sequentially according to the changing order; in the case of two phase loss, the count values ​​corresponding to the Hall signals of the phases that have not been lost are output.

[0098] More specifically, such as Figure 5 As shown, the OR logic unit 125 receives each edge response signal and performs an OR logic operation; when any one of the first edge response signal Wchg, the second edge response signal Vchg, and the third edge response signal Uchg is valid, the output signal of the OR logic unit 125 is valid (active high). As an example, the OR logic unit 125 is implemented using a three-input OR gate. In actual use, OR logic can be implemented based on multiple logic elements, and is not limited to this embodiment.

[0099] More specifically, such as Figure 5As shown, the trigger 126 is connected to the output terminal of the OR logic unit 125. When the output signal of the OR logic unit 125 is valid, the trigger signal DivTrig is output; that is, when any phase Hall signal changes, the trigger signal DivTrig is valid.

[0100] More specifically, as another implementation of the present invention, such as Figure 5 As shown, the counting module 12 further includes a filtering unit 127, which is connected to the output of the selection unit 124 and the OR logic unit 125, and receives the upper limit value rp_LmtH and the lower limit value rp_LmtL. When any phase Hall signal changes and the current count value UVW_Cnt is between the upper limit value rp_LmtH and the lower limit value rp_LmtL (including the endpoint values ​​rp_LmtH and rp_LmtL), the current count value UVW_Cnt is output. As an example, the filtering unit 127 includes a first comparator 12h, a second comparator 12i, an AND gate 12j, a sixth selector 12k, and a second D flip-flop 12l; the input of the first comparator 12h is connected to the output of the selector 124 and the lower filter limit value rp_LmtL, and outputs a first comparison result; the input of the second comparator 12i is connected to the output of the selector 124 and the upper filter limit value rp_LmtH, and outputs a second comparison result; the input of the AND gate 12j is connected to the first comparator 12h, the second comparator 12i, and the output of the OR logic unit 125, and outputs a second comparison result when the current count value is greater than or equal to the filter limit value rp_LmtH. The lower limit value rp_LmtL is less than or equal to the upper limit value rp_LmtH, and a valid filter control signal is output when any phase Hall signal changes. The first input terminal of the sixth selector 12k is connected to the output terminal of the second D flip-flop 12l, the second input terminal is connected to the output terminal of the selection unit 124, and the control terminal is connected to the output terminal of the AND logic gate 12j. When the filter control signal is valid, the output signal of the selection unit 124 is selected for output, and when the filter control signal is invalid, the output signal of the second D flip-flop 12l is selected for output. The data input terminal D of the second D flip-flop 12l is connected to the output terminal of the sixth selector 12k, and the filtered current count value Divisor is output.

[0101] It should be noted that the lower filter limit rp_LmtL and the upper filter limit rp_LmtH are provided by registers. In this embodiment, the registers are located in the central processing unit 14, such as... Figure 4As shown; in practical use, the position of the registers can be set as needed. Any circuit structure that can achieve the above filtering function is applicable to this invention, and is not limited to this embodiment. This invention only requires configuring two registers to eliminate unreasonable count values ​​and achieve the purpose of filtering. It does not require complex software programs, is convenient and simple to operate, has a short calculation time, and can also reduce CPU usage time.

[0102] like Figure 4 As shown, the division module 13 is connected to the output terminal of the counting module 12, and divides the angle difference between two adjacent transitions of the Hall signal by the count value output by the counting module 12 to obtain the motor speed Result.

[0103] Specifically, the angle difference between two consecutive Hall signal transitions is 180°. When the trigger signal DivTrig is active (for example, the trigger signal DivTrig is active high), the motor speed Result is obtained by dividing the angle difference between two consecutive Hall signal transitions by the time difference between two consecutive transitions of the same Hall signal. The implementation of the trigger module is not limited and will not be elaborated here. In this embodiment, the count value output by the counting module 12 is the filtered current count value Divisor. In actual use, the count value output by the counting module 12 can also be the current count value UVW_Cnt.

[0104] The working principle of this invention is as follows:

[0105] Ideally, the three Hall sensors are precisely installed, all three phases (UV, W, and RC) are working normally, and the Hall signals can accurately reflect the rotor's position information. At this time, the angle difference between two adjacent transitions of each phase (UV, W, RC) is 180°, and the count values ​​of the three phases (U_Cnt, V_Cnt, W_Cnt) are all normal. The rotational speed can be accurately calculated 6 times within one cycle of motor operation.

[0106] In the presence of Hall bias, the rotor position information reflected by the Hall signal is biased, but all three phases UVW can work. At this time, the angle difference between two adjacent jumps of each phase of UVW is 180°, and the count values ​​U_Cnt, V_Cnt, and W_Cnt of the three phases are normal. The speed can be accurately calculated 6 times within one cycle of motor operation.

[0107] In the event of a phase loss, if phase U is lost and phases V and W are operating, the angle difference between two consecutive transitions of phases V and W is 180°. The count values ​​V_Cnt and W_Cnt for phases V and W are normal, and the motor speed can be accurately calculated four times within one cycle. If phases U and V are lost and phase W is operating, the angle difference between two consecutive transitions of phase W is 180°, and the count value W_Cnt for phase W is normal. The motor speed can be accurately calculated twice within one cycle.

[0108] Therefore, the present invention is flexible and quick to operate, and has a wide range of applications. It is applicable not only to ideal situations, but also to situations involving Hall effect deviation and phase loss.

[0109] Example 2

[0110] This embodiment provides a method for automatically calculating rotor speed. As an example, the method for automatically calculating rotor speed is based on the circuit for automatically calculating rotor speed in Embodiment 1. In practical use, any hardware or software device capable of implementing this method is applicable. The method for automatically calculating rotor speed includes at least the following:

[0111] 1) Generate the edge response signals of the three-phase Hall signals U, V, and W respectively.

[0112] Specifically, each phase of the Hall signal corresponds to an edge response signal, which includes a rising edge response signal and a falling edge response signal. As an example, when the Hall signal changes, a pulse signal is generated, wherein the Hall signal change includes a rising edge change and a falling edge change, that is, a corresponding pulse signal is generated when the Hall signal changes to a rising edge or a falling edge.

[0113] 2) Based on the edge response signal of each phase Hall signal, count the time difference between two adjacent transitions of each phase Hall signal to obtain the count value of each phase, and output the current count value.

[0114] Specifically, the time difference between two adjacent transitions of each phase Hall signal is counted. For any phase Hall signal, counting begins when the current pulse of the edge response signal is received, and restarts when the next pulse is received, and so on, continuously updating the count value.

[0115] Specifically, in this embodiment, the current count value UVW_Cnt is obtained by selecting the output order of each phase count value. At this time, when two or more Hall signals change simultaneously, the count value corresponding to the Hall signal is output according to the priority order of U, V, and W. For example, when three Hall signals change simultaneously, the U-phase count value is output; when U and V change simultaneously, the U-phase count value is output; when U and W change simultaneously, the U-phase count value is output; when V and W change simultaneously, the V-phase count value is output. Normally, two or more Hall signals will not change simultaneously. If this occurs, it indicates a phase drop or other fault, and this situation will not last long; most of the time, each phase Hall signal changes independently. When each phase Hall signal changes independently, the count value corresponding to the change is output; that is, if any phase Hall signal has an output and changes, the count value corresponding to that phase Hall signal is output.

[0116] Specifically, as one implementation of the present invention, it further includes the step of filtering the current count value UVW_Cnt before outputting it. When any phase Hall signal changes and the current UVW_Cnt count value is between the upper limit of the count rp_LmtH and the lower limit of the count rp_LmtL, the current count value is output; otherwise, it is filtered out. This improves the accuracy of the final result.

[0117] It should be noted that the upper limit value rp_LmtH and the lower limit value rp_LmtL of the count are provided by registers, eliminating the need for software engineers to write complex filtering software programs based on motor theory and mathematical theory, making the operation convenient and simple.

[0118] 3) Divide the angle difference between two consecutive Hall signal transitions by the current count value to calculate the motor speed.

[0119] Specifically, the angle difference between two adjacent transitions of the Hall signal is 180°. Dividing 180° by the current count value yields the current motor speed Result. This method calculates the motor speed based on the signal from the same Hall sensor, without relying on the rotor's position information, and does not affect the accuracy of the rotor speed calculation. Furthermore, even if two Hall sensors lose phase, the rotor speed can be accurately calculated as long as one Hall sensor is working. Therefore, the applicability of this invention is more extensive.

[0120] It should be noted that after the filtering operation is performed in step 2), in step 3), 180° is divided by the current count value Divisor after filtering. This will not be elaborated on here.

[0121] In summary, this invention provides a circuit and method for automatically calculating rotor speed, comprising: an edge generation module that receives three-phase Hall signals (U, V, and W) and generates edge response signals for each phase Hall signal; a counting module connected to the output of the edge generation module that counts the time difference between two adjacent transitions of each phase Hall signal based on the output signal of the edge generation module to obtain a count value for each phase and outputs the current count value; and generates a trigger signal when any phase Hall signal transitions; and a division module connected to the output of the counting module that divides the angle difference between two adjacent transitions of the Hall signal by the current count value to obtain the motor speed. The circuit and method for automatically calculating rotor speed of this invention calculate the speed based on the transition of the same phase Hall signal using hardware circuitry and filters the time difference using register writing; it does not rely on rotor position information, and the speed calculation is accurate; it is convenient and simple to operate, requiring minimal technical expertise and reducing development time; it does not require complex software programs and consumes minimal CPU resources; it has a wide range of applications, suitable for ideal conditions, Hall signal deviation, and phase loss. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A circuit for automatically calculating rotor speed, characterized in that, The circuit for automatically calculating the rotor speed includes at least: The edge generation module receives the three-phase Hall signals U, V, and W, and generates the edge response signals of each phase Hall signal respectively. A counting module, connected to the output of the edge generation module, counts the time difference between two adjacent transitions of each phase Hall signal based on the output signal of the edge generation module to obtain the count value of each phase, and outputs the current count value; and generates a trigger signal when any phase Hall signal transitions; wherein, the counting module includes a first counting unit, a second counting unit, a third counting unit, a selection unit, an OR logic unit, and a flip-flop; the first counting unit, the second counting unit, and the third counting unit receive the counting trigger signal and the corresponding edge response signal, and count the time difference between two adjacent transitions of each phase Hall signal respectively. The system obtains the count values ​​for each phase; the selection unit is connected to the output terminals of the first counting unit, the second counting unit, and the third counting unit, and receives each edge response signal; when two or more Hall signals change simultaneously, the corresponding count value of the Hall signal of the corresponding phase is output as the current count value according to the priority order of U, V, W; when each Hall signal changes separately, the count value corresponding to the change is output as the current count value; the OR logic unit receives each edge response signal and performs OR logic operation; the trigger is connected to the output terminal of the OR logic unit, and outputs the trigger signal when the output signal of the OR logic unit is valid; The division module, connected to the output of the counting module, divides the angle difference between two adjacent transitions of the Hall signal by the current count value to obtain the motor speed.

2. The circuit for automatically calculating rotor speed according to claim 1, characterized in that: The first counting unit, the second counting unit, or the third counting unit includes a first selector, a second selector, a first D flip-flop, and an adder; The first input terminal of the first selector is connected to the output terminal of the first D flip-flop, the second input terminal is connected to the output terminal of the adder, and the control terminal is connected to the counting trigger signal. The first input terminal of the second selector is connected to the output terminal of the first selector, the second input terminal is connected to a low-level signal, and the control terminal is connected to the edge response signal of the corresponding phase Hall signal. The data input terminal of the first D flip-flop is connected to the output terminal of the second selector; The input terminals of the adder are respectively connected to the output terminal of the first D flip-flop and a high-level signal. When the output signal of the first D flip-flop is valid, an increment operation is performed, and the corresponding phase count value is output. When the control signal of each selector is valid, the signal output of the second input terminal is selected; when the control signal is invalid, the signal output of the first input terminal is selected.

3. The circuit for automatically calculating rotor speed according to claim 1, characterized in that: The selection unit includes a third selector, a fourth selector, and a fifth selector; The first input terminal of the third selector is connected to a low-level signal, the second input terminal is connected to the output terminal of the first counting unit, and the control terminal is connected to the edge response signal of the W-phase Hall signal. The first input terminal of the fourth selector is connected to the output terminal of the third selector, the second input terminal is connected to the output terminal of the second counting unit, and the control terminal is connected to the edge response signal of the V-phase Hall signal. The first input terminal of the fifth selector is connected to the output terminal of the fourth selector, the second input terminal is connected to the output terminal of the third counting unit, and the control terminal is connected to the edge response signal of the U-phase Hall signal. When the control signal of each selector is valid, the signal output of the second input terminal is selected; when the control signal is invalid, the signal output of the first input terminal is selected.

4. The circuit for automatically calculating rotor speed according to any one of claims 1-3, characterized in that: The counting module further includes a filtering unit; the filtering unit is connected to the output of the selection unit and the OR logic unit, and receives the upper limit value and the lower limit value of the count. When any phase Hall signal changes and the current count value is between the upper limit value and the lower limit value of the count, the current count value is output.

5. The circuit for automatically calculating rotor speed according to claim 4, characterized in that: The filtering unit includes a first comparator, a second comparator, an AND logic gate, a sixth selector, and a second D flip-flop; The input of the first comparator is connected to the output of the selection unit and the lower limit of the filter, respectively, and outputs the first comparison result; The input of the second comparator is connected to the output of the selection unit and the upper limit of the filter, respectively, and outputs the second comparison result; The input terminals of the AND logic gate are respectively connected to the first comparator, the second comparator, and the output terminal of the OR logic unit. When the current count value is greater than or equal to the lower limit of the filter and less than or equal to the upper limit of the filter, and any phase Hall signal changes, an effective filter control signal is output. The first input terminal of the sixth selector is connected to the output terminal of the second D flip-flop, the second input terminal is connected to the output terminal of the selection unit, and the control terminal is connected to the output terminal of the AND logic gate; when the filter control signal is valid, the output signal of the selection unit is selected for output; when the filter control signal is invalid, the output signal of the second D flip-flop is selected for output. The data input terminal of the second D flip-flop is connected to the output terminal of the sixth selector, and outputs the filtered current count value.

6. The circuit for automatically calculating rotor speed according to claim 4, characterized in that: The lower limit and the upper limit of the filter are provided by a register.

7. The circuit for automatically calculating rotor speed according to claim 1, characterized in that: The angle difference between two consecutive transitions of the Hall signal is 180°.

8. A method for automatically calculating rotor speed, characterized in that, The method for automatically calculating rotor speed includes at least the following: 1) Generate the edge response signals of the three-phase Hall signals U, V, and W respectively; 2) Based on the edge response signals of each phase Hall signal, the time difference between two adjacent transitions of each phase Hall signal is counted to obtain the count value of each phase, and the current count value is output; wherein, the time difference between two adjacent transitions of each phase Hall signal is counted; when two or more phase Hall signals transition simultaneously, the count value corresponding to the corresponding phase Hall signal is output as the current count value according to the priority order of U, V, W; when each phase Hall signal transitions separately, the count value corresponding to the transition is output as the current count value. 3) Divide the angle difference between two consecutive Hall signal transitions by the current count value to calculate the motor speed.

9. The method for automatically calculating rotor speed according to claim 8, characterized in that: In step 1), the edge response signal includes a rising edge response signal and a falling edge response signal.

10. The method for automatically calculating rotor speed according to any one of claims 8-9, characterized in that: Step 2) also includes the step of filtering the current count value and then outputting it.

11. The method for automatically calculating rotor speed according to claim 10, characterized in that: The filtering method includes: when any phase Hall signal changes and the current count value is between the upper and lower count limits, the current count value is output; otherwise, it is filtered out.

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