A dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors

Abstract

The application provides a dual-core wide-tuning millimeter wave voltage-controlled oscillator based on mode switching common-mode and differential-mode inductance, head drain end inductance and head source end inductance are added on the basis of head gate end inductance, so that a larger common-mode and differential-mode inductance value difference is realized under a small area, and the frequency is fixed by mode switching common-mode and differential-mode inductance value to expand the frequency tuning range of the dual-core VCO and keep low phase noise. The equivalent common-mode inductance can be flexibly changed by adjusting the head gate end inductance, the head drain end inductance and the coupling coefficient between the two, and the frequency gap between the highest frequency of the common-mode and the lowest frequency of the differential-mode is effectively controlled.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors. Background Technology

[0002] Software-defined radio frequency synthesizers, wireless infrastructure systems, and test equipment require voltage-controlled oscillators (VCOs) to meet stringent phase noise performance while covering a wide frequency tuning range. Unfortunately, widening the VCO's frequency tuning range while maintaining low phase noise in the millimeter-wave band is impractical due to the small variable capacitor regulation ratio and the presence of significant parasitic capacitance. Alternatively, frequency fixing by switching the transformer resonator to operate in low- or high-frequency mode, combined with variable capacitors, has been reported to widen the VCO's frequency tuning range. However, this wide-tuning VCO suffers from a frequency gap greater than 10 GHz between its high and low-frequency operating modes, limiting its application. Because the Q value of inductors is high in the millimeter-wave band, it becomes possible to increase the VCO's frequency tuning range while maintaining low phase noise by adjusting the inductance value. Current work has explored widening the VCO's operating range by adjusting the inductance value, but these methods suffer from various problems, such as the mode selection switch being directly connected in parallel with the inductor. The current flowing through the switch significantly reduces the resonator's Q value, severely deteriorating the phase noise performance of the wide-tuning VCO. Furthermore, the phase noise of some broadband VCOs varies significantly across the entire operating range, attributed to the varying losses between different modes, leading to substantial changes in the resonant cavity's Q value. To date, the most efficient method for widening the frequency tuning range of a VCO is through resonant mode switching. Ideally, since no current flows through the mode switching switch, the Q value of the resonant cavity is not reduced. Based on this, some have proposed using the center tap inductance of the mode switching inductor in the millimeter-wave band to fix the frequency and widen the VCO's frequency tuning range, mitigating the trade-off between tuning range and phase noise. However, to ensure the common-mode current returns to the short path and minimize the impact of the decoupling inductor, although this VCO has two operating modes, its tuning range is only 16.5%. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and propose a dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors. This oscillator achieves a large difference in inductance between the common-mode and differential-mode inductances within a small area, thereby widening the tuning range, reducing phase noise, and always ensuring that the common-mode current returns to the short path.

[0004] This invention is achieved through the following technical solution:

[0005] A dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors includes a first negative resistance amplifier, a second negative resistance amplifier, a first multi-coil coupled resonant cavity, a second multi-coil coupled resonant cavity, and a mode-switching module; the mode-switching module is used to switch the first and second multi-coil coupled resonant cavities between common-mode and differential-mode.

[0006] The first multi-winding transformer coupled resonant cavity includes a first drain inductor L. D1 Third leakage inductance L D3 First source inductor L S1 Third source inductor L S3 Fifth head source terminal inductor L S5 Second gate inductor L G2 Fourth gate inductor L G4 First head gate inductor L G5 and the first head drain inductance L D5 First drain inductance L D1 One end, the first source inductor L S1 One end and the second gate inductance L G2 One end of each is connected to the first negative resistance amplifier; the third leakage inductance L D3 One end, the third source end inductor L S3 One end and the fourth gate inductor L G4 One end of each is connected to the second negative resistance amplifier; the first source inductor L S1 The other end is connected to the third source inductor L S3 The other end is connected to the fifth head source inductor L. S5 One end is connected; the fifth head source inductor L S5 The other end is connected to ground; the second gate inductor L G2 The other end and the fourth gate inductor L G4 The other end is connected to the first head gate inductor L G5 One end is connected to the first head gate inductor L G5 The other end is connected to the first bias voltage input terminal V. B1 First drain inductance L D1 The other end and the third drain inductor L D3 The other end is connected to the drain inductance L of the first head. D5 One end is connected, and the first head drain inductance L D5 The other end is connected to the power supply voltage V. DD ;

[0007] The second multi-winding coupled transformer resonant cavity includes a second drain inductor L. D2 Fourth leakage inductance L D4 Second source inductor L S2Fourth source inductor L S4 The sixth head source inductor L S6 First gate inductance L G1 Third gate inductor L G3 Second head gate inductor L G6 Second head drain inductance L D6 First gate inductance L G1 One end and the second drain inductance L D2 One end and the second source end inductor L S2 One end of each is connected to the first negative resistance amplifier; the third gate inductor L G3 The other end, the fourth drain inductor L D4 One end and the fourth source end inductor L S4 One end of each is connected to the second negative resistance amplifier; the first gate inductor L G1 The other end and the third gate inductor L G3 The other end is connected to the second head gate inductor L G6 One end is connected, and the second head gate inductor L G6 The other end is connected to the second bias voltage input terminal V. B2 Second drain inductance L D2 The other end is connected to the fourth drain inductor L D4 The other end is connected to the drain inductance L of the second head. D6 One end is connected, and the drain inductance L of the second head is connected. D6 The other end is connected to the power supply voltage V. DD Second source inductor L S2 The other end is connected to the fourth source inductor L S4 The other end is connected to the sixth head source inductor L. S6 One end is connected; the fifth head source inductor L S5 The other end and the sixth head source inductor L S6 The other end of each is connected to the ground.

[0008] Preferably, the first drain inductance L D1 Each with the second gate inductor L G2 and the first source inductor L S1 In-phase coupling, first source inductor L S1 With the second gate inductor L G2 In-phase coupling, third drain inductance L D3 Each with the fourth gate inductor L G4 and the third source inductor L S3 In-phase coupling, third source inductor L S3 With the fourth gate inductor L G4 In-phase coupling, first head gate inductance L G5 With the first head drain inductance LD5 In-phase coupling; second drain inductance L D2 Each with the first gate inductor L G1 Second source inductor L S2 In-phase coupling, second source inductor L S2 With the first gate inductor L G1 In-phase coupling, fourth drain inductance L D4 Each with the third gate inductor L G3 and the fourth source inductor L S4 In-phase coupling, fourth source inductor L S4 With the third gate inductor L G3 In-phase coupling, second head gate inductance L G6 With the second head drain inductance L D6 In-phase coupling.

[0009] Preferably, the first head gate inductor L G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6 All four are the same size.

[0010] Preferably, the first negative resistance amplifier includes a first NMOS transistor M1, a second NMOS transistor M2, and a first gate capacitor C. G1 Second gate capacitor C G2 First drain capacitor C D1 Second drain capacitor C D2 First output terminal V OUT1 Second output terminal V OUT2 First bias voltage input terminal V B1 First frequency adjustment voltage input terminal V C1 Second frequency adjustable voltage input terminal V C2 ;

[0011] The gate terminal of the first NMOS transistor M1 and the first gate inductor L G1 One end and the first gate capacitor C G1 One end is connected to the drain of the first NMOS transistor M1 and the first drain inductor L. D1 One end, the first drain capacitor C D1 One end and the first output terminal V OUT1 The source terminal of the first NMOS transistor M1 is connected to the first source inductor L. S1 One end is connected; the gate of the second NMOS transistor M2 is connected to the second gate inductor L. G2 One end and the second gate capacitor C G2 One end is connected to the drain of the second NMOS transistor M2, and the drain inductor L is connected to the drain inductor L. D2One end and the second drain capacitor C D2 One end and the second output terminal V OUT2 Connected, the source terminal of the second NMOS transistor M2 is connected to the second source inductor L. S2 One end is connected; the first gate capacitor C G1 The other end is connected to the second gate capacitor C G2 The other end is connected to the first frequency-adjustable voltage input terminal V. C1 Connected; first drain capacitor C D1 The other end is connected to the second drain capacitor C D2 The other end is connected to the second frequency adjustment voltage input terminal V. C2 Connected.

[0012] Preferably, the second negative resistance amplifier includes a third NMOS transistor M3, a fourth NMOS transistor M4, and a third gate capacitor C. G3 Fourth gate capacitor C G4 Third drain capacitor C D3 Fourth drain capacitor C D4 Third output terminal V OUT3 Fourth output terminal V OUT4 Second bias voltage input terminal V B2 Third frequency adjustment voltage input terminal V C3 and the fourth frequency adjustment voltage input terminal V C4 ;

[0013] The gate terminal of the third NMOS transistor M3 and the third gate inductor L G3 The other end and the third gate capacitor C G3 One end is connected to the drain of the third NMOS transistor M3 and the third drain inductor L. D3 The other end, the third drain capacitor C D3 One end and the third output terminal V OUT3 Connected, the source terminal of the third NMOS transistor M3 is connected to the third source inductor L. S3 The other end is connected; the gate of the fourth NMOS transistor M4 is connected to the fourth gate inductor L. G4 The other end and the fourth gate capacitor C G4 One end is connected to the drain of the fourth NMOS transistor M4 and the fourth drain inductor L. D4 The other end, the fourth drain capacitor C D4 One end and the fourth output terminal V OUT4 Connected, the source terminal of the fourth NMOS transistor M4 is connected to the fourth source inductor L. S4 The other end is connected; the third gate capacitor C G3 The other end is connected to the fourth gate capacitor C G4 The other end is connected to the third frequency-adjustable voltage input terminal V. C3Connected; third drain capacitor C D3 The other end is connected to the fourth drain capacitor C D4 The other end is connected to the fourth frequency-adjustable voltage input terminal V. C4 Connected.

[0014] Preferably, the mode switching module includes a first mode switching unit G. mc1 Second mode switching unit G mc2 Third mode switching unit G mc3 and the fourth mode switching unit G mc4 First mode switching unit G mc1 Includes a first port I1, a second port I2, a third port O1, and a fourth port O2; and a second mode switching unit G. mc2 Including port 5 (I3), port 6 (I4), port 7 (O3), and port 8 (O4); third mode switching unit G mc3 Including port 9 (I5), port 10 (I6), port 11 (O5), and port 12 (O6); fourth mode switching unit G mc4 This includes port 13 (I7), port 14 (I8), port 15 (O7), and port 16 (O8);

[0015] The first negative resistance amplifier includes a first NMOS transistor M1, a second NMOS transistor M2, and a first output terminal V. OUT1 Second output terminal V OUT2 The drain terminal of the first NMOS transistor M1 is connected to the first output terminal V. OUT1 Connected, the drain of the second NMOS transistor M2 is connected to the second output terminal V. OUT2 Connected in series; the second negative resistance amplifier includes a third NMOS transistor M3, a fourth NMOS transistor M4, and a third output terminal V. OUT3 Fourth output terminal V OUT4 The drain terminal of the third NMOS transistor M3 is connected to the third output terminal V. OUT3 Connected, the drain of the fourth NMOS transistor M4 is connected to the fourth output terminal V. OUT4 Connected;

[0016] The first port I1, the seventh port O3, the ninth port I5, and the fifteenth port O7 are all connected to the first output terminal V. OUT1 Connected to each other; the second port I2, the eighth port O4, the tenth port I6, and the sixteenth port O8 are all connected to the second output terminal V. OUT2 Connected to each other; the third port O1, the fifth port I3, the twelfth port O6, and the fourteenth port I8 are all connected to the third output terminal V. OUT3 Connected; the fourth port O2, the sixth port I4, the eleventh port O5, and the thirteenth port I7 are all connected to the fourth output terminal V. OUT4 Connected.

[0017] Furthermore, the first mode switching unit G mc1 It also includes the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, and the first enable input terminal En1;

[0018] The gate of the fifth NMOS transistor M5 is connected to the first enable input En1. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6 and the source of the seventh NMOS transistor M7. The source of the fifth NMOS transistor M5 is connected to ground. The gate of the sixth NMOS transistor M6 is connected to the first port I1. The drain of the sixth NMOS transistor M6 is connected to the third port O1. The gate of the seventh NMOS transistor M7 is connected to the second port I2. The drain of the seventh NMOS transistor M7 is connected to the fourth port O2.

[0019] Furthermore, the second mode switching unit G mc2 It also includes the eighth NMOS transistor M8, the ninth NMOS transistor M9, and the tenth NMOS transistor M... 10 And the second enable input terminal En2;

[0020] The gate of the eighth NMOS transistor M8 is connected to the second enable input En2. The drain of the eighth NMOS transistor M8 is connected to the source of the ninth NMOS transistor M9 and the tenth NMOS transistor M10. 10 The source terminal of the eighth NMOS transistor M8 is connected to ground; the gate terminal of the ninth NMOS transistor M9 is connected to the fifth port I3, and the drain terminal of the ninth NMOS transistor M9 is connected to the seventh port O3; the tenth NMOS transistor M... 10 The gate terminal is connected to the sixth port I4, and the tenth NMOS transistor M 10 The drain end is connected to the eighth port O4.

[0021] Furthermore, the third mode switching unit G mc3 It also includes the eleventh NMOS transistor M. 11 The twelfth NMOS transistor M 12 The thirteenth NMOS transistor M 13 and the third enable input En3;

[0022] Eleventh NMOS transistor M 11 The gate terminal is connected to the third enable input terminal En3, and the eleventh NMOS transistor M 11 The drain terminal of the twelfth NMOS transistor M 12 The source terminal and the thirteenth NMOS transistor M 13 Connected to the source terminal, the eleventh NMOS transistor M 11 The source terminal is connected to ground; the twelfth NMOS transistor M 12The gate terminal is connected to the ninth port I5, and the twelfth NMOS transistor M 12 The drain of the thirteenth NMOS transistor is connected to the eleventh port O5; 13 The gate terminal is connected to the tenth port I6, and the thirteenth NMOS transistor M 13 The drain end is connected to the twelfth port O6.

[0023] Furthermore, the fourth mode switching unit G mc4 It also includes the fourteenth NMOS transistor M 14 The fifteenth NMOS transistor M 15 The sixteenth NMOS transistor M 16 and the fourth enable input, En4;

[0024] The fourteenth NMOS transistor M 14 The gate terminal is connected to the fourth enable input terminal En4, and the fourteenth NMOS transistor M 14 The drain terminal of the fifteenth NMOS transistor M 15 The source terminal and the sixteenth NMOS transistor M 16 The source terminal is connected, and the fourteenth NMOS transistor M 14 The source terminal is connected to ground; the fifteenth NMOS transistor M 15 The gate terminal is connected to the thirteenth port I7, and the fifteenth NMOS transistor M... 15 The drain of the transistor is connected to the fifteenth port O7; the sixteenth NMOS transistor M... 16 The gate terminal is connected to the fourteenth port I8, and the sixteenth NMOS transistor M 16 The drain end is connected to the sixteenth port O8.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors described in this invention has a first head gate inductor L G5 Second head gate inductor L G6 Based on this, an additional first head drain inductance L was added. D5 Fifth head source terminal inductor L S5 Second head drain inductance L D6 The sixth head source inductor L S6 This allows for a significant difference in common-mode and differential-mode inductance values ​​within a small area. By switching the common-mode and differential-mode inductance values, the frequency can be fixed to broaden the frequency tuning range of the dual-core VCO while maintaining low phase noise. This invention flexibly changes the equivalent common-mode inductance by adjusting the gate inductance, drain inductance, and the coupling coefficient between them, effectively controlling the frequency gap between the highest common-mode frequency and the lowest differential-mode frequency. In this invention, the power supply voltage V... DD With LS5 L S6 The close proximity of the grounding terminals increases the common-mode inductance while ensuring that the common-mode current returns to the short path. Furthermore, the separation of the power supply voltage and bias voltage helps reduce fluctuations in the VCO's oscillation frequency due to the power supply voltage.

[0027] Furthermore, the symmetrical center-tapped transformer proposed in the dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors described in this invention helps reduce magnetic field coupling between circuits with other inductive devices.

[0028] Furthermore, in this invention, the first negative resistance amplifier includes a first gate capacitor C. G1 Second gate capacitor C G2 First drain capacitor C D1 Second drain capacitor C D2 The second negative resistance amplifier includes a third gate capacitor C. G3 Fourth gate capacitor C G4 Third drain capacitor C D3 Fourth drain capacitor C D4 This means that the number of frequency-tuning capacitors in the VCO array is doubled compared to the traditional one-port architecture, further helping to expand the frequency tuning range of this dual-core VCO. Furthermore, this invention further increases the gate-to-source feedback voltage V by reverse coupling the voltage at the MOSFET gate to the source. GS This reduces the injection noise of the transconductance transistor, thereby improving the noise performance of the dual-core wide-tunable VCO and making the VCO more suitable for operation in low-supply-voltage systems.

[0029] Furthermore, the mode switching module required for the dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors described in this invention is placed only at the drain end to reduce the influence of parasitic capacitance, and the signal phase at the gate and source ends will change with the magnetic coupling direction. In addition, this mode switching module provides energy to the required mode while consuming energy for the unused mode, helping to avoid mode ambiguity and not degrading the Q value of the resonant cavity for the required mode. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the core principle of the wide-tuning millimeter-wave voltage-controlled oscillator designed in this invention;

[0031] Figure 2 This is a schematic diagram of the mode switching module of the wide-tunable millimeter-wave voltage-controlled oscillator designed in this invention. Detailed Implementation

[0032] To further understand the present invention, the present invention will be described below with reference to embodiments. These descriptions are only for further explaining the features and advantages of the present invention and are not intended to limit the claims of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] refer to Figure 1 The present invention proposes a dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors, comprising a first negative resistance amplifier G. m1 Second negative resistance amplifier G m2 The first multi-coil coupled resonant cavity Z1, the second multi-coil coupled resonant cavity Z2, and the mode switching module G MC The output is the first output terminal V. OUT1 Second output terminal V OUT2 Third output terminal V OUT3 and the fourth output terminal V OUT4 The input is the first bias voltage input terminal V. B1 Second bias voltage input terminal V B2 First frequency adjustment voltage input terminal V C1 Second frequency adjustment voltage input terminal V C2 Third frequency adjustment voltage input terminal V C3 and the fourth frequency adjustment voltage input terminal V C4 First enable input En1, second enable input En2, third enable input En3, fourth enable input En4.

[0035] The first negative impedance amplifier G m1 Includes the first NMOS transistor M1, the second NMOS transistor M2, and the first gate capacitor C. G1 Second gate capacitor C G2 First drain capacitor C D1 Second drain capacitor C D2 First output terminal V OUT1 Second output terminal V OUT2 First bias voltage input terminal VB1 First frequency adjustment voltage input terminal V C1 Second frequency adjustment voltage input terminal V C2 Second negative resistance amplifier G m2 Including the third NMOS transistor M3, the fourth NMOS transistor M4, and the third gate capacitor C G3 Fourth gate capacitor C G4 Third drain capacitor C D3 Fourth drain capacitor C D4 Third output terminal V OUT3 Fourth output terminal V OUT4 Second bias voltage input terminal V B2 Third frequency adjustment voltage input terminal V C3 Fourth frequency adjustment voltage input terminal V C4 The first multi-coil transformer-coupled resonant cavity Z1 includes a first drain inductance L. D1 Third leakage inductance L D3 First source inductor L S1 Third source inductor L S3 Fifth head source terminal inductor L S5 Second gate inductor L G2 Fourth gate inductor L G4 First head gate inductor L G5 First head drain inductance L D5 The second multi-coil coupled transformer resonant cavity Z2 includes a second drain inductor L. D2 Fourth leakage inductance L D4 Second source inductor L S2 Fourth source inductor L S4 The sixth head source inductor L S6 First gate inductance L G1 Third gate inductor L G3 Second head gate inductor L G6 Second head drain inductance L D6 .

[0036] First bias voltage input terminal V B1 External first bias voltage, second bias voltage input terminal V B2 External second bias voltage, first frequency adjustment voltage input terminal V C1 An external first frequency adjustment voltage is used to adjust the first gate capacitor C. G1 Second gate capacitance C G2 Size, second frequency adjustment voltage input terminal V C2 An external second frequency-adjustable voltage is used to adjust the first drain capacitor C. D1 Second drain capacitor C D2Size, third frequency adjustment voltage input terminal V C3 An external third frequency adjustment voltage is used to adjust the third gate capacitor C. G3 and the fourth gate capacitor C G4 Size, fourth frequency adjustment voltage input terminal V C4 An external fourth frequency adjustment voltage is used to adjust the third drain capacitor C. D3 and the fourth drain capacitor C D4 The size of the gate of the first NMOS transistor M1 and the first gate inductance L. G1 One end and the first gate capacitor C G1 One end is connected to the drain of the first NMOS transistor M1 and the first drain inductor L. D1 One end, the first drain capacitor C D1 One end and the first output terminal V OUT1 The source terminal of the first NMOS transistor M1 is connected to the first source inductor L. S1 One end is connected; the gate of the second NMOS transistor M2 is connected to the second gate inductor L. G2 One end and the second gate capacitor C G2 One end is connected to the drain of the second NMOS transistor M2, and the drain inductor L is connected to the drain inductor L. D2 One end and the second drain capacitor C D2 One end and the second output terminal V OUT2 Connected, the source terminal of the second NMOS transistor M2 is connected to the second source inductor L. S2 One end is connected; the gate of the third NMOS transistor M3 is connected to the third gate inductor L. G3 One end and the third gate capacitor C G3 One end is connected to the drain of the third NMOS transistor M3 and the third drain inductor L. D3 One end and the third drain capacitor C D3 One end and the third output terminal V OUT3 Connected, the source terminal of the third NMOS transistor M3 is connected to the third source inductor L. S3 One end is connected; the gate of the fourth NMOS transistor M4 is connected to the fourth gate inductor L. G4 One end and the fourth gate capacitor C G4 One end is connected to the drain of the fourth NMOS transistor M4 and the fourth drain inductor L. D4 One end, fourth drain capacitor C D4 One end and the fourth output terminal V OUT4 Connected, the source terminal of the fourth NMOS transistor M4 is connected to the fourth source inductor L. S4 One end is connected; the first gate inductor L G1 The other end and the third gate inductor L G3 The other end is connected to the second head gate inductor L G6One end is connected, and the second head gate inductor L G6 The other end is connected to the second bias voltage input terminal V B2 Phase connection; second gate inductance L G2 The other end and the fourth gate inductor L G4 The other end is connected to the first head gate inductor L G5 One end is connected to the first head gate inductor L G5 The other end is connected to the first bias voltage input terminal V B1 Phase connection; first drain inductance L D1 The other end and the third drain inductor L D3 The other end is connected to the drain inductance L of the first head. D5 One end is connected, and the first head drain inductance L D5 The other end is connected to the power supply voltage V DD Phase connection; second drain inductance L D2 The other end is connected to the fourth drain inductor L D4 The other end is connected to the drain inductance L of the second head. D6 One end is connected, and the drain inductance L of the second head is connected. D6 The other end is connected to the power supply voltage V DD Phase connection; first source inductor L S1 The other end is connected to the third source inductor L S3 The other end is connected to the fifth head source inductor L. S5 One end is connected; the second source inductor L S2 The other end is connected to the fourth source inductor L S4 The other end is connected to the sixth head source inductor L. S6 One end is connected; the fifth head source inductor L S5 The other end and the sixth head source inductor L S6 The other end is connected to ground; the first gate capacitor C G1 The other end is connected to the second gate capacitor C G2 The other end is connected to the first frequency-adjustable voltage input terminal V. C1 Connected; third gate capacitor C G3 The other end is connected to the fourth gate capacitor C G4 The other end is connected to the third frequency-adjustable voltage input terminal V. C3 Connected; first drain capacitor C D1 The other end is connected to the second drain capacitor C D2 The other end is connected to the second frequency adjustment voltage input terminal V. C2 Connected; third drain capacitor C D3 The other end is connected to the fourth drain capacitor C D4 The other end is connected to the fourth frequency-adjustable voltage input terminal V. C4 Connected.

[0037] First drain inductance L D1 Each with the second gate inductor L G2 and the first source inductor L S1 In-phase coupling, with coupling coefficients k gd1 and k ds1 First source inductor L S1 With the second gate inductor L G2 In-phase coupling, with a coupling coefficient of k gs1 Third drain inductance L D3 Each with the fourth gate inductor L G4 and the third source inductor L S3 In-phase coupling, with coupling coefficients k gd3 and k ds3 Third source inductor L S3 With the fourth gate inductor L G4 In-phase coupling, with a coupling coefficient of k gs3 First head gate inductance L G5 With the first head drain inductance L D5 In-phase coupling, with a coupling coefficient of k gd5 .

[0038] Second drain inductance L D2 Each with the first gate inductor L G1 Second source inductor L S2 In-phase coupling, with coupling coefficients k gd2 and k ds2 Second source inductor L S2 With the first gate inductor L G1 In-phase coupling, with a coupling coefficient of k gs2 Fourth drain inductance L D4 Each with the third gate inductor L G3 and the fourth source inductor L S4 In-phase coupling, with coupling coefficients k gd4 and k ds4 Fourth source inductor L S4 With the third gate inductor L G3 In-phase coupling, with a coupling coefficient of k gs4 Second head gate inductance L G6 With the second head drain inductance L D6 In-phase coupling, with a coupling coefficient of k gd6 .

[0039] First head gate inductor L G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6All four components are the same size. This symmetrical center-tapped transformer helps reduce magnetic field coupling between circuits with other inductive components.

[0040] refer to Figure 2 The mode switching module G MC Including the first mode switching unit G mc1 Second mode switching unit G mc2 Third mode switching unit G mc3 Fourth mode switching unit G mc4 The first mode switching output terminal D1, the second mode switching output terminal D2, the third mode switching output terminal D3, the fourth mode switching output terminal D4, the first enable input terminal En1, the second enable input terminal En2, the third enable input terminal En3, and the fourth enable input terminal En4.

[0041] The first mode switching unit G mc1 Includes the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, the first enable input En1, the first port I1, the second port I2, the third port O1, and the fourth port O2; and the second mode switching unit G. mc2 Including the eighth NMOS transistor M8, the ninth NMOS transistor M9, and the tenth NMOS transistor M 10 Second enable input En2, fifth port I3, sixth port I4, seventh port O3, eighth port O4; third mode switching unit G mc3 Including the eleventh NMOS transistor M 11 The twelfth NMOS transistor M 12 The thirteenth NMOS transistor M 13 The third enable input (En3), the ninth port (I5), the tenth port (I6), the eleventh port (O5), and the twelfth port (O6); the fourth mode switching unit (G) mc4 Including the fourteenth NMOS transistor M 14 The fifteenth NMOS transistor M 15 The sixteenth NMOS transistor M 16 Fourth enable input En4, thirteenth port I7, fourteenth port I8, fifteenth port O7, and sixteenth port O8.

[0042] The first enable input terminal En1 is connected to a first enable voltage, which controls the first mode switching unit G. mc1 Whether it is working or not, the second enable input terminal En2 is connected to a second enable voltage, which is responsible for controlling the second mode switching unit G. mc2 Whether it is working or not, the third enable input terminal En3 is connected to a third enable voltage, which is responsible for controlling the third mode switching unit G. mc3 Whether it is working or not, the fourth enable input terminal En4 is connected to the first enable voltage, which is responsible for controlling the fourth mode switching unit G.mc4 Is it working? First mode switching unit G mc1 The gate of the fifth NMOS transistor M5 is connected to the first enable input En1. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6 and the source of the seventh NMOS transistor M7. The source of the fifth NMOS transistor M5 is connected to ground. The gate of the sixth NMOS transistor M6 is connected to the first port I1, and the drain of the sixth NMOS transistor M6 is connected to the third port O1. The gate of the seventh NMOS transistor M7 is connected to the second port I2, and the drain of the seventh NMOS transistor M7 is connected to the fourth port O2. Second mode switching unit G mc2 The gate terminal of the eighth NMOS transistor M8 is connected to the second enable input terminal En2, and the drain terminal of the eighth NMOS transistor M8 is connected to the source terminal of the ninth NMOS transistor M9 and the tenth NMOS transistor M10. 10 The source terminal of the eighth NMOS transistor M8 is connected to ground; the gate terminal of the ninth NMOS transistor M9 is connected to the fifth port I3, and the drain terminal of the ninth NMOS transistor M9 is connected to the seventh port O3; the tenth NMOS transistor M... 10 The gate terminal is connected to the sixth port I4, and the tenth NMOS transistor M 10 The drain terminal is connected to the eighth port O4. Third mode switching unit G mc3 The eleventh NMOS transistor M 11 The gate terminal is connected to the third enable input terminal En3, and the eleventh NMOS transistor M 11 The drain terminal of the twelfth NMOS transistor M 12 The source terminal and the thirteenth NMOS transistor M 13 Connected to the source terminal, the eleventh NMOS transistor M 11 The source terminal is connected to ground; the twelfth NMOS transistor M 12 The gate terminal is connected to the ninth port I5, and the twelfth NMOS transistor M 12 The drain of the thirteenth NMOS transistor is connected to the eleventh port O5; 13 The gate terminal is connected to the tenth port I6, and the thirteenth NMOS transistor M 13 The drain terminal is connected to the twelfth port O6. Fourth mode switching unit G mc4 The fourteenth NMOS transistor M 14 The gate terminal is connected to the fourth enable input terminal En4, and the fourteenth NMOS transistor M 14 The drain terminal of the fifteenth NMOS transistor M 15 The source terminal and the sixteenth NMOS transistor M 16 The source terminal is connected, and the fourteenth NMOS transistor M 14 The source terminal is connected to ground; the fifteenth NMOS transistor M 15 The gate terminal is connected to the thirteenth port I7, and the fifteenth NMOS transistor M...15 The drain of the transistor is connected to the fifteenth port O7; the sixteenth NMOS transistor M... 16 The gate terminal is connected to the fourteenth port I8, and the sixteenth NMOS transistor M 16 The drain end is connected to the sixteenth port O8.

[0043] Ports I1, O3, I5, and O7 are all connected to the first mode switching output terminal D1; ports I2, O4, I6, and O8 are all connected to the second mode switching output terminal D2; ports O1, I3, O6, and I8 are all connected to the third mode switching output terminal D3; and ports O2, I4, O5, and I7 are all connected to the fourth mode switching output terminal D4. The first mode switching output terminal D1, the second mode switching output terminal D2, the third mode switching output terminal D3, and the fourth mode switching output terminal D4 are respectively connected to the first output terminal V. OUT1 Second output terminal V OUT2 Third output terminal V OUT3 Fourth output terminal V OUT4 Connected.

[0044] The VCO involved in this invention is a mode switching module G MC It determines whether to operate in common-mode or differential-mode. In common-mode, the first mode switching unit G... mc1 Second mode switching unit G mc2 Shutdown, third mode switching unit G mc3 and the fourth mode switching unit G mc4 Enabled, causing the first mode switching output terminal V to be switched. out1 and the third mode switching output terminal V out3 With the same phase, the second mode switching output terminal V out2 and the fourth mode switching output terminal V out4 With the same phase, current flows through the first head gate terminal inductor L G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6 Fifth head source terminal inductor L S5 The sixth head source inductor L S6 In this case, the first head gate inductance L G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6 Fifth head source terminal inductor L S5 The sixth head source inductor LS6 It contributes to the inductance value of the oscillation circuit, and the VCO operates at a low frequency. In differential mode, the first mode switching unit G... mc1 Second mode switching unit G mc2 Enable, third mode switching unit G mc3 and the fourth mode switching unit G mc4 Turn off, so that the first mode switching output V is turned off. out1 and the third mode switching output terminal V out3 Phase opposite, second mode switching output V out2 and the fourth mode switching output terminal V out4 The phases are opposite, and the current does not flow through the first head gate inductor L. G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6 Fifth head source terminal inductor L S5 The sixth head source inductor L S6 Therefore, the first head gate inductance L G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6 Fifth head source terminal inductor L S5 The sixth head source inductor L S6 It does not contribute to the inductance value of the oscillation circuit, and the VCO operates at a high frequency.

[0045] The above description is merely a detailed explanation and illustration of specific embodiments of the present invention as described in this specification, intended for illustrative purposes and not for limitation. However, the features of the present invention are not limited thereto. It is obvious to those skilled in the art that the entire scope of the present invention should be determined by the scope of its claims. Without departing from the spirit and scope of the invention as defined by the appended claims, all other instances implemented according to the spirit of the present invention and similar variations thereof should be included within the scope of protection of the present invention.

Claims

1. A dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors, characterized in that, It includes a first negative resistance amplifier, a second negative resistance amplifier, a first multi-coil coupled resonant cavity, a second multi-coil coupled resonant cavity, and a mode switching module; the mode switching module is used to switch the first multi-coil coupled resonant cavity and the second multi-coil coupled resonant cavity between common-mode mode and differential-mode mode. The first multi-winding transformer coupled resonant cavity includes a first drain inductor L. D1 Third leakage inductance L D3 First source inductor L S1 Third source inductor L S3 Fifth head source terminal inductor L S5 Second gate inductor L G2 Fourth gate inductor L G4 First head gate inductor L G5 and the first head drain inductance L D5 First drain inductance L D1 One end, the first source inductor L S1 One end and the second gate inductance L G2 One end of each is connected to the first negative resistance amplifier; the third leakage inductance L D3 One end, the third source end inductor L S3 One end and the fourth gate inductor L G4 One end of each is connected to the second negative resistance amplifier; the first source inductor L S1 The other end is connected to the third source inductor L S3 The other end is connected to the fifth head source inductor L. S5 One end is connected; the fifth head source inductor L S5 The other end is connected to ground; the second gate inductor L G2 The other end and the fourth gate inductor L G4 The other end is connected to the first head gate inductor L G5 One end is connected to the first head gate inductor L G5 The other end is connected to the first bias voltage input terminal V. B1 First drain inductance L D1 The other end and the third drain inductor L D3 The other end is connected to the drain inductance L of the first head. D5 One end is connected, and the first head drain inductance L D5 The other end is connected to the power supply voltage V. DD ; The second multi-winding coupled transformer resonant cavity includes a second drain inductor L. D2 Fourth leakage inductance L D4 Second source inductor L S2 Fourth source inductor L S4 The sixth head source inductor L S6 First gate inductance L G1 Third gate inductor L G3 Second head gate inductor L G6 Second head drain inductance L D6 First gate inductance L G1 One end and the second drain inductance L D2 One end and the second source end inductor L S2 One end of each is connected to the first negative resistance amplifier; the third gate inductor L G3 The other end, the fourth drain inductor L D4 One end and the fourth source end inductor L S4 One end of each is connected to the second negative resistance amplifier; the first gate inductor L G1 The other end and the third gate inductor L G3 The other end is connected to the second head gate inductor L G6 One end is connected, and the second head gate inductor L G6 The other end is connected to the second bias voltage input terminal V. B2 Second drain inductance L D2 The other end is connected to the fourth drain inductor L D4 The other end is connected to the drain inductance L of the second head. D6 One end is connected, and the drain inductance L of the second head is connected. D6 The other end is connected to the power supply voltage V. DD Second source inductor L S2 The other end is connected to the fourth source inductor L S4 The other end is connected to the sixth head source inductor L. S6 One end is connected; the fifth head source inductor L S5 The other end and the sixth head source inductor L S6 The other end of each is connected to the ground; First drain inductance L D1 Each with the second gate inductor L G2 and the first source inductor L S1 In-phase coupling, first source inductor L S1 With the second gate inductor L G2 In-phase coupling, third drain inductance L D3 Each with the fourth gate inductor L G4 and the third source inductor L S3 In-phase coupling, third source inductor L S3 With the fourth gate inductor L G4 In-phase coupling, first head gate inductance L G5 With the first head drain inductance L D5 In-phase coupling; second drain inductance L D2 Each with the first gate inductor L G1 Second source inductor L S2 In-phase coupling, second source inductor L S2 With the first gate inductor L G1 In-phase coupling, fourth drain inductance L D4 Each with the third gate inductor L G3 and the fourth source inductor L S4 In-phase coupling, fourth source inductor L S4 With the third gate inductor L G3 In-phase coupling, second head gate inductance L G6 With the second head drain inductance L D6 In-phase coupling; The first negative resistance amplifier includes a first NMOS transistor M1, a second NMOS transistor M2, and a first gate capacitor C. G1 Second gate capacitor C G2 First drain capacitor C D1 Second drain capacitor C D2 First output terminal V OUT1 Second output terminal V OUT2 First bias voltage input terminal V B1 First frequency adjustment voltage input terminal V C1 Second frequency adjustable voltage input terminal V C2 ; The gate terminal of the first NMOS transistor M1 and the first gate inductor L G1 One end and the first gate capacitor C G1 One end is connected to the drain of the first NMOS transistor M1 and the first drain inductor L. D1 One end, the first drain capacitor C D1 One end and the first output terminal V OUT1 The source terminal of the first NMOS transistor M1 is connected to the first source inductor L. S1 One end is connected; the gate of the second NMOS transistor M2 is connected to the second gate inductor L. G2 One end and the second gate capacitor C G2 One end is connected to the drain of the second NMOS transistor M2, and the drain inductor L is connected to the drain inductor L. D2 One end and the second drain capacitor C D2 One end and the second output terminal V OUT2 Connected, the source terminal of the second NMOS transistor M2 is connected to the second source inductor L. S2 One end is connected; the first gate capacitor C G1 The other end is connected to the second gate capacitor C G2 The other end is connected to the first frequency-adjustable voltage input terminal V. C1 Connected; first drain capacitor C D1 The other end is connected to the second drain capacitor C D2 The other end is connected to the second frequency adjustment voltage input terminal V. C2 Connected; The second negative resistance amplifier includes the third NMOS transistor M3, the fourth NMOS transistor M4, and the third gate capacitor C. G3 Fourth gate capacitor C G4 Third drain capacitor C D3 Fourth drain capacitor C D4 Third output terminal V OUT3 Fourth output terminal V OUT4 Second bias voltage input terminal V B2 Third frequency adjustment voltage input terminal V C3 and the fourth frequency adjustment voltage input terminal V C4 ; The gate terminal of the third NMOS transistor M3 and the third gate inductor L G3 The other end and the third gate capacitor C G3 One end is connected to the drain of the third NMOS transistor M3 and the third drain inductor L. D3 The other end, the third drain capacitor C D3 One end and the third output terminal V OUT3 Connected, the source terminal of the third NMOS transistor M3 is connected to the third source inductor L. S3 The other end is connected; the gate of the fourth NMOS transistor M4 is connected to the fourth gate inductor L. G4 The other end and the fourth gate capacitor C G4 One end is connected to the drain of the fourth NMOS transistor M4 and the fourth drain inductor L. D4 The other end, the fourth drain capacitor C D4 One end and the fourth output terminal V OUT4 Connected, the source terminal of the fourth NMOS transistor M4 is connected to the fourth source inductor L. S4 The other end is connected; the third gate capacitor C G3 The other end is connected to the fourth gate capacitor C G4 The other end is connected to the third frequency-adjustable voltage input terminal V. C3 Connected; third drain capacitor C D3 The other end is connected to the fourth drain capacitor C D4 The other end is connected to the fourth frequency-adjustable voltage input terminal V. C4 Connected.

2. The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors according to claim 1, characterized in that, First head gate inductor L G5 First head drain inductance L D5 Second head gate inductor L G6 Second head drain inductance L D6 All four are the same size.

3. The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors according to claim 1, characterized in that, The mode switching module includes a first mode switching unit G. mc1 Second mode switching unit G mc2 Third mode switching unit G mc3 and the fourth mode switching unit G mc4 First mode switching unit G mc1 Includes a first port I1, a second port I2, a third port O1, and a fourth port O2; and a second mode switching unit G. mc2 Including port 5 (I3), port 6 (I4), port 7 (O3), and port 8 (O4); third mode switching unit G mc3 Including port 9 (I5), port 10 (I6), port 11 (O5), and port 12 (O6); fourth mode switching unit G mc4 This includes port 13 (I7), port 14 (I8), port 15 (O7), and port 16 (O8); The first port I1, the seventh port O3, the ninth port I5, and the fifteenth port O7 are all connected to the first output terminal V. OUT1 Connected to each other; the second port I2, the eighth port O4, the tenth port I6, and the sixteenth port O8 are all connected to the second output terminal V. OUT2 Connected to each other; the third port O1, the fifth port I3, the twelfth port O6, and the fourteenth port I8 are all connected to the third output terminal V. OUT3 Connected; the fourth port O2, the sixth port I4, the eleventh port O5, and the thirteenth port I7 are all connected to the fourth output terminal V. OUT4 Connected.

4. The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors according to claim 3, characterized in that, The first mode switching unit G mc1 It also includes the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, and the first enable input terminal En1; The gate of the fifth NMOS transistor M5 is connected to the first enable input En1. The drain of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6 and the source of the seventh NMOS transistor M7. The source of the fifth NMOS transistor M5 is connected to ground. The gate of the sixth NMOS transistor M6 is connected to the first port I1. The drain of the sixth NMOS transistor M6 is connected to the third port O1. The gate of the seventh NMOS transistor M7 is connected to the second port I2. The drain of the seventh NMOS transistor M7 is connected to the fourth port O2.

5. The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors according to claim 3, characterized in that, Second mode switching unit G mc2 It also includes the eighth NMOS transistor M8, the ninth NMOS transistor M9, and the tenth NMOS transistor M... 10 And the second enable input terminal En2; The gate of the eighth NMOS transistor M8 is connected to the second enable input En2. The drain of the eighth NMOS transistor M8 is connected to the source of the ninth NMOS transistor M9 and the tenth NMOS transistor M10. 10 The source terminal of the eighth NMOS transistor M8 is connected to ground; the gate terminal of the ninth NMOS transistor M9 is connected to the fifth port I3, and the drain terminal of the ninth NMOS transistor M9 is connected to the seventh port O3; the tenth NMOS transistor M... 10 The gate terminal is connected to the sixth port I4, and the tenth NMOS transistor M 10 The drain end is connected to the eighth port O4.

6. The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors according to claim 3, characterized in that, The third mode switching unit G mc3 It also includes the eleventh NMOS transistor M. 11 The twelfth NMOS transistor M 12 The thirteenth NMOS transistor M 13 and the third enable input En3; Eleventh NMOS transistor M 11 The gate terminal is connected to the third enable input terminal En3, and the eleventh NMOS transistor M 11 The drain terminal of the twelfth NMOS transistor M 12 The source terminal and the thirteenth NMOS transistor M 13 Connected to the source terminal, the eleventh NMOS transistor M 11 The source terminal is connected to ground; the twelfth NMOS transistor M 12 The gate terminal is connected to the ninth port I5, and the twelfth NMOS transistor M 12 The drain of the thirteenth NMOS transistor is connected to the eleventh port O5; 13 The gate terminal is connected to the tenth port I6, and the thirteenth NMOS transistor M 13 The drain end is connected to the twelfth port O6.

7. The dual-core wide-tunable millimeter-wave voltage-controlled oscillator based on mode-switching common-mode and differential-mode inductors according to claim 3, characterized in that, The fourth mode switching unit G mc4 It also includes the fourteenth NMOS transistor M 14 The fifteenth NMOS transistor M 15 The sixteenth NMOS transistor M 16 and the fourth enable input, En4; The fourteenth NMOS transistor M 14 The gate terminal is connected to the fourth enable input terminal En4, and the fourteenth NMOS transistor M 14 The drain terminal of the fifteenth NMOS transistor M 15 The source terminal and the sixteenth NMOS transistor M 16 The source terminal is connected, and the fourteenth NMOS transistor M 14 The source terminal is connected to ground; the fifteenth NMOS transistor M 15 The gate terminal is connected to the thirteenth port I7, and the fifteenth NMOS transistor M... 15 The drain of the transistor is connected to the fifteenth port O7; the sixteenth NMOS transistor M... 16 The gate terminal is connected to the fourteenth port I8, and the sixteenth NMOS transistor M 16 The drain end is connected to the sixteenth port O8.

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