A low-speed oscillator for mcu built-in

Abstract

The application relates to the technical field of oscillators, and discloses a low-speed oscillator for an MCU (Micro Control Unit), which comprises a clock signal generating unit, a frequency testing unit, a frequency calibration unit and an output unit; the clock signal generating unit inputs clock signals to the frequency testing unit and the output unit respectively; the frequency testing unit tests the clock signals based on the input second clock signals, and inputs the testing results to the frequency calibration unit; the frequency calibration unit adjusts the frequency of the clock signals output by the clock signal generating unit based on the testing results, and sends a calibration completion signal to the output unit when the testing results meet the requirements; the output unit outputs the clock signals after receiving the calibration completion signal; when in use, the frequency testing unit and the frequency calibration unit are used for testing and calibration, so that the frequency of the clock signals output by the clock signal generating unit is adjusted, and thus the precision of the finally output clock signals of the application can be ensured.

Description

Technical Field

[0001] This invention relates to the field of oscillator technology, and more specifically to a low-speed oscillator for use in an MCU. Background Technology

[0002] In MCU circuits, oscillators are an extremely important component; almost all MCU circuits are equipped with both high-speed and low-speed oscillators. High-speed oscillators, in conjunction with bandgap reference circuits, generate a master clock signal with excellent stability and accuracy, which is used in the normal operating mode of the MCU circuit. Low-speed oscillators are generally used to generate a secondary clock signal, which is typically used in the circuit's low-power mode.

[0003] To meet different accuracy requirements for secondary clock signals, two methods are currently used to generate them: ring oscillators and external crystal oscillators. Ring oscillators have advantages such as small size, low power consumption, and fast start-up, but they suffer from poor accuracy and stability, so they are mostly used for watchdog clocks. External crystal oscillators, on the other hand, offer higher accuracy and better stability, but they consume more power, have a longer start-up time, and increase costs due to the external crystal. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the present invention provides a low-speed oscillator for use in MCU. The technical problem to be solved is that there is currently no high-precision low-speed oscillator.

[0005] To solve the above technical problems, the present invention provides the following technical solution: a low-speed oscillator for use in MCU, comprising a clock signal generation unit, a frequency testing unit, a frequency calibration unit, and an output unit;

[0006] The clock signal generation unit is used to provide a frequency-adjustable clock signal, which is input to the frequency testing unit and the output unit respectively.

[0007] The frequency testing unit tests the clock signal based on the input second clock signal and inputs the test result to the frequency calibration unit, wherein the frequency of the second clock signal is greater than the frequency of the clock signal;

[0008] The frequency testing unit adjusts the frequency of the clock signal output by the clock signal generation unit based on the test results, and sends a calibration completion signal to the output unit when the test results meet the requirements.

[0009] After receiving the calibration completion signal, the output unit outputs the clock signal.

[0010] In one embodiment, the clock signal generating unit includes MOS transistors N1, N2, and N3 forming a current mirror; the gate of MOS transistor N1 is electrically connected to the drain of MOS transistor N1, the gate of MOS transistor N2, and the gate of MOS transistor N3, respectively, and serves as a reference voltage terminal.

[0011] The sources of MOSFET N1, MOSFET N2, and MOSFET N3 are all grounded;

[0012] The drain of MOSFET N1 is electrically connected to the power supply terminal through a resistor branch. The resistor branch includes multiple resistors connected in series. In addition to the resistors electrically connected to the power supply terminal, a control switch is connected in parallel across each resistor. The frequency calibration unit adjusts the frequency of the output clock signal by controlling the on and off state of the control switches.

[0013] The drain of MOSFET N2 is electrically connected to the power supply terminal through MOSFET P1 and grounded through capacitor C1;

[0014] The drain of MOSFET N3 is electrically connected to the power supply terminal through MOSFET P2, and is grounded through capacitor C2;

[0015] The reference voltage terminal is electrically connected to the negative input terminal of the first comparator and the negative input terminal of the second comparator, respectively. The positive input terminal of the first comparator is electrically connected to the drain of MOSFET N2, and the positive input terminal of the second comparator is electrically connected to the drain of MOSFET N3. Both the first and second comparators output a high-level signal when the voltage at the positive input terminal is greater than the voltage at the negative input terminal, and output a low-level signal when the voltage at the positive input terminal is less than the voltage at the negative input terminal.

[0016] The output of the first comparison unit is electrically connected to the S input of the SR latch, the output of the second comparison unit is electrically connected to the D input of the SR latch, the Q output of the SR latch is electrically connected to the gate of MOS transistor P2 and the input of the first inverting unit, the output of the first inverting unit is electrically connected to the gate of MOS transistor P1 and the input of the second inverting unit, and the output of the second inverting unit outputs a clock signal. The first and second inverting units are used to invert the input signal.

[0017] In one embodiment, the MOS transistors N1, N2, and N3 are of the same size.

[0018] In one embodiment, in the resistor branch, along the direction from the power supply terminal to the MOS transistor N1, the resistance value of the previous resistor is twice the resistance value of the next resistor.

[0019] In an embodiment, the SR latch comprises a first NAND gate and a second NAND gate, a first input terminal of the first NAND gate is the S input terminal of the SR flip-flop, and a second input terminal of the first NAND gate is electrically connected to the output terminal of the second NAND gate;

[0020] a first input terminal of the second NAND gate is electrically connected to the output terminal of the first NAND gate, the output terminal of the first NAND gate is the Q output terminal of the SR latch, and a second input terminal of the second NAND gate is the R input terminal of the SR flip-flop.

[0021] In an embodiment, the frequency testing unit comprises a first counter, a second counter and a register, wherein the first counter counts the input second clock signal, and the register is configured to store the count value of the first counter; the second counter counts the input clock signal, and controls the register to send the count value of the first counter to the frequency calibration unit when the count value reaches a preset value.

[0022] In an embodiment, the frequency calibration unit outputs a calibration value for calibrating the clock signal by a successive approximation method, the calibration value is used to control the on-off of a control switch in a resistance branch, let the actual count value of the first counter be B, the ideal count value of the first counter be M, and the error range is set to ±x%;

[0023] when M*(1-x)% < B < M*(1+x)%, the frequency calibration unit outputs the calibration completion signal;

[0024] when B < M*(1-x)%, the frequency calibration unit increases the calibration value to reduce the frequency of the clock signal, then recalibrates the frequency of the clock signal until the actual count value B satisfies M*(1-x)% < B < M*(1+x)%;

[0025] when B > M*(1+x)%, the frequency calibration unit decreases the calibration value to increase the frequency of the clock signal, then recalibrates the frequency of the clock signal until the actual count value B satisfies M*(1-x)% < B < M*(1+x)%.

[0026] In an embodiment, when B < M*(1-x)%, the frequency calibration unit adds 1 to the calibration value each time to reduce the frequency of the clock signal; when B > M*(1+x)%, the frequency calibration unit subtracts 1 from the calibration value each time to increase the frequency of the clock signal.

[0027] In an embodiment, the output unit comprises an AND gate, a first input terminal of the AND gate receives the calibration completion signal, and a second input terminal of the AND gate receives the clock signal.

[0028] The advantages of this invention compared to the prior art are as follows: This invention uses a frequency testing unit and a frequency calibration unit to test and calibrate, thereby adjusting the frequency of the clock signal output by the clock signal generation unit, which can ensure the accuracy of the final clock signal output by this invention. Moreover, the output unit can only output the clock signal when the frequency of the clock signal meets the requirements. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of the present invention;

[0030] Figure 2 This is a circuit diagram of the clock signal generation unit of the present invention;

[0031] Figure 3 This is a circuit diagram of resistor branch 1 of the present invention;

[0032] Figure 4 This is a schematic diagram of the frequency testing unit.

[0033] Figure 5 for Figure 2 Waveform diagram of the relevant nodes. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0035] The existing low-speed oscillator structure inside MCUs is shown in Table 1. Table 1 shows that the clock accuracy of the oscillator built into the MCU is low. Improving the clock signal accuracy by adding an external crystal oscillator would increase cost and power consumption. Therefore... Figure 1 As shown, the present invention provides a low-speed oscillator for use in an MCU, including a clock signal generation unit 1, a frequency testing unit 2, a frequency calibration unit 3, and an output unit 4.

[0036] Clock signal generation unit 1 is used to provide a frequency-adjustable clock signal FS, which is input to frequency test unit 2 and output unit 4 respectively.

[0037] Frequency test unit 2 tests clock signal FS based on the input second clock signal FM and inputs the test result to frequency calibration unit 3. The frequency of the second clock signal FM is greater than the frequency of clock signal FS.

[0038] The frequency test unit 2 adjusts the frequency of the clock signal output by the clock signal generation unit 1 based on the test results, and sends a calibration completion signal to the output unit 4 when the test results meet the requirements.

[0039] After receiving the calibration completion signal, output unit 4 outputs the clock signal FS.

[0040] In practical use, the present invention performs testing and calibration through frequency testing unit 2 and frequency calibration unit 3 to adjust the frequency of the clock signal FS output by clock signal generation unit 1, thereby ensuring the accuracy of the final clock signal FS output by the present invention. Moreover, through output unit 4, the present invention will only output the clock signal FS when the frequency of the clock signal FS meets the requirements.

[0041] Specifically, such as Figure 2 As shown, the clock signal generation unit 1 includes MOS transistors N1, N2, and N3 that form a current mirror; the gate of MOS transistor N1 is electrically connected to the drain of MOS transistor N1, the gate of MOS transistor N2, and the gate of MOS transistor N3, respectively, and serves as the reference voltage terminal vref;

[0042] The sources of MOSFET N1, MOSFET N2, and MOSFET N3 are all grounded;

[0043] The drain of MOSFET N1 is electrically connected to the power supply terminal VDD through resistor branch 10, such as... Figure 3 As shown, resistor branch 10 includes multiple resistors connected in series. Besides the resistor electrically connected to the power supply terminal VDD, each resistor has a control switch connected in parallel across it. The frequency calibration unit 3 adjusts the frequency of the output clock signal FS by controlling the on / off state of the control switch. Figure 3 The resistor branch 10 shown includes resistors R0, R1, R2, Rn, ..., Rn+1, where n is a positive integer greater than 1; the control switches include switches S0, S1, S2, ..., Sn; in a certain embodiment, the number of resistors in the resistor branch 10 can be set according to actual needs, wherein the number of control switches is one less than the number of resistors.

[0044] The drain of MOSFET N2 is electrically connected to the power supply terminal VDD through MOSFET P1, and is grounded through capacitor C1;

[0045] The drain of MOSFET N3 is electrically connected to the power supply terminal VDD through MOSFET P2, and grounded through capacitor C2;

[0046] The reference voltage terminal vref is electrically connected to the negative input terminal of the first comparison unit 11 and the negative input terminal of the second comparison unit 12, respectively. The positive input terminal of the first comparison unit 11 is electrically connected to the drain of MOSFET N2, and the positive input terminal of the second comparison unit 12 is electrically connected to the drain of MOSFET N3. Both the first comparison unit 11 and the second comparison unit 12 output a high-level signal when the voltage at the positive input terminal is greater than the voltage at the negative input terminal, and output a low-level signal when the voltage at the positive input terminal is less than the voltage at the negative input terminal. The first comparison unit 11 includes a comparator CMP1, and the second comparison unit 12 includes a comparator CMP2.

[0047] The output of the first comparison unit 11 is electrically connected to the S input of the SR latch 13. The output of the second comparison unit 12 is electrically connected to the D input of the SR latch 13. The Q output of the SR latch 13 is electrically connected to the gate of the MOS transistor P2 and the input of the first inverting unit 14. The output of the first inverting unit 14 is electrically connected to the gate of the MOS transistor P1 and the input of the second inverting unit 15. The output of the second inverting unit 15 outputs a clock signal. The first inverting unit 14 and the second inverting unit 15 are used to invert the input signal. The first inverting unit 14 includes an inverter INV, and the second inverting unit includes an inverter INV.

[0048] Specifically, in this embodiment, MOS transistors N1, N2, and N3 have the same dimensions.

[0049] Specifically, in this embodiment, in the resistor branch 10, along the direction from the power supply terminal to the MOS transistor N1, the resistance value of the previous resistor is twice the resistance value of the next resistor.

[0050] Specifically, in this embodiment, the SR latch 13 includes a first NAND gate NAND1 and a second NAND gate NAND2. The first input terminal of the first NAND gate NAND1 is the S input terminal of the SR flip-flop 13, and the second input terminal of the first NAND gate NAND1 is electrically connected to the output terminal of the second NAND gate NAND2.

[0051] The first input terminal of the second NAND gate NAND2 is electrically connected to the output terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is the Q output terminal of the SR latch 13, and the second input terminal of the second NAND gate NAND2 is the R input terminal of the SR flip-flop 13.

[0052] Specifically, in this embodiment, the output unit 4 includes an AND gate. The first input of the AND gate receives a calibration completion signal, the second input of the AND gate receives a clock signal, and the output of the AND gate finally outputs the clock signal FS.

[0053] First, fix the resistance value of resistor branch 10 as R1, and then... Figure 2 The circuit shown will be analyzed as follows:

[0054] First, connect the power input terminal VDD to the power supply. The gate and drain of MOSFET N1 are electrically connected, therefore MOSFET N1 is in the saturation region. According to the saturation region current formula...

[0055]

[0056] The current flowing through MOSFET N1 can be obtained.

[0057]

[0058] Since MOSFETs N2, N3, and N1 form a current mirror, MOSFETs N2 and N3 replicate the current of MOSFET N1. Therefore, the current I flowing through MOSFET N2 is... DSN2 and the current flowing through MOSFET N3 I DSN3 The current flowing through the MOSFET N1 is the same as the current flowing through the MOSFET N1, i.e., I DSN2 =I DSN3 =I DSN1 It should be noted that since voltages V2 and V3 vary between vref and VDD, the condition V is always satisfied. DS >V GS -V TH As required, MOSFETs N1, N2, and N3 always operate in the saturation region;

[0059] In actual work, Figure 2 The circuit shown has two processes, namely process 1 and process 2, which are as follows:

[0060] Process 1: Voltage V3 = 0, voltage V4 = 1. At this time, MOSFET P1 is turned on and MOSFET P2 is turned off. We can obtain voltage V1 = VDD. Voltage V2 will decrease from VDD, and the rate of decrease depends on the current I. DSN3 With the value of capacitor C2, at this time, voltage CMP1_OUT = 1 and voltage CMP2_OUT = 1. When voltage V2 drops to vref, voltage CMP2_OUT changes from 1 to 0. At this time, voltage V4 becomes 0, voltage V3 changes to 1, MOSFET P2 turns on, voltage V2 is instantly pulled up to VDD, MOSFET P1 turns off, and voltage V1 begins to drop.

[0061] Process 2: From Process 1, we know that at this point, voltage V3 = 1, voltage V4 = 0, MOSFET P1 is off, and MOSFET P2 is on. We know that voltage V2 = VDD. Voltage V1 starts to decrease from VDD until voltage V2 decreases to vref, at which point voltage CMP_OUT changes from 1 to 0. At this time, voltage V4 changes from 0 to 1. Voltage V3 changes from 1 to 0. MOSFET P1 then turns on, pulling voltage V1 to VDD, MOSFET P2 turns off, and voltage V2 begins to decrease slowly. Then, Process 1 continues to repeat.

[0062] Process 1 and process 2 combined constitute one complete oscillation cycle, as shown in the specific timeline diagram. Figure 5 As shown, from Figure 5 From this, we can know that:

[0063] Time of process 1

[0064] Time of process 2

[0065] The oscillation period of the clock signal FS is T = T1 + T2;

[0066] To ensure the duty cycle of clock signal FS is 1:1, capacitors C1 and C2 are exactly equal, and their values ​​are denoted as C. MOSFETs N1 and N2 are perfectly symmetrical on the layout, as are MOSFETs N3 and N4. Current I... DSN2 = Current I DSN3 = Current I DSN1

[0067] At this time, the oscillation period

[0068] Since the current flowing through resistor branch 10 is the same as the current flowing through MOSFET N1, the resistance of resistor branch 10 is R1.

[0069]

[0070] Substituting this formula into the formula for the oscillation period T, we can obtain...

[0071]

[0072] frequency

[0073] As can be seen from the formula for frequency F, frequency F is only related to the resistance value of resistor branch 10 and resistor C. Therefore, the clock signal FS generated by this invention is not sensitive to temperature and voltage.

[0074] It can be seen from the formula of frequency F that the main factors affecting the frequency value are the resistance R1 and the capacitance C. Since the values of resistance and capacitance may deviate from the theoretical values during process manufacturing, in order to improve the accuracy of the oscillator, the present invention can change the total resistance of the resistor branch 10 by controlling the on-off of the control switch connected in parallel with the resistor in the resistor branch 10. In addition, the frequency calibration unit 3 outputs a calibration value TRIM to control the on-off of the control switch, at this time the total resistance of the resistor branch 10 R is the resistance of Rn+1; in addition, in Figure 3 placing the resistor Rn+1 is to provide the minimum initial resistance value, and changing the value of the calibration value TRIM can change the value of the total resistance Rz; it can be known from combining the above formula

[0075]

[0076] Therefore Figure 2 the circuit shown can be controlled by the frequency calibration unit 3 to output a clock signal FS with adjustable frequency.

[0077] As shown in Figure 4 , the frequency testing unit 2 includes a first counter 20, a second counter 21 and a register 22. The first counter 20 counts the input second clock signal FM, and the register 22 is configured to store the count value of the first counter 20; the second counter 21 counts the input clock signal FS, and when the count value reaches a preset value, controls the register 22 to send the count value of the first counter 20 to the frequency calibration unit 3.

[0078] In an embodiment, the frequency calibration unit 3 outputs a calibration value TRIM for calibrating the clock signal FS by a successive approximation method. The calibration value TRIM is used to control the on-off of the control switches in the resistor branch 10. The actual count value of the first counter 20 is taken as B, the ideal count value of the first counter 20 is taken as M, and the error range is set to ±x%;

[0079] when M*(1-x)% < B < M*(1+x)%, the frequency calibration unit 3 outputs a calibration completion signal;

[0080] when B < M*(1-x)%, the frequency calibration unit 3 increases the calibration value TRIM to reduce the frequency of the clock signal FS, and then re-calibrates the frequency of the clock signal FS until the actual count value B satisfies M*(1-x)% < B < M*(1+x)%;

[0081] when B > M*(1+x)%, the frequency calibration unit 3 decreases the calibration value TRIN to increase the frequency of the clock signal FS, and then re-calibrates the frequency of the clock signal FS until the actual count value B satisfies M*(1-x)% < B < M*(1+x)%.

[0082] More specifically, when B < M*(1-x)%, the frequency calibration unit 3 increments the calibration value by 1 each time to decrease the frequency of the clock signal; when B > M*(1+x)%, the frequency calibration unit decrements the calibration value by 1 each time to increase the frequency of the clock signal.

[0083] In an embodiment, the frequency calibration unit 3 may adjust the value of the calibration value TRIM by using a binary search method.

[0084] In summary, the low-speed oscillator provided by the present invention controls the on / off of the control switches in the resistor branch 10 through the frequency test unit 2 and the frequency calibration unit 3, thereby being capable of outputting a high-precision clock signal FS. In addition, the frequency of the clock signal FS is insensitive to temperature and voltage, the structure is simple, and the adopted resistors and capacitors can be fully integrated inside the circuit. Furthermore, a high-precision voltage source or current source is not required to supply power to the oscillator, thereby reducing the power consumption and complexity of the circuit, as well as reducing the circuit area and cost, which has very high practical value.

[0085] Based on the teaching of the present invention, relevant staff can make various changes and modifications without departing from the technical idea of the present invention through the above description. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the claims.

Claims

1. A low-speed oscillator for use in an MCU, characterized in that, It includes a clock signal generation unit, a frequency testing unit, a frequency calibration unit, and an output unit; The clock signal generation unit is used to provide a frequency-adjustable clock signal, which is input to the frequency testing unit and the output unit respectively. The frequency testing unit tests the clock signal based on the input second clock signal and inputs the test result to the frequency calibration unit, wherein the frequency of the second clock signal is greater than the frequency of the clock signal; The frequency calibration unit adjusts the frequency of the clock signal output by the clock signal generation unit based on the test results, and sends a calibration completion signal to the output unit when the test results meet the requirements. After receiving the calibration completion signal, the output unit outputs the clock signal; The clock signal generation unit includes MOS transistors N1, N2, and N3 that form a current mirror; the gate of MOS transistor N1 is electrically connected to the drain of MOS transistor N1, the gate of MOS transistor N2, and the gate of MOS transistor N3, respectively, and serves as a reference voltage terminal. The sources of MOSFET N1, MOSFET N2, and MOSFET N3 are all grounded; The drain of MOSFET N1 is electrically connected to the power supply terminal through a resistor branch. The resistor branch includes multiple resistors connected in series. In addition to the resistors electrically connected to the power supply terminal, a control switch is connected in parallel across each resistor. The frequency calibration unit adjusts the frequency of the output clock signal by controlling the on and off state of the control switches. The drain of MOSFET N2 is electrically connected to the power supply terminal through MOSFET P1 and grounded through capacitor C1; the drain of MOSFET N3 is electrically connected to the power supply terminal through MOSFET P2 and grounded through capacitor C2. The reference voltage terminal is electrically connected to the negative input terminal of the first comparator and the negative input terminal of the second comparator, respectively. The positive input terminal of the first comparator is electrically connected to the drain of MOSFET N2, and the positive input terminal of the second comparator is electrically connected to the drain of MOSFET N3. Both the first and second comparators output a high-level signal when the voltage at the positive input terminal is greater than the voltage at the negative input terminal, and output a low-level signal when the voltage at the positive input terminal is less than the voltage at the negative input terminal. The output of the first comparison unit is electrically connected to the S input of the SR latch, the output of the second comparison unit is electrically connected to the R input of the SR latch, the Q output of the SR latch is electrically connected to the gate of MOS transistor P2 and the input of the first inverting unit, the output of the first inverting unit is electrically connected to the gate of MOS transistor P1 and the input of the second inverting unit, and the output of the second inverting unit outputs a clock signal. The first and second inverting units are used to invert the input signal.

2. A low-speed oscillator for use in an MCU according to claim 1, characterized in that, The MOS transistors N1, N2, and N3 are of the same size.

3. A low-speed oscillator for use in an MCU according to claim 1, characterized in that, In the resistor branch, along the direction from the power supply terminal to the MOS transistor N1, the resistance value of the previous resistor is twice the resistance value of the next resistor.

4. A low-speed oscillator for use in an MCU according to claim 1, characterized in that, The SR latch comprises a first NAND gate and a second NAND gate. A first input terminal of the first NAND gate is the S input terminal of the SR latch, and a second input terminal of the first NAND gate is electrically connected to an output terminal of the second NAND gate; A first input terminal of the second NAND gate is electrically connected to an output terminal of the first NAND gate, the output terminal of the first NAND gate is the Q output terminal of the SR latch, and a second input terminal of the second NAND gate is the R input terminal of the SR latch.

5. A low-speed oscillator for use in an MCU according to claim 1, characterized in that, The frequency testing unit comprises a first counter, a second counter and a register. The first counter counts an input second clock signal, and the register is configured to store the count value of the first counter; the second counter counts an input clock signal, and controls the register to send the count value of the first counter to the frequency calibration unit when the count value reaches a preset value.

6. A low-speed oscillator for use in an MCU according to claim 5, characterized in that, The frequency calibration unit outputs a calibration value for calibrating the clock signal through a successive approximation method, the calibration value is used for controlling on-off of a control switch in a resistor branch, taking an actual count value of the first counter as B, taking an ideal count value of the first counter as M, and setting an error range as ±x%; when M×(1-x%) < B < M×(1+x%), the frequency calibration unit outputs the calibration completion signal; when B < M×(1-x%), the frequency calibration unit increases the calibration value to reduce the frequency of the clock signal, and then recalibrates the frequency of the clock signal until the actual count value B satisfies M×(1-x%) < B < M×(1+x%); when B > M×(1+x%), the frequency calibration unit reduces the calibration value to increase the frequency of the clock signal, and then recalibrates the frequency of the clock signal until the actual count value B satisfies M×(1-x%) < B < M×(1+x%).

7. A low-speed oscillator for use in an MCU according to claim 6, characterized in that, when B < M×(1-x%), the frequency calibration unit adds 1 to the calibration value each time to reduce the frequency of the clock signal; when B > M×(1+x%), the frequency calibration unit subtracts 1 from the calibration value each time to increase the frequency of the clock signal.

8. A low-speed oscillator for use in an MCU according to claim 1, characterized in that, The output unit comprises an AND gate, a first input terminal of the AND gate receives the calibration completion signal, and a second input terminal of the AND gate receives the clock signal.

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