A multi-octave bandwidth power amplifier

Abstract

The application discloses a kind of multi-octave bandwidth power amplifier, radio frequency circuit design technical field, solve the existing power amplifier bandwidth small, volume is relatively large, the problem of poor linearity index.Power amplifier includes: input matching network, input end connects signal source, the input end of output end connection stable network, for matching signal source internal resistance value to first real impedance, again first real impedance is matched to the conjugate of the best source impedance of transistor;The input end of stable network is also connected with the output end of gate bias network;First, second parasitic capacitance compensation network is used for compensating the parasitic capacitance of transistor at gate input side, drain output side respectively;Output matching network, input end connects the output end of drain bias network, and output end is connected with load end;For matching the conjugate of the best load impedance of transistor to second real impedance, again second real impedance is matched to load resistance value, wherein, signal source internal resistance value is consistent with load resistance value.

Description

Technical Field

[0001] This invention relates to the field of radio frequency circuit design technology, and in particular to a power amplifier with a multi-octave bandwidth. Background Technology

[0002] With the development of wireless communication technology and the current promotion of 5G technology, wireless devices need to have higher information transmission rates, anti-interference capabilities, and higher efficiency. This places higher technical demands on wireless transceivers. As the terminal of the RF transmitter, the power amplifier plays a crucial role in the entire transceiver, and its high power consumption will also have a significant impact on communication equipment. Therefore, the efficiency and other indicators of the power amplifier are of paramount importance. Furthermore, long-distance communication and radar communication require bandwidth covering multiple octaves, necessitating power amplifiers with higher bandwidth specifications. Currently, various methods have been developed both domestically and internationally to improve power amplifier efficiency. For example, different types of power amplifiers, such as Class E, Class F, or Doherty amplifiers, are used to improve the overall system efficiency. However, Class E power amplifiers require low delay in the drive signal and require the power amplifier tubes to withstand higher voltages; while Class F power amplifiers, although highly efficient, have low linearity; and Doherty power amplifiers use λ / 4 microstrip lines during matching, resulting in a larger overall design size. In addition, in order to enable power amplifiers to cover bandwidths of multiple octaves, some domestic and foreign scholars have applied the stepped impedance transformation method to match the input and output impedances. However, the power amplifiers designed by this method are relatively large and do not meet the trend of miniaturization. Furthermore, distributed amplifiers connect transistors in parallel on two microstrip transmission lines to increase bandwidth, but in reality, the linearity index is poor. Summary of the Invention

[0003] In view of the above analysis, the present invention aims to provide a power amplifier with a multi-octave bandwidth to solve the above-mentioned problems in the prior art.

[0004] This invention discloses a multi-octave bandwidth power amplifier, comprising an input matching network, a stabilization network, a transistor, first and second parasitic capacitance compensation networks, an output matching network, a gate bias network, and a drain bias network; wherein... The input matching network is connected to the signal source at its input and to the input of the stabilization network at its output. It is used to match the internal resistance of the signal source to the first real impedance and then match the first real impedance to the conjugate of the transistor's optimal source impedance. The input of the stabilization network is also connected to the output of the gate bias network. The first and second parasitic capacitance compensation networks are used to compensate for the parasitic capacitance of the transistor on the gate input side and the drain output side, respectively. An output matching network is provided, with its input connected to the output of a drain bias network and its output connected to the load. It is used to match the optimal load impedance of the transistor to a second real impedance, and then match the second real impedance to the load resistance, wherein the internal resistance of the signal source is the same as the load resistance.

[0005] Based on the above solution, the present invention also makes the following improvements: Furthermore, for each network in the power amplifier, First, determine the design architecture of each network, which consists of resistors, capacitors, and / or inductors; the design architecture includes component values, component composition, and component connection relationships. Once the design architecture of each network in the power amplifier is determined, the lumped parameters of each network are converted into distributed parameters, and the distributed parameters are optimized according to the design specifications of the power amplifier to obtain the actual architecture of each network. The power amplifier is obtained by connecting the actual architecture of each network.

[0006] Furthermore, the input matching network includes a T-type real-resistance conversion network and a first bandpass Chebyshev matching network; wherein, The T-type real resistance conversion network is used to match the internal resistance of the signal source to the first real impedance; the input terminal of the T-type real resistance conversion network is the input terminal of the input matching network, and the output terminal is connected to the input terminal of the first band-pass Chebyshev matching network. The first bandpass Chebyshev matching network is used to match the first real impedance to the conjugate of the transistor's optimal source impedance; the output of the first bandpass Chebyshev matching network is the output of the input matching network.

[0007] Furthermore, the design architecture of the first band-pass Chebyshev matching network is obtained through the following method: Impedance transformation is performed on the conjugate of the transistor's optimal source impedance to obtain the corresponding transformed real impedance and transformed capacitance; Based on the bandpass Chebyshev matching method, the conjugate corresponding real impedance and real impedance of the optimal source impedance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network; the real impedance to be matched is the first real impedance; each circuit consists of capacitors and inductors. By organizing the circuits of each order (excluding the capacitor in the first-order circuit) sequentially from the gate of the transistor to the left and from low to high order, the design architecture of the first band-pass Chebyshev matching network is obtained.

[0008] Furthermore, the design architecture of the first parasitic capacitance compensation network is obtained through the following method: The design architecture of the first parasitic capacitance compensation network is obtained by connecting the capacitor in the first-order circuit of the first-band Chebyshev matching network and the compensation capacitor of the gate parasitic capacitance of the transistor in parallel.

[0009] Furthermore, the design architecture of the T-type real resistance conversion network is obtained through the following method: Assuming the primary side of the transformer is connected in parallel with the internal resistance of the signal source, and the secondary side is connected in parallel with the inductor in the highest-order circuit of the first bandpass Chebyshev matching network, determine the number of turns of the transformer with the aim of matching the internal resistance of the signal source to the first real impedance. The transformer with a fixed number of turns and the inductor in the highest-order circuit of the parallel first bandpass Chebyshev matching network are equivalently transformed into a T-type structure, thus obtaining the design architecture of the T-type real resistance conversion network.

[0010] Furthermore, the output matching network includes a second bandpass Chebyshev matching network and a low-bandpass Chebyshev matching network; wherein, The second bandpass Chebyshev matching network is used to conjugate the transistor's optimal load impedance to the second real impedance; the input of the second bandpass Chebyshev matching network is the input of the output matching network, and the output is connected to the input of the low-pass Chebyshev matching network. A low-pass Chebyshev matching network is used to match the second real impedance to the load resistance; the output of the low-pass Chebyshev matching network is the output of the output matching network.

[0011] Furthermore, the design architecture of the second band Tun Chebyshev matching network is obtained through the following method: Impedance transformation is performed on the conjugate of the transistor's optimal load impedance to obtain the corresponding converted real impedance and converted capacitance; Based on the bandpass Chebyshev matching method, the conjugate corresponding real impedance and real impedance of the optimal load impedance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network; the real impedance to be matched is the second real impedance; each circuit consists of capacitors and inductors. By organizing the circuits of each order (excluding the capacitor in the first-order circuit) sequentially from the drain of the transistor to the right and from low to high order, the design architecture of the second-band Chebyshev matching network is obtained.

[0012] Furthermore, the design architecture of the second parasitic capacitance compensation network is obtained through the following method: The design architecture of the second parasitic capacitance compensation network is obtained by connecting the capacitor in the first-order circuit of the second band Chebyshev matching network and the compensation capacitor of the transistor drain parasitic capacitance in parallel.

[0013] Furthermore, the real impedance and capacitance are processed to obtain the real impedance to be matched, as well as the circuits of each order in the matching network, and then the following steps are performed: Calculate the first to second order in the matching network according to formula (1). The normalized value of the element of order; (1) in, Indicates the first The normalized value of the element of order, Take 1 to ; This represents the maximum order of the Tun Chebyshev matching network; and Let be two unknown parameters in the Chebyshev polynomial; when When the value is 3, it is determined according to formulas (2) and (3). and ;when When the value is 4, it is determined according to formulas (2) and (4). and ; (2) in, , , , These represent the converted real impedance and the converted capacitance, respectively. , These represent the angular frequencies of the upper and lower cutoff frequencies, respectively. (3) (4) According to formula (5), the actual impedance to be matched is obtained. : (5) According to formulas (6) and (7), calculate the inverse normalization values ​​of each element; where, The inverse normalized value of an odd-order element refers to the capacitance in an odd-order circuit. Capacitors in a step circuit The value can be: (6) Take 1 to Odd numbers in; The inverse normalized value of an even-order element refers to the inductance in an even-order circuit. Inductance in a step circuit The value can be: (7) Take 1 to Even numbers in; According to formulas (8) and (9), bandpass matching is performed on the inverse normalized values ​​of elements of each order; where, The bandpass matching result of the inverse normalization value of odd-order elements refers to the inductance in odd-order circuits. Inductance in a step circuit The value can be: (8) The bandpass matching result of the inverse normalized value of even-order elements refers to the capacitance in an even-order circuit. Capacitors in a step circuit The value can be: (9).

[0014] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: The multi-octave bandwidth power amplifier provided in this embodiment has the following effects: (1) This embodiment uses a T-type network design, which can effectively reduce the number of microstrip line segments and thus reduce the overall circuit size; (2) In this embodiment, the power amplifier with multiple octave bandwidth operates in deep Class AB mode, thereby ensuring that the linearity of the overall circuit is maintained at a certain level; (3) This embodiment improves upon the existing Chebyshev matching method by proceduralizing the simplified algorithm, enabling the matching of complex impedance to real impedance in any frequency band within the design range, effectively solving the problems of high complexity and low efficiency in the complex impedance to real impedance matching process. (4) In this embodiment, the combination of the bandpass Chebyshev matching network method and the lowpass Chebyshev matching method can achieve multiple octave bandwidth.

[0015] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0016] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0017] Figure 1 A schematic diagram of a power amplifier with a multi-octave bandwidth. Figure 2 A schematic diagram of the architecture for a power amplifier with a multi-octave bandwidth design; Figure 3 A schematic diagram of the actual architecture of a power amplifier with multiple octave bandwidth; Figure 4 The simulation results of the power amplifier with a multi-octave bandwidth are shown in the figure. Detailed Implementation

[0018] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0019] This invention discloses a power amplifier with a multi-octave bandwidth, the structural schematic of which is shown below. Figure 1 As shown, it includes an input matching network, a stabilization network, a transistor, first and second parasitic capacitance compensation networks, an output matching network, a gate bias network, and a drain bias network; wherein, The input matching network is connected to the signal source at its input and to the input of the stabilization network at its output. It is used to match the internal resistance of the signal source (typically 50 ohms) to the first real impedance and then match the first real impedance to the conjugate of the transistor's optimal source impedance. The input of the stabilization network is also connected to the output of the gate bias network. The first and second parasitic capacitance compensation networks are used to compensate for the parasitic capacitance of the transistor on the gate input side and the drain output side, respectively. The input terminal of the first parasitic capacitance compensation network is connected to the output terminal of the stabilization network, and the output terminal is connected to the gate of the transistor. The input terminal of the second parasitic capacitance compensation network is connected to the drain of the transistor, and the output terminal is connected to the input terminal of the output matching network. The output matching network has its input terminal connected to the output terminal of the drain bias network, and its output terminal connected to the load terminal. It is used to match the conjugate of the transistor's optimal load impedance to the second real impedance, and then match the second real impedance to the load resistance value, wherein the internal resistance value of the signal source is consistent with the load resistance value.

[0020] During the operation of the power amplifier, the signal source passes sequentially through a DC blocking capacitor, an input matching network, a stabilization network, and a first parasitic capacitance compensation network to achieve gate impedance matching and parasitic capacitance compensation. Then, the compensated signal is sent to the gate of the transistor. After being amplified by the transistor, the signal passes sequentially through a second parasitic capacitance compensation network and an output matching network to achieve drain parasitic capacitance compensation and impedance matching. Finally, the load resistance of the transistor is converted into a real impedance that is matched to 50 ohms, and the signal is output through the DC blocking capacitor.

[0021] Preferably, for each network in the power amplifier, the design architecture of each network, including resistors, capacitors, and / or inductors, is first determined; the design architecture includes component values, component composition, and component connection relationships; after the design architecture of each network in the power amplifier is determined, the lumped parameters of each network are converted into distributed parameters, and the distributed parameters are optimized according to the design specifications of the power amplifier to obtain the actual architecture of each network; the actual architectures of each network are connected to obtain the power amplifier. To facilitate those skilled in the art to better implement the solution in this application, the design architecture of each network involved in this embodiment is described below: (1) Input matching network In this embodiment, the input matching network includes a T-type real impedance conversion network and a first band-through Chebyshev matching network; wherein, the T-type real impedance conversion network is used to match the 50 ohms to the first real impedance; the input terminal of the T-type real impedance conversion network is the input terminal of the input matching network, and the output terminal is connected to the input terminal of the first band-through Chebyshev matching network; the first band-through Chebyshev matching network is used to match the first real impedance to the conjugate of the transistor's optimal source impedance; the output terminal of the first band-through Chebyshev matching network is the output terminal of the input matching network.

[0022] Specifically, the design architecture of the first bandpass Chebyshev matching network is obtained through the following method: 1) Perform impedance transformation on the conjugate of the transistor's optimal source impedance to obtain the corresponding transformed real impedance and transformed capacitance; In this embodiment, the effects of the second and third harmonics are considered during source-driven (load-driven) impedance to ensure that the selected source impedance (or load impedance) has the optimal performance across the entire bandwidth. Using formula This converts the conjugate of the transistor's optimal source impedance (or load impedance) into a parallel combination of resistor and capacitor.

[0023] 2) Based on the bandpass Chebyshev matching method, the conjugate corresponding real impedance and real impedance of the optimal source impedance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network; the real impedance to be matched is the first real impedance; each circuit consists of capacitors and inductors. 3) Organize the circuits of each order, except for the capacitor in the first order circuit, in order from the gate of the transistor to the left and from low to high order to obtain the design architecture of the first band-pass Chebyshev matching network.

[0024] In step 2), the real impedance and capacitance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network. Then, the following steps are performed: Calculate the first to second order in the matching network according to formula (1). The normalized value of the element of order; (1) in, Indicates the first The normalized value of the element of order, Take 1 to ; This represents the maximum order of the Tun Chebyshev matching network; and Let be two unknown parameters in the Chebyshev polynomial; when When the value is 3, it is determined according to formulas (2) and (3). and ;when When the value is 4, it is determined according to formulas (2) and (4). and ; (2) in, , , , These represent the converted real impedance and the converted capacitance, respectively. , These represent the angular frequencies of the upper and lower cutoff frequencies, respectively. (3) (4) According to formula (5), the actual impedance to be matched is obtained. : (5) According to formulas (6) and (7), calculate the inverse normalization values ​​of each element; where, The inverse normalized value of an odd-order element refers to the capacitance in an odd-order circuit. Capacitors in a step circuit The value can be: (6) Take 1 to Odd numbers in; The inverse normalized value of an even-order element refers to the inductance in an even-order circuit. Inductance in a step circuit The value can be: (7) Take 1 to Even numbers in; According to formulas (8) and (9), bandpass matching is performed on the inverse normalized values ​​of elements of each order; where, The bandpass matching result of the inverse normalization value of odd-order elements refers to the inductance in odd-order circuits. Inductance in a step circuit The value can be: (8) The bandpass matching result of the inverse normalized value of even-order elements refers to the capacitance in an even-order circuit. Capacitors in a step circuit The value can be: (9) The capacitors in each order of the circuit are placed in parallel and the inductors are placed in series, thus obtaining the connection relationship of each order of the circuit.

[0025] This embodiment improves upon the existing Chebyshev matching method by proceduralizing the simplified algorithm and designing the above formulas (1)-(9). Within the design range, it can achieve the matching of complex impedance to real impedance in any frequency band, effectively solving the problems of high complexity and low efficiency in the process of matching complex impedance to real impedance.

[0026] Specifically, the design architecture of the T-type real resistance conversion network is obtained through the following method: Assuming a 50-ohm resistor is connected in parallel to the primary side of the transformer and an inductor from the highest-order circuit of the first band-pass Chebyshev matching network is connected in parallel to the secondary side, determine the number of turns of the transformer with the aim of matching the 50-ohm resistor to the first real impedance. The transformer with a fixed number of turns and the inductor in the highest-order circuit of the parallel first bandpass Chebyshev matching network are equivalently transformed into a T-type structure, thus obtaining the design architecture of the T-type real resistance conversion network.

[0027] The T-type real resistance conversion network designed in this embodiment simplifies the design structure of the input matching network while meeting bandwidth requirements.

[0028] (2) First parasitic capacitance compensation network The design architecture of the first parasitic capacitance compensation network is obtained through the following method: The capacitor in the first-order circuit of the first-band Chebyshev matching network and the compensation capacitor for the gate parasitic capacitance of the transistor are connected in parallel to obtain the design architecture of the first parasitic capacitance compensation network. In later optimization of distributed parameters, the gate parasitic capacitance of the transistor can be adjusted to meet the technical requirements of the power amplifier.

[0029] (3) Output matching network The output matching network includes a second band-pass Chebyshev matching network and a low-pass Chebyshev matching network. The second band-pass Chebyshev matching network is used to match the optimal load impedance of the transistor to the second real impedance. The input of the second band-pass Chebyshev matching network is the input of the output matching network, and the output is connected to the input of the low-pass Chebyshev matching network. The low-pass Chebyshev matching network is used to match the second real impedance to 50 ohms. The output of the low-pass Chebyshev matching network is the output of the output matching network.

[0030] Specifically, the design architecture of the second band-through Chebyshev matching network is obtained through the following method: Impedance transformation is performed on the conjugate of the transistor's optimal load impedance to obtain the corresponding converted real impedance and converted capacitance; Based on the bandpass Chebyshev matching method, the conjugate corresponding real impedance and real impedance of the optimal load impedance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network; the real impedance to be matched is the second real impedance; each circuit consists of capacitors and inductors. By organizing the circuits of each order (excluding the capacitor in the first-order circuit) sequentially from the drain of the transistor to the right and from low to high order, the design architecture of the second-band Chebyshev matching network is obtained.

[0031] The design architecture of the low-pass Chebyshev matching network can be implemented using conventional design methods, and will not be elaborated here.

[0032] It is important to emphasize that, since the output matching network of the overall circuit has a significant impact on the overall performance, the influence of the second harmonic on the output matching network needs to be considered. Therefore, a low-pass Chebyshev matching method is chosen to suppress the second harmonic. In contrast, the harmonic components in the input matching network have little impact on the power amplifier performance. To simplify the circuit and reduce design complexity, a T-type real-resistance converter network is used for real-resistance matching.

[0033] (4) Second parasitic capacitance compensation network The design architecture of the second parasitic capacitance compensation network is obtained through the following method: The capacitor in the first-order circuit of the second-band Chebyshev matching network and the compensation capacitor for the transistor's drain parasitic capacitance are connected in parallel to obtain the design architecture of the second parasitic capacitance compensation network. In later optimization of distributed parameters, the transistor's drain parasitic capacitance can be adjusted to meet the technical requirements of the power amplifier.

[0034] (5) Stable network In this embodiment, the stabilizing network is designed with a resistor and a capacitor connected in parallel. High-frequency signals can directly enter the transistor through the capacitor, while low-frequency signals are attenuated after passing through the resistor, thus preventing the circuit from self-oscillating.

[0035] (6) Gate bias network The gate bias network is used to provide a stable DC operating voltage to the gate of the transistor.

[0036] In this embodiment, the gate bias network is designed with several capacitors connected in parallel and then an inductor connected in series. Specifically, the input terminal of the gate bias network is connected to the gate power supply, several capacitors are connected in parallel between the input terminal and ground, and one end of an inductor is connected in series with the input terminal, with the other end of the inductor serving as the output terminal of the gate bias network. For example, the gate power supply voltage is -2.5V.

[0037] (7) Drain bias network Drain biasing networks are used to provide a stable DC operating voltage to the drain of a transistor.

[0038] In this embodiment, the drain bias network is designed with several capacitors connected in parallel and then an inductor connected in series. Specifically, the input terminal of the drain bias network is connected to the drain power supply, and several capacitors are connected in parallel between the input terminal and ground. One end of an inductor is also connected in series with the input terminal, and the other end of the inductor is used as the output terminal of the drain bias network. For example, the drain power supply voltage is 28V.

[0039] The gate bias circuit and drain bias network suppress high-frequency signals through inductors and bypass capacitors (a type of stray filtering network) select different values ​​to bypass each harmonic to ground, preventing harmonics from entering the circuit and causing irreversible effects.

[0040] The power amplifier obtained after designing the architecture of each network is as follows: Figure 2 As shown. It should be noted that the DC blocking capacitor connected in series with the input side and the 50-ohm input side resistor is a standard feature in power amplifiers.

[0041] Once the design architecture of each network in the power amplifier is determined, the lumped parameters of each network can be converted into distributed parameters, and the distributed parameters can be optimized according to the design specifications of the power amplifier to obtain the actual architecture of each network. During this process, note the following: When converting lumped parameters to distributed parameters, the network of parallel capacitors and inductors is fitted with an optimized microstrip short circuit. This effectively reduces the number of microstrip line segments and lowers the difficulty of circuit optimization while ensuring bandwidth. For the first and second band Chebyshev matching networks, a high-low impedance transformation method is used to convert the series inductor into a series high-impedance stub and the parallel capacitor into a series low-impedance stub.

[0042] For a T-type real resistance transformation network, the lumped parameter T-type structure is transformed into a distributed parameter T-type structure.

[0043] The first and second parasitic capacitance compensation networks use parallel capacitors converted into microstrip lines to compensate for the parasitic capacitance of transistors, making the input and output matching networks more accurate.

[0044] A tapered microstrip line is used to smoothly transition and optimize the connection between the second-band Chebyshev matching network and the low-band Chebyshev matching network to prevent deterioration of the port reflection coefficient. The parallel capacitor at the right end of the tapered microstrip line is approximated by an open-circuit stub, and the parallel inductor is approximated by a short-circuit stub.

[0045] By using the Tunner tool to optimize each microstrip line to achieve the desired effect, a power amplifier design with multi-octave bandwidth was completed. This enabled the overall circuit to achieve multi-octave bandwidth matching while also meeting certain efficiency requirements. Figure 3 This is a schematic diagram of the actual architecture of a power amplifier with a multi-octave bandwidth.

[0046] Figure 4 The diagram shows the power simulation results of a power amplifier with a multi-octave bandwidth. Curve 1 represents the power-added efficiency of the amplifier, curve 2 represents the output power, and curve 3 represents the gain. Simulation examples demonstrate that the power amplifier obtained according to this embodiment can achieve multi-octave bandwidth.

[0047] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0048] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A power amplifier with a multi-octave bandwidth, characterized in that, This includes an input matching network, a stabilization network, a transistor, first and second parasitic capacitance compensation networks, an output matching network, a gate bias network, and a drain bias network; among which... The input matching network is connected to the signal source at its input and to the input of the stabilization network at its output. It is used to match the internal resistance of the signal source to the first real impedance and then match the first real impedance to the conjugate of the transistor's optimal source impedance. The input of the stabilization network is also connected to the output of the gate bias network. The first and second parasitic capacitance compensation networks are used to compensate for the parasitic capacitance of the transistor on the gate input side and the drain output side, respectively. An output matching network is provided, with its input connected to the output of a drain bias network and its output connected to the load. This network is used to match the optimal load impedance of the transistor to a second real impedance, and then to match the second real impedance to the load resistance. The internal resistance of the signal source is the same as the load resistance. The input matching network includes a T-type real-resistance conversion network and a first-band Chebyshev matching network; wherein... The T-type real resistance conversion network is used to match the internal resistance of the signal source to the first real impedance; the input terminal of the T-type real resistance conversion network is the input terminal of the input matching network, and the output terminal is connected to the input terminal of the first band-pass Chebyshev matching network. The first bandpass Chebyshev matching network is used to match the first real impedance to the conjugate of the transistor's optimal source impedance; the output of the first bandpass Chebyshev matching network is the output of the input matching network.

2. The power amplifier with multiple octave bandwidth according to claim 1, characterized in that, For each network in the power amplifier First, determine the design architecture of each network, which consists of resistors, capacitors, and / or inductors; the design architecture includes component values, component composition, and component connection relationships. Once the design architecture of each network in the power amplifier is determined, the lumped parameters of each network are converted into distributed parameters, and the distributed parameters are optimized according to the design specifications of the power amplifier to obtain the actual architecture of each network. The power amplifier is obtained by connecting the actual architecture of each network.

3. The power amplifier with multiple octave bandwidth according to claim 2, characterized in that, The design architecture of the first bandpass Chebyshev matching network was obtained through the following method: Impedance transformation is performed on the conjugate of the transistor's optimal source impedance to obtain the corresponding transformed real impedance and transformed capacitance; Based on the bandpass Chebyshev matching method, the conjugate corresponding real impedance and real impedance of the optimal source impedance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network; the real impedance to be matched is the first real impedance. Each level of circuit consists of capacitors and inductors; By organizing the circuits of each order (excluding the capacitor in the first-order circuit) sequentially from the gate of the transistor to the left and from low to high order, the design architecture of the first band-pass Chebyshev matching network is obtained.

4. The power amplifier with multiple octave bandwidth according to claim 3, characterized in that, The design architecture of the first parasitic capacitance compensation network is obtained through the following method: The design architecture of the first parasitic capacitance compensation network is obtained by connecting the capacitor in the first-order circuit of the first-band Chebyshev matching network and the compensation capacitor of the gate parasitic capacitance of the transistor in parallel.

5. The power amplifier with multiple octave bandwidth according to claim 3, characterized in that, The design architecture of the T-type real resistance conversion network is obtained through the following method: Assuming the primary side of the transformer is connected in parallel with the internal resistance of the signal source, and the secondary side is connected in parallel with the inductor in the highest-order circuit of the first bandpass Chebyshev matching network, determine the number of turns of the transformer with the aim of matching the internal resistance of the signal source to the first real impedance. The transformer with a fixed number of turns and the inductor in the highest-order circuit of the parallel first bandpass Chebyshev matching network are equivalently transformed into a T-type structure, thus obtaining the design architecture of the T-type real resistance conversion network.

6. The power amplifier with multiple octave bandwidth according to claim 1, characterized in that, The output matching network includes a second-band Chebyshev matching network and a low-band Chebyshev matching network; wherein... The second bandpass Chebyshev matching network is used to conjugate the transistor's optimal load impedance to the second real impedance; the input of the second bandpass Chebyshev matching network is the input of the output matching network, and the output is connected to the input of the low-pass Chebyshev matching network. A low-pass Chebyshev matching network is used to match the second real impedance to the load resistance; the output of the low-pass Chebyshev matching network is the output of the output matching network.

7. The power amplifier with multiple octave bandwidth according to claim 6, characterized in that, The design architecture of the second band-pass Chebyshev matching network is obtained through the following method: Impedance transformation is performed on the conjugate of the transistor's optimal load impedance to obtain the corresponding converted real impedance and converted capacitance; Based on the bandpass Chebyshev matching method, the conjugate corresponding real impedance and real impedance of the optimal load impedance are processed to obtain the real impedance to be matched and the circuits of each order in the matching network; the real impedance to be matched is the second real impedance; each circuit consists of capacitors and inductors. By organizing the circuits of each order (excluding the capacitor in the first-order circuit) sequentially from the drain of the transistor to the right and from low to high order, the design architecture of the second-band Chebyshev matching network is obtained.

8. The power amplifier with multiple octave bandwidth according to claim 7, characterized in that, The design architecture of the second parasitic capacitance compensation network is obtained through the following method: The design architecture of the second parasitic capacitance compensation network is obtained by connecting the capacitor in the first-order circuit of the second band Chebyshev matching network and the compensation capacitor of the transistor drain parasitic capacitance in parallel.

9. A power amplifier with a multi-octave bandwidth according to any one of claims 3-5, 7 or 8, characterized in that, Process the converted real impedance and the converted capacitor to obtain the real impedance to be matched, as well as the circuits of each order in the matching network, and then execute: Calculate the first to second order in the matching network according to formula (1). The normalized value of the element of order; （1） in, Indicates the first The normalized value of the element of order, Take 1 to ; This represents the maximum order of the Tun Chebyshev matching network; and Let be two unknown parameters in the Chebyshev polynomial; when When the value is 3, it is determined according to formulas (2) and (3). and ;when When the value is 4, it is determined according to formulas (2) and (4). and ; （2） in, , , , These represent the converted real impedance and the converted capacitance, respectively. , These represent the angular frequencies of the upper and lower cutoff frequencies, respectively. （3） （4） According to formula (5), the actual impedance to be matched is obtained. : （5） According to formulas (6) and (7), calculate the inverse normalization values ​​of each element; where, The inverse normalized value of an odd-order element refers to the capacitance in an odd-order circuit. Capacitors in a step circuit The value can be: （6） Take 1 to Odd numbers in; The inverse normalized value of an even-order element refers to the inductance in an even-order circuit. Inductance in a step circuit The value can be: （7） Take 1 to Even numbers in; According to formulas (8) and (9), bandpass matching is performed on the inverse normalized values ​​of elements of each order; where, The bandpass matching result of the inverse normalization value of odd-order elements refers to the inductance in odd-order circuits. Inductance in a step circuit The value can be: （8） The bandpass matching result of the inverse normalized value of even-order elements refers to the capacitance in an even-order circuit. Capacitors in a step circuit The value can be: （9）。

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