A circuit and method for reconstructing the performance of an analog-to-digital converter based on a segmented capacitor array.

Abstract

This invention provides a reconstruction circuit and method for the performance of an analog-to-digital converter (ADC) based on a segmented capacitor array. The reconstruction circuit includes a high-precision comparator, a medium-precision comparator, and a three-segment capacitor array. By connecting different comparators and switching switches, the structure of the capacitor array and the input method of the input signal are changed, allowing the ADC to switch between a high-precision operating mode and a medium-precision operating mode, thereby achieving sampling and quantization output of the input signal. In the high-precision operating mode, this invention uses a larger high-level capacitor array for sampling and a high-precision comparator, resulting in higher power consumption and lower speed. In the medium-precision operating mode, medium-precision reconstruction is performed by grounding the high-level capacitors, while simultaneously using a medium-precision high-speed comparator and some ADC logic, resulting in overall improved speed and reduced power consumption. This invention simplifies the reconstruction operation, saves on reconstruction switches, and avoids the impact of non-ideal switching effects on the quantization process of the ADC.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit technology, specifically relating to a circuit and method for reconstructing the performance of an analog-to-digital converter based on a segmented capacitor array. Background Technology

[0002] With the rapid development of integrated circuit technology, the application fields of analog-to-digital converters (ADCs) are constantly expanding, and performance requirements are continuously increasing. They have become core components in applications such as portable electronic devices, biomedicine, wireless communication, and smart radar. End users are seeking ADCs with varying levels of accuracy and speed to support a wide range of applications. Therefore, reconfigurable ADCs have emerged, offering more flexible accuracy, speed, and power consumption to meet the application needs of different scenarios.

[0003] Traditional analog-to-digital converter (ADC) reconfiguration methods use reconfiguration switches to directly disconnect the capacitor array, thereby separating the required ADC and achieving ADC reconfiguration. However, reconfiguration switches in the signal path can produce non-ideal effects such as charge injection, which can affect the quantization process of the entire ADC. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a circuit and method for reconstructing the performance of an analog-to-digital converter based on a segmented capacitor array. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a reconfiguration circuit for an analog-to-digital converter based on a segmented capacitor array, comprising: a high-precision low-speed comparator, a medium-precision high-speed comparator, and a three-segment capacitor array.

[0006] The negative input terminal of the high-precision low-speed comparator is connected to the upper-level board of the first capacitor array, and the negative input terminal of the medium-precision high-speed comparator is connected to the upper-level board of the second capacitor array. The lower-level board of each capacitor array is connected to the corresponding switching switch. The positive input terminals of the high-precision low-speed comparator and the medium-precision high-speed comparator are connected to the common-mode signal VCM. The switching switch switches between the input signal VIN, ground GND, and reference voltage VREF.

[0007] This invention provides a reconstruction method for an analog-to-digital converter (ADC) based on a segmented capacitor array, employing a reconstruction circuit for the ADC based on a segmented capacitor array. The reconstruction method includes:

[0008] The high-precision comparator is connected through the first capacitor array, and the corresponding switch of the first capacitor array is switched to the input signal VIN, so that the analog-to-digital converter based on the segmented capacitor array enters the high-precision working mode and outputs M+K+L bit digital code.

[0009] The intermediate precision comparator is connected through the second capacitor array, and the corresponding switch of the second capacitor array is switched to the input signal VIN. The lower plates of the first capacitor array are grounded to GND, so that the analog-to-digital converter based on the segmented capacitor array enters the intermediate precision working mode and outputs a K+L bit digital code.

[0010] This invention provides a reconfiguration circuit and method for analog-to-digital converter (ADC) performance based on a segmented capacitor array. The reconfiguration circuit includes a high-precision comparator, a medium-precision comparator, and a three-segment capacitor array. By connecting different comparators and switching switches, the capacitor array structure and the input signal input method are changed, allowing the ADC to switch between a high-precision operating mode and a medium-precision operating mode, thereby achieving sampling and quantization output of the input signal. This invention can achieve mutual reconfiguration of ADCs in two different application scenarios: high-precision, low-speed, high-power, and medium-precision, high-speed, low-power. Due to sampling noise limitations, the high-precision operating mode uses a larger high-level capacitor array as the sampling capacitor and a high-precision comparator, resulting in higher power consumption and lower speed. In the medium-precision operating mode, the entire high-level capacitor array is grounded, and the remaining capacitor array completes the quantization, achieving the reconfiguration from high-precision to medium-precision. Simultaneously, a medium-precision high-speed comparator and some ADC logic are used, improving overall speed and reducing power consumption, ultimately reconfiguring into a medium-precision, high-speed, low-power ADC. This invention simplifies the reconfiguration operation, saves on reconfiguration switches, and avoids the impact of non-ideal switching effects on the quantization process of the ADC.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the reconfiguration circuit of the analog-to-digital converter based on a segmented capacitor array proposed in this invention;

[0013] Figure 2 A high-precision operating mode analog-to-digital converter capacitor array is an example of the present invention;

[0014] Figure 3 This invention relates to a reconstructed analog-to-digital converter capacitor array operating in a medium-precision mode. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] Combination Figures 1 to 3 As shown, the present invention provides a reconfiguration circuit for an analog-to-digital converter based on a segmented capacitor array, comprising: a high-precision low-speed comparator, a medium-precision high-speed comparator, and a three-segment capacitor array.

[0017] The high-precision low-speed comparator's negative input is connected to the upper-level board of the first capacitor array, and the medium-precision high-speed comparator's negative input is connected to the upper-level board of the second capacitor array. Each capacitor array's lower-level board is connected to a corresponding switching switch. The positive inputs of the high-precision low-speed comparator and the medium-precision high-speed comparator are connected to the common-mode signal VCM. The switching switch toggles between the input signal VIN, ground GND, and reference voltage VREF. The three-segment capacitor array has an M+K+L segmented structure, with each segment containing M, K, and L quantization bits, respectively. Each segment includes a ground GND capacitor. The reconstruction circuit has two operating modes: a high-precision operating mode and a medium-precision operating mode.

[0018] In high-precision operating mode, the input signal VIN is sampled using the lower plate of the first capacitor array and compared using a high-precision, low-speed comparator connected to the upper board of the first capacitor array. Quantization is performed after sampling by the first capacitor array, outputting an M+K+L bit digital code. In medium-precision operating mode, all lower plates of the first capacitor array are connected to GND, and comparison is performed using a medium-precision, high-speed comparator connected to the upper board of the second capacitor array. Quantization is performed after sampling by the second capacitor array, using only a portion of the logic from the high-precision operating mode, outputting a K+L bit digital code.

[0019] like Figure 2 The diagram illustrates a three-segment high-precision capacitor array, an analog-to-digital converter implemented using an M+K+L segmented structure. Sampling is performed using the lower plates of M binary capacitors on the first segment of the capacitor array. Switching to high-precision operating mode: the negative input of the high-precision low-speed comparator is connected to the upper-level board of the first segment of the capacitor array. The corresponding switch for the first segment of the capacitor array is connected to the input signal VIN and switches between the input signal VIN, ground GND, and the reference voltage VREF. The switches for the second and third segments of the capacitor array switch between ground GND and the reference voltage VREF.

[0020] Wherein, the reference voltage VREF is the reference voltage of the analog-to-digital converter (ADC).

[0021] like Figure 3The diagram illustrates an example of a two-segment medium-precision capacitor array reconstructed from a three-segment high-precision capacitor array, using the reconstructed K+L segmented capacitor array to implement a medium-precision analog-to-digital converter. Switching to medium-precision operating mode: the negative input terminal of the medium-precision high-speed comparator is connected to the upper-level board of the second segment capacitor array; the corresponding switch for the second segment capacitor array is connected to the input signal VIN and switches between the input signal VIN, ground GND, and reference voltage VREF; the corresponding switch for the first segment capacitor array is connected to ground GND, and the corresponding switch for the third segment capacitor array switches between ground GND and reference voltage VREF.

[0022] In medium-precision operating mode, the capacitor array is reconfigured, the comparator is replaced with a medium-precision high-speed comparator, and some analog-to-digital converter (ADC) logic is used. All switches on the lower plate of the first capacitor array are grounded and connected in series with the bridging capacitor Cb1 between the first and second capacitor arrays. This is equivalent to adding a small grounding capacitor to the second capacitor array, which does not affect the overall quantization of the ADC. After reconfiguration, the overall circuit becomes a K+L two-stage medium-precision ADC.

[0023] The sampling and quantization process in both high-precision and medium-precision working modes is divided into a sampling phase, a holding phase, and a charge redistribution phase.

[0024] During the sampling phase of the high-precision working mode, the upper board of the first capacitor array is connected to the common-mode signal VCM, the corresponding switch of the first capacitor array is connected to the input signal VIN, and the corresponding switches of the second and third capacitor arrays are all connected to GND. Then, the input signal VIN is sampled.

[0025] During the holding phase in high-precision working mode, the common-mode signal (VCM) is disconnected from the upper-level board of the first capacitor array, and the corresponding switching switches of the first, second, and third capacitor arrays are all connected to GND to keep the input signal stable.

[0026] During the charge redistribution stage in high-precision operating mode, a high-precision low-speed comparator connected to the upper-level board of the first capacitor array is used for comparison. The corresponding switching timing is switched according to the comparison result to complete the ADC quantization work.

[0027] refer to Figure 2During the sampling phase, the lower plates of the M binary capacitors in the first capacitor array are connected to the input signal VIN, and the upper plate of the first capacitor array is connected to the common-mode signal VCM. All capacitors in the second and third segments are connected to GND. During the hold phase, the switch on the upper plate of the first capacitor array connected to the common-mode signal VCM is opened, the lower plates of the binary capacitors in the first capacitor array are connected to GND, and the remaining switches remain unchanged. During the charge redistribution phase, according to charge conservation, the highest-order capacitor switch is switched to VREF. The voltage change at the comparator input point Vo is compared with the voltage VCM at the other input of the comparator. Then, based on the comparator result, the capacitor array switches are switched to either the positive reference voltage VREF or the negative reference voltage GND according to the traditional switching sequence, and so on, to complete all quantization.

[0028] During the sampling phase in medium-precision working mode, the upper board of the second capacitor array is connected to the common-mode signal VCM, the corresponding switch of the second capacitor array is connected to the input signal VIN, and the corresponding switches of the second and third capacitor arrays are all connected to GND. Then, the input signal VIN is sampled.

[0029] During the holding phase in medium-precision working mode, the upper board of the second capacitor array disconnects the common-mode signal VCM, and the corresponding switching switches of the first, second, and third capacitor arrays are all connected to GND to keep the input signal stable.

[0030] During the charge redistribution stage in medium-precision operating mode, a medium-precision high-speed comparator connected to the upper-level board of the second-stage capacitor array is used for comparison. The corresponding switching timing is switched according to the comparison result to complete the ADC quantization work.

[0031] refer to Figure 3 During the sampling phase, the lower plates of the K binary capacitors in the second capacitor array are connected to the input signal VIN, the upper plate of the second capacitor array is connected to the common-mode signal VCM, and all capacitors in the first and third segments are connected to GND. During the hold phase, the switch on the upper plate of the second capacitor array connected to the common-mode signal VCM is turned off, the lower plates of the binary capacitors in the second capacitor array are connected to GND, and the remaining switches remain unchanged. During the charge redistribution phase, the switching timing is the same as that of the high-precision capacitor array. The upper plate of the second capacitor array is connected to a medium-precision high-speed comparator for comparison, and the comparison result is output, completing the quantization.

[0032] This invention provides a reconstruction method for an analog-to-digital converter (ADC) based on a segmented capacitor array. The reconstruction method utilizes the aforementioned reconstruction circuit for the ADC based on a segmented capacitor array and includes:

[0033] The high-precision comparator is connected through the first capacitor array, and the corresponding switch of the first capacitor array is switched to the input signal VIN, so that the analog-to-digital converter based on the segmented capacitor array enters the high-precision working mode and outputs M+K+L bit digital code.

[0034] The intermediate precision comparator is connected through the second capacitor array, and the corresponding switch of the second capacitor array is switched to the input signal VIN. The lower plates of the first capacitor array are grounded to GND, so that the analog-to-digital converter based on the segmented capacitor array enters the intermediate precision working mode and outputs a K+L bit digital code.

[0035] The reconstruction process and the reconstruction circuit operate in the same way in high-precision and medium-precision modes, and will not be described in detail here.

[0036] It's worth noting that both high-precision and medium-precision operating modes use lower plate sampling. In high-precision mode, sampling uses only the binary capacitors of the first capacitor array; the remaining capacitors are not involved in sampling. In medium-precision mode, sampling uses the binary capacitors of the second capacitor array; the remaining capacitors are not involved in sampling. When a high-precision analog-to-digital converter (ADC) is reconstructed into a medium-precision ADC, the entire first capacitor array is grounded and connected in series with the bridging capacitor Cb1 between the first and second capacitor arrays. This is equivalent to adding a small grounding capacitor to the second capacitor array, and the quantization of the entire medium-precision ADC remains unaffected. The high-precision ADC uses a high-precision comparator for comparison, resulting in lower speed and higher power consumption. After reconstructing into a medium-precision ADC, the comparator switches to a medium-precision, high-speed, low-power comparator, achieving higher speed and lower power consumption. Both comparators can be directly connected to the capacitor array, and their impact on the quantization of the ADC is negligible.

[0037] A high-precision analog-to-digital converter (ADC) requires M+K+L bit quantization, while a medium-precision ADC requires K+L bit quantization. The medium-precision ADC has even fewer comparison cycles and can use some of the digital logic from the high-precision ADC to complete the required quantization.

[0038] The reconstruction method of this invention avoids the use of a reconstruction switch when reconstructing a high-precision analog-to-digital converter (ADC) to a medium-precision ADC. It completes the capacitor array reconstruction by grounding all high-order capacitors, ensuring that the quantization of the entire ADC remains unaffected. Furthermore, it utilizes higher-speed, lower-power comparators and fewer ADC logic elements, resulting in higher overall speed and lower power consumption. The two operating modes can be switched between each other, achieving reconstruction of the ADC's accuracy, speed, and power consumption.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0040] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0041] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A reconfiguration circuit for an analog-to-digital converter based on a segmented capacitor array, characterized in that, include: High-precision low-speed comparators, medium-precision high-speed comparators, and three-segment capacitor arrays; The negative input terminal of the high-precision low-speed comparator is connected to the upper-level board of the first capacitor array, and the negative input terminal of the medium-precision high-speed comparator is connected to the upper-level board of the second capacitor array. The lower-level board of each capacitor array is connected to a corresponding switching switch. The positive input terminals of the high-precision low-speed comparator and the medium-precision high-speed comparator are connected to a common-mode signal. The switching switch switches between the input signal ground and the reference voltage. The reconfiguration circuit has two operating modes: a high-precision operating mode and a medium-precision operating mode. Switching to high-precision operating mode: The negative input terminal of the high-precision low-speed comparator is connected to the upper-level board of the first capacitor array. The corresponding switch of the first capacitor array is connected to the input signal and switches between the input signal, ground, and reference voltage. The switches of the second and third capacitor arrays switch between ground and reference voltage. Switching to medium precision operating mode: The negative input terminal of the medium precision high-speed comparator is connected to the upper-level board of the second capacitor array. The switch corresponding to the second capacitor array is connected to the input signal and switches between the input signal, ground, and reference voltage. The switch corresponding to the first capacitor array is connected to ground, and the switch corresponding to the third capacitor array switches between ground and reference voltage. In the sampling phase of the high-precision working mode, the upper board of the first capacitor array is connected to the common-mode signal, the corresponding switch of the first capacitor array is connected to the input signal, and the corresponding switches of the second and third capacitor arrays are all connected to ground. Then the input signal is sampled. During the holding phase in high-precision working mode, the common-mode signal is disconnected from the upper board of the first capacitor array, and the switching switches corresponding to the first, second, and third capacitor arrays are all grounded to keep the input signal stable. In the charge redistribution stage of high-precision working mode, a high-precision low-speed comparator connected to the upper board of the first capacitor array is used for comparison. The corresponding switching timing is switched according to the comparison result to complete the ADC quantization work. During the sampling phase of the medium-precision working mode, the upper board of the second capacitor array is connected to the common-mode signal, the corresponding switch of the second capacitor array is connected to the input signal, and the corresponding switches of the second and third capacitor arrays are all connected to ground. Then the input signal is sampled. During the holding phase in medium-precision working mode, the common-mode signal is disconnected from the upper board of the second capacitor array, and the switching switches corresponding to the first, second, and third capacitor arrays are all grounded to keep the input signal stable. During the charge redistribution stage in medium-precision operating mode, a medium-precision high-speed comparator connected to the upper-level board of the second-stage capacitor array is used for comparison. The corresponding switching timing is switched according to the comparison result to complete the ADC quantization work.

2. The reconfiguration circuit of the analog-to-digital converter based on a segmented capacitor array according to claim 1, characterized in that, The three-segment capacitor array has an M+K+L segmented structure, with each segment containing capacitors M, K, and L.

3. The reconfiguration circuit of the analog-to-digital converter based on a segmented capacitor array according to claim 2, characterized in that, Each segment of the capacitor array contains a grounded capacitor.

4. The reconfiguration circuit of the analog-to-digital converter based on a segmented capacitor array according to claim 1, characterized in that, The sampling and quantization process in both high-precision and medium-precision working modes is divided into a sampling phase, a holding phase, and a charge redistribution phase.

5. A reconstruction method for an analog-to-digital converter based on a segmented capacitor array, characterized in that, The reconstruction circuit of the analog-to-digital converter based on a segmented capacitor array according to any one of claims 1 to 4, the reconstruction method comprising: The high-precision comparator is connected through the first segment capacitor array, and the corresponding switch of the first segment capacitor array is switched to the input signal, so that the analog-to-digital converter based on the segment capacitor array enters the high-precision working mode and outputs M+K+L bit digital code. The second capacitor array is connected to a medium-precision comparator, and the corresponding switch of the second capacitor array is switched to the input signal. The lower plates of the first capacitor array are all grounded, so that the analog-to-digital converter based on the segmented capacitor array enters the medium-precision working mode and outputs a K+L bit digital code.

Images