A capacitor array for a multi-channel SAR ADC

Abstract

The application discloses a kind of capacitor arrays of multichannel SAR ADC, including K highest bit capacitors, N-1 low bit capacitors, sample-and-hold circuit, control switch and comparator, each channel uses the weight capacitor identical to the highest bit of DAC capacitor array as tracking holding capacitor, while realizing the synchronous sampling of each channel, the total capacitance of capacitor is reduced, thereby reducing the layout area.When working, first enter the synchronous sampling stage and holding stage, then connect the tracking holding capacitor of one of the channels with the comparator, redistribute the charge through switch control, complete the analog-digital conversion of the input signal on one channel;For multiple channels, connect the tracking holding capacitor on the corresponding channel to the comparator and go through the above conversion process, and the analog-digital conversion result of this channel can be obtained.The application is suitable for the design of SAR ADC with multichannel synchronous sampling, and can greatly reduce the capacitor area.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital converter technology and relates to a capacitor array for a multi-channel SAR ADC. Background Technology

[0002] Analog-to-digital converters (ADCs) can convert continuous analog signals from nature into discrete digital signals in the digital domain. They serve as the interface for information exchange between the real world and electronic products, playing a crucial role in chips. Among them, SAR ADCs (Successive Approximation Register ADCs) are widely used in many fields due to their high precision, simple structure, and low power consumption.

[0003] SAR ADCs primarily come in three architectures: resistive, capacitive, and hybrid (resistive-capacitive). Among these, capacitive SAR ADCs include... Figure 1 As shown, it mainly includes a sample-and-hold circuit, a DAC array, successive approximation logic, and a comparator. The sample-and-hold circuit samples the analog input voltage during the sampling phase. Then, the DAC array and comparator, under the control of the successive approximation logic, quantize and convert the input signal. The core idea of ​​its working principle is a binary search: the output voltage of the DAC before the nth comparison will change according to the result of the previous comparison. It achieves successive approximation of the input voltage and ultimately completes analog-to-digital conversion.

[0004] For multi-channel converters, multiple sampling capacitors are typically used to sample and hold the analog input voltage on each channel. Then, a multiplexer sequentially selects each channel for analog-to-digital conversion. To ensure sufficient charge is transferred to the conversion section, one approach is to use an active charge-balancing switch structure to transfer all the charge from the sampling capacitors to the conversion section; another approach is to use a large sampling capacitor. Since the sampling capacitor needs to be close to the total capacitance of the conversion section, even without considering active methods, the expected area required is quite large. Summary of the Invention

[0005] To overcome the problems in the prior art, the present invention provides a capacitor array for a multi-channel SAR ADC, which uses the highest bit weight capacitor of the DAC as the sample-and-hold capacitor in multiple channels. By switching the sampling capacitor and the conversion capacitor of each channel in sequence, the analog-to-digital conversion can be achieved, which can effectively reduce the total capacitor area.

[0006] A capacitor array for a multi-channel SAR ADC, the capacitor array comprising K most significant bit capacitors C M(1) ~C M(K) N-1 low-order capacitors CL1 ~C L(N-1) The sample and hold circuit, control switch, and comparator are included, where K represents the number of channels and N represents the number of bits of the ADC. The highest-order capacitor participates in the sampling and charge redistribution process, while the lowest-order capacitor does not participate in the sampling process.

[0007] The sample-and-hold circuit employs a gate voltage bootstrap sampling switch to facilitate sampling of the input signal and charge retention.

[0008] The control switch is composed of MOSFETs and is used to control the input level or signal of each capacitor plate corresponding to it.

[0009] The comparator is used to compare the output value of the capacitor array with the common-mode voltage. The value of VREF is calculated and the comparison result is output, where VREF is the reference voltage value.

[0010] The switching method utilizes a switch to control the K highest-order capacitors C during the sampling phase. M(1) ~C M(K) For the input voltage V on the corresponding channel in(1) ~V un(K) After synchronous sampling is performed, the process enters the hold phase, and then the highest bit capacitor C is switched off via a switching action. M(1) ~C M(K) Each signal is connected to a comparator and a low-order capacitor array for charge redistribution, ultimately yielding the conversion results of the input signals on the corresponding channels.

[0011] Preferably, the value of the nth capacitor in the capacitor array is twice the value of the (n-1)th capacitor. <n<N;

[0012] Preferably, the highest bit capacitor C M(1) =C M(2) =…=C M(K) =2 N-1 Cu, the upper electrode is controlled by switch S M Select Connect to V cm The lower plate of the voltage or comparator is controlled by switch S. S Decision to connect to V cm Potential or corresponding input signal V in(L) .

[0013] Preferably, the low-side capacitor C L(i) =2 i-1 Cu, where i = 1, 2, ..., N-1, and the upper plates of each capacitor are connected together by switch S. L The control determines whether the capacitor is connected to the inverting input of the comparator. The lower plate of each capacitor is controlled by the corresponding control switch S. i Decide to connect to V cmEither VREF or ground.

[0014] Preferably, the non-inverting input of the comparator is constantly connected to V. cm Potential.

[0015] The capacitor array switching steps of the multi-channel SAR ADC are as follows:

[0016] 1) Sampling stage

[0017] The upper plates of the K highest-order capacitors are connected via switch S. M All connected to common-mode voltage V cm The lower electrode plate is controlled by switch S. S Connect to the corresponding input voltage V respectively in(K) Low-level capacitor C L1 ~C L(N-1) The upper electrode plate is controlled by switch S L Control connected to common-mode voltage V cm The lower electrode plate is controlled by switch S. i All are connected to common-mode voltage V cm The non-inverting input of the comparator is connected to V. cm ;

[0018] 2) Maintenance phase

[0019] The highest bit capacitance C of all channels M(1) ~C M(K( The upper electrode is disconnected, and the lower electrode is connected via switch S. S Connect to V cm Potential;

[0020] 3) Charge redistribution stage

[0021] The charge of the highest-order capacitors on channels 1 through K is redistributed sequentially. First, the input signal V on the first channel is converted. in(1) The specific process is as follows:

[0022] A1. Determine the highest bit B(N): Set the highest bit capacitor C... M(1) The upper plate is connected to the inverting input of the comparator, and the highest bit capacitor C on the other channels... M(2) ~C M(K) The connected switch is not working, and the low-level capacitor C... L1 ~C L(N-1) The upper electrode plate is controlled by switch S L Connected to the inverting input of the comparator, the lower plate remains connected to the common-mode voltage V. cm At this time, the non-inverting input of the comparator is connected to V. cm With the voltage connected, the first conversion result B(N) can be obtained directly from the comparator output;

[0023] A2. Determine the second highest value B(N-1): If B(N) = 1, then change the second highest value capacitor C. L(N-1) The lower electrode plate is controlled by switch S N-1 Ground to GND; if B(N) = 0, then the second highest capacitor C... L(N-1) The lower electrode plate is controlled by switch S N-1 Connect to reference voltage VREF, switch S N-1 After the action and charge redistribution are completed, the comparator outputs the conversion result B(N-1) in the second bit.

[0024] A3. Determine the conversion result B(N+1-j) for the j-th bit, where 3≤j≤N: If B(N+2-j)=1, then change the capacitor C for the j-th bit. L(N+1-j) The lower electrode plate is controlled by switch S N+1-j Ground GND; if B(N+2-j)=0, then the j-th capacitor C L(N+1-j) The lower electrode plate is controlled by switch S N+1-j Connect to reference voltage VREF, switch S N+1-j After the action and charge redistribution are completed, the comparator outputs the conversion result B(N+1-j) of the j-th bit;

[0025] After all capacitors have completed charge redistribution, an N-bit binary code B[N:1] is obtained, and the analog-to-digital conversion on the first channel is complete; next, the low-order capacitors are reset, and the highest-order capacitor C of the second channel is reset. M(2) Connect the comparator and repeat steps A1 to A3 to obtain the second channel input signal V. in(2) The conversion results are obtained by repeating steps A1 to A3 K times, and finally the conversion results of K channels are obtained.

[0026] Based on the above technical solution, the present invention has the following beneficial effects:

[0027] 1. This invention uses the highest-order capacitor C in the DAC array. M For sampling, the sampling capacitance of K channels is K*C M The total capacitance of the transformation section is equal to the capacitance of the highest-order bit, that is, the total capacitance of the transformation section is C. M Therefore, the total capacitance required in this invention is (K+1)*C M If the sampling capacitor is independent, then generally speaking, the sampling capacitor must be equal to the total capacitance of the transformation section, both being 2C. M Therefore, the total capacitance of the K channels is (2K+2)*C M Therefore, compared with independent sampling capacitor schemes, the present invention can greatly reduce the number of capacitors used, thereby reducing the layout area.

[0028] 2. The more channels there are, the more capacitors this invention can reduce the number of capacitors used.

[0029] 3. During the sampling process, the highest bit capacitance C M The required settling time is less than 2C for independent sampling capacitors. M The setup time is reduced, so the overall operating frequency of the ADC can be higher. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the architecture of a capacitive SAR ADC.

[0031] Figure 2 This is a schematic diagram of the capacitor array structure of the SAR ADC that enables K-channel synchronous sampling according to the present invention.

[0032] Figure 3 This is the circuit used when one channel is working in this invention.

[0033] Figure 4 This invention relates to the switching states of a 2-channel 3-bit SAR ADC under different operating stages.

[0034] Figure 5 This refers to the switching state of the second channel when the second channel of the present invention is just entering the charge redistribution stage in a 2-channel 3-bit SAR ADC. Detailed Implementation

[0035] The present invention will be described and explained below with reference to the accompanying drawings and examples, but the examples are not intended to limit the present invention.

[0036] like Figure 2 As shown, a capacitor array for a multi-channel SAR ADC includes K most significant bit capacitors C. M(1) ~C M(K) N-1 low-order capacitors C L1 ~C L(N-1) Sample hold switch S S(1) ~S S(K) Control switches S1 to S2 11 S L S M The comparator is CMP, where K represents the number of channels and N represents the number of bits in the ADC. The sample-and-hold circuit uses a gate-voltage bootstrap sampling switch to facilitate sampling of the input signal and charge holding. The control switch, composed of MOSFETs, controls the input level or signal of each corresponding bit capacitor plate. The non-inverting input of the comparator is constantly connected to a common-mode voltage. The inverting input is connected to a DAC array to compare the output value of the capacitor array with the magnitude of the common-mode voltage and output the comparison result.

[0037] according to Figure 2 The operating steps of the K-channel 12-bit SAR ADC shown are as follows:

[0038] 1) Sampling stage

[0039] The upper plates of the K highest-order capacitors are connected via switch S. M(1) ~S M(K) Connected to common-mode voltage V cm The lower electrode plate is controlled by switch S. S(1) ~S S(K) Connect to the corresponding input voltage V respectively in(1) ~V in(K) Low-level capacitor C L1 ~C L(N-1) The upper electrode plate is controlled by switch S L Control connected to common-mode voltage V cm The lower electrode plate is connected to switches S1 to S2. 11 All are connected to common-mode voltage V cm ;

[0040] 2) Maintenance phase

[0041] The highest bit capacitance C of all channels M(1) ~C M(K) The upper plate and the common-mode voltage V cm Disconnect, the lower electrode plate is connected via switch S S(1) ~S S(K) Connect to V cm Potential;

[0042] 3) Charge redistribution stage

[0043] The charge of the highest-order capacitors on channels 1 through K is redistributed sequentially. First, the input signal V on the first channel is converted. in(1) ,like Figure 3 As shown, this is essentially a manifestation of the dichotomy method, and the specific process is as follows:

[0044] A1. Determine the highest bit B(12): Set the highest bit capacitor C M(1) The upper electrode plate is connected to S M(1) Connect the inverting input of the comparator, and the highest bit capacitor C on the other channels M(2) ~C M(K) The connected switch is not working, and the low-level capacitor C... L1 ~C L11 The upper electrode plate is controlled by switch S L Connected to the inverting input of the comparator, the lower plate remains connected to the common-mode voltage V. cm At this time, the non-inverting input of the comparator is connected to V. cm With the potential connected, the first conversion result B(12) can be obtained directly from the comparator output;

[0045] A2. Determine the second highest value B(11): If B(12) = 1, then change the second highest value capacitor C.L11 The lower electrode plate is controlled by switch S 11 Ground GND; if B(12)=0, then the second highest capacitor C L11 The lower electrode plate is controlled by switch S 11 Connect to reference voltage VREF; switch S 11 After the action and charge redistribution are completed, the comparator outputs the conversion result B(11) of the second bit;

[0046] A3. Determine the conversion result B(13-j) for the j-th bit, where 3≤j≤12: If B(14-j)=1, then change the capacitor C for the j-th bit. L(13-j) The lower electrode plate is controlled by switch S 13-j Ground to GND; if B(14-j)=0, then the j-th capacitor C L(13-j) The lower electrode plate is controlled by switch S 13-j Connect to reference voltage VREF, switch S 13-j After the action and charge redistribution are completed, the comparator outputs the conversion result B(13-j) of the j-th bit;

[0047] After all capacitors have completed charge redistribution, a 12-bit binary code B[12:1] is obtained, and the analog-to-digital conversion on the first channel is completed; next, the low-order capacitors are reset, and the highest-order capacitor C of the second channel is reset. M(2) Connect the comparator and repeat steps A1 to A3 to obtain the second channel input signal V. in(2) The conversion results are obtained by repeating steps A1 to A3 K times, and finally the conversion results of K channels are obtained.

[0048] The rationality of the structure and sampling method of this invention is explained below using the working process of a 2-channel 3-bit SAR ADC as an example. Figure 4 As shown, the steps are as follows:

[0049] 1) Sampling stage

[0050] The upper plate of the highest-order capacitor is connected to switch S. M(1) S M(2) Connected to common-mode voltage V cm The lower electrode plate is controlled by switch S. S(1) S S(2) Connect to the corresponding input voltage V respectively in(1) V in(2) Low-level capacitor C L1 C L2 The upper electrode plate is controlled by switch S L Control connected to common-mode voltage V cm The lower electrode is connected to the common-mode voltage V through switches S1 and S2. cm At this time, C L1 C L2 The charges on them are respectively:

[0051] Q1=(V cm -V in(1) )*4Cu#(1)

[0052] Q2=(V cm -V in(2) )*4Cu#(2)

[0053] 2) Maintenance phase

[0054] The highest bit capacitance C of the two channels M(1) C M(2) The upper plate and the common-mode voltage V cm Disconnect, the lower electrode is connected to V via a switch. cm Potential.

[0055] 3) Charge redistribution stage

[0056] First, the charge on the highest-order capacitor of channel 1 is converted:

[0057] a. Turn switch S M(1) and S L Connected to the inverting input of the comparator, since C is at this time M(1) Since the total charge on the input remains constant, the voltage at the inverting input terminal can be calculated as follows:

[0058]

[0059] The potential at the non-inverting input of the comparator is V. cm Therefore, the comparator's output is affected by (V) cm -V in(1) The effect of the sign: If V cm -V in(1) >0, that is, V cm >V in(1) Then V X1 >V cm The comparator outputs AMP = 0; if V cm <V in(1) If AMP = 1, then this output is the first bit of the ADC conversion result, B(3).

[0060] b. If B(3) = 0, it means that the output voltage of the DAC array is too large. At this time, switch S2 is connected to GND, and the voltage at the inverting input of the comparator is obtained.

[0061]

[0062] That is: V in(1) and In comparison, if Then B(2) = AMP = 0; if Then B(2) = AMP = 1.

[0063] If B(3) = 1, switch S2 is connected to VREF, and the voltage at the inverting input of the comparator is obtained.

[0064]

[0065] At this time V in(1) and In comparison, if Then B(2) = AMP = 0; if Then B(2) = AMP = 1.

[0066] c. If B(2) = 0, refer to step b. At this time, switch S1 is connected to GND, and the voltage at the inverting input terminal of the comparator is obtained.

[0067]

[0068] That is: V in(1) and In comparison, if Then B(1) = AMP = 0; if Then B(1) = AMP = 1.

[0069] If B(2) = 1, switch S1 is connected to VREF, and the voltage at the inverting input of the comparator is obtained.

[0070]

[0071] At this time V in(1) and In comparison, if Then B(1) = AMP = 0; if Then B(1) = AMP = 1.

[0072] After completing steps a, b, and c above, the input voltage V on the first channel can be obtained. in(1) The corresponding numerical code is B[3:1]. Next, according to... Figure 5 Switches S1, S2 and S L Connected to common-mode voltage V cm Disconnect S M(1) and S M(2) Connect the inverting input of the comparator to begin the conversion on the second channel. Repeat steps a, b, and c to obtain the analog-to-digital conversion result on the second channel.

[0073] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention, and is not intended to limit the concept and scope of the invention. Any equivalent substitutions, modifications, and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the inventive concept should be considered within the scope of protection of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims

1. A capacitor array for a multi-channel SAR ADC, characterized in that: The capacitor array includes K most significant bit capacitors. N-1 low-level capacitors The sample-and-hold circuit, control switch, and comparator are provided, where K represents the number of channels, N represents the number of bits in the ADC, the most significant bit capacitor participates in the sampling and charge redistribution process, and the least significant bit capacitor does not participate in the sampling process. The sample-and-hold circuit employs a gate voltage bootstrap sampling switch to facilitate sampling of the input signal and charge retention. The control switch is composed of MOSFETs and is used to control the input level or signal of each corresponding capacitor plate. The comparator is used to compare the output value of the capacitor array with the common-mode voltage. The value of VREF is calculated and the comparison result is output, where VREF is the reference voltage value. The capacitor array switch switching: During the sampling phase, the K most significant bit capacitors are controlled by a switch. For the input voltage on the corresponding channel After synchronous sampling is performed, the process enters the hold phase, and then the highest bit capacitor is switched off via a switching action. Each signal is connected to a comparator and a low-order capacitor array for charge redistribution, and the conversion results of the input signals on the corresponding channels are obtained sequentially. The highest bit capacitor The upper electrode plate is controlled by a switch. Select Link The lower plate of the voltage or comparator is controlled by a switch. Decision to connect Potential or corresponding input signal ; low-position capacitor ,in The upper plates of each capacitor are connected together by a switch. The control determines whether the capacitor is connected to the inverting input of the comparator; the lower plate of each capacitor is controlled by the corresponding control switch. Decide to connect or Or grounded.

2. The capacitor array of the multi-channel SAR ADC according to claim 1, characterized in that: The value of the nth capacitor in the capacitor array is equal to twice the value of the (n-1)th capacitor. <n<N。 3. The capacitor array of the multi-channel SAR ADC according to claim 1, characterized in that: The non-inverting input of the comparator is constantly connected to... Potential.

4. The capacitor array of the multi-channel SAR ADC according to claim 1, characterized in that, The steps for switching the capacitor array switch are as follows: 1) Sampling stage The upper plates of the K highest-order capacitors are connected by a switch. All connected to common-mode voltage The lower electrode plate is controlled by a switch. Connect to the corresponding input voltage respectively Low-level capacitors The upper electrode plate is controlled by a switch Control connected to common mode voltage The lower electrode plate is controlled by a switch. Connected to common mode voltage The non-inverting input of the comparator is connected to ; 2) Maintenance phase The highest bit capacitance of all channels The upper electrode is disconnected, and the lower electrode is switched off. Following Potential; 3) Charge redistribution stage The charge of the highest-order capacitors on channels 1 through K is redistributed sequentially, starting with the conversion of the input signal on the first channel. The process is as follows: A1. Determine the most significant bit B(N): Set the most significant bit capacitor... The upper plate is connected to the inverting input of the comparator, and the highest bit capacitor on the other channels... The connected switch is not working, low-level capacitor The upper electrode plate is controlled by a switch. Connected to the inverting input of the comparator, the lower plate remains connected to the common-mode voltage. At this time, the non-inverting input of the comparator is... With the voltage connected, the first conversion result B(N) can be obtained directly from the comparator output; A2. Determine the second highest bit B(N-1): If B(N) = 1, then set the second highest bit capacitor... The lower electrode plate is controlled by a switch. Ground to GND; if B(N) = 0, then the second highest capacitor... The lower electrode plate is controlled by a switch. Connect to reference voltage VREF, switch After the action and charge redistribution are completed, the comparator outputs the conversion result B(N-1) in the second bit. A3. Determine the conversion result B(N+1-j) for the j-th bit, where 3≤j≤N: If B(N+2-j) = 1, then change the capacitance of the j-th bit. The lower electrode plate is controlled by a switch. Ground GND; if B(N+2-j) = 0, then the j-th capacitor... The lower electrode plate is controlled by a switch. Connect to reference voltage VREF, switch After the action and charge redistribution are completed, the comparator outputs the conversion result B(N+1-j) of the j-th bit; After all capacitors have completed charge redistribution, an N-bit binary code B[N:1] is obtained, and the analog-to-digital conversion on the first channel is complete; next, the highest bit of the capacitor in the second channel is converted. Connect the comparator and repeat steps A1~A3 to obtain the second channel input signal. The conversion results are obtained by repeating steps A1 to A3 K times, and finally the conversion results of K channels are obtained.

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