Communication device and semiconductor device

Abstract

Embodiments of the present invention relate to communication devices and semiconductor devices. According to this embodiment, a main pulse signal generation circuit generates a first main pulse signal corresponding to a rising logical signal and a second main pulse signal corresponding to a falling logical signal. A sub-pulse signal generation circuit performs at least one of a first generation process and a second generation process. In the first generation process, a first sub-pulse signal corresponding to the first main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the first main pulse signal was generated. In the second generation process, a second sub-pulse signal corresponding to the second main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the second main pulse signal was generated. An output circuit outputs at least one of the first main pulse signal, the second main pulse signal, the first sub-pulse signal, and the second sub-pulse signal. The output circuit also stops the output of at least one of the first sub-pulse signal and the second sub-pulse signal.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-34687 (filed on March 7, 2022). This application incorporates the entire contents of this base application by reference. Technical Field

[0003] Embodiments of the present invention relate to communication devices and semiconductor devices. Background Technology

[0004] Communication devices that transmit signals via AC coupling elements are commonly known. However, the receiving circuit of such communication devices may malfunction due to signal noise or other reasons. Summary of the Invention

[0005] The present invention provides a communication device and a semiconductor device capable of suppressing malfunctions.

[0006] According to this embodiment, the communication device includes a transmitting circuit. The transmitting circuit includes an encoder. The encoder includes a main pulse signal generation circuit, a sub-pulse signal generation circuit, and an output circuit. The main pulse signal generation circuit generates a first main pulse signal corresponding to a rising logical signal and a second main pulse signal corresponding to a falling logical signal. The sub-pulse signal generation circuit performs at least one of a first generation process and a second generation process. In the first generation process, a first sub-pulse signal corresponding to the first main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the first main pulse signal was generated. In the second generation process, a second sub-pulse signal corresponding to the second main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the second main pulse signal was generated. The output circuit stops the output of at least one of the first sub-pulse signal and the second sub-pulse signal. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a structural example of a communication device.

[0008] Figure 2 It is a diagram that schematically represents the signals output by each circuit.

[0009] Figure 3 This is a block diagram representing an example of the encoder's structure.

[0010] Figure 4 This is a diagram illustrating an example of the structure of the main pulse signal generation circuit.

[0011] Figure 5 This is a diagram showing an example of the output signal of the main pulse signal generation circuit.

[0012] Figure 6 This is a diagram illustrating an example of the structure of a sub-pulse signal generation circuit.

[0013] Figure 7A This is a diagram showing an example of the output signal of the sub-pulse signal generation circuit.

[0014] Figure 7B This is a diagram illustrating an example of the generation of the main pulse signal and the sub-pulse signal.

[0015] Figure 8A This is a diagram illustrating an example of the structure of a switching signal generation circuit.

[0016] Figure 8B This is a diagram showing an example of the output signal of the switching signal generation circuit.

[0017] Figure 9 This is a diagram illustrating an example of signal switching in the encoder's selection circuit.

[0018] Figure 10 This is a schematic diagram illustrating the structure of a comparative example without a selection circuit.

[0019] Figure 11 This is a diagram illustrating an example of action when the input signal rises.

[0020] Figure 12 This is a diagram illustrating an example of operation when the input signal rises during the generation of the sub-pulse signal.

[0021] Figure 13 This is a diagram illustrating an example of the decoder's structure.

[0022] Figure 14 This is a diagram illustrating the decoder's operation when a third master pulse signal is input.

[0023] Figure 15 This diagram illustrates the decoder's operation when the fourth master pulse signal is input. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, the description will focus on the characteristic structures and operations of communication devices and semiconductor devices, but structures and operations omitted in the following description may also exist in communication devices and semiconductor devices.

[0025] (First Implementation)

[0026] use Figure 1 and Figure 2 The structure of communication device 1 will be described as an example. Figure 1 This is a block diagram illustrating an example of the structure of communication device 1. For example... Figure 1As shown, communication device 1 is, for example, a digital isolator, which is a device for transmitting digital logic signals in a state of electrical isolation between the transmitting and receiving sides. This digital isolator is a semiconductor device that can be formed using highly versatile semiconductor processes such as CMOS technology.

[0027] The communication device 1, for example, includes a primary-side transmitting circuit (TX) 10 and a secondary-side receiving circuit (RX) 20, both galvanically isolated. Specifically, the communication device 1 includes an input buffer 102, an encoder 104, a converter 106, an AC coupling element 108, an amplifier (AMP) 110, multiple comparators 112a, b, a decoder 114, a range shifter 116, and an output buffer 118. Furthermore, Figure 1 The middle diagram shows the signal input terminal VIx and the input signal Svix, and the signal output terminal VOx and the output signal Svox.

[0028] Figure 2 This is a schematic diagram illustrating the signals output by each circuit. The vertical axis represents the signal level, and the horizontal axis represents time. Signals Svix, Sp1, Sn1, Spi1, Sni1, Dpi02, Dni02, Dpi2, Dni2, Sp2, Sn2, Svo0, and Svox are... Figure 1 The signals correspond to each other. Signals Svix, Sp1, Sn1, Dpi2, Dni2, Sp2, Sn2, Svo0, and Svox are voltage signals, while signals Spi1, Sni1, Dpi02, and Dni02 are current signals.

[0029] The signal Svix is, for example, a square wave logic signal, input to the input terminal VIx (see reference). Figure 1 H transmission represents the transmission example of the main signal when the signal Svix changes from low to high, and L transmission represents the transmission example of the main signal when the signal Svix changes from high to low. That is, it shows the case where the signal Svix changes in a time sequence as signals Sp1, Sn1, Spi1, Sni1, Dpi02, Dni02, Dpi2, Dni2, Sp2, Sn2, Svo0, and Svox. For example, the labels p and P represent the positive side as the first pole side, and the labels n and N represent the second pole side, i.e., the negative side, which is different from the first pole side.

[0030] More specifically, the signal Svix is ​​input from the signal input terminal VIx to the input buffer 102. The signal Svix consists, for example, a 5-volt high-level signal and, for example, a 0-volt low-level signal. In the signal Svix, the 5-volt high-level signal corresponds to "1", and the 0-volt low-level signal corresponds to "0". Thus, in this embodiment, the high-level signal corresponds to "1", and the low-level signal corresponds to "0".

[0031] While maintaining the shape of the rectangular wave, the input buffer 102 outputs the rectangular wave input signal Svix to the encoder 104. The encoder 104 generates pulse signals Sp1 and Sn1 based on the rectangular wave input signal Svix. The encoder 104 generates a first combination of predetermined pulse signals, namely the first main pulse signals SHp1 and SHn2, as the main signals based on the rising edge of the rectangular wave's logic signal. For example, the encoder 104 generates the main pulse signal SHp1 before the main pulse signal SHn2, relative to the rising edge of the rectangular wave's logic signal.

[0032] On the other hand, encoder 104 generates second main pulse signals SLn1 and SLp2, which are the main signals and are defined pulse signals, based on the descent of the logic signal of the rectangular wave. For example, encoder 104 generates the main pulse signal before the main pulse signal SLp2 in response to the descent of the logic signal of the rectangular wave.

[0033] Thus, the rising edge of the logic signal of the encoder 104 relative to the rectangular wave causes the pulse signal Sp1 on the p-side (positive side) to go high before the pulse signal Sn1 on the n-side (negative side). Conversely, the falling edge of the logic signal of the encoder 104 relative to the rectangular wave causes the pulse signal Sn1 on the n-side to go high before the pulse signal Sp1 on the p-side. Furthermore, the specified combination of pulse signals is only required to differ between the rising and falling edges of the logic signal of the rectangular wave, and is not limited to two pulse signals. For example, it could also be a one-pulse signal, a three-pulse signal, a four-pulse signal, etc.

[0034] In addition to generating the main pulse signals SHp1, SHn2, SLp1, and SLp2, encoder 104 also generates a first sub-pulse signal Shp1, Shn2 or a second sub-pulse signal Ssn1, Slp2 (not shown) for refreshing decoder 114. Encoder 104 outputs the generated pulse signals to converter 106. Details of encoder 104 will be described later. In this embodiment, the first main pulse signals SHp1, SHn2 and the first sub-pulse signals Shp1, Shn2 are described with the same shape, and the second main pulse signals SLn1, SLp2 and the second sub-pulse signals Ssn1, Slp2 are described with the same shape, but this is not a limitation. The first sub-pulse signals Shp1, Shn2 or the second sub-pulse signals Sln1, Slp2 are generated for what is called refresh processing of decoder 114, described later.

[0035] The converter 106 converts the voltage pulse signals Sp1 and Sn1 into current pulse signals Spi1 and Sni1, and outputs them to the AC coupling element 108. The AC coupling element 108 transmits the signal generated by the encoder 104 to the decoder 114. This AC coupling element is an insulated miniature transformer, for example, transmitting the differential waves Dpi02 and Dni corresponding to the pulse signals Spi1 and Sni1 to the secondary receiving circuit 20 while ensuring galvanic insulation. The AC coupling element 108 outputs the differential waves Dpi02 and Dni02 to the amplifier 110. Furthermore, the AC coupling element 108 in this embodiment is an insulated miniature transformer, but it is not limited to this. For example, the AC coupling element 108 could also be a galvanic-insulated miniature capacitor.

[0036] Amplifier 110 amplifies the differential waves Dpi02 and Dni02, and outputs the amplified differential waves Dpi2 and Dni to multiple comparators 112a and b, respectively. That is, signals Dpi2 and Dni2 are amplified 3-wave differential signals.

[0037] Comparators 112a and 112b output pulse signals Sp2 and Sn2, which have been pulse-shaped from the differential waves Dpi2 and Dni, respectively, to decoder 114. More specifically, comparators 112a and 112b generate third main pulse signals SHap1, SHan2, and SHap2, corresponding to the first main pulse signals SHp1 and SHn2, through pulse shaping. Similarly, comparators 112a and 112b generate fourth main pulse signals SLan1, SLap2, and SLan2, corresponding to the second main pulse signals SLn1 and SLp2, through pulse shaping.

[0038] Furthermore, comparators 112a and 112b generate third sub-pulse signals Shap1, Shan2, and Shap2 corresponding to the first sub-pulse signals Shp1 and Shn2 through pulse signal shaping. Similarly, fourth sub-pulse signals Sn1, Slap2, and Sla2 corresponding to the second sub-pulse signals Sln1 and Slp2 are generated through pulse signal shaping. Decoder 114 decodes the rectangular wave logic signal Svox0 based on pulse signals Sp2 and Sn2. That is, the third sub-pulse signals Shap1, Shan2, and Shap2 are pulse signals equivalent to the third main pulse signals SHap1, Shan2, and SHap2. Similarly, the fourth sub-pulse signals Slap1, Slap2, and Slan2 are pulse signals equivalent to the fourth main pulse signals SLan1, SLap2, and SLan2. In addition, in this embodiment, the third sub-pulse signals Shap1, Shan2, and Shap2 and the third main pulse signals SHap1, Shan2, and SHap2 are set as equivalent pulse signals, but it is not limited to this. Similarly, the fourth sub-pulse signals Slap1, Slap2 and Slan2 have the same pulse signals as the fourth main pulse signals SLan1, SLap2 and SLan2, but are not limited to this.

[0039] Decoder 114 outputs the rectangular wave logic signal Svox0 to range shifter 116. Furthermore, decoder 114 maintains a high output value for the third main pulse signals SHap1, SHan2, SHap2 and the third auxiliary pulse signals Shap1, Shan2, Shap2 corresponding to the rising edge of the rectangular wave logic signal. Therefore, even if the third auxiliary pulse signals Shap1, Shan2, and Shap2 corresponding to the rising edge are input multiple times, a high-level signal output is maintained.

[0040] On the other hand, the decoder 114 maintains the output value at a low level for the fourth main pulse signals SLan1, SLap2, SLan2 and the fourth sub-pulse signals Slan1, Slap2, SLD2 corresponding to the falling logic signals of the rectangular wave. Therefore, even if the fourth sub-pulse signals Slan1, Slap2, Slan2 corresponding to the falling signals are input multiple times, the output of the signal remains at a low level.

[0041] For example, a third sub-pulse signal Shap1, Shan2, and Shap2 are inserted between the first main pulse signals SHp1 and SHn2 corresponding to the rising phase of the rectangular wave input signal Svix and the second main pulse signals SLn1 and SLp2 corresponding to the falling phase. In this case, even with the insertion of the third sub-pulse signals Shap1, Shan2, and Shap2, the shape of the rectangular wave logic signal Svox0 remains unchanged and remains at a high level until the second main pulse signals SLn1 and SLp2 are input.

[0042] Similarly, a fourth sub-pulse signal Slan1, Slap2, Slan2 is inserted between the second main pulse signals SLn1, SLp2 corresponding to the falling pulse and the first main pulse signals SHp1, SHn2 corresponding to the rising pulse. In this case, even with the insertion of the fourth sub-pulse signals Slan1, Slap2, Slen2, the shape of the rectangular wave logic signal Svox0 remains unchanged and remains at a low level until the first main pulse signals SHp1, SHn2 are input.

[0043] Decoder 114, for example, has a flip-flop that sets a predetermined value whenever the third main pulse signal SHap1, SHAN2, SHap2, the third sub-pulse signal Shap1, Shan2, Shap2, the fourth main pulse signal SLan1, SLap2, SLan2, or the fourth sub-pulse signal Slan1, Slap2, SLan2 is input. That is, when the third sub-pulse signal Shap1, Shan2, Shap2 or the fourth sub-pulse signal Slan1, Slap2, SLan2 is inserted, decoder 114 sets the predetermined value of the flip-flop according to the sub-pulse signal. In this case, even if the predetermined value is set for the flip-flop, decoder 114 maintains a high-level output value when the third main pulse signal SHap1, SHAN2, SHap2, SHap2 is input, until the fourth main pulse signal SLan1, SLap2, SLan2 is input. Similarly, even if the trigger is set to a specified value, the decoder 114 maintains a low output value when the fourth main pulse signal SLan1, SLap2, SLan2 is input, until the third main pulse signal SHap1, SHan2, SHap2 is input.

[0044] In this way, the decoder 114 repeatedly performs the action of setting the flip-flop to a predetermined value using the third sub-pulse signals Shap1, Shap2, Shap2, or the fourth sub-pulse signals Slan1, Slap2, Slan2, repeatedly performing the so-called refresh process. Therefore, for example, even if the output value of the flip-flop is reversed due to signal noise, it is corrected to the correct output value. For details on the decoder 114, please refer to the usage... Figures 13 to 15 Described later.

[0045] Range shifter 116 switches the logic signal Svox0, for example, from 5 volts to 30 volts, and outputs it as the logic signal Svox to output buffer 118. Output buffer 118 outputs the logic signal Svox from terminal VOx while maintaining the output waveform of the logic signal Svox.

[0046] Figure 3This is a block diagram showing an example of the structure of encoder 104. Encoder 104 includes a main pulse signal generation circuit 200, a secondary pulse signal generation circuit 202, a switching signal generation circuit 204, and a selection circuit 206.

[0047] The main pulse signal generation circuit 200 generates first main pulse signals SHp1 and SHn2 corresponding to the rising edge of the rectangular wave input signal Svix, and second main pulse signals SLn1 and SLp2 corresponding to the falling edge of the rectangular wave input signal Svix. That is, the main pulse signal generation circuit 200 includes a delay circuit 208 and a first pulse signal generation circuit 210. Further details of the main pulse signal generation circuit 200 will be described later.

[0048] The secondary pulse signal generation circuit 202 generates first secondary pulse signals Shp1 and Shn2 corresponding to the first main pulse signals SHp1 and SHn2 between the first main pulse signals SHp1 and SHn2 and the second main pulse signals SLn1 and SLp2. Additionally, the secondary pulse signal generation circuit 202 generates second secondary pulse signals Sln1 and Slp2 corresponding to the second main pulse signals SLp1 and SLp2 between the second main pulse signals SLp1 and SLp2 and the first main pulse signals SHp1 and SHn2.

[0049] More specifically, if the sub-pulse signal generation circuit 202 detects an increase in the input signal Svix, it repeatedly generates first sub-pulse signals Shp1 and Shn2 at predetermined intervals after a predetermined time. Conversely, if the sub-pulse signal generation circuit 202 detects a decrease in the input signal Svix, it repeatedly generates second sub-pulse signals Sln1 and Slp2 at predetermined intervals after a predetermined time. This sub-pulse signal generation circuit 202 includes an edge detection circuit 212, a refresh timer 214, and a second pulse signal generation circuit 216. Further details of the sub-pulse signal generation circuit 202 will be described later.

[0050] If the switching signal generation circuit 204 detects a rise or fall in the input signal Svix, it outputs, for example, a high-level switching signal select_pulse_sig during the period corresponding to the main pulse selection period. Conversely, if the switching signal generation circuit 204 uses the period other than the main pulse selection period as the sub-pulse signal selection period, it outputs the switching signal select_pulse_sig as a low-level signal. Details of the switching signal generation circuit 204 will be described later.

[0051] The selection circuit 206, for example, is a multiplexer. If a high-level input signal is used as the switching signal select_pulse_sig, it selects and outputs the output signal of the main pulse signal generation circuit 200. Conversely, if a low-level input signal is used as the switching signal select_pulse_sig, it selects and outputs the output signal of the secondary pulse signal generation circuit 202. Thus, the selection circuit 206 outputs the secondary pulse signal and stops the output of the main pulse signal when the switching signal select_pulse_sig is low. Conversely, the selection circuit 206 outputs the main pulse signal and stops the output of the secondary pulse signal when the switching signal select_pulse_sig is high. In this embodiment, the selection circuit 206 corresponds to the output circuit.

[0052] Here, use Figures 4 to 8B The encoder 104 is described in detail. Figure 4 This is a diagram illustrating a structural example of a main pulse signal generation circuit 200. The main pulse signal generation circuit 200 includes a delay circuit 208 and a first pulse signal generation circuit 210. The first pulse signal generation circuit 210 includes multiple delay circuits 210a and 210b and multiple logic circuits 210c and e.

[0053] Figure 5 This diagram illustrates an example of the output signal from the main pulse signal generation circuit 200. From top to bottom, it shows the input signal Svix, the output signal wait_dt_sig from the delay circuit 208, the delayed signal wait_dt_sig_d1T generated by the delay circuit 210a of the first pulse signal generation circuit 210, the delayed signal wait_dt_sig_d2T generated by the delay circuit 210b, and the pulse signals Sp1 and Sn1. Additionally, it shows the switching signal select_pulse_sig generated by the switching signal generation circuit 204. The vertical axis represents the signal level, and the horizontal axis represents time. As mentioned above, a high-level signal corresponds to 1, and a low-level signal corresponds to 0.

[0054] The delay circuit 208 is configured, for example, by connecting multiple buffers in series. The delay circuit 208 outputs a wait_dt_sig signal, which is the output signal delayed by the input signal Svix according to a delay time Tx_wait. This delay time Tx_wait is set according to the signal form of the differential signals Dpi2 and Dni2. For example, a signal level below a specified absolute value of the differential signals Dpi2 and Dni2 is called a trailing signal. The delay time Tx_wait is set, for example, according to the length of the trailing signal. For example, if the first main pulse signals SHp1 and SHn2 and the second main pulse signals SLn1 and SLp2 are generated consecutively, the trailing signals overlap, and the pulse signals Sp2 and Sn2 generated by comparators 112a and b are distorted. Therefore, the delay time Tx_wait is set, for example, in a way that the trailing signals do not overlap.

[0055] Delay circuit 210a generates a delayed signal wait_dt_sig_D1T that delays the output signal wait_dt_sig by 1T. Delay circuit 210b generates a delayed signal wait_dt_sig_d2T that further delays the delayed signal wait_dt_sig_d1T by 1T.

[0056] The logic circuit 210c performs logic operations according to equation (1).

[0057] Sp1=(wait_dt_sig&~wait_dt_sig_d1T)|(~wait_dt_sig_d1T&wait_dt_sig_d2T) (1)

[0058] That is, when the output signal wait_dt_sig is high and the delay signal wait_dt_sig_d1T is low, the logic circuit 210c outputs the pulse signal Sp1 as a high-level signal. Specifically, the main pulse signal SHP1 is a high-level signal with a time width of 1T starting from the rise of the input signal Svix after a delay time Tx_wait.

[0059] Furthermore, when the delay signal wait_dt_sig_d1T is low and the delay signal wait_dt_sig_d2T is high, the logic circuit 210c outputs the pulse signal Sp1 as a high-level signal. That is, the main pulse signal SLp2 is a high-level signal with a time width of 1T starting from the moment when the input signal Svix falls after the delay time Tx_wait and 1T.

[0060] The logic circuit 210e performs logic operations according to equation (2).

[0061] Sn1=(wait_dt_sig_d1T&~wait_dt_sig_d2T)|(~wait_dt_sig&wait_dt_sig_d1T) (2)

[0062] That is, when the delay signal wait_dt_sig_d1T is high and the delay signal wait_dt_sig_D2T is low, the logic circuit 210e outputs the pulse signal Sn1 as a high level. In other words, the main pulse signal SHn2 is a high-level signal with a time width of 1T starting from the rise of the input signal Svix after the delay time Tx_wait and 1T.

[0063] Furthermore, when the output signal wait_dt_sig is low and the delay signal wait_dt_sig_d1T is high, the logic circuit 210e outputs the pulse signal Sn1 as a high-level signal. That is, the main pulse signal SLn1 is a high-level signal with a time width of 1T starting from the moment when the falling input signal Svix has passed the delay time Tx_wait.

[0064] Thus, the first pulse signal generation circuit 210 generates the first main pulse signals SHp1 and SHn2 starting from the moment the input signal Svix rises after a delay time Tx_wait. Additionally, the first pulse signal generation circuit 210 generates the second main pulse signals SLn1 and SLp2 starting from the moment the input signal Svix falls after a delay time Tx_wait.

[0065] Figure 6 This diagram illustrates a structural example of the sub-pulse signal generation circuit 202. As described above, the sub-pulse signal generation circuit 202 includes an edge detection circuit 212, a refresh timer 214, and a second pulse signal generation circuit 216. The edge detection circuit 212 includes, for example, a delay circuit 212a and an XOR circuit 212b. The second pulse signal generation circuit 216 includes multiple delay circuits 216a and 216b and multiple logic circuits 216c and e.

[0066] Figure 7A This diagram illustrates an example of the output signal from the sub-pulse signal generation circuit 202. From top to bottom, it shows the input signal Svix, the generated signal Srefresh_timer within the refresh timer 214, the generated pulse signal timeout_refresh from the refresh timer 214, the delayed signal timeout_refresh_D1T generated by the delay circuit 216a, the delayed signal timeout_refresh_D2T generated by the delay circuit 216b, and the pulse signals Sp1 and Sn1. As described above, a high-level signal corresponds to 1, and a low-level signal corresponds to 0.

[0067] like Figure 6 As shown, the XOR circuit 212b outputs 1 when the input signal is a combination of 1, 0, or 0, 1. That is, the edge detection circuit 212 outputs a high-level signal, i.e., 1, at the moment when the value of the input signal Svix is ​​different from the value of the output signal of the delay circuit 212a, i.e., the moment when the signal corresponding to the edge is input.

[0068] The refresh timer 214, for example, has an internal capacitor. Starting from the moment a high-level signal is input to the edge detection circuit 212, the capacitor is repeatedly charged and discharged, thereby internally generating a signal Srefresh_timer. Then, when the signal Srefresh_timer exceeds a predetermined threshold Svref, the refresh timer 214 outputs a pulse signal timeout_refresh with a time width of 2T. Thus, the refresh timer 214 repeatedly outputs the pulse signal timeout_refresh at predetermined time intervals (Trefresh+2T) starting from the moment a high-level signal is input to the edge detection circuit 212. However, when the edge detection circuit 212 detects the next edge, the refresh timer 214 internally generates a new signal Srefresh_timer. That is, when the edge detection circuit 212 detects the next edge, the refresh timer 214 refreshes the capacitor, and the charging and discharging of the capacitor is repeated again.

[0069] Delay circuit 216a generates a delayed signal timeout_refresh_D1T that delays the pulse signal timeout_refresh by 1T. Delay circuit 216b generates a delayed signal timeout_refresh_D2T that delays the delayed signal timeout_refresh_D1T by 1T.

[0070] The logic circuit 216c performs logic operations according to equation (3).

[0071] Sp1=(~timeout_refresh&timeout_refresh_D1T&Svix)|(~timeout_refresh_D1T&timeout_refresh_D2T&~Svix) (3)

[0072] That is, when the pulse signal timeout_refresh is low, the delay signal timeout_refresh_D1T is high, and the input signal Svix is ​​high, the logic circuit 216c outputs the pulse signal Sp1 as a high-level signal. In other words, the sub-pulse signal Shp1 is a high-level signal with a time width of 1T starting from the rise of the input signal Svix after the delay time Trefresh and 2T.

[0073] Furthermore, when the delay signal timeout_refresh_D1T is low, the delay signal timeout_refresh_D2T is high, and the input signal Svix is ​​low, the logic circuit 216c outputs the pulse signal Sp1 as a high-level signal. That is, the sub-pulse signal Slp2 is a high-level signal with a time width of 1T starting from the moment when the falling input signal Svix passes through the delay time Trefresh and 3T.

[0074] The logic circuit 216e performs logic operations according to equation (4).

[0075] Sn1=(~timeout_refresh&timeout_refresh_D1T&~Svix)|(~timeout_refresh_D1T&timeout_refresh_D2T&Svix) (4)

[0076] That is, when the delay signal timeout_refresh_D1T is low, the delay signal timeout_refresh_D2T is high, and the input signal Svix is ​​high, the logic circuit 216e outputs the pulse signal Sn1 as a high-level signal. In other words, the secondary pulse signal Shn2 is a high-level signal with a time width of 1T starting from the rise of the input signal Svix after the delay time Trefresh and 3T have elapsed.

[0077] Furthermore, when the pulse signal timeout_refresh is low, the delay signal timeout_refresh_D1T is high, and the input signal Svix is ​​low, the logic circuit 216e outputs the pulse signal Sn1 as a high-level signal. That is, the sub-pulse signal Sln1 is a high-level signal with a time width of 1T starting from the moment when the falling input signal Svix passes through the delay time Trefresh and 2T.

[0078] Thus, the sub-pulse signal generation circuit 202 repeatedly and alternately generates the first sub-pulse signals Shp1 and Shn2 starting from the rise of the input signal Svix after the delay time Trefresh and 2T. Meanwhile, the first pulse signal generation circuit 210 repeatedly and alternately generates the second main pulse signals Sln1 and Slp2 starting from the fall of the input signal Svix after the delay time Trefresh and 2T.

[0079] Figure 7B This diagram illustrates an example of the generation of the main pulse signal and the sub-pulse signal. From top to bottom, it shows the input signal Svix, pulse signals Sp1 and Sn1, the threshold voltage Svref within the refresh timer 214, the internal signal Srefresh_Timer, and the output signal Swox. The vertical axis represents signal level, and the horizontal axis represents time. The first sub-pulse signal is repeatedly generated after the first main pulse signal. Similarly, the second sub-pulse signal is repeatedly generated after the second main pulse signal. The output signal Swox has a delay time TX_wait and a delay of 2T, and has a high-level signal for the same duration as the input signal Svix.

[0080] Here, use Figure 8A as well as Figure 8B The structure of the switching signal generation circuit 204 will be described in an example. Figure 8A This is a diagram illustrating an example of the structure of the switching signal generation circuit 204. (See diagram for example.) Figure 8A As shown, the switching signal generation circuit 204 has delay circuits 208 and 204a and an ExOR circuit (all-different circuit) 204b. Figure 8B This diagram illustrates an example of the output signal from the switching signal generation circuit 204. From top to bottom, it shows the input signal Svix, the delayed signals from delay circuits 208 and 204a, and the switching signal select_pulse_sig output from the ExOR circuit (all-differential circuit) 204b. The horizontal axis represents time. As mentioned above, a high-level signal corresponds to 1, and a low-level signal corresponds to 0.

[0081] like Figure 8B As shown, delay circuit 208 delays the input signal Svix by Tx_Wait, and then delay circuit 204a delays the input signal Svix by 2T, outputting it to ExOR circuit (all-different circuit) 204b. ExOR circuit (all-different circuit) 204b generates a switching signal select_pulse_sig with a pulse width of Tx_Wait+2T.

[0082] That is, the switching signal generation circuit 204 performs the logical operation according to equation (5).

[0083] select_pulse_sig=(Svix&~wait_dt_sig_d2T)|(~Svix&wait_dt_sig_d2T) (5)

[0084] Thus, when the input signal Svix is ​​high and the delay signal wait_dt_sig_d2T is low, the switching signal generation circuit 204 outputs the selection signal select_pulse_sig as a high level. When the input signal Svix is ​​low and the delay signal wait_dt_sig_d2T is high, the logic circuit 204b outputs the selection signal select_pulse_sig as a high level. That is, the selection signal select_pulse_sig is a high-level signal with a rise time width of (Tx_wait+2T) from the rise or fall of the input signal Svix.

[0085] Figure 9 This diagram illustrates an example of signal switching in the selection circuit 206 of encoder 104. From top to bottom, it shows the input signal Svix, pulse signals Sp1 and Sn1 for case 1 (CASE-1), pulse signals Sp1 and Sn1 for case 2 (CASE-2), pulse signals Sp1 and Sn1 for case 3 (CASE-3), and the selection signal select_pulse_sig. The horizontal axis represents time, and the vertical axis represents signal level.

[0086] Scenario 1 is in Figure 7A Case 1 shows a decrease in the input signal Svix at the end of each of the recorded first sub-pulse signals Shp1 and Shn2. Case 2 shows a decrease in the input signal Svix midway through the generation of the first sub-pulse signals Shp1 and Shn2. Case 3 shows a decrease in the input signal Svix just before the first sub-pulse signals Shp1 and Shn2 are about to occur.

[0087] like Figure 9 As shown, in this embodiment, if the selection signal select_pulse_sig becomes high, the selection circuit 206 stops the output of the sub-pulse signal generation circuit 202. Therefore, by stopping the output of the sub-pulse signal generation circuit 202 during or before the generation of the first sub-pulse signals Shp1 and Shn2 as in cases 2 and 3, the influence of the first sub-pulse signals Shp1 and Shn2 can be suppressed. In other words, the pulse signal generation circuit 200 can generate the second main pulse signals SLn1 and SLp2 immediately after a delay time TX_Wait from the moment the rise and fall of the input signal Svix occur (see reference). Figure 5Thus, in the communication device 1 of this embodiment, the timing of the rise and fall of the input signal Svix is ​​unclear before the actual rise and fall of the input signal Svix occurs, but the pulse signal generation circuit 200 can generate the second main pulse signals SLn1 and SLp2 without being affected by the first sub-pulse signals Shp1 and Shn2. Similarly, the main pulse signal generation circuit 200 can generate the first main pulse signals SHp1 and SHn2 without being affected by the second sub-pulse signals Sln1 and Slp2.

[0088] Figure 10 This diagram schematically illustrates the structure of a comparative example without the selection circuit 206. In the comparative example, the selection circuit 206 is not present. Therefore, during the generation of a sub-pulse signal at the moment when the rise and fall of the input signal Svix occur, in order to suppress the interference between the sub-pulse signal and the main pulse signal, the main pulse signal is generated after TX_Wait from the moment the sub-pulse signal ends.

[0089] Figure 11 This diagram illustrates an example of operation when the input signal Svix rises. From top to bottom, it shows the input signal Svix, the pulse signals Sp1 and Sn1 of the comparative example, and the pulse signals Sp1 and Sn1 of the communication device 1 according to this application. The horizontal axis represents time, and the vertical axis represents the signal level. Since it is the case where the input signal Svix rises, the second pulse signals Sln1 and Slp2 are repeatedly generated.

[0090] like Figure 11 As shown, when the input signal Svix rises after the second auxiliary pulse signals Sln1 and Slp2 are generated, neither the comparative example nor the present application is affected by the second auxiliary pulse signals Sln1 and Slp2. That is, in either the comparative example or the present application, the first main pulse signals SHp1 and SHn2 can be generated immediately after the TX_Wait period from the timing of the rise of the input signal Svix.

[0091] on the other hand, Figure 12 This diagram illustrates an example of operation when the input signal Svix rises during the generation of the second sub-pulse signals Sn1 and Slp2. From top to bottom, it shows the input signal Svix, the pulse signals Sp1 and Sn1 of the comparative example, and the pulse signals Sp1 and Sn1 of the communication device 1 according to this application. The horizontal axis represents time, and the vertical axis represents the signal level.

[0092] like Figure 12As shown, when the input signal Svix rises during the generation of the second sub-pulse signals Sln1 and Slp2, in the comparative example, the second sub-pulse signals Sln1 and Slp2 are included during the TX_Wait period. Consequently, interference occurs between the second sub-pulse signals Sln1 and Slp2 and the first main pulse signals SHp1 and SHn2 in the decoder 114. Therefore, in the comparative example, even after the generation of the second sub-pulse signals Sln1 and Slp2 ends, reception is still required during the TX_Wait period, resulting in a communication delay. In contrast, in the communication device 1 according to this application, since the output of the second sub-pulse signals Sln1 and Slp2 is stopped, the generation of the first main pulse signals SHp1 and SHn2 can be performed without waiting for the generation of the second sub-pulse signals Sln1 and Slp2 to end.

[0093] Here, use Figures 13 to 15 The structure of decoder 114 will be explained. Figure 13 This is a diagram illustrating an example of the structure of decoder 114. Decoder 114 includes a decoding circuit 40, a signal holding circuit 50, multiple detection circuits 60 and 70, and a reset circuit 80. Figure 13 The diagram also shows the terminals INP, INN, and DEC_OUT.

[0094] When the decoding circuit 40 receives any one of the third main pulse signals SHap1, SHAN2, SHap2, or the third sub-pulse signals Shap1, Shan2, and Shap2, it outputs a first signal pair (set = 1, reset = 0) as the specified signal. Additionally, when the decoding circuit 40 receives any one of the fourth main pulse signals SLan1, SLap2, SLan2, or the fourth sub-pulse signals Slan1, Slap2, and Slan2, it outputs a second signal pair (set = 0, reset = 1) as the specified signal.

[0095] The signal holding circuit 50 is, for example, an RS flip-flop circuit that functions as a sequential circuit. The signal holding circuit 50 outputs a high-level signal (1) for example, during the first signal pair (set = 1, reset = 0), and a low-level signal (0) for example, during the second signal pair (set = 0, reset = 1). Furthermore, it holds the signal value for example, during the third signal pair (set = 0, reset = 0).

[0096] The detection circuit (DECODE completion timing detection circuit) 60 detects the completion timing of the decoding by the decoding circuit 40. That is, the detection circuit 60 detects whether either the main pulse signal or the sub-pulse signal has been input. For example, when the input signal of the detection circuit 60 changes from the third signal pair (set=0, reset=0) to the first signal pair (set=1, reset=0) or the second signal pair (set=0, reset=1), the NOR circuit 316a changes the output signal from a high-level signal to a low-level signal. As a result, the flip-flop 316b outputs a high-level signal (1) when either the main pulse signal or the sub-pulse signal has been input. When the flip-flop 316b is reset, it outputs a low-level signal (0).

[0097] The detection circuit (output inversion detection circuit) 70 detects output inversion. That is, the detection circuit 70 detects the inversion of the output value of the signal holding circuit 50. When the edge detection circuit is input with a time-sequentially different level signal, it changes the output from a high-level signal to a low-level signal. As a result, the flip-flop 318b outputs a high-level signal (1) when the output value of the signal holding circuit 50 is inverted. When the flip-flop 318b is reset, it outputs a low-level signal (0). In addition, the detection circuit 70 does not detect output inversion during the signal holding operation performed on the sub-pulse signal of the signal holding circuit 50.

[0098] The reset circuit 80 has a condition determination circuit 330 and a reset output circuit 340. The reset circuit 80 resets the triggers 308a, 308b, 310a, and 310b to a low-level signal (0) for example, based on the detection results of multiple detection circuits 60 and 70.

[0099] For example, when the input high-level signal (1) is used as the determination result of detection circuits 60 and 70, the condition determination circuit 330 outputs an error signal to the reset output circuit 340. As a result, the reset output circuit 340 resets the triggers 308a, 308b, 310a, and 310b to a low-level signal (0).

[0100] Furthermore, when signal R_INP1 or signal R_INN1 becomes a high-level signal (1), the condition determination circuit 330 outputs an error signal to the reset output circuit 340 after a predetermined time. As a result, the reset output circuit 340 resets flip-flops 308a, 308b, 310a, and 310b to a low-level signal (0). Therefore, even without input signals from detection circuits 60 and 70, the flip-flops 308a, 308b, 310a, and 310b can be reset.

[0101] Furthermore, based on signals INP_X, INP_dly, INN_X, and INN_dly1, the reset output circuit 340 resets flip-flops 308a, 308b, 310a, and 310b to a low-level signal (0) when no signal is input. Thus, even without signals from the detection circuits 60 and 70, the flip-flops 308a, 308b, 310a, and 310b can be repeatedly reset.

[0102] If the system signal UVLO is input as another signal, the reset output circuit 340 resets the flip-flops 308a, 308b, 310a, 310b, 316b, and 318b to a low-level signal (0). Therefore, based on the system signal UVLO from the host device, the flip-flops 308a, 308b, 310a, 310b, 316b, and 318b can be reset.

[0103] More specifically, the decoding circuit 40 has multiple buffer circuits 302 and 306, multiple negation (Not) circuits 300 and 304, a first flip-flop group 308, a second flip-flop group 310, and a decision circuit 312.

[0104] The first pulse detection circuit 308 is, for example, a first trigger group, having multiple first triggers 308a and 308b. This first pulse detection circuit 308, for example, detects the first pulses of the third main pulse signals SHap1, SHAN2, SHap2, the third secondary pulse signals Shap1, Shan2, Shap2, the fourth main pulse signals SLan1, SLap2, SLan2, and the fourth secondary pulse signals Slan1, Slap2, Slan2. That is, the first pulse detection circuit 308 detects SHap1, Shap1, SLan1, and Slan1.

[0105] The second pulse detection circuit 310 is, for example, a second flip-flop group, having multiple second flip-flops 310a and 310b. This second pulse detection circuit 310, for example, detects the second pulses of the third main pulse signals SHap1, SHAN2, SHap2, the third secondary pulse signals Shap1, Shan2, Shap2, the fourth main pulse signals SLan1, SLap2, SLan2, and the fourth secondary pulse signals Slan1, Slap2, Slan2. That is, the first pulse detection circuit 308 detects SHAN2, Shan2, SLan1, SLap2, and Slap2. The determination circuit 312 has multiple logic circuits 312a and 312b.

[0106] The rejection circuit 300 uses the signal input from terminal INP as signal INP_X, delaying the clock terminal of the first flip-flop 308a by Δt and inverting its output. The buffer circuit 302 delays the signal input from terminal INP by Δt and outputs it as signal INP_dly to the determination circuit 312. Similarly, the rejection circuit 304 uses the signal input from terminal INN as signal INN_X, delaying the clock terminal of the first flip-flop 308b by Δt and inverting its output. The buffer circuit 306 delays the signal input from terminal INN by Δt and outputs it as signal INN_dly to the determination circuit 312.

[0107] The first flip-flops 308a and 308b, and the second flip-flops 310a and 310b are, for example, D flip-flops. In the first flip-flops 308a and 308b, a high-level signal is always input to the D terminal. In addition, when the high-level signal (1) is input as a reset input, a low-level signal (0) is output.

[0108] First, refer to Figure 13 and use Figure 14 This section describes an example of how the decoder 114 operates when the third main pulse signals SHap1, SHan2, and SHap2 are input. Figure 14 This is a diagram illustrating the operation of decoder 114 when the third main pulse signals SHap1, SHan2, and SHap2 are input. Figure 14 The signal in corresponds to Figure 13 The signal in the image. The horizontal axis represents time.

[0109] like Figure 14 As shown, firstly, the first flip-flop 308a of the first pulse detection circuit 308 receives the third main pulse signal SHap1 from the terminal INP side at timing t1. Based on timing t2 when the signal changes from high level (1) to low level (0), the signal R_INP1 is changed from low level (0) to high level (1) and input to the D terminal of the second flip-flop 310a of the second pulse detection circuit 310. That is, the first flip-flop 308a changes the signal R_INP1 from low level (0) to high level (1) based on timing t2 when the signal INP_X changes from low level (0) to high level (1).

[0110] Next, the second flip-flop 310a receives the third main pulse signal SHAN2 from the terminal INN side at timing t2. According to timing t3 when the signal changes from high level (1) to low level (0), the signal R_INP2 is changed from low level (0) to high level (1) and output to the determination circuit 312. That is, the second flip-flop 310a sets the signal R_INP2 from low level (0) to high level (1) according to timing t3 when the signal INN_X changes from low level (0) to high level (1).

[0111] Next, the logic circuit 312a of the determination circuit 312 sets the signal set to a high level signal (1) when the signal INP_dly and the signal R_INP2 become high level signals (1) and the signal INN_dly and the signal R_INN2 become low level signals (0).

[0112] On the other hand, the logic circuit 312b of the determination circuit 312 outputs a signal opposite to that of the logic circuit 312a. That is, when the logic circuit 312a outputs a high-level signal (1), the logic circuit 312b outputs a high-level signal (1) when the logic circuit 312a outputs a high-level signal (1), and the logic circuit 312b outputs a high-level signal (1) when the logic circuit 312b outputs a high-level signal (1), and the logic circuit 312b outputs a high-level signal (1). That is, when the logic circuit 312a outputs a high-level signal (1), the logic circuit 312b outputs a low-level signal (0). Therefore, in the signal holding circuit 50, the signal set is a high-level signal (1), the signal reset is a low-level signal (0), and the signal Svox is set to a high-level signal (1) and maintained.

[0113] Then, when signals Sp2, Sn2, INP_dly and INN_dly become no signal, i.e. low level signal (0), they are reset by the FF of the reset circuit 80, and the flip-flops 308a, 308b, 310a, 316b, 318b and 310 are reset to low level signal (0).

[0114] The detection circuit 70 sets the output signal R_DEC_out__chang from low level signal (0) to high level signal (1) according to the timing of the signal Svox changing from low level signal (0) to high level signal (1).

[0115] The detection circuit 60 sets the output signal R_DEC_end from low level (0) to high level (1) based on the timing of the signal set or reset changing from low level (0) to high level (1). Furthermore, when the third sub-pulse signals Shap1, Shap2, and Shap2 are input, the same operation is performed as when the third main pulse signals SHap1, SHan2, and SHap2 are input.

[0116] Next, refer to Figure 13 and use Figure 15 This section describes an example of how the decoder 114 operates when the fourth main pulse signals SLan1, SLap2, and SLan2 are input. Figure 15 This is a diagram illustrating the operation of decoder 114 when the fourth main pulse signal SLan1, SLap2, SLan2 is input. Figure 15 The signal in corresponds to Figure 13 The signal in the image. The horizontal axis represents time.

[0117] like Figure 15 As shown, firstly, the first flip-flop 308b of the first pulse detection circuit 308 receives the fourth main pulse signal SLan1 from the terminal INN side at timing t6. Based on timing t7 when the signal changes from high level (1) to low level (0), the signal R_INN1 is set from low level (0) to high level (1) and input to the D terminal of the second flip-flop 310b. That is, the first flip-flop 308b sets the signal R_INN1 from low level (0) to high level (1) based on timing t7 when the signal INN_X changes from low level (0) to high level (1).

[0118] Next, the second trigger 310b of the second pulse detection circuit 310 receives the fourth main pulse signal SLap2 from the terminal INP side at timing t7. According to timing t8 when the signal changes from high level (1) to low level (0), the signal R_INN2 is set from low level (0) to high level (1) and output to the determination circuit 312. That is, the second trigger 310b sets the signal R_INN2 from low level (0) to high level (1) according to timing t8 when the signal INP_X changes from low level (0) to high level (1).

[0119] Next, the logic circuit 312b of the determination circuit 312 sets the signal reset to a high level (1) when the signals INN_dly and R_INN2 become high level signals (1) and the signals INP_dly and R_INP2 become low level signals (0).

[0120] As described above, logic circuit 312a outputs a low-level signal (0) when the output of logic circuit 312b is a high-level signal (1). Therefore, signal holding circuit 50 sets signal Svox to a low-level signal (0) and maintains it because signal reset is a high-level signal (1) and signal set is a low-level signal (0).

[0121] The detection circuit 70 changes the output signal R_DEC_out__chang from low level signal (0) to high level signal (1) according to the timing of the signal Svox changing from high level signal (1) to low level signal (0).

[0122] The detection circuit 60 sets the output signal R_DEC_end from low level (0) to high level (1) according to the timing of the signal set or reset changing from low level (0) to high level (1). In addition, when the fourth sub-pulse signals Slan1, Slap2, and Slan2 are input, the same operation is performed as when the fourth main pulse signals SLan1, SLap2, and SLan2 are input.

[0123] In this way, the signal holding circuit 50 can independently maintain the output value along with the reset actions of the triggers 308a, 308b, 310a, 310b, 316b, and 318b of the reset circuit 80. Therefore, while maintaining the output value of the signal holding circuit 50, even if the outputs of triggers 308a, 308b, 310a, and 310b are erroneously reversed due to noise or other reasons between the third main pulse signals SHap1, SHan2, SHap2 and the fourth main pulse signals SLan1, SLap2, SLan2, the correct output value can still be returned based on the third auxiliary pulse signals Shap1, Shap2, Shap2 or the fourth auxiliary pulse signals Slan1, Slap2, Slan2.

[0124] As explained above, according to this embodiment, the main pulse signal generation circuit 200 generates first main pulse signals SHp1 and SHn2 corresponding to the rising of the logic signal Sxix, and second main pulse signals SLn1 and SLp2 corresponding to the falling of the logic signal Sxix. The sub-pulse signal generation circuit 202 performs at least one of a first generation process and a second generation process. In the first generation process, after a predetermined time has elapsed since the first main pulse signals SHp1 and SHn2 were generated, a first sub-pulse signal Shp1 and Shn2 corresponding to the first main pulse signals SHp1 and SHn2 is generated at a predetermined interval (Trefresh+2T). In the second generation process, after a predetermined time has elapsed since the second main pulse signals SLn1 and SLp2 were generated, a second sub-pulse signal Sln1 and Slp2 corresponding to the second main pulse signals SLn1 and SLp2 is generated at a predetermined interval (Trefresh+2T). The selection circuit (output circuit) 206 stops the output of the sub-pulse signal generated by the sub-pulse signal generation circuit 202 according to at least one of the rising and falling of the logic signal Sxix. Therefore, when at least one of the rising and falling of the logic signal Sxix is ​​generated in the output of the sub-pulse signals Shp1, Shn2, Sln1, and Slp2, the sub-pulse signals Shp1, Shn2, Sln1, and Slp2 are stopped. Thus, even when the sub-pulse signals Shp1, Shn2, Sln1, and Slp2 interfere with the main pulse signals SHp1, SHn2, SLn1, and SLp2 on the receiving circuit 20 side, the main pulse signal generation circuit 200 can also generate the main pulse signals SHp1, SHn2, SLn1, and SLp2 immediately after time Tx_Wait without waiting for the sub-pulse signals Shp1, Shn2, Sln1, and Slp2 to end.

[0125] Additionally, the decoder 114 has triggers 308a, 308b, 310a, 310, 316b, and 318b. Whenever a third sub-pulse signal Shap1, Shan2, Shap2 corresponding to the first sub-pulse signals Shp1 and Shn2, or a fourth sub-pulse signal Slan1, Slap2, and Slan2 corresponding to the second sub-pulse signals Sln1 and Slp2, is input, the decoder 114 sets a predetermined value for triggers 308a, 308b, 310a, 310b, 316b, and 318b. That is, when the third sub-pulse signal Shap1, Shan2, Shap2, or the fourth sub-pulse signal Slan1, Slap2, and Slan2 is inserted, the decoder 114 sets a predetermined value for triggers 308a, 308b, 310a, 310b, 316b, and 318b according to the sub-pulse signal. Therefore, even if the outputs of triggers 308a, 308b, 310a, 310b, 316b, and 318b are erroneously reversed due to noise or other reasons between the first main pulse signals SHp1 and SHn2 and the second main pulse signals SLn1 and SLp2, the correct output value can still be returned. Thus, malfunctions of the communication device 1 can be suppressed.

[0126] Furthermore, even if any one of the third main pulse signals SHap1, SHAN2, SHap2, or the third sub-pulse signals Shap1, Shan2, and Shap2 is input, the signal holding circuit 50 maintains a high-level signal; and even if any one of the fourth main pulse signals SLan1, SLap2, SLan2, or the fourth sub-pulse signals Slan1, Slap2, and Slan2 is input, it maintains a low-level signal. Therefore, even if the third sub-pulse signals Shap1, Shan2, and Shap2, or the fourth sub-pulse signals Slan1, Slap2, and Slan2 are input, the value of the output signal Swox corresponding to the logic signal Sxix can be maintained. Thus, malfunctions of the communication device 1 can be suppressed.

[0127] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A communication device comprising a transmitting circuit and a receiving circuit for receiving signals via an AC coupling element. The transmitting circuit has an encoder. The encoder has: The main pulse signal generation circuit generates a first main pulse signal corresponding to the rising edge of the logic signal and a second main pulse signal corresponding to the falling edge. A secondary pulse signal generation circuit performs at least one of a first generation process and a second generation process. In the first generation process, a first secondary pulse signal corresponding to the first main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the first main pulse signal was generated. In the second generation process, a second secondary pulse signal corresponding to the second main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the second main pulse signal was generated. The output circuit outputs at least one of the following: the first main pulse signal, the second main pulse signal, the first secondary pulse signal, and the second secondary pulse signal. The output circuit stops the output of the first sub-pulse signal and the second sub-pulse signal based on at least one of the rising and falling pulses.

2. The communication device according to claim 1, The first main pulse signal is a first combination of multiple pulse signals, and the second main pulse signal is a second combination of multiple pulse signals that are different from the first combination.

3. The communication device according to claim 1, The receiving circuit has a decoder. The decoder generates high-level signals based on the third main pulse signal and the third sub-pulse signal, which correspond to the first main pulse signal and the first sub-pulse signal, respectively. The communication device has a signal holding circuit that outputs a high-level signal until one of the fourth main pulse signal and the fourth sub-pulse signal, which correspond to the second main pulse signal and the second sub-pulse signal respectively, is input.

4. The communication device according to claim 3, The decoder generates low-level signals based on the fourth main pulse signal and the fourth sub-pulse signal, respectively. The signal holding circuit outputs a low-level signal until one of the third main pulse signal and the third sub-pulse signal is input.

5. The communication device according to claim 4, The first sub-pulse signal is a first combination of multiple pulse signals, and the second sub-pulse signal is a second combination of multiple pulse signals. The decoder performs a refresh operation based on the first sub-pulse signal and the second sub-pulse signal.

6. The communication device according to claim 5, The decoder has: The first pulse detection circuit outputs a predetermined signal based on the first pulse signal among the multiple pulse signals possessed by the third main pulse signal, the third secondary pulse signal, the fourth main pulse signal, and the fourth secondary pulse signal. The second pulse detection circuit, based at least on the output signal of the first pulse detection circuit, outputs a predetermined signal according to the second pulse signal among the plurality of pulse signals possessed by the third main pulse signal, the third secondary pulse signal, the fourth main pulse signal, and the fourth secondary pulse signal; The detection circuit, based at least on the output signal of the second pulse detection circuit, outputs a first signal corresponding to the rise and a second signal corresponding to the fall. as well as The reset circuit generates a reset signal that initializes the first pulse detection circuit and the second pulse detection circuit based on the last pulse signal from among the multiple pulse signals of the third main pulse signal, the third secondary pulse signal, the fourth main pulse signal, and the fourth secondary pulse signal. The signal holding circuit outputs the high-level signal or the low-level signal based on the first signal and the second signal.

7. The communication device according to claim 3, It also includes an AC coupling element that transmits at least one of the first main pulse signal, the second main pulse signal, the first sub-pulse signal, and the second sub-pulse signal output by the output circuit to the receiving circuit.

8. The communication device according to claim 7, The AC coupling element is one of an insulated miniature transformer and a miniature capacitor. The transmitting circuit and the receiving circuit are galvanically insulated by one of the insulated micro transformer and the micro capacitor.

9. A semiconductor device comprising a transmitting circuit with an encoder and a receiving circuit for receiving signals via an AC coupling element. The encoder has: The main pulse signal generation circuit generates a first main pulse signal corresponding to the rising edge of the logic signal and a second main pulse signal corresponding to the falling edge. A secondary pulse signal generation circuit performs at least one of a first generation process and a second generation process. In the first generation process, a first secondary pulse signal corresponding to the first main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the first main pulse signal was generated. In the second generation process, a second secondary pulse signal corresponding to the second main pulse signal is generated at a predetermined interval after a predetermined time has elapsed since the second main pulse signal was generated. The output circuit outputs at least one of the following: the first main pulse signal, the second main pulse signal, the first secondary pulse signal, and the second secondary pulse signal. The output circuit stops the output of the first sub-pulse signal and the second sub-pulse signal based on at least one of the rising and falling pulses.

10. The semiconductor device according to claim 9, The first main pulse signal is a first combination of multiple pulse signals, and the second main pulse signal is a second combination of multiple pulse signals that are different from the first combination.

11. The semiconductor device according to claim 9, The receiving circuit has a decoder. The decoder generates high-level signals based on the third main pulse signal and the third sub-pulse signal, which correspond to the first main pulse signal and the first sub-pulse signal, respectively. The semiconductor device has a signal holding circuit that outputs a high-level signal until one of the fourth main pulse signal and the fourth sub-pulse signal, which correspond to the second main pulse signal and the second sub-pulse signal respectively, is input.

12. The semiconductor device according to claim 11, The decoder generates low-level signals based on the fourth main pulse signal and the fourth sub-pulse signal, respectively. The signal holding circuit outputs a low-level signal until one of the third main pulse signal and the third sub-pulse signal is input.

13. The semiconductor device according to claim 12, The first sub-pulse signal is a first combination of multiple pulse signals, and the second sub-pulse signal is a second combination of multiple pulse signals. The decoder performs a refresh operation based on the first sub-pulse signal and the second sub-pulse signal.

14. The semiconductor device according to claim 13, The decoder has: The first pulse detection circuit outputs a predetermined signal based on the first pulse signal among the multiple pulse signals possessed by the third main pulse signal, the third secondary pulse signal, the fourth main pulse signal, and the fourth secondary pulse signal. The second pulse detection circuit, based at least on the output signal of the first pulse detection circuit, outputs a predetermined signal according to the second pulse signal among the plurality of pulse signals possessed by the third main pulse signal, the third secondary pulse signal, the fourth main pulse signal, and the fourth secondary pulse signal; The detection circuit, based at least on the output signal of the second pulse detection circuit, outputs a first signal corresponding to the rise and a second signal corresponding to the fall. as well as The reset circuit generates a reset signal that initializes the first pulse detection circuit and the second pulse detection circuit based on the last pulse signal from among the multiple pulse signals of the third main pulse signal, the third secondary pulse signal, the fourth main pulse signal, and the fourth secondary pulse signal. The signal holding circuit outputs the high-level signal or the low-level signal based on the first signal and the second signal.

15. The semiconductor device according to claim 11, It also includes an AC coupling element that transmits at least one of the first main pulse signal, the second main pulse signal, the first sub-pulse signal, and the second sub-pulse signal output by the output circuit to the receiving circuit.

16. The semiconductor device according to claim 15, The AC coupling element is one of an insulated miniature transformer and a miniature capacitor. The transmitting circuit and the receiving circuit are galvanically insulated by one of the insulated micro transformer and the micro capacitor.

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