A multi-antenna signal concatenation apparatus based on chirp signals

Abstract

The application provides a multi-antenna signal cascading device based on a linear frequency modulation signal, and relates to the technical field of signal processing, and comprises: a plurality of linear frequency modulation chips, each of the linear frequency modulation chips is cascaded in sequence, each of the linear frequency modulation chips is connected with a receiving antenna, is used for processing a linear frequency modulation signal received by the receiving antenna to obtain a corresponding signal frequency component, and the last linear frequency modulation chip in the cascade is further used for performing merging processing on each of the signal frequency components obtained by each of the remaining linear frequency modulation chips to obtain a linear frequency modulation signal with a preset signal-to-noise ratio. The beneficial effect is that the input linear frequency modulation signal is received by using multiple antennas and is cascaded by using multiple linear frequency modulation chips, the input linear frequency modulation signal is merged, the number of interfaces required on the linear frequency modulation chip is reduced, the complexity of design is reduced, the signal-to-noise ratio of the signal is effectively improved, and the transmission distance of the system is improved.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a multi-antenna signal cascading device based on linear frequency modulated signals. Background Technology

[0002] In common communication systems, a single antenna is typically used for transmission and reception. This approach is simple, but lacks directivity. It's impossible to control the phase of multiple antennas to achieve the directivity of a single antenna, thereby increasing transmit and receive power in a specific direction and improving system gain and transmission distance. To further enhance the gain of communication systems, existing technologies often employ multi-antenna transceiver systems, such as MIMO (Multiple-Input Multiple-Output) technology. MIMO uses multiple antennas at both the transmitting and receiving ends, creating multiple channels between the transmitter and receiver, significantly increasing channel capacity. MIMO systems utilize the multipath effect of signals to improve communication quality. In MIMO systems, the transmitter and receiver use multiple antennas that can operate simultaneously. The transmitter sends multiple radio frequency signals simultaneously, and the receiver combines these signals to improve the signal-to-noise ratio (SNR). However, existing signal combining methods are complex, and the SNR cannot be flexibly adjusted. Summary of the Invention

[0003] To address the problems existing in the prior art, the present invention provides a multi-antenna signal cascade device based on linear frequency modulation (LFM) signals, comprising multiple LFM chips, which are cascaded sequentially. Each LFM chip is connected to a receiving antenna and is used to process the LFM signal received by the receiving antenna to obtain corresponding signal frequency components. The last cascaded LFM chip is also used to merge the signal frequency components obtained by the remaining LFM chips to obtain an LFM signal with a preset signal-to-noise ratio.

[0004] Preferably, each of the linear frequency modulation chips includes:

[0005] A signal processing module, wherein the input terminal of the signal processing module is connected to the receiving antenna, and the output terminal of the signal processing module is connected to the first conversion interface and the signal combining module respectively;

[0006] The first conversion interfaces of each of the linear frequency modulation chips, except for the last one, are cascaded in sequence to receive the signal frequency component output by the previous linear frequency modulation chip and its own signal frequency component through the first conversion interface and send them to the next linear frequency modulation chip.

[0007] The input terminal of the signal combining module of the last linear frequency modulation chip is connected to the first conversion interface of the previous linear frequency modulation chip to receive each signal frequency component sent by the previous linear frequency modulation chip and its own signal frequency component, and perform combining processing to obtain a linear frequency modulation signal with the preset signal-to-noise ratio.

[0008] Preferably, it also includes a control chip, which is connected to each of the linear frequency modulation chips respectively. The output terminal of the signal processing module of each linear frequency modulation chip is connected to the first conversion interface through a first switch and to the signal merging module through a second switch.

[0009] The control chip includes a control unit, which controls the first switch of the last linear frequency modulation chip to open and the second switch to close, and controls the first switch of each of the remaining linear frequency modulation chips to close and the second switch to open, so as to realize the sequential cascading of each of the linear frequency modulation chips.

[0010] Preferably, the control chip further includes a computing unit connected to the control unit, used to calculate the number of cascaded chips based on the required signal-to-noise ratio and the pre-acquired single-signal signal-to-noise ratio of each of the linear frequency modulation chips, and to determine the last linear frequency modulation chip based on the number of cascaded chips;

[0011] The control unit is also used to control the first switch of the last linear frequency modulation chip to be open and the second switch to be closed, and to control the first switch of each of the remaining linear frequency modulation chips before the chip number to be closed and the second switch to be open.

[0012] Preferably, the control chip further includes a storage unit connected to the computing unit, used to store the chip number of each of the linear frequency modulation chips, wherein the chip numbers are arranged sequentially in a cascaded order;

[0013] The computing unit determines the chip number of the last linear frequency modulation chip based on the number of cascaded chips and sends it to the control unit.

[0014] Preferably, the computing unit calculates the number of cascaded chips according to the following formula:

[0015] in,

[0016] Where m represents the number of cascaded chips, SNR1 represents the required signal-to-noise ratio, SNR2 represents the single-signal signal-to-noise ratio, s represents the signal frequency component, and n represents the single-signal noise of the linear frequency modulation chip.

[0017] Preferably, the signal processing module includes a radio frequency front-end, an analog-to-digital converter, a digital filter, a digital intermediate frequency mixer, and a Fourier transform unit connected in sequence. The radio frequency front-end serves as the input terminal of the signal processing module and is connected to the corresponding receiving antenna. The output terminal of the Fourier transform unit serves as the output terminal of the signal processing module.

[0018] Preferably, the signal combining module includes a maximum ratio combining unit and a digital demodulator connected in sequence, and the input terminal of the maximum ratio combining unit is connected to the output terminal of the signal processing module.

[0019] Preferably, it also includes multiple second conversion interfaces. The input terminal of the signal combining module of the last cascaded linear frequency modulation chip is connected to the first conversion interface of the previous linear frequency modulation chip through the corresponding second conversion interface. The first conversion interfaces of the remaining linear frequency modulation chips are respectively connected to the first conversion interfaces of the adjacent linear frequency modulation chips through the corresponding second conversion interfaces.

[0020] Preferably, the first conversion interface is a parallel-to-serial conversion interface, and the second conversion interface is a parallel-to-serial conversion interface.

[0021] The above technical solution has the following advantages or beneficial effects:

[0022] 1) By using multiple antennas to receive the input linear frequency modulation (LFM) signal and cascading multiple LFM chips, the input LFM signals can be combined, which can reduce the number of interfaces required on the LFM chip, reduce the complexity of the design, and effectively improve the signal-to-noise ratio, thereby increasing the transmission distance of the system.

[0023] 2) By using the frequency components of the linear frequency modulated signal instead of the linear frequency modulated signal itself, the amount of data transmitted can be reduced, and the computational latency and power consumption can be decreased.

[0024] 3) The number of cascaded linear frequency modulation chips can be flexibly adjusted based on the required signal-to-noise ratio. Attached Figure Description

[0025] Figure 1 A schematic diagram of a multi-antenna signal cascade device based on linear frequency modulation signal is provided in a preferred embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the control chip in a preferred embodiment of the present invention. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within the scope of the present invention.

[0028] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a multi-antenna signal cascading device based on linear frequency modulated signals is provided, such as... Figure 1 and Figure 2 As shown, the system includes multiple linear frequency modulation (LFM) chips 100, which are cascaded in sequence. Each LFM chip 100 is connected to a receiving antenna 200 to process the LFM signal received by the receiving antenna 200 to obtain the corresponding signal frequency components. The last cascaded LFM chip 100 is also used to combine the signal frequency components obtained by the other LFM chips 100 to obtain a LFM signal with a preset signal-to-noise ratio.

[0029] Specifically, in this embodiment, by cascading multiple linear frequency modulation (LFM) chips 100 sequentially, each LFM chip 100, except for the last one, only needs to process the LFM signal it receives to obtain the corresponding signal frequency component before sending it to the next cascaded LFM chip 100. This process continues, enabling the last LFM chip 100 to receive the signal frequency components from the other LFM chips 100 and combine them with its own signal frequency components for unified signal merging. This achieves single-channel transmission and multi-channel reception, effectively improving the signal-to-noise ratio and saving power consumption.

[0030] In a preferred embodiment of the present invention, each linear frequency modulation chip 100 includes:

[0031] The signal processing module 101 has its input terminal connected to the receiving antenna 200, and its output terminal connected to the first conversion interface 102 and the signal combining module 103, respectively.

[0032] The first conversion interfaces 102 of each linear frequency modulation chip 100 except the last linear frequency modulation chip 100 are cascaded in sequence so as to receive the signal frequency component output by the previous linear frequency modulation chip 100 and its own signal frequency component through the first conversion interface 102 and send it to the next linear frequency modulation chip 100.

[0033] The input terminal of the signal combining module 103 of the last linear frequency modulation chip 100 is connected to the first conversion interface 102 of the previous linear frequency modulation chip 100 to receive the signal frequency components sent by the previous linear frequency modulation chip 100 and its own signal frequency components, and perform combining processing to obtain a linear frequency modulation signal with a preset signal-to-noise ratio.

[0034] Specifically, in this embodiment, after the signal processing module 101 of each linear frequency modulation chip 100 processes the received linear frequency modulation signal to obtain the signal frequency component, there are two selectable transmission paths. The first transmission path is to send the signal frequency component to the first conversion interface 102, that is, without signal merging processing, the purpose of which is to send the signal frequency component obtained by itself to the next linear frequency modulation signal. The second transmission path is to send the signal frequency component to the signal merging module 103 for signal fusion processing. One of the two transmission paths is selected to be activated.

[0035] As can be seen, the last linear frequency modulation (LFM) chip 100 does not need to send signal frequency components to the next LFM chip 100, so its first transmission path is not conducting. All other LFM chips 100 need to send signal frequency components to the next LFM chip 100, so their first transmission paths need to be conducting. The last LFM chip 100 needs to combine the signal frequency components from the other LFM chips 100 and its own signal frequency components, so its second transmission path needs to be conducting. The other LFM chips 100 do not need to perform further signal processing, so their second transmission paths do not need to be conducting.

[0036] Therefore, flexible control of linear frequency modulation signal processing can be achieved by controlling the conduction state of the two transmission paths of each linear frequency modulation chip 100. Based on this, in a preferred embodiment of the present invention, a control chip 300 is also included, which is connected to each linear frequency modulation chip 100. The output terminal of the signal processing module 101 of each linear frequency modulation chip 100 is connected to the first conversion interface 102 through the first switch S1 and to the signal merging module 103 through the second switch S2.

[0037] The control chip 300 includes a control unit 301, which controls the first switch S1 of the last linear frequency modulation chip 100 to open and the second switch S2 to close, and controls the first switch S1 of each of the remaining linear frequency modulation chips 100 to close and the second switch S2 to open, so as to realize the cascading of each linear frequency modulation chip 100.

[0038] Specifically, in this embodiment, the conduction state of the two transmission paths is achieved by controlling the opening and closing of the first switch S1 and the second switch S2. Furthermore, since the first switch S1 and the second switch S2 of each linear frequency modulation chip 100 can be independently controlled, the number of cascaded chips can also be flexibly controlled. Taking n linear frequency modulation chips 100 as an example, where chips 1#, 2#, and n# are cascaded sequentially, in actual use, it is not necessarily necessary to use n# as the last linear frequency modulation chip; instead, the signal-to-noise ratio can be flexibly adjusted as needed.

[0039] More specifically, the number of cascaded chips can be flexibly adjusted by the control chip 300. In a preferred embodiment of the present invention, the control chip 300 further includes a calculation unit 302 connected to the control unit 301, which is used to calculate the number of cascaded chips based on the required signal-to-noise ratio and the pre-acquired single signal-to-noise ratio of each linear frequency modulation chip 100, and determine the last linear frequency modulation chip 100 based on the number of cascaded chips.

[0040] The control unit 301 is also used to control the first switch S1 of the last linear frequency modulation chip 100 to be open and the second switch S2 to be closed, and to control the first switch S1 of each of the remaining linear frequency modulation chips 100 before the chip number to be closed and the second switch S2 to be open.

[0041] Specifically, in this embodiment, if the calculated number of cascaded chips is 5, then the 5# linear frequency modulation chip is designated as the last linear frequency modulation chip 100. The first switch S1 of the 5# linear frequency modulation chip is then opened, preventing the 6# linear frequency modulation chip and subsequent cascaded linear frequency modulation chips from receiving signal frequency components. The second switch S2 of the 5# linear frequency modulation chip is then closed. The first switches S1 of the 1# to 4# linear frequency modulation chips are closed, and the second switches S2 are opened. The signal frequency component output by the 1# linear frequency modulation chip is then sent via the first conversion interface 102 of the 1# linear frequency modulation chip to the first conversion interface 102 of the 2# linear frequency modulation chip. The first conversion interface 102 of the 2# linear frequency modulation chip combines the signal frequency component output by the 1# linear frequency modulation chip with its own signal frequency component and sends them together to the first conversion interface 102 of the 3# linear frequency modulation chip, and so on. The merging method for each signal frequency component is as follows:

[0042] The signal frequency component output by the #1 linear frequency modulation chip is signal frequency component 1, and the signal frequency component output by the #2 linear frequency modulation chip is signal frequency component 2. Therefore, the preferred data structure after merging at the first conversion interface 102 of the #2 linear frequency modulation chip is (signal frequency component 1, signal frequency component 2). The preferred data structure after merging at the first conversion interface 102 of the #3 linear frequency modulation chip is (signal frequency component 1, signal frequency component 2, signal frequency component 3), and so on. In other words, the signal frequency component is added to the received signal frequency component to form a data packet, which is then sent to the next linear frequency modulation chip. Finally, all the signal frequency components are concentrated in the last linear frequency modulation chip for merging and demodulation to output a linear frequency modulation signal.

[0043] As can be seen, by cascading, compared to processing and demodulating the linear frequency modulation (LFM) signal separately with each LFM chip, and then combining the signals with another signal fusion chip, there is no need to coordinate the order of signal reception, nor is it necessary to set up separate connection interfaces for each LFM chip, thus reducing the overall design complexity. Furthermore, by transmitting the signal frequency components as frequency information of the LFM signal instead of the signal itself, the amount of data transmitted can be reduced, lowering computational latency and power consumption.

[0044] In a preferred embodiment of the present invention, the control chip 300 further includes a storage unit 303 connected to the computing unit 302, for storing the chip number of each linear frequency modulation chip 100, and the chip numbers are arranged sequentially in cascade order;

[0045] The calculation unit 302 determines the chip number of the last linear frequency modulation chip 100 based on the number of cascaded chips and sends it to the control unit 301.

[0046] In a preferred embodiment of the present invention, the calculation unit 302 calculates the number of cascaded chips according to the following formula:

[0047] in,

[0048] Where m represents the number of cascaded chips, SNR1 represents the required signal-to-noise ratio, SNR2 represents the single-signal signal-to-noise ratio, s represents the signal frequency component, and n represents the single-signal noise of the linear frequency modulation chip.

[0049] In a preferred embodiment of the present invention, the signal processing module 101 includes a radio frequency front-end RF, an analog-to-digital converter ADC, a digital filter Filter, a digital intermediate frequency mixer Mixer, and a Fourier transform unit FFT connected in sequence. The radio frequency front-end RF serves as the input terminal of the signal processing module 101 and is connected to the corresponding receiving antenna 200. The output terminal of the Fourier transform unit FFT serves as the output terminal of the signal processing module 101.

[0050] In a preferred embodiment of the present invention, the signal combining module 103 includes a maximum ratio combining unit (MRC) and a digital demodulator (Demod) connected in sequence, with the input terminal of the MRC connected to the output terminal of the signal processing module 101.

[0051] Specifically, in this embodiment, the Maximum Ratio Combining (MRC) unit in the last linear frequency modulation (LFM) chip 100 performs the final signal-to-noise ratio (SNR) calculation and signal fusion. Based on the SNR data sent from each chip, the percentage of the output is determined by comparing the SNR of this signal with the SNR of all signals, resulting in an output signal frequency component with increased SNR. The signal SNR is then optimized and enters the digital demodulator (Demod) to recover the information. The calculation of the single-signal SNR is defined by the following formula:

[0052]

[0053] Where s represents the signal frequency component, n represents the single-signal noise of the linear frequency modulation chip, and σ represents the root mean square. The signal-to-noise ratio is calculated by combining n signals according to the following formula:

[0054]

[0055] In other words, combining n signals can at least improve the signal-to-noise ratio. Based on this, the signal-to-noise ratio can be increased by an external control chip 300 according to the required ratio. The number of chips n in the chipset is determined, and then the opening and closing status of the first switch S1 and the second switch S2 in each linear frequency modulation chip is determined. Since the number of receiving antennas used is proportional to the degree of signal-to-noise ratio optimization, the number of receiving antennas can also be selected as needed.

[0056] In a preferred embodiment of the present invention, a plurality of second conversion interfaces 400 are further included. The input terminal of the signal combining module 103 of the last cascaded linear frequency modulation chip 100 is connected to the first conversion interface 102 of the previous linear frequency modulation chip 100 through the corresponding second conversion interface 400. The first conversion interfaces 102 of the remaining linear frequency modulation chips 100 are respectively connected to the first conversion interfaces 102 of the adjacent linear frequency modulation chips 100 through the corresponding second conversion interfaces 400.

[0057] Specifically, in this embodiment, serial-to-parallel conversion and parallel-to-serial conversion are realized through the first conversion interface 102 and the second conversion interface 400, thereby realizing the combined transmission of signal frequency components. The second conversion interface 400 can be integrated on the linear frequency modulation chip 100 or set separately, which is not limited here.

[0058] In a preferred embodiment of the present invention, the first conversion interface 102 is a parallel-to-serial conversion interface, and the second conversion interface 400 is a parallel-to-serial conversion interface.

[0059] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A multi-antenna signal cascading device based on linear frequency modulated signals, characterized in that, It includes multiple linear frequency modulation (LFM) chips, which are cascaded in sequence. Each LFM chip is connected to a receiving antenna and is used to process the LFM signal received by the receiving antenna to obtain the corresponding signal frequency components. The last cascaded LFM chip is also used to combine the signal frequency components obtained by the other LFM chips to obtain a LFM signal with a preset signal-to-noise ratio. Each of the linear frequency modulation chips includes: A signal processing module, wherein the input terminal of the signal processing module is connected to the receiving antenna, and the output terminal of the signal processing module is connected to the first conversion interface and the signal combining module respectively; The first conversion interfaces of each of the remaining linear frequency modulation chips, except for the last one, are cascaded in sequence to receive data packets formed by the signal frequency components output by the previous linear frequency modulation chip through the first conversion interface, and add their own signal frequency components to the data packets to form a new data packet containing all the received signal frequency classifications and their own signal frequency components, which is then sent to the next linear frequency modulation chip. The input terminal of the signal combining module of the last linear frequency modulation chip is connected to the first conversion interface of the previous linear frequency modulation chip to receive each signal frequency component sent by the previous linear frequency modulation chip and its own signal frequency component, combine them and demodulate them to obtain a linear frequency modulation signal with the preset signal-to-noise ratio. It also includes a control chip, which includes a computing unit for calculating the number of cascaded chips based on the required signal-to-noise ratio and the pre-acquired single-signal signal-to-noise ratio of each of the linear frequency modulation chips, and determining the last linear frequency modulation chip based on the number of cascaded chips. The computing unit calculates the number of cascaded chips according to the following formula: ,in, ; Where m represents the number of cascaded chips, SNR1 represents the required signal-to-noise ratio, SNR2 represents the single-signal signal-to-noise ratio, s represents the signal frequency component, and n represents the single-signal noise of the linear frequency modulation chip.

2. The multi-antenna signal cascading device according to claim 1, characterized in that, It also includes a control chip, which is connected to each of the linear frequency modulation chips. The output terminal of the signal processing module of each linear frequency modulation chip is connected to the first conversion interface through a first switch and to the signal merging module through a second switch. The control chip includes a control unit, which controls the first switch of the last linear frequency modulation chip to open and the second switch to close, and controls the first switch of each of the remaining linear frequency modulation chips to close and the second switch to open, so as to realize the sequential cascading of each of the linear frequency modulation chips.

3. The multi-antenna signal cascading device according to claim 2, characterized in that, The computing unit is connected to the control unit; The control unit is also used to control the first switch of the last linear frequency modulation chip to be open and the second switch to be closed, and to control the first switch of each of the remaining linear frequency modulation chips before the chip number to be closed and the second switch to be open.

4. The multi-antenna signal cascading device according to claim 3, characterized in that, The control chip also includes a storage unit connected to the computing unit, used to store the chip number of each of the linear frequency modulation chips, and the chip numbers are arranged sequentially in cascade order; The computing unit determines the chip number of the last linear frequency modulation chip based on the number of cascaded chips and sends it to the control unit.

5. The multi-antenna signal cascading device according to claim 1, characterized in that, The signal processing module includes a radio frequency front-end, an analog-to-digital converter, a digital filter, a digital intermediate frequency mixer, and a Fourier transform unit connected in sequence. The radio frequency front-end serves as the input terminal of the signal processing module and is connected to the corresponding receiving antenna. The output terminal of the Fourier transform unit serves as the output terminal of the signal processing module.

6. The multi-antenna signal cascading device according to claim 1, characterized in that, The signal combining module includes a maximum ratio combining unit and a digital demodulator connected in sequence, with the input of the maximum ratio combining unit connected to the output of the signal processing module.

7. The multi-antenna signal cascading device according to claim 1, characterized in that, It also includes multiple second conversion interfaces. The input terminal of the signal combining module of the last cascaded linear frequency modulation chip is connected to the first conversion interface of the previous linear frequency modulation chip through the corresponding second conversion interface. The first conversion interfaces of the remaining linear frequency modulation chips are respectively connected to the first conversion interfaces of the adjacent linear frequency modulation chips through the corresponding second conversion interfaces.

8. The multi-antenna signal cascading device according to claim 7, characterized in that, The first conversion interface is a parallel-to-serial conversion interface, and the second conversion interface is a parallel-to-serial conversion interface.

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