A manufacturing process of a PCB jack hole and a PCB manufactured thereby

Abstract

The application discloses a manufacturing process of a PCB jack and a manufactured PCB. The PCB comprises a multilayer circuit board, the multilayer circuit board is provided with a via hole, a drill hole is formed into a stepped hole with different inner diameters through a depth-controlled drilling manner, a non-conductive layer and a conductive layer are arranged in the via hole, the conductive layer is arranged as at least two layers, the non-conductive layer is arranged as at least three layers, and the non-conductive layer and the conductive layer are alternately arranged. When the via hole of the PCB is manufactured, the stepped hole with different inner diameters is drilled in the through hole for multiple times, and the non-conductive resin or the conductive paste is vacuumed into the jack and is solidified, so that multiple alternately arranged non-conductive layers and conductive layers are obtained, a structure of multiple different interlayer network connections in one via hole is realized, one hole is used for multiple wiring, the wiring density of a product is improved, and the material cost is reduced. The application can be widely applied to the technical field of circuit board production.

Description

Technical Field

[0001] This application relates to the field of circuit board manufacturing technology, and in particular to a PCB via plugging process and the PCB produced therefrom. Background Technology

[0002] With the development of high-density integrated circuit technology and microelectronics technology, electronic products have become lighter, thinner and smaller. Traditional high-density designs usually use HDI design, N+N technology and via / hole technology. HDI technology is complex and has a low product yield. N+N technology and via / hole technology can only run two wires per hole, resulting in low product wiring density and increased production costs. Summary of the Invention

[0003] To solve at least one of the above-mentioned technical problems, this application provides a PCB via-filling manufacturing process and the PCB manufactured therefrom, and the technical solution adopted is as follows.

[0004] This application provides a manufacturing process for PCB via plugs, the workflow of which includes:

[0005] S1, Drilling through holes on a multilayer circuit board, with a drill bit diameter of A;

[0006] S2, electroplating inside the through hole is conductive;

[0007] S3, vacuum plugging and curing of the through holes with non-conductive resin;

[0008] S4, drill the stepped hole 1 from one end of the through hole or drill the stepped hole 1 from both ends of the through hole, with the drill bit diameter being B1 and B1 > A;

[0009] S5, Vacuum plugging and curing of the stepped hole 1 with conductive paste;

[0010] S6, drill step hole 2 at step hole 1 with controlled depth, the drill bit diameter is B2, and B2>B1;

[0011] S7, Vacuum plugging and curing of the stepped hole 2 with non-conductive resin;

[0012] S8, perform steps S4 to S7 at least N times to control the depth of drilling step hole 2N+1 and step hole 2(N+1), with a drill bit diameter of B. 2N+1 and B 2(N+1) And B 2(N+1) >B 2N+1 N≥1, N is an integer;

[0013] After the PCB is filled with vias, the outer layer of the multilayer circuit board is electroplated.

[0014] In some embodiments of this application, step S9 is performed to drill a controlled-depth hole to the conductive layer of the stepped hole 2i-1, obtaining hole 1, where i ≥ 1, i is an integer, the drill bit diameter is C, and C < B. 2i-1 The borehole 1 was vacuum plugged and cured with non-conductive resin.

[0015] In some embodiments of this application, step S10 is performed to drill a hole to the conductive layer of the stepped hole 2i-1 or to drill a hole to the non-conductive layer below the conductive layer of the stepped hole 2i-1, to obtain a drill hole 2. The drill bit diameter is D, and D < C. The drill hole 2 is then vacuum plugged with conductive paste and cured.

[0016] In some embodiments of this application, step S11 is performed, which is to perform step S8 at least once.

[0017] In some embodiments of this application, step S12 is performed, which is to perform at least one step S8, step S9 and step S10.

[0018] In some embodiments of this application, when stepped holes are drilled at controlled depths at both ends of the through hole, the drilling at at least one end of the through hole is performed at least once through steps S8, S9 and S10.

[0019] In some embodiments of this application, when stepped holes are drilled at controlled depths at both ends of the through hole, the workflow of the manufacturing process is redesigned as follows:

[0020] S1, Drill through holes on a multilayer circuit board with a drill diameter of A, and use conductive paste to vacuum plug the through holes and then cure them.

[0021] S2, drill a stepped hole M from one end of the through hole or drill a stepped hole M from both ends of the through hole, with a drill bit diameter of E and E > A;

[0022] S3, Vacuum plugging and curing of the stepped hole M with non-conductive resin;

[0023] S4, control the depth of drilling step hole 1 at step hole M, with drill bit diameter B1 and B1>E;

[0024] S5, Vacuum plugging and curing of the stepped hole 1 with conductive paste;

[0025] S6, drill step hole 2 at step hole 1 with controlled depth, the drill bit diameter is B2, and B2>B1;

[0026] S7, Vacuum plugging and curing of the stepped hole 2 with non-conductive resin;

[0027] S8, perform steps S4 to S7 at least N times to control the depth of drilling step hole 2N+1 and step hole 2(N+1), with a drill bit diameter of B.2N+1 and B 2(N+1) And B 2(N+1) >B 2N+1 ;

[0028] Where N≥1, and N is an integer.

[0029] The PCB provided in this application includes a multilayer circuit board. The multilayer circuit board is provided with vias. The vias are formed by controlled-depth drilling to form stepped holes with different inner diameters. The vias are provided with non-conductive layers and conductive layers. The conductive layers are provided with at least two layers, and the non-conductive layers are provided with at least three layers, and the non-conductive layers and conductive layers are alternately provided.

[0030] In some embodiments of this application, the via is provided with a cross-layer conductive structure, which penetrates at least one of the non-conductive layers, so that the conductive layer in the via is connected to the electroplated layer network on the surface of the multilayer circuit board through the cross-layer conductive structure.

[0031] In some embodiments of this application, the via is provided with a cross-layer conductive structure, which penetrates at least one of the non-conductive layers, so that the conductive layers of two different layers are connected through the cross-layer conductive structure network.

[0032] In some embodiments of this application, when the cross-layer conductive structure penetrates at least one of the conductive layers, a non-conductive isolation structure is provided in the via, the non-conductive isolation structure is formed into a cylindrical shape, and the cross-layer conductive structure penetrates the non-conductive isolation structure.

[0033] The embodiments of this application have at least the following beneficial effects: When fabricating vias for a PCB, stepped holes of different inner diameters are drilled multiple times with controlled depth within the through-hole, and the holes are then vacuum-sealed and cured with non-conductive resin or conductive paste to obtain multiple alternating non-conductive and conductive layers. This achieves a structure where multiple different interlayer networks are connected within a single via, enabling multiple traces to be routed through one via, increasing product wiring density, and reducing material costs. This application can be widely applied in the field of PCB manufacturing technology. Attached Figure Description

[0034] The aspects and advantages described and / or added to the embodiments of this application will become apparent and readily understood in conjunction with the following drawings. It should be noted that the embodiments illustrated in the following drawings are exemplary and are used only to explain this application, and should not be construed as limiting this application.

[0035] Figure 1-1 This is a schematic diagram showing the structural changes of the via during steps S1 to S7.

[0036] Figure 1-2 This is a schematic diagram showing the structural changes of the via during step S8.

[0037] Figure 1-3 This is a schematic diagram showing the structural changes of the via during step S9.

[0038] Figure 1-4 This is a schematic diagram of the structural changes of the via during step S10.

[0039] Figure 1-5 This is a schematic diagram of the structure of a multilayer circuit board after the outer layer is electroplated.

[0040] Figure 2-1 This is a schematic diagram of the via structure obtained through steps S1 to S10.

[0041] Figure 2-2 This is a schematic diagram of the via structure obtained through steps S1 to S10.

[0042] Figure 3-1 This is a schematic diagram of the via structure obtained through steps S1 to S11.

[0043] Figure 3-2 This is a schematic diagram of the via structure obtained through steps S1 to S11.

[0044] Figure 4-1 This is a schematic diagram of the via structure in some examples.

[0045] Figure 4-2 This is a schematic diagram of the via structure in some other examples.

[0046] Figure 5 This is a schematic diagram of the via structure in some other examples.

[0047] Figure 6-1 This is a schematic diagram of the via structure in some other examples.

[0048] Figure 6-2 This is a schematic diagram of the via structure in some other examples.

[0049] Figure 6-3 This is a schematic diagram of the via structure in some other examples.

[0050] Figure 6-4 This is a schematic diagram of the via structure in some other examples.

[0051] Figure 6-5 This is a schematic diagram of the via structure in some other examples.

[0052] Figure 7 This is a schematic diagram of the via structure in some other examples.

[0053] Reference numerals: 100, multilayer circuit board; 101, non-conductive layer; 102, conductive layer; 103, cross-layer conductive structure; 104, electroplated layer. Detailed Implementation

[0054] The following is combined Figures 1-1 to 7 The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0055] In the description of this application, it should be understood that the use of terms such as "center," "middle," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" to indicate orientation or positional relationships is based on the orientation or positional relationships shown in the accompanying drawings and is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, features defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0056] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0057] This application relates to a PCB, which includes a multilayer circuit board 100. The multilayer circuit board 100 has vias, which are formed into stepped holes of different inner diameters by controlled-depth drilling. Specifically, the vias are provided with non-conductive layers 101 and conductive layers 102. The conductive layers 102 are provided in at least two layers, and the non-conductive layers 101 are provided in at least three layers. The non-conductive layers 101 and conductive layers 102 are alternately arranged, and the non-conductive layers 101 separate the conductive layers 102 to prevent electrical series connection.

[0058] Understandably, the non-conductive layer 101 is formed by vacuum filling the vias with non-conductive resin to separate different networks. The conductive layer 102 is formed by vacuum filling the vias with conductive paste to make different networks conductive, so as to realize the formation of multiple different interlayer network connections within a single via, and to achieve a network connectivity structure with multiple network traces within a single via.

[0059] Furthermore, in conjunction with the appendix Figure 2-1 In the example shown, a cross-layer conductive structure 103 is provided in the via. The cross-layer conductive structure 103 is formed by vacuum filling the via with conductive paste. The cross-layer conductive structure 103 penetrates at least one non-conductive layer 101. The PCB achieves cross-layer network conduction through the cross-layer conductive structure 103.

[0060] In some examples, when the cross-layer conductive structure 103 penetrates at least two non-conductive layers 101, it also penetrates at least one conductive layer 102. To prevent network connectivity between the cross-layer conductive structure 103 and the penetrated conductive layer 102, a non-conductive isolation structure is provided in the via. This non-conductive isolation structure is disposed in the borehole formed by penetrating the non-conductive layer 101 and the conductive layer 102. The non-conductive isolation structure is shaped like a cylinder, and the cross-layer conductive structure 103 penetrates through it. In this case, the non-conductive isolation structure isolates the cross-layer conductive structure 103 from the penetrated conductive layer 102.

[0061] It is understandable that a hole penetrating the non-conductive layer 101 and the conductive layer 102 is obtained by controlled-depth drilling, and then the hole is filled by vacuum plugging and curing with non-conductive resin. Finally, a hole for arranging the cross-layer conductive structure 103 is obtained by controlled-depth drilling.

[0062] In some examples, combined with appendix Figure 2-1 and attached Figure 2-2 In the example shown, the conductive layer 102 in the PCB via is connected to the electroplated layer 104 on the surface of the multilayer circuit board 100 via a cross-layer conductive structure 103. In this case, holes are drilled to the conductive layer 102 to be connected across layers using controlled-depth drilling. After the cross-layer conductive structure 103 is placed, the surface of the multilayer circuit board 100 is subjected to outer layer electroplating and pattern etching to achieve cross-layer network connectivity, thereby achieving overall board network connectivity.

[0063] Furthermore, if the cross-layer conductive structure 103 penetrates both the non-conductive layer 101 and the conductive layer 102, a non-conductive isolation structure is also required.

[0064] In some examples, combined with appendix Figure 3-1 and attached Figure 3-2 In the example shown, two conductive layers 102 of different layers in a PCB via are connected by a cross-layer conductive structure 103. In this case, a hole is drilled to the conductive layer 102 to be connected by controlled-depth drilling. The cross-layer conductive structure 103 is then arranged. One end of the cross-layer conductive structure 103 is connected to the conductive layer 102 to which the hole is drilled, and a stepped hole is drilled at the other end of the cross-layer conductive structure 103 by controlled-depth drilling. The hole is then vacuum-sealed and cured with conductive paste, forming a conductive layer 102 at the other end of the cross-layer conductive structure 103, thereby achieving cross-layer network connectivity.

[0065] Furthermore, if the cross-layer conductive structure 103 penetrates both the non-conductive layer 101 and the conductive layer 102, a non-conductive isolation structure is also required.

[0066] In some examples, two conductive layers 102 of different layers in a PCB via are connected by a cross-layer conductive structure 103 network. At least two such structures are provided to achieve cross-layer network connectivity at least two locations in the via.

[0067] In some examples, the PCB can also be designed to: combine with... Figure 4-1 and attached Figure 4-2 In the example shown, different conductive layers 102 are designed in the vias to achieve cross-layer network connectivity through cross-layer conductive structures 103, and another conductive layer 102 is connected to the electroplated layer 104 on the surface of the multilayer circuit board 100 through the cross-layer conductive structures 103. It can be understood that the electroplated layer 104 also serves as a conductive layer 102.

[0068] It should be noted that the appendix Figure 5 To be continued Figure 7 The structure shown is the form of a via in some examples.

[0069] The manufacturing process of this application is described in detail below with reference to specific embodiments. It should be noted that the following description is only an illustrative example and not a specific limitation of this application.

[0070] This application relates to a PCB via fabrication process that enables multiple traces to be routed through a single via on a PCB, significantly increasing the wiring density of the product. Specifically, a via is drilled at the same location on a multilayer circuit board to achieve multiple interlayer network connections through a single via, enabling multiple network traces to be routed.

[0071] Before proceeding with the manufacturing process, a multi-layer circuit board is first made, combined with the attached... Figure 1-1 and attached Figure 1-2 The example shown illustrates the following manufacturing process.

[0072] S1, Drilling through holes on a multilayer circuit board, with a drill bit diameter of A.

[0073] S2, electroplating inside the through hole is conductive.

[0074] S3, vacuum plugging and curing of the through holes with non-conductive resin, the non-conductive resin fills the through holes.

[0075] S4. Drill a stepped hole 1 with controlled depth from one end of the through hole. The drill bit diameter is B1, and B1 > A. The drilling depth is determined according to the network. The drilling depth is less than the depth of the through hole. Excess non-conductive resin in the through hole is removed by controlled depth drilling.

[0076] S5, Vacuum plugging and curing of the stepped hole 1 with conductive paste, the conductive paste filling the drilled hole obtained in step S4.

[0077] S6, drill a stepped hole 2 at stepped hole 1 with controlled depth. The drill bit diameter is B2, and B2 > B1. The drilling depth is determined according to the network. The drilling depth is less than the drilling depth in step S4. Remove excess conductive paste in stepped hole 1 by using a hollow drilling method.

[0078] S7, vacuum plug the stepped hole 2 with non-conductive resin and cure it, the non-conductive resin fills the hole obtained in step S6.

[0079] S8, perform steps S4 to S7 at least N times to control the depth of drilling step hole 2N+1 and step hole 2(N+1), with a drill bit diameter of B. 2N+1 and B 2(N+1) And B 2(N+1) >B 2N+1 Where N≥1, N is an integer, and the value of N depends on the design requirements of the PCB.

[0080] Furthermore, after the PCB is filled with vias, the outer layer of the multilayer circuit board is electroplated to obtain the surface electroplating layer.

[0081] Understandably, after step S4, a non-conductive layer is obtained. After step S6, a conductive layer is obtained on top of the non-conductive layer, and the conductive layer achieves network connectivity. Therefore, in step S8, each time steps S4 to S7 are performed, a non-conductive layer and a conductive layer are obtained, achieving network connectivity and layering. By repeating steps S4 to S7, the obtained borehole has an alternating structure of conductive and non-conductive layers, forming a multi-layered network connectivity structure, enabling multiple lines to run through a single borehole.

[0082] It should be noted that after obtaining a non-conductive layer in step S4, non-conductive resin is deeply filled into the stepped hole to isolate the conductive layer obtained in step S6 from the electroplated layer on the inner wall of the via. Alternatively, after obtaining a non-conductive layer in step S4, non-conductive resin is filled into the stepped hole, and then steps S5 and S6 are performed, which can also achieve the isolation between the conductive layer obtained in step S6 and the electroplated layer on the inner wall of the via.

[0083] Combined with appendix Figure 1-1 and attached Figure 1-2 In the example shown, after completing steps S4 to S7, stepped via 1 and stepped via 2 are obtained. In step S8, steps S4 to S7 are performed twice to obtain stepped via 3, stepped via 4, stepped via 5, and stepped via 6. A total of three conductive layers and four non-conductive layers are obtained from the PCB vias.

[0084] In one implementation, after completing step S8, step S9 is performed. Specifically, in step S9, the depth of the borehole is controlled to the conductive layer of the stepped hole 2i-1, obtaining borehole 1, where i ≥ 1, i is an integer, the drill bit diameter is C, and C < B. 2i-1 .

[0085] The drilling depth in step S9 is determined according to the network, and the drill hole 1 can obtain an annular concave area at the conductive layer of the stepped hole 2i-1, and the drill hole 1 is vacuum plugged and cured with non-conductive resin.

[0086] Further, in step S10, a controlled-depth drill hole is drilled to the conductive layer of the stepped hole 2i-1. The drilling depth is determined according to the network to obtain hole 2. The drill diameter is D, and D < C. The hole 2 is then vacuum plugged and cured with conductive paste.

[0087] It is understandable that after the non-conductive resin filled in step S9 is cured, a non-conductive isolation structure in the PCB is obtained through controlled-depth drilling in step 10, and after the conductive paste filled in step S10 is cured, a cross-layer conductive structure is obtained.

[0088] To ensure network connectivity between the cross-layer conductive structure and the conductive layer of the stepped hole 2i-1, the depth of drill hole 2 is greater than the depth of drill hole 1. This ensures that during controlled-depth drilling of drill hole 2, the non-conductive resin adhering to the conductive layer of the stepped hole 2i-1 is removed, thus ensuring full conductivity between the cross-layer conductive structure and the conductive layer of the stepped hole 2i-1.

[0089] Combined with appendix Figure 1-3 and attached Figure 1-4 In the example shown, step S9 involves drilling to the conductive layer of the stepped hole 2, and step S10 involves drilling to the conductive layer of the stepped hole 2, with the drilling depth in step S10 being greater than the drilling depth in step S9.

[0090] In some examples, after completing step S10, the outer layer of the multilayer circuit board is electroplated, and the surface pattern of the multilayer circuit board is etched to form an electroplated layer on the surface of the multilayer circuit board. The conductive layer of the stepped via 2i-1 is connected to the electroplated layer network on the surface of the multilayer circuit board through a cross-layer conductive structure, thereby achieving a complete network conductive connection of the entire board. (See attached figure.) Figure 1-5 and attached Figure 2-1 The example shown is a PCB where the conductive layer in the via is connected to the electroplated layer through a cross-layer conductive structure network.

[0091] Regarding the process of step S10, as an alternative, it can also be designed as follows: when drilling to the conductive layer of the stepped hole 2i-1, further drill to the non-conductive layer below the conductive layer of the stepped hole 2i-1. In this case, combined with the attached... Figure 2-1In the example shown, due to the isolation of the next non-conductive layer, the cross-layer conductive structure formed by the conductive paste can achieve cross-layer network connectivity between the conductive layer of the stepped hole 2i-1 and other conductive layers.

[0092] In one implementation, after completing step S10, step S11 is performed. Step S11 involves performing step S8 at least once, i.e., performing steps S4 to S7 at least once, and the number of repetitions depends on the PCB design requirements. In this case, after achieving cross-layer network connectivity using cross-layer conductive structures in the vias, a multi-layer network connectivity structure is further obtained.

[0093] Furthermore, after completing step S11, the outer layer of the multilayer circuit board is electroplated to achieve the overall network conductivity connection.

[0094] Combined with appendix Figure 3-1 In the example shown, step S8 is performed once in step S11, where N=1, resulting in a conductive layer and a non-conductive layer, with the conductive layer connected to the interlayer conductive structure network. (Appendix) Figure 3-2 In the example shown, step S8 is performed twice in step S11, where N=1, to obtain two conductive layers and two non-conductive layers, with the conductive and non-conductive layers alternating.

[0095] In one implementation, after completing step S11, step S12 is performed. Specifically, step S12 involves performing steps S8, S9, and S10 at least once, and the number of repetitions depends on the PCB design requirements. This results in at least two cross-layer conductive structures within the vias, achieving at least two cross-layer network connections when layered network connectivity is achieved using conductive layers.

[0096] Furthermore, after completing step S12, the outer layer of the multilayer circuit board is electroplated to achieve the overall network conductivity connection.

[0097] Combined with appendix Figure 4-1 In the example shown, step S12 is performed once, and a network connectivity structure with two cross-layer conductive structures is obtained by drilling the PCB.

[0098] In some examples, when step S12 is performed on at least both sides, at least one step S8 is performed during the phase after the previous step S12 is completed and before the next step S12 begins, thereby realizing a hierarchical network conduction structure between two adjacent cross-layer network conduction structures.

[0099] Combined with appendix Figure 4-2 In the example shown, step S12 is performed twice, with step S8 performed once between the two steps S12, and N = 1.

[0100] As one implementation method, if the outer layer of the multilayer circuit board is electroplated after completing steps S1 to S8, then without further fabricating a cross-layer conductive structure, a multilayer layered network conductive structure can be formed in the drill holes of the PCB. (See attached diagram.) Figure 5 In the example shown, step S8 is performed three times from step S4 to step S7, and based on step hole 1 and step hole 2, step hole 3, step hole 4, step hole 5, step hole 6, step hole 7 and step hole 8 (step holes 1-8, not labeled in the figure) are further obtained.

[0101] In one implementation, step S4 can also be alternatively designed as follows: drilling stepped holes 1 with controlled depth from both ends of the through hole. In this case, a non-conductive layer is formed in the middle of the through hole, and steps S4 and S5 are performed from the middle of the through hole to both ends. Thus, a structure combining a non-conductive layer and a conductive layer can be obtained from the middle of the through hole to both ends.

[0102] Furthermore, when stepped holes are drilled at controlled depths at both ends of the through hole, step S8 is performed at both ends of the through hole, thereby obtaining a structure of alternating non-conductive and conductive layers from the middle of the through hole to both ends.

[0103] In some examples, when stepped holes are drilled at both ends of a through-hole with controlled depth, steps S8, S9, and S10 are performed on at least one end of the through-hole to obtain a cross-layer conductive structure. Furthermore, steps S8, S9, and S10 are performed at least once, and the number of repetitions depends on the PCB design requirements.

[0104] Combined with appendix Figure 6-1 In the example shown, steps S8, S9 and S10 are performed from the middle of the via to both ends, and the outer layer of the multilayer circuit board is electroplated to obtain a structure in which the conductive layers at both ends of the via are connected to the electroplated layer through a cross-layer conductive structure network.

[0105] Combined with appendix Figure 6-2 In the example shown, steps S8, S9, S10 and S11 are performed from the middle of the via to both ends, and the outer layer of the multilayer circuit board is electroplated to obtain a structure in which different conductive layers at both ends of the via are interconnected through a cross-layer conductive structure.

[0106] Combined with appendix Figure 6-3 In the example shown, steps S8, S9 and S10 are performed at one end of the via, step S8 is performed at the other end of the via, and the outer layer of the multilayer circuit board is electroplated to obtain a structure in which one end of the via has an internal conductive layer connected to the electroplated layer through a cross-layer conductive structure network, and the other end of the via has a structure in which multiple conductive layers are connected by a layered network.

[0107] Combined with appendix Figure 6-4 In the example shown, steps S8, S9, S10 and S11 are performed on one end of the via, and step S8 is performed on the other end of the via. The outer layer of the multilayer circuit board is electroplated to obtain a structure in which different conductive layers are connected through a cross-layer conductive structure at one end of the via, and a structure in which multiple conductive layers are connected in a layered network at the other end of the via.

[0108] In some examples, step S8 is performed from the middle of the via towards both ends, but steps S9 and S10 are not performed, and the via does not have a cross-layer conductive structure. (See attached...) Figure 6-5 The example shown illustrates a structure in which both ends of the via are connected by a layered network with multiple conductive layers.

[0109] As one implementation method, when stepped holes are drilled at controlled depths at both ends of the through hole, steps S1 to S4 in the manufacturing process can be replaced as follows.

[0110] S1, Drill through holes on a multilayer circuit board with a drill diameter of A, vacuum plug the through holes with conductive paste and cure it, and the conductive paste fills the through holes.

[0111] S2, drill stepped holes M from both ends of the through hole with controlled depth. The drill bit diameter is E, and E > A. The drilling depth is determined according to the network. The sum of the drilling depths at both ends of the through hole is less than the depth of the through hole. The excess conductive paste in the through hole is removed by hollow drilling, so that a conductive layer can be formed in the middle of the through hole.

[0112] S3, vacuum plugging and curing of non-conductive resin into the stepped hole M, the non-conductive resin filling the stepped hole M.

[0113] S4, drill step hole 1 at step hole M with controlled depth, the drill bit diameter is B1 and B1>E, the drilling depth is determined according to the network, and the excess non-conductive resin in step hole M is removed by empty deep drilling, so that non-conductive layers are formed on both sides of the conductive layer in the middle of the through hole.

[0114] After completing step S4, proceed to steps S5, S6, S7, and S8 to achieve network connectivity and layering. It should be noted that in step S8, when drilling stepped holes at both ends of the through-hole with controlled depth, the number of times N is performed in steps S4 to S7 can be the same or different.

[0115] In some examples, depending on the actual design requirements of the PCB, the processing flow at both ends of the through-hole can be selected from the following options: steps S9 and S10; steps S9, S10, and S11; or steps S9, S10, S11, and S12. It is understood that after the network connection is completed within the drilled holes at both ends of the through-hole, the multilayer circuit board undergoes outer layer electroplating.

[0116] Combined with appendix Figure 7 In the example shown, the via of the PCB has a conductive layer in the middle and non-conductive layers on both sides, and steps S4 to S10 are performed from the middle of the via to both ends. After completion, the outer layer of the multilayer circuit board is electroplated, and the two ends of the via have a structure with an internal conductive layer connected to the electroplated layer through a cross-layer conductive structure network.

[0117] In the description of this specification, the use of terms such as "an embodiment," "some examples," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0118] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

[0119] In the description of this application, the presence of a comma ("、") in the patent title indicates an "and" relationship, not an "or" relationship. For example, if the patent title is "A and B", it means that the content claimed in this application is: a technical solution with the subject matter title A and a technical solution with the subject matter title B.

Claims

1. A manufacturing process for PCB via plugging, characterized in that: The workflow of the manufacturing process includes S1, Drilling through holes on a multilayer circuit board, with a drill bit diameter of A; S2, electroplating inside the through hole is conductive; S3, vacuum plugging and curing of the through holes with non-conductive resin; S4, drill the stepped hole 1 from one end of the through hole or drill the stepped hole 1 from both ends of the through hole, with the drill bit diameter being B1 and B1 > A; S5, Vacuum plugging and curing of the stepped hole 1 with conductive paste; S6, drill step hole 2 at step hole 1 with controlled depth, the drill bit diameter is B2, and B2>B1; S7, Vacuum plugging and curing of the stepped hole 2 with non-conductive resin; S8, perform steps S4 to S7 at least N times, controlling the depth of drilled stepped holes 2N+1 and 2N+2, with a drill bit diameter of B. 2N+1 and B 2（N+1） And B 2（N+1） >B 2N+1 N≥1, N is an integer; After the PCB is filled with vias, the outer layer of the multilayer circuit board is electroplated.

2. The PCB via-filling manufacturing process according to claim 1, characterized in that: Perform step S9, drill a controlled-depth hole to the conductive layer of the stepped hole 2i-1, obtaining hole 1, where i ≥ 1, i is an integer, the drill bit diameter is C, and C < B. 2i-1 The borehole 1 was vacuum plugged and cured with non-conductive resin.

3. The PCB via-filling manufacturing process according to claim 2, characterized in that: In step S10, drill a hole to the conductive layer of the stepped hole 2i-1 or further drill a hole to the non-conductive layer below the conductive layer of the stepped hole 2i-1 to obtain a hole 2. The diameter of the drill bit is D, and D < C. Vacuum plug the hole 2 with conductive paste and cure it.

4. The PCB via-filling manufacturing process according to claim 3, characterized in that: Proceed to step S11, which involves performing step S8 at least once.

5. The PCB via-filling manufacturing process according to claim 4, characterized in that: Proceed to step S12, which involves performing steps S8, S9, and S10 at least once.

6. The PCB via-filling manufacturing process according to any one of claims 3 to 5, characterized in that: When stepped holes are drilled at both ends of a through hole with controlled depth, the drilling at at least one end of the through hole shall be performed at least once through steps S8, S9 and S10.

7. The PCB via-filling manufacturing process according to any one of claims 1 to 5, characterized in that: With stepped holes drilled at controlled depths at both ends of the through hole, the workflow of the manufacturing process is redesigned as follows: S1, Drill through holes on a multilayer circuit board with a drill diameter of A, and use conductive paste to vacuum plug the through holes and then cure them. S2, drill stepped holes M from both ends of the through hole with controlled depth, the drill bit diameter is E, and E>A; S3, Vacuum plugging and curing of the stepped hole M with non-conductive resin; S4, control the depth of drilling step hole 1 at step hole M, with drill bit diameter B1 and B1>E; S5, Vacuum plugging and curing of the stepped hole 1 with conductive paste; S6, drill step hole 2 at step hole 1 with controlled depth, the drill bit diameter is B2, and B2>B1; S7, Vacuum plugging and curing of the stepped hole 2 with non-conductive resin; S8, perform steps S4 to S7 at least N times, controlling the depth of drilled stepped holes 2N+1 and 2N+2, with a drill bit diameter of B. 2N+1 and B 2（N+1） And B 2（N+1） >B 2N+1 ; Where N≥1, and N is an integer.

8. A PCB manufactured using the PCB via-filling process according to any one of claims 1-7, characterized in that: The PCB includes a multilayer circuit board with vias. The vias are formed by drilling with controlled depth to create stepped holes of different inner diameters. The vias contain non-conductive layers and conductive layers. There are at least two conductive layers and at least three non-conductive layers, with the non-conductive and conductive layers alternating.

9. The PCB according to claim 8, characterized in that: The via is provided with a cross-layer conductive structure, which penetrates at least one of the non-conductive layers, so that the conductive layer in the via is connected to the electroplated layer network on the surface of the multilayer circuit board through the cross-layer conductive structure.

10. The PCB according to claim 9, characterized in that: When the cross-layer conductive structure penetrates at least one of the conductive layers, a non-conductive isolation structure is provided in the via, the non-conductive isolation structure is formed into a cylindrical shape, and the cross-layer conductive structure penetrates the non-conductive isolation structure.

Images