Semiconductor structure and method of forming the same

Abstract

Disclosed are a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes forming a mask layer on a substrate, the mask layer and the substrate having an opening; forming an isolation structure in the opening; removing the mask layer; forming a first conductive layer on the isolation structure and the substrate; performing a first implantation process on the first conductive layer and the isolation structure to form a doped portion in the first conductive layer and a doped portion in the isolation structure; forming a second conductive layer on the first conductive layer and the isolation structure; and performing a first planarization process so that the top surfaces of the second conductive layer, the first conductive layer and the isolation structure are flush. The present application can effectively adjust the aspect ratio of the opening and / or the trench, thereby reducing the probability of voids or seams in the material filled into the opening and / or the trench, and also enabling the upper portion of the opening and / or the trench to have a greater width, thereby further improving the filling capacity of the filling process.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of forming them, and in particular to semiconductor structures and methods of forming them that can be used as memory devices. Background Technology

[0002] As semiconductor devices become increasingly miniaturized, the size of memory devices continues to shrink, leading to increased capacitive coupling between adjacent components or interconnect structures, resulting in leakage current and / or short circuits. Furthermore, the continuous reduction in size makes infill processes more difficult, often creating voids or seams within the filled material, which negatively impacts the reliability and electrical performance of the subsequently formed memory devices. Summary of the Invention

[0003] In view of the above problems, this invention improves the uniformity of the planarization process, thereby enhancing the accuracy of controlling the etching depth in the subsequent etching process. This effectively adjusts the aspect ratio of the openings and / or trenches, reducing the probability of voids or seams in the material filling the openings and / or trenches. Furthermore, this invention combines the implantation process with the planarization process to perform a rounding process. Therefore, the upper part of the openings and / or trenches can have a larger width, further improving the filling capacity of the filling process.

[0004] According to some embodiments, a method for forming a semiconductor structure is provided, comprising: forming a mask layer on a substrate, wherein the mask layer and the substrate have openings; forming an isolation structure in the openings; removing the mask layer; forming a first conductive layer on the isolation structure and the substrate; performing a first implantation process on the first conductive layer and the isolation structure to form a doped portion in the first conductive layer and in the isolation structure; forming a second conductive layer on the first conductive layer and the isolation structure; and performing a first planarization process to make the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure flush.

[0005] According to some embodiments, a semiconductor structure is provided, including: a substrate, a pad, a first conductive layer, a second conductive layer, an interlayer dielectric layer, and a control gate. The pad is disposed on the substrate. The first conductive layer is disposed on the pad. The second conductive layer is disposed on the first conductive layer. The interlayer dielectric layer is disposed on the first conductive layer and the second conductive layer, and contacts the top surfaces of the first conductive layer and the second conductive layer. The control gate is disposed on the interlayer dielectric layer. Attached Figure Description

[0006] Figures 1 to 13 The diagram illustrates cross-sectional views of the semiconductor structure being formed at various stages, according to some embodiments of the present invention.

[0007] Figure Labels

[0008] 1: Semiconductor Structure

[0009] 100:Substrate

[0010] 101: First Opening

[0011] 102: Second opening

[0012] 110: Padding

[0013] 120: Masking layer

[0014] 120°C, 200°C, 410°C: Corner

[0015] 130: Lining

[0016] 130A, 200A, 410A: Doped portion

[0017] 130B, 200B, 410B, 500B: Remaining portion

[0018] 140: Bottom isolation structure

[0019] 200: Isolation Structure

[0020] 300: concave part

[0021] 400, 410: First conductive layer

[0022] 410S: Side surface

[0023] 500: Second conductive layer

[0024] 501: Opening

[0025] 600: Interlayer dielectric layer

[0026] 700: Third conductive layer

[0027] a1: First angle

[0028] a2: Second angle

[0029] a3: Third angle

[0030] AA: Active Zone

[0031] h: height

[0032] P1: First Implantation Process

[0033] P2: Second implantation process

[0034] P3: Third Implantation Technique

[0035] PA: Surrounding Area

[0036] t1: First thickness

[0037] t2: Second thickness

[0038] t3: Third thickness

[0039] t4: Fourth thickness

[0040] w1: First width

[0041] w2: Second width

[0042] w3: Third width

[0043] w4: Fourth width

[0044] w5: Fifth width Detailed Implementation

[0045] Reference Figure 1 A substrate 100 is provided. The substrate 100 may include an active region AA and a peripheral region PA. The active region AA may include active elements such as flash memory cells and isolation structures that isolate the active elements from each other. The peripheral region PA may surround the active region AA. In some embodiments, circuitry connecting the active elements may be disposed in the peripheral region PA.

[0046] A pad 110 and a mask layer 120 are sequentially formed on a substrate 100. Next, the mask layer 120, the pad 110, and the substrate 100 are patterned to form openings in the mask layer 120, the pad 110, and the substrate 100. Then, a liner 130 is compliantly formed in the openings. In some embodiments, a portion of the liner 130 is removed to expose the top surface of the mask layer 120. The liner 130 may be compliantly formed in a first opening 101 in the active region AA and a second opening 102 in the peripheral region PA. The depth and / or width of the first opening 101 may be smaller than the depth and / or width of the second opening 102.

[0047] The substrate 100 may be a silicon wafer, a bulk semiconductor, or a semiconductor-on-insulation (SOI) substrate. Other types of substrates 100 include, for example, multilayer substrates or gradient substrates. The substrate 100 may be an elemental semiconductor, a compound semiconductor, or an alloy semiconductor, but this application is not limited thereto. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate.

[0048] The pad 110, mask layer 120, and / or liner 130 may comprise oxides, nitrides, oxynitrides, combinations thereof, or any other suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, any other suitable dielectric materials, or combinations thereof. High-k dielectric materials may be metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium silicates, or zirconium aluminates. In some embodiments, the pad 110 may be silicon oxide, the mask layer 120 may be silicon nitride, and the liner 130 may be a high-temperature oxide (HTO) or silicon oxide. In some embodiments, additional mask layers may be included.

[0049] The pad 110, the masking layer 120, and / or the liner 130 can be formed by a deposition process or a thermal oxidation process. The aforementioned deposition process may include a chemical vapor deposition (CVD) process.

[0050] Reference Figure 2 A bottom isolation structure 140 is formed in the first opening 101 and the second opening 102. In some embodiments, in the active region AA, the top surface of the bottom isolation structure 140 is lower than the bottom surface of the pad 110. In some embodiments, in the peripheral region PA, the top surface of the bottom isolation structure 140 is higher than the top surface of the pad 110. The forming process and materials of the bottom isolation structure 140 may be the same as or different from those of the pad 110, the mask layer 120, and / or the liner 130. The bottom isolation structure 140 may be silicon oxide. In some embodiments, the bottom isolation structure 140 may be formed by a liquid filling process to avoid the problem of voids easily generated due to a high aspect ratio. Therefore, the top surface of the bottom isolation structure 140 in the active region AA may be lower than the top surface of the bottom isolation structure 140 in the peripheral region PA. The top surface of the bottom isolation structure 140 in the active region AA can be lower than the top surface of the substrate 100, thus leaving sufficient space above the bottom isolation structure 140 for the subsequent formation of the control dielectric layer and control gate, and avoiding compression of the floating gate's placement space during the formation of the control dielectric layer. The top surface of the bottom isolation structure 140 in the peripheral region PA can be higher than the top surface of the substrate 100, thus avoiding the problem of the substrate 100 being easily damaged during the implantation process due to the relatively open space in the peripheral region PA. In other words, the bottom isolation structure 140 in the peripheral region PA can prevent damage to the top surface of the substrate 100 during the implantation process. The density of the substrate 130 can be greater than that of the bottom isolation structure 140, thus improving the insulation and isolation performance of the semiconductor device, thereby improving reliability.

[0051] like Figure 2As shown, the isolation structure 200 is formed in a blanket manner on the first opening 101, the second opening 102, and the masking layer 120. Specifically, the isolation structure 200 may be formed on the bottom isolation structure 140, the liner 130, and the masking layer 120. The formation process and materials of the isolation structure 200 may be the same as or different from those of the pad 110, the masking layer 120, the liner 130, and / or the bottom isolation structure 140. The isolation structure 200 may be, for example, silicon oxide and may be silicon oxide formed by a high-density plasma chemical vapor deposition (HDP-CVD) process. In some embodiments, the bottom isolation structure 140 and the isolation structure 200 may be formed simultaneously by HDP-CVD.

[0052] Next, a first implantation process P1 is performed on the isolation structure 200 and the masking layer 120 at a first angle a1, therefore, as Figure 2 One part of the structure shown will become a natural mask for another part, so the process of forming an additional mask can be omitted during the first implantation process P1.

[0053] Reference Figure 3 A second implantation process P2 is performed on the isolation structure 200 and the masking layer 120 at a second angle a2, different from the first angle a1. The first implantation process P1 and / or the second implantation process P2 can be ion implantation processes, and P-type dopants such as boron (B), aluminum (Al), and gallium (Ga), or N-type dopants such as nitrogen (N), phosphorus (P), and arsenic (As), or dopants such as argon (Ar) can be implanted according to the requirements of the implantation process. Therefore, dopants of different atomic weights can be selected to bombard dielectric layers (e.g., masking layer 120) comprising different materials to break the molecular bonds of the dielectric layer accordingly.

[0054] The implantation energy, dopant type, and dopant concentration of the first implantation process P1 and the second implantation process P2 may be the same or different. The molecular weight of the dopant in the first implantation process P1 and the second implantation process P2 may be greater than the molecular weight of the isolation structure 200 and the masking layer 120. Therefore, after performing the first implantation process P1 and the second implantation process P2, the structure of the upper part of the isolation structure 200 and the upper part of the masking layer 120 is damaged and becomes looser. In some embodiments, nitrogen gas (N2) is introduced into the first implantation process P1 and the second implantation process P2 to dope nitrogen (N) atoms into the upper part of the isolation structure 200 and the masking layer 120.

[0055] In some embodiments, the first angle a1 may be greater than 0 degrees and less than 90 degrees, and the second angle a2 may be greater than 90 degrees. In some embodiments, the first angle a1 may be 1 to 45 degrees. For example, the first angle a1 may be 1 degree, 15 degrees, 30 degrees, 45 degrees, or any combination of the aforementioned values. In some embodiments, the second angle a2 may be 135 to 179 degrees. For example, the second angle a2 may be 135 degrees, 150 degrees, 165 degrees, 179 degrees, or any combination of the aforementioned values. The first angle a1 and the second angle a2 may be complementary angles. In other words, the sum of the first angle a1 and the second angle a2 is 180 degrees. By using a first implantation process P1 and a second implantation process P2, which respectively have the first angle a1 and the second angle a2, the angle of arrival is controlled, thereby avoiding damage to the integrity of the active region or other components located below the isolation structure 200 and the mask layer 120, thereby improving the reliability of the semiconductor structure.

[0056] In some embodiments, with the normal direction of the substrate 100 as the axis of symmetry, the implantation angle of the first implantation process P1 and the implantation angle of the second implantation process P2 may be symmetrical or asymmetrical.

[0057] Reference Figure 4 A planarization process is performed to make the top surface of the isolation structure 200 and the top surface of the masking layer 120 flush. In some embodiments, the planarization process may be a chemical mechanical polishing (CMP) process.

[0058] After the planarization process, the upper parts of the isolation structure 200 and the masking layer 120 are rounded due to the disruption of the upper parts of the isolation structure 200 and the masking layer 120 by the first implantation process P1 and the second implantation process P2, and a recess 300 is formed on the top surface of the isolation structure 200 and the top surface of the masking layer 120. In some embodiments, the recess 300 is located at the interface between the side surface of the isolation structure 200 and the side surface of the masking layer 120. In some embodiments, the recess 300 is formed between the corner 200C of the isolation structure 200 and the corner 120C of the masking layer 120. After the chemical mechanical polishing process, the top surface of the liner 130 may be lower than the top surface of the isolation structure 200 and the masking layer 120.

[0059] In detail, because the top surfaces of the isolation structure 200 and the masking layer 120 are damaged, the corners 200C of the isolation structure 200 and the corners 120C of the masking layer 120 will be rounded after a chemical mechanical polishing process using a polishing slurry. This is because, since the first implantation process P1 has a first angle a1 and the second implantation process P2 has a second angle a2, based on the principle of the angle of arrival, the corners 200C of the isolation structure 200 and the corners 120C of the masking layer 120 are subject to a higher degree of doping damage from the implantation process, resulting in a looser structure for the corners 200C and 120C. Therefore, after the chemical mechanical polishing process, the corners 200C of the isolation structure 200 and the corners 120C of the masking layer 120 can be rounded. The curvature radii of corners 200C and 120C can be controlled based on the parameters of the first implantation process P1, the second implantation process P2, and the chemical mechanical polishing process.

[0060] In subsequent processes, the mask layer 120 is removed, and a first conductive layer and a second conductive layer are disposed at the original location where the mask layer 120 was. Therefore, when the corner 200C of the isolation structure 200 adjacent to the mask layer 120 is an arc corner, it is easier to fill and / or deposit the first conductive layer and the second conductive layer to form the floating gate. Thus, the probability of voids and / or seams in the floating gate can be reduced, thereby improving the yield and reliability of the semiconductor process.

[0061] Reference Figure 3 and Figure 4 In embodiments where the implantation angle of the first implantation process P1 is symmetrical to that of the second implantation process P2, the recess 300 may have a symmetrical profile with the normal direction of the substrate 100 as the axis of symmetry. In embodiments where the implantation angles of the first implantation process P1 and the second implantation process P2 are asymmetrical, the recess 300 may have an asymmetrical profile with the normal direction of the substrate 100 as the axis of symmetry. Therefore, further doping processes can be performed to adjust the electrical properties. For example, the asymmetrical profile of the recess 300 will affect the shape of the subsequently formed floating gate. Therefore, a doping process can be performed on the subsequently formed floating gate to form a PN junction in the floating gate, thereby improving the electron mobility and / or the switching rate of the on-state of the semiconductor structure.

[0062] Reference Figure 5After rounding the corners of the isolation structure 200 and the masking layer 120, the masking layer 120 is removed to expose the side surfaces of the isolation structure 200 and the liner 130. In some embodiments, a portion of the side surface of the liner 130 is covered by the substrate 100, exposing another portion of the side surface of the liner 130. In some embodiments, the liner 130 and the isolation structure 200 protrude upward from the substrate 100.

[0063] The removal process may include etching processes, such as dry etching, wet etching, or other suitable etching methods. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using acidic solutions, alkaline solutions, or solvents to remove at least a portion of the structure to be removed. Furthermore, the etching process may also be purely chemical etching, purely physical etching, or any combination thereof. In some embodiments, a wet etching process is used to remove the rounded mask layer 120.

[0064] A portion of the upper part of the liner 130 may be further removed, causing the liner 130 to shrink upwards. For example, the liner 130 may be thinned so that the liner 130 has a decreasing thickness in a direction away from the substrate 100. In some embodiments, the lower portion of the liner 130 may have a first thickness t1, and the upper portion of the liner 130 may have a gradually decreasing second thickness t2, and the first thickness t1 may be greater than the second thickness t2. In some embodiments, the liner 130 may have a pointed portion.

[0065] Removing the rounded masking layer 120 and removing a portion of the upper part of the substrate 130 can be done in the same process or in different processes. For example, the rounded masking layer 120 can be removed simultaneously with the removal of the upper part of the substrate 130. Alternatively, the rounded masking layer 120 can be removed first, followed by the removal of the upper part of the substrate 130. Depending on the shape of the floating gate to be formed, further removal processes can be performed to adjust the contour of the substrate 130.

[0066] Reference Figure 6 A first conductive layer 400 is formed on the top and side surfaces of the isolation structure 200 and the substrate 100. The first conductive layer 400 can be conformally formed on the top and side surfaces of the pad 110, the liner 130, and the isolation structure 200. The first conductive layer 400 may have a third thickness t3. The third thickness t3 of the first conductive layer 400 located in the active region AA may be greater than the thickness of the first conductive layer 400 located in the peripheral region PA.

[0067] The first conductive layer 400 may include polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, combinations thereof, or other suitable materials, but this application is not limited thereto. In some embodiments, the first conductive layer 400 may include undoped or doped polycrystalline silicon to adjust the electrical properties of the first conductive layer 400 by means of dopant. The first conductive layer 400 may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

[0068] like Figure 6 As shown, since the upper part of the isolation structure 200 has an arc-shaped corner 200C and a recess 300, and the liner 130 has a second thickness t2 that decreases upwards, the first conductive layer 400 can be formed more easily according to the aforementioned contour. Specifically, because the isolation structure 200 has the arc-shaped corner 200C and the recess 300, the stepped coverage of the first conductive layer 400 over the isolation structure 200 and the liner 130 can be improved, thereby enhancing the reliability of the first conductive layer 400.

[0069] Furthermore, since the liner 130 has a second thickness t2 that decreases upwards, the aspect ratio and profile of the trench between adjacent isolation structures 200 can be adjusted so that the area of ​​the top surface of the trench is larger than the area of ​​the bottom surface, thereby making it easier for the first conductive layer 400 to fill. Therefore, porosity and / or seams in the formed first conductive layer 400 can be avoided or reduced, thus improving the reliability of the first conductive layer 400.

[0070] Reference Figure 7 A portion of the top and side surfaces of the first conductive layer 400 are removed to thin the first conductive layer 400. As a result, the third thickness t3 of the first conductive layer 410 located on the substrate 100 and the pad 110 (e.g., ...) is reduced. Figure 6 (As shown) can be greater than the fourth thickness t4 of the first conductive layer 410 located on the top and side surfaces of the isolation structure 200 and the side surface of the liner 130. In other words, the first conductive layer 410 located on the top and side surfaces of the isolation structure 200 and the liner 130 is thinned by a removal process.

[0071] The aforementioned portions of the top and side surfaces of the first conductive layer 410 can be removed using a wet etching process. In the case where the first conductive layer 410 is polysilicon, an etching gas with a high etch selectivity for polysilicon is introduced. Since the introduced etching gas first contacts the top and side surfaces of the first conductive layer 410, a portion of the top and side surfaces of the first conductive layer 410 can be primarily removed. In this embodiment, removal of the first conductive layer 400 located on the substrate 100 and the pad 110 can be avoided or almost avoided.

[0072] In some embodiments, since the third thickness t3 of the first conductive layer 410 can be greater than the fourth thickness t4, the doping energy and doping depth during subsequent implantation processes on the first conductive layer 410 can be reduced, thereby improving the controllability of subsequent implantation processes. Because the isolation structure 200 is covered with the first conductive layer 410, the first conductive layer 410 can serve as a buffer layer that absorbs doping energy first. Furthermore, since the third thickness t3 of the first conductive layer 410 can be greater than the fourth thickness t4, it is easier to dope other components located below the top surface of the first conductive layer 410 through the implantation process.

[0073] Reference Figure 8 A third implantation process P3 is performed on the first conductive layer 410 and the isolation structure 200 at a third angle a3 to form a doped portion 410A in the first conductive layer 410 and a doped portion 200A in the isolation structure 200. A third implantation process P3 can be further performed on the substrate 130 to form a doped portion 130A in the substrate 130. The third angle a3 can be greater than 0 degrees and less than 90 degrees. The third angle a3 can be the same as or different from the first angle a1.

[0074] The implantation energy, dopant type, and dopant concentration of the third implantation process P3 may be the same as or different from those of the first implantation process P1 and / or the second implantation process P2. In some embodiments, the implantation energy of the third implantation process P3 may be lower than that of the first implantation process P1 and / or the second implantation process P2. In some embodiments, the molecular weight of the dopant in the third implantation process P3 is greater than that of the first conductive layer 410, the isolation structure 200, and the liner 130. Therefore, the upper structure of the first conductive layer 410, the isolation structure 200, and the liner 130 can be made more loosely structured through the third implantation process P3. In some embodiments, a mixture of nitrogen and argon (N2 / Ar) gas can be introduced into the third implantation process P3 to dope nitrogen atoms and argon (Ar) atoms. In other embodiments, the third implantation process P3 may dope arsenic (As) atoms.

[0075] Reference Figure 9The doped portion 410A of the first conductive layer 410 is removed to expose the doped portion 200A of the isolation structure 200, while the remaining portion 410B of the first conductive layer 410 is retained. In some embodiments, the doped portion 130A of the substrate 130 is exposed. Since the remaining portion 410B of the first conductive layer 410 is not damaged by the third implantation process P3, the polishing rate of the remaining portion 410B is lower than that of the doped portion 410A. Therefore, the removal of the remaining portion 410B of the first conductive layer 410 can be avoided. In some embodiments, the top surface of the remaining portion 410B of the first conductive layer 410 is lower than the top surface of the doped portion 200A of the isolation structure 200. In some embodiments, the top surfaces of the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130 protrude upward beyond the remaining portion 410B of the first conductive layer 410.

[0076] The top surface of the doped portion 200A of the isolation structure 200 and the top surface of the remaining portion 410B of the first conductive layer 410 have a height h. Therefore, the height h between the doped portion 200A of the isolation structure 200 and the remaining portion 410B of the first conductive layer 410 can be controlled based on the selection of different materials, thereby improving the uniformity of the planarization process. For example, the height h can be in the range of approximately 1 nm to 10 nm. The height h can be in the range of 1 nm, 2.5 nm, 5 nm, 7.5 nm, 10 nm, or combinations thereof. When the polishing selection between different materials to be planarized is relatively large, that is, when the polishing rate difference between different materials is large, the height h can be controlled to be higher.

[0077] This application improves the uniformity of the planarization process by using an implantation process to damage materials with low polishing rates in chemical mechanical polishing (CMP) slurries, thereby making the polishing selectivity of various materials in the semiconductor structure substantially the same or similar. In other words, the uniformity of the planarization process can be adjusted by controlling the third implantation process P3 and the height h.

[0078] Reference Figure 10A second conductive layer 500 is formed on the first conductive layer 410 and the isolation structure 200. Specifically, the second conductive layer 500 is formed on the remaining portion 410B of the first conductive layer 410, the doped portion 200A of the isolation structure 200, and the doped portion 130A of the substrate 130. The material and formation process of the second conductive layer 500 may be the same as or different from those of the first conductive layer 410. For example, the material may be polysilicon, so that the first conductive layer 410 and the second conductive layer 500 do not substantially have an interface. In some embodiments, the first conductive layer 410 and the second conductive layer 500 may have an interface due to the different forming materials. Since a portion of the second conductive layer 500 is formed directly on the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130, the second conductive layer 500 can be prevented from being over-deposited on the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130 based on the different compatibility of the materials.

[0079] In some embodiments, the isolation structure 200 has an arc-shaped corner 200C and a recess 300 (e.g. Figure 7 As shown, the top surface of the remaining portion 410B of the first conductive layer 410 is lower than the top surface of the doped portion 130A of the substrate 130 and the doped portion 200A of the isolation structure 200. Therefore, the coverage of the second conductive layer 500 over the isolation structure 200, the substrate 130, and the remaining portion 410B of the first conductive layer 410 can be improved, thereby enhancing the reliability of the second conductive layer 500.

[0080] Furthermore, the liner 130 has a second thickness t2 that decreases upwards, and the fourth thickness t4 of the remaining portion 410B of the first conductive layer 410 located on the side surface of the liner 130 is less than the third thickness t3 of the remaining portion 410B of the first conductive layer 410 located on the substrate 100. Therefore, the aspect ratio and profile of the trench between adjacent isolation structures 200 can be adjusted so that the area of ​​the top surface of the trench is larger than the area of ​​the bottom surface, allowing the second conductive layer 500 to be filled more easily. Thus, porosity and / or seams in the formed second conductive layer 500 can be avoided or reduced, thereby improving the reliability of the second conductive layer 500. In some embodiments, the first conductive layer 400 and the second conductive layer 500 can be formed by a deposition-etching-deposition (DED) process.

[0081] In other embodiments, the second conductive layer 500 can be formed directly on the doped portion 410A of the first conductive layer 410 without first removing the doped portion 410A of the first conductive layer 410. Then, a planarization process is performed to make the top surfaces of the remaining portion 410B of the first conductive layer 410, the remaining portion 500B of the second conductive layer 500, and the remaining portion 200B of the isolation structure 200 flush.

[0082] Reference Figure 11 A planarization process is performed to make the top surfaces of the second conductive layer 500, the first conductive layer 410, the isolation structure 200, and the substrate 130 flush. In some embodiments, a planarization process is performed to remove a portion of the second conductive layer 500, the doped portion 200A of the isolation structure 200, and the doped portion 130A of the substrate 130, so that the top surfaces of the remaining portion 500B of the second conductive layer 500, the remaining portion 410B of the first conductive layer 410, the remaining portion 200B of the isolation structure 200, and the remaining portion 130B of the substrate 130 are flush with each other.

[0083] In detail, planarization can be a chemical mechanical polishing (CMP) process using polishing slurries. Therefore, CMP can simultaneously utilize both mechanical and chemical forces to planarize materials. However, the polishing slurries used in CMP processes are often limited by their physical properties. For example, insufficient selectivity of the slurry for the material to be polished can lead to over-polishing of some areas and under-polishing of others. In other words, a non-planar top surface may still exist after performing a CMP process.

[0084] For example, the polishing slurry used in typical chemical mechanical polishing (CMP) processes achieves a high polishing rate for polycrystalline silicon but a lower polishing rate for oxide-like materials. Therefore, after CMP, the top surface of the polycrystalline silicon material may be lower than that of other materials such as oxides, resulting in insufficient polishing uniformity. Insufficient polishing uniformity affects the controllability and reliability of subsequent processes, ultimately degrading the entire semiconductor device. For instance, without performing the third implantation process P3, after planarization, the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130 may still protrude beyond the remaining portions 410B of the first conductive layer 410 and the second conductive layer 500.

[0085] However, in this application, the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130 protrude upwards beyond the remaining portion 410B of the first conductive layer 410, creating a step difference. Furthermore, the structure of the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130 is relatively loose due to the influence of the third implantation process P3. Therefore, during the planarization process, it is easier to remove the doped portion 200A of the isolation structure 200 and the doped portion 130A of the substrate 130, thereby making the top surfaces of the remaining portion 200B of the isolation structure 200, the remaining portion 130B of the substrate 130, the remaining portion 410B of the first conductive layer 410, and the remaining portion 500B of the second conductive layer 500 flush. In other words, by performing the third implantation process P3 to destroy components that may protrude above the remaining portion 410B of the first conductive layer 410, the uniformity of the planarization process is increased.

[0086] Reference Figure 12 The remaining portion 200B of the isolation structure 200 is etched back so that the top surface of the remaining portion 200B of the isolation structure 200 is lower than the top surfaces of the remaining portion 500B of the second conductive layer 500 and the remaining portion 410B of the first conductive layer 410. Since the remaining portion 200B of the isolation structure 200 is etched back to form a trench for subsequently housing the control gate, the parameters of the etch-back process significantly affect the electrical performance of the subsequently formed semiconductor structure. For example... Figure 11 As shown, after performing the planarization process, a highly uniform flat top surface can be obtained, which allows for more precise control of the etching depth in the etching process, thereby improving the reliability of the semiconductor structure.

[0087] The etching process can further remove the remaining portion 130B of the liner 130, making the top surface of the remaining portion 130B of the liner 130 flush with the top surface of the remaining portion 200B of the isolation structure 200. The etching process can expose the side surfaces of the remaining portion 410B of the first conductive layer 410, forming an opening 501. For example... Figure 12 As shown, due to Figure 5 The liner 130 shown has a second thickness t2 that decreases upward, so that after the back etching process is performed, the first width w1 at the bottom of the opening 501 can be greater than the second width w2 at the middle portion of the opening 501.

[0088] Furthermore, the etching process can further round off the remaining portion 410B of the first conductive layer 410 adjacent to the opening 501, giving the remaining portion 410B of the first conductive layer 410 a rounded corner 410C. Therefore, the third width w3 at the top of the opening 501 can be greater than the second width w2 at the middle portion of the opening 501. When the third width w3 of the opening 501 is greater than the second width w2, it is easier to fill the subsequent interlayer dielectric layer and the third conductive layer into the opening 501. In other words, the remaining portion 410B of the first conductive layer 410 having a rounded corner 410C improves the reliability of the subsequently formed third conductive layer.

[0089] Reference Figure 13 An interlayer dielectric layer 600 is compliantly formed on the remaining portion 500B of the second conductive layer 500, the remaining portion 410B of the first conductive layer 410, the remaining portion 130B of the liner 130, and the remaining portion 200B of the isolation structure 200. The interlayer dielectric layer 600 may be a single-layer structure or include multiple sublayers, such as an oxide-nitride-oxide (ONO) structure.

[0090] like Figure 13 As shown, a third conductive layer 700 is formed on the interlayer dielectric layer 600 to obtain a semiconductor structure 1. The semiconductor structure 1 may be a memory device, or further processes may be performed on the semiconductor structure 1 to form a memory device. In some embodiments, a double patterning process may be further performed on the third conductive layer 700 to form word lines. In some embodiments, spacers may be further formed on the sidewalls of the third conductive layer 700 to reduce leakage current generation.

[0091] In semiconductor structure 1, the remaining portion 500B of the second conductive layer 500 and the remaining portion 410B of the first conductive layer 410 can jointly serve as a floating gate in a memory device. The remaining portion 410B of the first conductive layer 410 may have a recess. The remaining portion 410B of the first conductive layer 410 may be U-shaped, V-shaped, or concave. The remaining portion 410B of the first conductive layer 410 may have a recessed top surface. The remaining portion 500B of the second conductive layer 500 may be disposed in the aforementioned recess. The remaining portion 410B of the first conductive layer 410 may cover the remaining portion 500B of the second conductive layer 500. The remaining portion 410B of the first conductive layer 410 may contact the bottom surface and side surface of the remaining portion 500B of the second conductive layer 500.

[0092] In some embodiments, because the remaining portion 130B of the substrate 130 may have a second thickness t2 that decreases upward, and the outline of the floating gate corresponds to the outline of the substrate 130, the floating gate formed by the remaining portion 500B of the second conductive layer 500 and the remaining portion 410B of the first conductive layer 410 may have a sloping side surface 410S, thereby increasing the charge capacity stored in the floating gate and thus increasing the storage capacity of the subsequently formed flash memory device. In the cross-sectional view, the fourth width w4 of the upper portion of the floating gate formed by the remaining portion 500B of the second conductive layer 500 and the remaining portion 410B of the first conductive layer 410 may be greater than the fifth width w5 of the lower portion of the floating gate. For example, the area of ​​the top surface of the floating gate may be greater than the area of ​​the bottom surface of the floating gate. Therefore, the charge capacity stored in the floating gate may also be increased. In some embodiments, the charge capacity of the floating gate may be increased by 1.01 times to 2 times. In some embodiments, the interlayer dielectric layer 600 may serve as a control dielectric layer in a memory device, and the third conductive layer 700 may serve as a control electrode in a memory device.

[0093] In summary, this application deposits conductive materials such as polycrystalline silicon in stages by forming a first conductive layer and a second conductive layer, respectively. An implantation process is performed between the formation processes of the first and second conductive layers to disrupt the structure of non-polycrystalline silicon materials such as oxide materials, thereby improving the uniformity of subsequent chemical mechanical polishing (CMP) processes. This improves the reliability of subsequent etching-back and filling processes. For example, when using a single CMP process for planarization, the top surface of the semiconductor structure may still be uneven due to the different polishing selectivity of the various materials included in the semiconductor structure. However, this application can improve the uniformity of the planarization process by combining an implantation process with a CMP process.

[0094] In detail, by using an implantation process (such as a third implantation process) to disrupt a portion of the first conductive layer and the isolation structure, making some parts of the first conductive layer and the isolation structure more fragile, a second conductive layer is then formed on the first conductive layer. Subsequently, a planarization process is performed to make the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure flush, thereby obtaining a flatter top surface. In short, this application improves the uniformity of the subsequent chemical mechanical polishing process by performing a deposition process in stages and an implantation process between the deposition processes to disrupt the upper part of the oxide-based material.

[0095] Furthermore, this application can be further enhanced by using a rounded corner process, making the upper width of the opening and / or trench greater than the lower width, thereby improving the reliability of the filling process. This application can achieve a curved corner structure by first performing an implantation process with different arrival angles, followed by a chemical mechanical polishing process. With a curved corner structure, subsequent filling processes for the first and second conductive layers, which serve as floating gates, are easier to execute, thus improving the reliability of the first and second conductive layers.

[0096] The foregoing summary outlines the components of several embodiments of this application, enabling those skilled in the art to better understand the nature of this application. Those skilled in the art should understand that they can readily use this application as a basis for changing, replacing, substituting, and / or modifying other processes and structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this application, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A masking layer is formed on a substrate, and the masking layer and the substrate have an opening; An isolation structure is formed in the opening; Remove the mask layer; A first conductive layer is formed on the isolation structure and the substrate; A first implantation process is performed on the first conductive layer and the isolation structure to form a doped portion in the first conductive layer and a doped portion in the isolation structure; A second conductive layer is formed on the first conductive layer and the isolation structure; as well as A first planarization process is performed to make the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure flush.

2. The forming method as described in claim 1, characterized in that, Including: Before forming the second conductive layer, the doped portion of the first conductive layer is removed to expose the doped portion of the isolation structure.

3. The forming method as described in claim 2, characterized in that, The second conductive layer is formed on a remaining portion of the first conductive layer and the doped portion of the isolation structure, wherein the first planarization process removes the doped portion of the isolation structure, such that the top surfaces of the remaining portion of the first conductive layer and the remaining portion of the isolation structure are flush.

4. The forming method as described in claim 1, characterized in that, Including: Before forming the isolation structure, a liner is formed in the opening, and The first implantation process is performed on the substrate to form a doped portion in the substrate.

5. The forming method as described in claim 4, characterized in that, Including: Before forming the second conductive layer, the doped portion of the first conductive layer is removed such that the top surface of a remaining portion of the first conductive layer is lower than the top surface of the doped portion of the isolation structure, thereby exposing the doped portion of the isolation structure and the doped portion of the liner.

6. The forming method as described in claim 4, characterized in that, Removing the mask layer further includes: Remove a portion of the liner, causing it to shrink upwards.

7. The forming method as described in claim 1, characterized in that, The insulating structure blanket is formed in the opening and on the shielding layer, and the method further includes: A second planarization process is performed to make the top surfaces of the isolation structure and the masking layer flush.

8. The forming method as described in claim 7, characterized in that, Prior to performing the second planarization process, the method further includes: A second implantation process is performed on the isolation structure and the masking layer at a first angle; and A third implantation process is performed on the isolation structure and the masking layer at a second angle different from the first angle; and After performing the second planarization process, the corners of the isolation structure and the masking layer are rounded, and a recess is formed on the top surface of the isolation structure and the masking layer.

9. The forming method as described in claim 1, characterized in that, Including: The isolation structure is etched back so that the top surface of the isolation structure is lower than the top surface of the second conductive layer; A dielectric layer is formed on the second conductive layer, the first conductive layer, and the isolation structure; and A third conductive layer is formed on the interlayer dielectric layer.

10. The forming method as described in claim 9, characterized in that, The erosion isolation structure further includes: Remove a portion of the first conductive layer to round the corners of the first conductive layer.

11. The forming method as described in claim 1, characterized in that, Prior to performing the first implantation procedure, the method further includes: A portion of the first conductive layer is removed so that the thickness of the first conductive layer on the substrate is greater than the thickness of the first conductive layer on the isolation structure.

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