Stacked three-dimensional semiconductor memory

Abstract

The present application provides a laminated three-dimensional semiconductor memory capable of high-density cell density. The laminated three-dimensional semiconductor memory of the embodiment includes: a first electrode line extending in a first direction orthogonal to a semiconductor substrate; a second electrode line extending in a second direction orthogonal to the first direction, adjacent to the first electrode line, and extending in the first direction; a first resistance change film extending in the first direction and contacting the second electrode line; a first semiconductor film contacting the first resistance change film and the first electrode line; a first insulator layer extending in the first direction and contacting the first semiconductor film; a first potential application electrode extending in the second direction and contacting the first insulator layer; a second resistance change film extending in the first direction and disposed in a negative direction of a third direction orthogonal to the first direction and the second direction, and contacting the second electrode line; a second semiconductor film contacting the second resistance change film and the first electrode line; a second insulator layer extending in the second direction and contacting the second semiconductor film; and a second potential application electrode extending in the second direction and contacting the second insulator layer. The first potential application electrode and the second potential application electrode are electrically different nodes.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-034559 (filed on March 7, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The embodiments of the present invention relate to a multilayered three-dimensional semiconductor memory. Background Technology

[0004] The industry has proposed a multilayer three-dimensional semiconductor memory that integrates resistive random access memory (ReRAM), phase change memory (PCM), and interfacial phase change memory (iPCM) elements on a semiconductor substrate. In this non-volatile semiconductor memory device with memory cells containing resistive elements, the resistive elements can be made to either a high-resistance state or a low-resistance state by allowing current to flow through them. Summary of the Invention

[0005] The problem to be solved by the implementation method is to provide a multilayer three-dimensional semiconductor memory that can achieve high cell density.

[0006] A multilayer three-dimensional semiconductor memory according to an embodiment includes: a semiconductor substrate; a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line disposed adjacent to the first electrode line in a second direction orthogonal to the first direction and extending in the first direction; a first resistive switching film extending in the first direction and contacting the second electrode line; a first semiconductor film contacting the first resistive switching film and the first electrode line; a first insulating layer extending in the first direction and contacting the first semiconductor film; a first potential application electrode extending in the second direction and contacting the first insulating layer; a second resistive switching film extending in the first direction, disposed in the negative direction of a third direction orthogonal to the first and second directions, and contacting the second electrode line; a second semiconductor film contacting the second resistive switching film and the first electrode line; a second insulating layer extending in the second direction and contacting the second semiconductor film; and a second potential application electrode extending in the second direction and contacting the second insulating layer. The first potential application electrode and the second potential application electrode are at electrically different nodes. Attached Figure Description

[0007] Figure 1This is a block diagram of a storage system using the stacked three-dimensional semiconductor memory according to the first embodiment.

[0008] Figure 2 This is a top view showing the configuration of the cell array of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0009] Figure 3 yes Figure 2 The equivalent circuit diagram of a single cell of a multilayer three-dimensional semiconductor memory, as shown in Part A of the comparative example.

[0010] Figure 4 This is an equivalent circuit diagram of one cell portion of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0011] Figure 5 This is a cross-sectional view along the XY plane of the cell block structure of a comparative example of a multilayered three-dimensional semiconductor memory.

[0012] Figure 6 This is a circuit diagram showing the configuration of a multilayered three-dimensional semiconductor memory block for a comparative example.

[0013] Figure 7 This is a circuit diagram illustrating the operation of a cell block in a comparative example of a multilayered three-dimensional semiconductor memory.

[0014] Figure 8A This is an equivalent circuit diagram of the two-cell portion of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0015] Figure 8B This is a cross-sectional view along the XY plane showing the cell block structure of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0016] Figure 8C This is a cross-sectional view along the XZ plane showing the cell block structure of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0017] Figure 9A This is a circuit diagram showing the configuration of the multilayer three-dimensional semiconductor memory block according to the first embodiment.

[0018] Figure 9B This is a block diagram showing the configuration of the cell array of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0019] Figure 9C This is a block diagram showing the configuration of the block BLKi of the stacked three-dimensional semiconductor memory in the first embodiment, along with the even-number decoder and the odd-number decoder.

[0020] Figure 10A This is a timing diagram of the operation waveforms during cell block reading of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0021] Figure 10B This is a timing diagram of the operation waveforms during cell block writing of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0022] Figure 11 This is a top view of the cell array of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0023] Figure 12 This is a top view of the word line level of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0024] Figure 13 This is a top view of the selected gate line level of the multilayer three-dimensional semiconductor memory according to the first embodiment.

[0025] Figure 14 It is along Figure 12 Line II and Figure 13 A cross-sectional view along line IV-IV.

[0026] Figure 15 It is along Figure 12 Line II-II and Figure 13 A cross-sectional view of the VV line.

[0027] Figure 16 It is along Figure 12 A cross-sectional view along line III-III.

[0028] Figure 17 It is along Figure 12 A sectional view along line VI-VI.

[0029] Figure 18 It is along Figure 12 A sectional view along line VII-VII.

[0030] Figure 19 This is a top view of the word line level of the multilayer three-dimensional semiconductor memory according to the second embodiment.

[0031] Figure 20 This is a top view of the selected gate line level of the multilayer three-dimensional semiconductor memory according to the second embodiment.

[0032] Figure 21 It is along Figure 19 and Figure 20 A cross-sectional view of line VIII-VIII.

[0033] Figure 22 It is along Figure 19 and Figure 20 A cross-sectional view of the IX-IX line.

[0034] Figure 23This is a top view of the selected gate line level of the multilayer three-dimensional semiconductor memory according to the third embodiment.

[0035] Figure 24 It is along Figure 23 A cross-sectional view along the XX line.

[0036] Figure 25 It is along Figure 23 A cross-sectional view along line XI-XI.

[0037] Figure 26 It is along Figure 23 A cross-sectional view along line XII-XII.

[0038] Figure 27 It is along Figure 23 A cross-sectional view of line XIII-XIII.

[0039] Figure 28 This is a top view of the peripheral portion of a comparative example multilayer three-dimensional semiconductor memory.

[0040] Figure 29 This is a top view of the peripheral portion of the multilayer three-dimensional semiconductor memory according to the fourth embodiment.

[0041] Figure 30 It is a multilayered three-dimensional semiconductor memory according to the fourth embodiment, and it is along... Figure 29 A cross-sectional view of line XIV-XIV. Detailed Implementation

[0042] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and structure will be labeled with common reference numerals. In the following description, the direction perpendicular to the semiconductor substrate extending in the XY plane is defined as the Z direction, the extension direction of the word line WL orthogonal to the Z direction is defined as the X direction, and the extension direction of the bit line perpendicular to both the Z and X directions is defined as the Y direction. Additionally, there is a case where the resistive switching element RE is shown as a resistive switching film RE.

[0043] (First Embodiment)

[0044] (Storage system)

[0045] The block structure of the storage system 1 using the multilayer three-dimensional semiconductor memory 100 of the first embodiment will be described. For example... Figure 1 As shown, the storage system 1 includes a stacked three-dimensional semiconductor memory 100 and a controller 200. The stacked three-dimensional semiconductor memory 100 and the controller 200 can be combined to form a semiconductor device, for example, a memory card, an SSD (Solid State Drive), etc.

[0046] The stacked 3D semiconductor memory 100 has multiple storage cells for non-volatile data storage. A controller 200 is connected to the stacked 3D semiconductor memory 100 via a storage bus and to a host computer 300 via a host bus. The controller 200 controls the stacked 3D semiconductor memory 100 and, in response to host commands received from the host computer 300, accesses the stacked 3D semiconductor memory 100. The host computer 300 is, for example, a digital camera or a personal computer, and the host bus is, for example, a bus adapted to a memory interface. The storage bus performs signal transmission and reception adapted to the memory interface.

[0047] (Composition of controller 200)

[0048] like Figure 1 As shown, the controller 200 includes a host interface circuit (host I / F) 210, a built-in memory (RAM: RandomAccess Memory) 220, a processor (CPU: Central Processing Unit) 230, a buffer memory 240, a memory interface circuit (memory I / F) 250, and an ECC (Error Checking and Correcting) circuit 260.

[0049] The host interface circuit 210 is connected to the host 300 via the host bus, and transmits host instructions and data received from the host 300 to the processor 230 and the buffer memory 240, respectively. In addition, the host interface circuit 210 responds to the commands of the processor 230 and transmits the data in the buffer memory 240 to the host 300.

[0050] Processor 230 controls the overall operation of controller 200. For example, when processor 230 receives a read-related host instruction from host 300, it responds to the instruction by causing memory interface circuit 250 to issue a read instruction (memory instruction) for stacked three-dimensional semiconductor memory 100. Processor 230 performs the same action when it receives a write-related host instruction from host 300. In addition, processor 230 executes various processes for managing stacked three-dimensional semiconductor memory 100.

[0051] The memory interface circuit 250 is connected to the stacked 3D semiconductor memory 100 via a memory bus and manages communication with the stacked 3D semiconductor memory 100. Based on commands received from the processor 230, the memory interface circuit 250 sends various signals to the stacked 3D semiconductor memory 100 and receives various signals from the stacked 3D semiconductor memory 100.

[0052] The buffer memory 240 temporarily stores data written to or read from the stacked three-dimensional semiconductor memory 100.

[0053] The built-in memory 220, such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), is used as the working area of ​​the processor 230. Furthermore, the built-in memory 220 stores firmware, or various management tables such as movement tables, history tables, and identification tables used to manage the stacked three-dimensional semiconductor memory 100.

[0054] The ECC (Error Checking and Correcting) circuit 260 performs error detection and correction processing related to the data stored in the multilayer three-dimensional semiconductor memory 100. That is, the ECC circuit 260 generates an error correction symbol when writing data, assigns the error correction symbol to the written data, and decodes it when reading data.

[0055] (The structure of the multilayer three-dimensional semiconductor memory 100)

[0056] like Figure 1 As shown, the multilayer three-dimensional semiconductor memory 100 includes a cell array 110, a row decoder 120, a driver circuit 130, a sense amplifier 140, an address register 150, an instruction register 160, and a sequence generator 170. The peripheral circuitry 108 includes the driver circuit 130, the address register 150, the instruction register 160, and the sequence generator 170.

[0057] Cell array 110 has multiple block BLKs containing multiple non-volatile memory cells that correspond to rows (word lines) and columns (bit lines). Figure 1 The diagram illustrates m blocks BLK0 to BLK(m-1) as an example. The bit lines of blocks BLK0 to BLK(m-1) are connected in a common manner. The word lines of blocks BLK0 to BLK(m-1) are connected to the line decoder 120. Furthermore, the cell array 110 stores data provided by the controller 200. The configuration of the cell array 110 will be described below (see [reference]). Figure 9B ).

[0058] The line decoder 120 selects any one of the blocks BLK0 to BLK(m-1) in the cell array 110 based on the block address BA in the address register 150, and further selects the word line direction in the selected block BLK. The configuration of the line decoder 120 is described below (refer to...). Figure 9C ).

[0059] The driver circuit 130 supplies voltage to the selected block BLK via the line decoder 120 based on the page address PA in the address register 150. The driver circuit 130 may also include, for example, a source line driver.

[0060] The sensing amplifier 140 has a sensing amplifier module configured for each bit line BL. During data reading, it senses the data read from the cell array 110 and performs necessary calculations. Then, it outputs the data DAT to the controller 200. During data writing, it transmits the write data DAT received from the controller 200 to the cell array 110. The address register 150 stores the address ADD received from the controller 200. This address ADD contains the block address BA and the page address PA.

[0061] Instruction register 160 stores the instruction CMD received from controller 200.

[0062] The sequence generator 170 controls the overall operation of the stacked three-dimensional semiconductor memory 100 based on the instruction CMD stored in the instruction register 160.

[0063] (Stacked three-dimensional semiconductor memory according to the first embodiment)

[0064] Figure 2 This is a top view showing the cell array configuration of the multilayer three-dimensional semiconductor memory according to the first embodiment. (Example) Figure 2 As shown, the stacked three-dimensional semiconductor memory of the first embodiment includes multiple word lines WL0, WL1, and WL2 extending in the X direction, and multiple local bit lines LBL and multiple local source lines LSL sandwiched between a gate insulating film GD and a semiconductor film CH between adjacent word lines WL in the Y direction. A resistive switching film RE is disposed between the local bit lines LBL and the semiconductor film CH. Furthermore, the multiple local bit lines LBL0, LBL1, and LBL2 and the multiple local source lines LSL0, LSL1, and LSL2 are arranged alternately in a straight line, separated by an insulating film DF. The multiple local bit lines LBL0, LBL1, and LBL2 and the multiple local source lines LSL0, LSL1, and LSL2 are arranged in a columnar shape in the Z direction. Additionally, the multiple word lines WL0, WL1, and WL2 have a planar structure extending in the XY plane and are stacked in the Z direction. Furthermore, regarding the three-dimensional structure of the stacked three-dimensional semiconductor memory of the first embodiment, in... Figure 11 The description provides a detailed account. Furthermore, details regarding each part are also provided. Figures 8B-8C and Figures 12-18 The details will be described in the explanation.

[0065] Figure 3 yes Figure 2The equivalent circuit diagram of one cell of the comparative example of the multilayer three-dimensional semiconductor memory in Part A is shown below. The comparative example's multilayer three-dimensional semiconductor memory constitutes one memory cell MC using two resistive switching films RE and four unit transistors (two MT and two MT'). Word lines WL1 and WL2 are electrically connected in common and connected to a word line select transistor WLSW.

[0066] Figure 4 This is an equivalent circuit diagram of one cell portion of the multilayer three-dimensional semiconductor memory according to the first embodiment. In the first embodiment, the memory cell MC of the multilayer three-dimensional semiconductor memory is constructed using one resistive switching film RE and two unit transistors MT and MT'. Word lines WL1 and WL2 are electrically isolated; word line WL1 is connected to word line select transistor WLSW1, and word line WL2 is connected to word line select transistor WLSW2. Word line select transistors WLSW1 and WLSW2 are connected to the line decoder 120 and the driver 130, and can be controlled independently.

[0067] In the stacked three-dimensional semiconductor memory of the first embodiment, such as Figure 4 As shown, every other word line WL is configured as an individual electrode. Therefore, an ON (connected) voltage can be applied to any word line WL. That is, a single unit can be formed using one resistive switching film RE and two unit transistors MT and MT', compared to the comparative example ( Figure 3 Compared to the previous method, the unit density is twice as high. Furthermore, Figures 1-3 In the structure, the left and right local source lines LSL1 and LSL2 become local source lines common to adjacent units on the same line. Furthermore, multiple local source lines are not only connected to adjacent units, but also to a wider, plate-like source line SL common to the entire layer (see reference). Figure 11 ).

[0068] As an example of a resistive switching element (RE), an alloy-type phase-transition element (Ge2Sb2Te5) can be cited. The resistive switching element RE changes its crystalline state, becoming either low-resistance or high-resistance. This change in the crystalline state of the resistive switching element RE is called a "phase transition," and the state where the resistive switching element RE is in a low-resistance state (LRS) is denoted as the "set state," while the state where it is in a high-resistance state (HRS) is denoted as the "reset state." For example, when the crystalline state changes to amorphous, it becomes a high-resistance state. When the crystalline state changes to crystallization, it becomes a low-resistance state.

[0069] (Comparative Example)

[0070] Figure 5 This is a cross-sectional view along the XY plane showing the configuration of cell blocks CB0 to CB3 of the comparative example multilayer three-dimensional semiconductor memory. Additionally, Figure 5 The equivalent circuit of unit 1 and Figure 3 Similarly, it is expressed. Figure 5 The example shows a configuration in which four cell blocks CB0 to CB3 are arranged within a memory hole MH surrounded by word lines WL.

[0071] The memory aperture MH is configured as a line extending in the X direction when viewed along the XY plane, and as a plate extending in the XZ direction. Multiple cell blocks CB0 to CB3 are arranged relative to each other in the X direction. Each cell block CB is composed of a columnar structure. The columnar structure has multiple local source lines LSL0 to LSL3 and multiple local bit lines LBL0 to LBL3.

[0072] For example, the columnar structure of unit block CB0 has a local bit line LBL0 and multiple local source lines LSL0 and LSL1. Local source line LSL0 is located on the -X side of local bit line LBL0, extending in the Z direction and penetrating multiple word lines WL0 to WL63. Local source line LSL1 is located on the +X side of local bit line LBL0, extending in the Z direction and penetrating multiple word lines WL0 to WL63. The columnar structure of unit block CB3 has a local bit line LBL3 and multiple local source lines LSL3 and LSL4. Local source line LSL3 is located on the -X side of local bit line LBL3, extending in the Z direction and penetrating multiple word lines WL0 to WL63. Local source line LSL4 is located on the +X side of local bit line LBL3, extending in the Z direction and penetrating multiple word lines WL0 to WL63.

[0073] That is, within the memory hole MH, the local source line LSL and the local bit line LBL are alternately and repeatedly arranged along the X direction, separated by an insulating film DF. Figure 5 In the memory hole MH, local source line LSL0, local bit line LBL0, local source line LSL1, local bit line LBL1, local source line LSL2, local bit line LBL2, local source line LSL3, local bit line LBL3, and local source line LSL4 are arranged from the -X side to the +X side.

[0074] The local source line (LSL) consists of a point shared by multiple cell blocks (CB) and... Figures 2-4 Similarly, for example, local source line LSL1 is shared by cell block CB0 and cell block CB1. Local source line LSL3 is shared by cell block CB2 and cell block CB3.

[0075] Figure 6 This is an equivalent circuit diagram showing the configuration of the block BLKi of the multilayer three-dimensional semiconductor memory, as in the comparative example. For example... Figure 6As shown, memory cell MC contains two series connections. For example, memory cell MC0 of cell block CB0 contains a series connection of resistive switching element RE and unit transistor MT' between local bit line LBL0 and local source line LSL0, and a series connection of resistive switching element RE and unit transistor MT between local bit line LBL0 and local source line LSL1. Both unit transistors MT' and MT in memory cell MC0 have their gates connected to word line WL0. Similarly, memory cell MC1 of cell block CB1 contains a series connection of resistive switching element RE and unit transistor MT' between local bit line LBL1 and local source line LSL1, and a series connection of resistive switching element RE and unit transistor MT between local bit line LBL1 and local source line LSL2. Both unit transistors MT' and MT in memory cell MC1 have their gates connected to word line WL1. The memory cell MC63 of block CB3 contains a series connection of a resistive switching element RE and a unit transistor MT' between the local bit line LBL3 and the local source line LSL3, and a series connection of a resistive switching element RE and a unit transistor MT between the local bit line LBL3 and the local source line LSL4. Both the unit transistor MT' and the unit transistor MT in memory cell MC63 have their gates connected to word line WL63.

[0076] Local bit lines LBL0 to LBL3 are connected to bit lines BL0 to BL3 via select gate lines SGD0 to SGD3, as described below. Local source lines LSL0 to LSL2 are connected to source line SL. Furthermore, the number of memory cells MC contained in each cell block CB can be 8, 32, 48, 64, 96, or 128, etc., and their quantity is not limited. Additionally, the number of local source lines and local bit lines can be 4, 8, 32, 48, 64, 96, or 128, etc., and their quantity is not limited.

[0077] When accessing the resistive switching element (resistive switching film) RE, the selection transistor SG of the selection cell block CB is turned on, while the selection transistor SG of the non-selection cell block CB remains off. Within the selection cell block CB, the cell transistor MT of the selection memory cell MC is turned on, while the cell transistor MT of the non-selection memory cell MC remains off. When a voltage is applied to the bit line BL and the source line SL, a cell current flows in the path: bit line BL → local bit line LBL → resistive switching element RE of the selection memory cell MC → cell transistor MT of the selection memory cell MC → local source line LSL → source line SL.

[0078] That is, by connecting in parallel with the channel regions of multiple unit transistors MT in the unit block CB, the current path through the semiconductor film (CH) can be shortened when accessing the resistive switching element (resistive switching film) RE. Therefore, even if the current decreases due to the influence of grain boundaries or the like within the semiconductor film, the unit current can be ensured to be sufficient for writing operations (Set / Reset operations) and reading operations (Detection of Set / Reset state) of the resistive switching element RE.

[0079] Figure 7 This is a circuit diagram illustrating the operation of a cell block in a comparative example of a multilayer three-dimensional semiconductor memory. Based on this configuration, as... Figure 7 As shown, current can flow from the local bit line LBL1 through the resistive switching element RE and via the semiconductor channels of the left and right cell transistors MT and MT' to the left and right local source lines LSL1 and LSL2. When word line WL1 among the multiple word lines WL0 to WL63 is selectively set to a high level VH3, and bit line BL1 among the multiple bit lines BL0 to BL3 is selectively set to a high level VH4, cell transistors MT' and MT of memory cell MC1 are respectively turned on. Therefore, the current path of the cell current is paralleled with the current path of bit line BL1 → local bit line LBL1 → resistive switching element RE → cell transistor MT' → local source line LSL1 → source line SL1, and the current path of bit line BL1 → local bit line LBL1 → resistive switching element RE → cell transistor MT → local source line LSL2 → source line SL2. Therefore, the current path of the cell current can be made low-resistive, thus easily ensuring the cell current.

[0080] Next, we will return to the description of the stacked three-dimensional semiconductor memory of the first embodiment. Figure 8A This is an equivalent circuit diagram of the two-cell portion of the multilayer three-dimensional semiconductor memory according to the first embodiment. Figure 4 In the equivalent circuit shown, every other word line WL is set as an individual electrode, without distinguishing between odd and odd number lines WL1. o Even number line WL1 e . Figure 8A In the middle, connected to the odd-number line WL1 o The memory cell MC1 has unit transistors MT and MT' and resistive switching element RE. o and connected to even-number line WL1 e The memory cell MC1 has unit transistors MT and MT' and resistive switching element RE. e Opposite configuration. With Figure 4 Similarly, two local source lines LSL0 and LSL1 and one local bit line LBL0 are in memory cell MC1 o With storage unit MC1 eThey are used as common lines respectively.

[0081] Figure 8B This is a cross-sectional view along the XY plane showing the cell block configuration of the multilayer three-dimensional semiconductor memory according to the first embodiment. In the multilayer three-dimensional semiconductor memory cell block of the first embodiment, as... Figure 8B As shown, Figure 5 (Comparative Example) The word line WL is divided into odd number lines WL1. o Even number line WL1 e Other components and Figure 5 (Comparative example) Similarly.

[0082] Figure 8B In the example shown, the odd-numbered line WL1 o Even number line WL1 e The memory hole MH is composed of four unit blocks CB0 to CB3. The number of unit blocks CB arranged in one memory hole MH can be one to three, or even five or more.

[0083] The memory hole MH is configured as a line extending along the X direction when viewed in the XY plane, and as a plate extending in the XZ direction. Multiple unit blocks CB0 to CB3 are arranged within the memory hole MH. These unit blocks CB0 to CB3 are arranged relative to each other in the X direction. Each unit block CB is as follows... Figure 8B , Figure 8C The diagram shows a columnar structure. Each columnar structure has multiple local source lines LSL0–LSL3 and multiple local bit lines LBL0–LBL3. Furthermore, the multiple unit blocks CB0–CB3 may not necessarily have an odd-number bit line WL1. o Even number line WL1 e The surrounding memory hole MH. As follows. Figures 11 to 27 As shown, multiple unit blocks CB0 to CB3 are all connected by odd-number lines WL1. o Even number line WL1 e The construction can be completed by the lines that are sandwiched between them.

[0084] For example, the columnar structure of unit block CB0 has a local bit line LBL0 and multiple local source lines LSL0 and LSL1. Local source line LSL0 is located on the -X side of local bit line LBL0, extending in the Z direction and penetrating multiple word lines WL0 to WL63. Local source line LSL1 is located on the +X side of local bit line LBL0, extending in the Z direction and penetrating multiple word lines WL0 to WL63. The columnar structure of unit block CB3 has a local bit line LBL3 and multiple local source lines LSL3 and LSL4. Local source line LSL3 is located on the -X side of local bit line LBL3, extending in the Z direction and penetrating multiple word lines WL0 to WL63. Local source line LSL4 is located on the +X side of local bit line LBL3, extending in the Z direction and penetrating multiple word lines WL0 to WL63.

[0085] That is, within the memory hole MH, the local source line LSL and the local bit line LBL are arranged alternately and repeatedly along the X direction. Figure 8B In the memory hole MH, local source line LSL0, local bit line LBL0, local source line LSL1, local bit line LBL1, local source line LSL2, local bit line LBL2, local source line LSL3, local bit line LBL3, and local source line LSL4 are arranged from the -X side to the +X side.

[0086] Local source lines (LSLs) are shared by multiple cell blocks (CBs). For example, local source line LSL1 is shared by cell blocks CB0 and CB1. Local source line LSL3 is shared by cell blocks CB2 and CB3.

[0087] Figure 8C This is a cross-sectional view along the XZ plane showing the cell block configuration of the multilayer three-dimensional semiconductor memory according to the first embodiment. Figure 8C Corresponding to Figure 8B The cross-sectional structure along line JJ′. Or, Figure 8B Corresponding to Figure 8C The cross-sectional structure along HH′. For example... Figure 8C As shown, odd number line WL0 o ~WL63 o Layered in the Z direction through insulating layer 222. Similarly, even-number lines WL0. e ~WL63 e An insulating layer 222 is deposited in the Z direction. A select gate line SGD is disposed on the uppermost insulating layer 222. Local source lines LSL0 to LSL4 are electrically connected to the plate-shaped source line SL at the bottom in the Z direction via contact plug CP2. Local bit lines LBL0 to LBL3 are connected to the bit lines BL0 to BL3 extending in the Y direction at the uppermost part (local bit line termination part) in the Z direction via contact plug CP1.

[0088] In addition, such as Figures 8B-8C As shown, in each unit block CB, a thermal barrier film HB1 can be disposed between the resistive switching film RE and the local bit line LBL, and a thermal barrier film HB2 can be disposed between the resistive switching film RE and the semiconductor film CH. Furthermore, a thermal barrier film HB3 can also be disposed between the local source line LSL and the semiconductor film CH.

[0089] Here, both thermal barrier films HB1 and HB2 have the same thickness, for example, made of TiN, TaN, or TiO. x Formed from C, CN, CW, C-WN, etc. Furthermore, a heating film HT can be used instead of thermal barrier films HB1 and HB2. Additionally, where structurally permissible, both thermal barrier films HB1 and HB2 and a heating film HT can be used. For example, the heating film HT can be disposed between the semiconductor films CH on the outer periphery of the resistive switching film RE.

[0090] In addition, although conductive materials such as TiN, TaN, TiOx, C, and CN can also be used for thermal barrier films HB1 and HB2, the use of conductive materials such as CW and C-WN can further improve the thermal resistance. From the perspective of suppressing heat leakage to the local bit line LBL side, the heating efficiency can be improved.

[0091] For example, germanium containing indium as an impurity can be used as a material for heating films (HT). Indium-containing germanium can be easily made highly resistive by adjusting the concentration of indium as an impurity and its conductivity type (p-type or n-type). Ideally, for example, the concentration of p-type indium impurity can be adjusted to 1 × 10⁻⁶. 15 ~1×10 16 cm -3 The resistivity of the heating film HT is set to approximately 0.5–4 Ωcm. Furthermore, the material used for the heating film HT can be tellurium containing indium as an impurity, or a group III-V compound.

[0092] Figures 8B-8C The illustrated structure, by forming the memory aperture MH as a line when viewed in the XY plane, easily ensures sufficient lithography margin, enabling the formation of an arrangement of cell blocks CB with narrow spacing in the Y direction. Furthermore, the local bit line LBL and local source line LSL are formed separately in the X direction within the memory aperture MH, which extends linearly along the X direction. Therefore, sufficient lithography margin is easily ensured, enabling the formation of an arrangement of cell blocks CB with narrow spacing in the X direction.

[0093] Figure 9AThis is an equivalent circuit diagram showing the configuration of block BLKi in the multilayer three-dimensional semiconductor memory of the first embodiment. Block BLKi (here, i = 0 to m-1) corresponds to the configuration of the multilayer three-dimensional semiconductor memory. Figure 1 Any one of the blocks BLK0 to BLK(m-1) in the unit array 110 shown. Figure 9A This is the equivalent circuit for the arrangement of multiple unit blocks CB0 to CB3. For example... Figure 9A As shown, the storage cell MC contains two serially connected units. For example, storage cell MC0 of cell block CB0. o A series connection of a resistive switching element RE and a unit transistor MT' is included between the local bit line LBL0 and the local source line LSL0, and a series connection of a resistive switching element RE and a unit transistor MT is included between the local bit line LBL0 and the local source line LSL1. Memory cell MC0 o Both the unit transistor MT' and the unit transistor MT have their gates connected to the odd-number line WL0. o Similarly, the storage unit MC0 of cell block CB0 e A series connection of a resistive switching element RE and a unit transistor MT' is included between the local bit line LBL0 and the local source line LSL0, and a series connection of a resistive switching element RE and a unit transistor MT is included between the local bit line LBL0 and the local source line LSL1. Memory cell MC0 e Both the unit transistor MT' and the unit transistor MT have their gates connected to the even-number line WL0. e .

[0094] Storage unit MC1 of cell block CB1 o A series connection of a resistive switching element RE and a unit transistor MT' is included between local bit line LBL1 and local source line LSL1, and a series connection of a resistive switching element RE and a unit transistor MT is included between local bit line LBL1 and local source line LSL2. Memory cell MC1 o Both the unit transistor MT' and the unit transistor MT have their gates connected to the odd-number line WL1. o Similarly, the storage unit MC1 of cell block CB1 e A series connection of a resistive switching element RE and a unit transistor MT' is included between local bit line LBL1 and local source line LSL1, and a series connection of a resistive switching element RE and a unit transistor MT is included between local bit line LBL1 and local source line LSL2. Memory cell MC1 e Both the unit transistor MT' and the unit transistor MT have their gates connected to the even-number line WL1. e .

[0095] Storage cell MC63 of block CB63 oA series connection of a resistive switching element RE and a unit transistor MT' is included between local bit line LBL3 and local source line LSL3, and a series connection of a resistive switching element RE and a unit transistor MT is included between local bit line LBL3 and local source line LSL4. Memory cell MC63 o Both the unit transistor MT' and the unit transistor MT have their gates connected to the odd-number line WL63. o Similarly, the storage unit MC63 of cell block CB63 e A series connection of a resistive switching element RE and a unit transistor MT' is included between local bit line LBL3 and local source line LSL3, and a series connection of a resistive switching element RE and a unit transistor MT is included between local bit line LBL3 and local source line LSL4. Memory cell MC63 e Both the unit transistor MT' and the unit transistor MT have their gates connected to the even-number line WL63. e .

[0096] (Operation of the cell block of the stacked three-dimensional semiconductor memory according to the first embodiment)

[0097] The cell block operation of the stacked three-dimensional semiconductor memory in the first embodiment and Figure 7 The same applies. Current can flow from the local bit line LBL1 through the resistive switching element RE, via the semiconductor channels of the left and right unit transistors MT and MT', into the left and right local source lines LSL1 and LSL2. In multiple word lines WL0... o ~WL63 o WL1 o When bit line BL1 among multiple bit lines BL0 to BL3 is selectively set to a high level VH4, the memory cell MC1... o Unit transistors MT' and MT' are turned on. Therefore, the current path of the unit current is connected in parallel with the current path of bit line BL1 → local bit line LBL1 → resistive switching element RE → unit transistor MT' → local source line LSL1 → source line SL1, and the current path of bit line BL1 → local bit line LBL1 → resistive switching element RE → unit transistor MT → local source line LSL2 → source line SL2. Thus, the resistance of the unit current path can be reduced, and the unit current can be easily ensured.

[0098] As described above, in the stacked three-dimensional semiconductor memory of the first embodiment, each cell block in the cell array 110 of the stacked three-dimensional semiconductor memory 100 contains a plurality of local source lines (LSLs) in its columnar structure. This allows the current paths of the cell currents in each cell block to be parallelized, thereby reducing the resistance of the cell current paths. Furthermore, by configuring even-numbered lines and odd-numbered lines, the memory capacity can be doubled compared to the comparative example.

[0099] Figure 9B This is a block diagram illustrating the configuration of the cell array 110 of the stacked three-dimensional semiconductor memory according to the first embodiment. The stacked three-dimensional semiconductor memory of the first embodiment is as follows: Figure 9B As shown, there are m blocks BLK0 to BLK(m-1). Each of the m blocks BLK0 to BLK(m-1) has n bit lines BL0 to BL(n-1). Each block has... Figure 9A The circuit configuration shown is the same as that of the BLKi block. Additionally, the block contains, for example,... Figure 8B and Figure 8C The three-dimensional structure of the unit blocks CB0 to CB3 is shown.

[0100] Figure 9C This refers to the block BLKi and odd decoder 120 in the stacked three-dimensional semiconductor memory of the first embodiment. o Even number decoder 120 e A block diagram illustrating the structure. For example, the odd decoder 120. o With block BLKi via odd number line WL0 o ~WL(k-1) o And the connection. Similarly, even-numbered decoder 120. e With block BLKi via even number line WLO e ~WL(k-1) e And the connection. For Figure 9B Each of the blocks BLK0 to BLK(m-1) shown is connected by an odd-number line WL0. o ~WL(k-1) o Even number lines WLO e ~WL(k-1) e Even number decoder 120 e Odd number decoder 120 o Each of them is connected to a driver and can be controlled independently.

[0101] (Timing diagram of the operation waveform of the stacked three-dimensional semiconductor memory according to the first embodiment)

[0102] Figure 10A This is a timing diagram of the operation waveforms during cell block reading of the multilayer three-dimensional semiconductor memory according to the first embodiment. Figure 10BIt is a timing diagram of the waveform during the write operation. Figure 10A and Figure 10B This describes an example of the operation of a memory cell block. When memory cell MC is not selected, the cell transistors MT and MT' are set to the off state (non-conducting state). With cell transistors MT and MT' in the off state, an inversion layer cannot be formed in the semiconductor film of cell transistors MT and MT'. Therefore, almost no current flows in the conductor film, and no current flows in the resistive switching element RE. When memory cell MC is selected, the cell transistors MT and MT' are set to the on state (conducting state). Because an inversion layer is formed in the semiconductor film of cell transistors MT and MT', current flows in the inversion layer. This current also flows in the resistive switching element RE, which is connected in series with cell transistors MT and MT'.

[0103] Figure 10A and Figure 10B In the middle, before time point t1, the standby actions are performed. Odd decoder 120 o Even number decoder 120 e Keep the source line SL at a low level V L1 (For example, V) L1 =0V), keep the cell block select gate line SGD0 and the cell block non-select gate lines SGD1 to SGD(n-1) at a low level. L2 (For example, V) L2 =0V or negative potential), turn the non-select word line WL0 e WL0 o WL1 o WL2 e WL2 o ..., WL63 e WL63 o and select word line WL1 e All remain at a low level V L3 (For example, V) L3 =0V). To improve the disconnection characteristics of the unit transistors MT and MT', a low level V L3 It can be a negative potential (e.g., -2V). Because the cell block select transistor SG0 remains off, the bit line BL can be 0V or any potential.

[0104] At time t1, the read / write operation begins. For example, even-number decoder 120. e When reading the signal from the low level V of the cell block select gate line SGD0. L2 Transition to high level V RH2 During writing, from low level V L2 Transition to high level V WH2Select cell block CB0. Here, the signal for the cell block selection gate line SGD0 should be set higher during writing compared to reading. That is, it should be V. WH2 >V RH2 The reason is that the higher potential of the bit line BL0 can be transmitted during writing compared to reading.

[0105] For example, when selecting with word line WL1 e Corresponding storage unit MC1 e Time (reference) Figure 9A ), when reading even-number line WL1 e The signal is from low level V L3 Transition to high level V RH3 During writing, from low level V L2 Transition to high level V WH3 , add other character lines WL0 e WL0 o WL1 o WL2 e WL2 o ..., WL63 e WL63 o The signal remains at a low level V L3 Even-numbered line WL1 e The low level of the signal V L3 The high level V during reading is the non-selection voltage. RH3 and the high level V during writing. WH3 To select the voltage. Here, for example, regarding the even-number line WL1. e The signal should be set higher during writing compared to reading. That is, it should be V. WH3 >V RH3 The reason is that the potential of the higher bit line BL0 can be transmitted during writing compared to reading.

[0106] Therefore, the cell block select gate line SGD0 and the even number line WL1 in cell block CB0 e Corresponding storage unit MC1 e It is capable of access. That is, bit line BL0 and source lines SL0 and SL1 are accessed via the select memory cell MC1. e The resistive switching element RE is turned on. One memory cell MC1 e When the selected state is reached, the source lines SL0 and SL1 are fixed at a low level V. L1 In the state where the selection bit line BL0 is selected from the low level V among multiple bit lines BL0 and BL1, L4 The voltage level V rises high during reading. RH4 It rises to a high level V during writing. WH4Fix the remaining bit line BL1 to a low level V. L4 This will cause current to flow between the select bit line BL0 and the source lines SL0 and SL1. The potential of the bit line BL0 during reading is at the high level V. RH4 High level V during writing WH4 To select the potential, low level V L4 This is a non-selection potential. Here, for example, the potential of the select bit line BL0 should be at the high level V during reading. RH4 High level V during writing WH4 The time is set to different values. That is, V WH4 >V RH4 For example, a high level V during reading. RH4 The value is set low, below 1V, and a high level V is applied during writing. WH4 The value is set relatively high, around 5V.

[0107] During reading, at time point t1, even-numbered decoders 120 e Select bit line BL0 from low level V L4 Rise to high level V RH4 Then set to float. Correspondingly, simply select memory cell MC1. e In the high-resistance state (Reset state), the potential of bit line BL0 is not easily reduced and remains at a high level V. RH4 Nearby. Therefore, the sensing amplifier 140 detects a high-level V at bit line BL0. RH4 From storage unit MC1 e Read "1". This is only necessary for memory cell MC1. e When in a low-resistance state (Set state), the potential of bit line BL0 will drop to a low level V. L4 Therefore, the sensing amplifier 140 detects a low-level V at bit line BL0. L4 From storage unit MC1 e Read "0". At this time, the number of transistors through which the cell current in cell block CB0 passes is 2.

[0108] During writing, at time t1, the sense amplifier 140 moves the potential of the bit line BL0 to be written from a low level V. L4 Rise to high level V WH4 In selecting storage unit MC1 e The current flows through the cell. At this time, the number of transistors through which the cell current in cell block CB0 passes is 2.

[0109] At time t2, after time t1, the sensing amplifier 140 abruptly changes the potential of the bit line BL0 from high level V. WH4 Drop to low level V L4 When selecting storage unit MC1e The resistive switching element (phase change element) RE is rapidly cooled and decrystalline (high resistivity). Thus, the memory cell MC1... e The memory cell MC1 becomes a high-resistance state (Reset state). e Write a "1" into it. The sensing amplifier 140 only needs to change the potential of the bit line BL0 from high level V. WH4 Drop to low level V L4 Select storage unit MC1 e The resistive switching element (phase change element) RE will gradually cool and crystallize (low resistance). Therefore, the memory cell MC1... e The memory cell MC1 enters a low-resistance state (Set state). e Write "0" in it.

[0110] Then, as the read and write operations are completed, each signal can return to its pre-transition level. For example, the signal on the cell block select gate line SGD0 changes from the high level V during read operation. RH2 High level V during writing WH2 Return to low level V L2 Non-select word line WL0 e WL0 o WL1 o WL2 e WL2 o ..., WL63 e WL63 o The signal remains at a low level V L3 Select word line WL1 e The signal is read from the high level V RH3 High level V during writing WH3 Return to low level V L3 Furthermore, when bit line BL0 is set to the HOLD state, it remains at the hold level V. L5 .

[0111] As described above, in the multilayer three-dimensional semiconductor memory 100 of the first embodiment, when reading or writing a selected memory cell MC, the number of transistors through which the cell current in the cell block CB0 passes is two. That is, during the read and write operations, the path length of the semiconductor film through which the cell current passes can be suppressed, thus making it easy to increase the cell current and easily perform the Set / Reset drive operation of the resistive switching element RE.

[0112] (Top view of the cell array 110 of the multilayer three-dimensional semiconductor memory according to the first embodiment)

[0113] Figure 11 This is a top view of the cell array 110 of the multilayer three-dimensional semiconductor memory according to the first embodiment. Figure 11 In this context, the extension direction of the bit line BL is defined as the Y direction, the stacking direction of the memory cell MC is defined as the Z direction, and the direction perpendicular to both the Y and Z directions is defined as the X direction. For example... Figure 11 As shown, in the first embodiment of the stacked three-dimensional semiconductor memory, the cell array 110 arranges columnar cell blocks CB0 to CB3 in a two-dimensional arrangement in the XY direction on the +Z side. The columnar cell blocks CB0 to CB3 are connected in the Z direction to form a three-dimensional arrangement of memory cells MC. On the semiconductor substrate 21, source lines SL are arranged in a two-dimensional arrangement in the XY direction. It is not necessary for the multiple cell blocks CB0 to CB3 to be connected by odd-number lines WL1. o Even number line WL1 e The surrounding memory aperture MH. Multiple cell blocks CB0~CB3 are all connected by odd-number lines WL1. o Even number line WL1 e The line structure can be used. The number of unit blocks CB configured in the line structure can be 1 to 3, or even more than 5.

[0114] Each cell block CB0 to CB3 extends in the Z direction and penetrates the stacked layer 22 in the Z direction. Each cell block CB is composed of a columnar structure through which multiple conductive films WL0 to WL63 penetrate in the Z direction. The multiple cell blocks CB0 to CB3 are arranged in two dimensions in the XY direction. Each cell block CB includes a semiconductor film CH(WL) extending in the Z direction and functioning as a semiconductor channel, and a semiconductor film CH(SG). The semiconductor film CH(WL) penetrates the stacked layer 22 in the Z direction and functions as a semiconductor channel. A memory cell MC is formed at the intersection of the semiconductor film CH(WL) and the conductive film WL, and a cell block selection transistor SG is formed at the intersection of the semiconductor film CH(SG) and the conductive film SGD. The semiconductor film CH(SG) is the channel of the cell block selection transistor SG, connecting / disconnecting the bit line BL and the local bit line LBL.

[0115] Figure 12 The odd-number line WL1 of the multilayer three-dimensional semiconductor memory in the first embodiment o Even number line WL1 e A top view of the level. Figure 11 The three-dimensional composition in Figure 12 The middle corresponds to region B, which is surrounded by a dashed line.

[0116] like Figure 12 and Figure 13As shown, in the first embodiment of the multilayer three-dimensional semiconductor memory, the local bit lines LBL and local source lines LSL are configured such that the even-numbered lines and the odd-numbered lines have the same structure in the X direction. Here, the even-numbered lines refer to the odd-numbered lines WL0 and the even-numbered lines WL0 disposed on the -Y side relative to the odd-numbered lines WL0. e The configuration lines of local bit lines LBL and local source lines LSL are arranged alternately in a linear pattern along the X direction. The odd-numbered line is the even-numbered line WL. e With respect to even-numbered lines WL e The configuration lines of local bit lines LBL and local source lines LSL, arranged alternately in a linear pattern along the X direction between the odd-numbered lines WL0 on the -Y side. For example, Figure 12 In the example, line 0 is the odd-numbered line WL10 and the even-numbered line WL1, which is positioned on the -Y side relative to the odd-numbered line WL0. e The local source lines LSL and local bit lines LBL are arranged alternately in a linear configuration along the X direction. The first line is the even-numbered line WL1. e With respect to even-numbered lines WL e The first line is a configuration line of local source lines LSL and LBL, alternately arranged in a linear pattern along the X direction between the odd-numbered lines WL10 on the -Y side. The second line is the configuration line between the odd-numbered line WL10 and the even-numbered line WL1 on the -Y side relative to the odd-numbered line WL0. e The configuration lines are arranged in a linear pattern along the X direction, with local source lines LSL and local bit lines LBL arranged alternately. The same structure is arranged on each line in sequence as LSL0, LBL0, LSL1, LBL1, LSL2, LBL2, LSL3, LBL3, and LSL4.

[0117] like Figure 12 As shown, the multilayer three-dimensional semiconductor memory of the first embodiment includes: a plurality of odd-number lines WL1 extending in the X direction. o and multiple even-numbered lines WL1 e ; and the adjacent odd-numbered line WL1 in the Y direction. o and even number line WL1 e Multiple local bit lines LBL0-LBL3 and multiple local source lines LSL0-LSL4 are sandwiched between a gate insulator film GD and a semiconductor film CH (WL). A resistive switching film RE is disposed between the local bit lines LBL0-LBL3 and the semiconductor film CH (WL). Furthermore, the multiple local bit lines LBL0-LBL3 and the multiple local source lines LSL0-LSL4 are sandwiched by an insulating film DF and arranged alternately in a straight line. The multiple local bit lines LBL0-LBL3 and the multiple local source lines LSL0-LSL4 are arranged in a columnar shape in the Z direction. Additionally, multiple odd-number lines WL1... o and multiple even-numbered lines WL1e It features a flat plate structure extending in the XY plane and is stacked in the Z direction. Multiple odd-numbered lines WL1 o The ends are connected in a common manner in the +X direction. Multiple even-numbered lines WL1 e The ends are connected in a common manner in the -X direction. Odd-number lines WL1 o Select transistor WLSW1 connected to odd-number lines o Even number line WL1 e Connect the even-numbered selection transistor WLSW1 e Each part can be controlled independently. The structure of each part can be compared with... Figure 8B Similarly, it is formed. For example, the resistive switching film RE can be disposed around the local bit lines LBL0 to LBL3. A thermal barrier film HB1 can be disposed between the resistive switching film RE and the local bit line LBL, or a thermal barrier film HB2 can be disposed between the resistive switching film RE and the semiconductor film CH. Furthermore, a thermal barrier film HB3 can be disposed between the local source line LSL and the semiconductor film CH. A heating film HT can also be used instead of thermal barrier films HB1 and HB2. Alternatively, both films HB1, HB2, and HT can be used. The heating film HT can be disposed on the outer periphery of the resistive switching film RE between the semiconductor films CH.

[0118] The stacked three-dimensional semiconductor memory of the first embodiment is as follows: Figure 11 and Figure 12 As shown, it includes a semiconductor substrate 21, a first electrode line (LSL1), a second electrode line (LBL1), a first resistive switching film RE1, a first semiconductor film CH(WL)1, a first gate insulating film GD1, and a first potential application electrode (WL1). o ), the second resistive switching film RE2, the second gate insulator film GD2, and the second potential application electrode (WL1) e ).

[0119] The first electrode line (LSL1) extends in the Z direction orthogonal to the semiconductor substrate 21. The second electrode line (LBL1) is disposed adjacent to the first electrode line in the X direction orthogonal to the Z direction and extends in the Z direction. The first resistive switching film RE1 extends in the Z direction and contacts the second electrode line (LBL1). The first semiconductor film CH(WL)1 contacts the first resistive switching film RE1 and the first electrode line (LSL1). The first gate insulator film GD1 extends in the Z direction and contacts the first semiconductor film CH(WL)1. The first potential application electrode (WL1) oThe first electrode (LBL1) extends in the X direction and contacts the first gate insulator film GD1. The second resistive switching film RE2 extends in the Z direction and is disposed in the negative direction (-Y direction) relative to the first resistive switching film RE1, contacting the second electrode line (LBL1). The second semiconductor film CH(WL)2 contacts the second resistive switching film RE2 and the first electrode line (LSL1). The second gate insulator film GD2 extends in the X direction and contacts the second semiconductor film CH(WL)2. The second potential application electrode (WL1) e It extends in the X direction and contacts the second gate insulating film GD2. Here, the first potential application electrode (WL1) o ) and the second potential applied electrode (WL1) e These are electrically distinct nodes that can be controlled independently.

[0120] Electrode (WL1) is applied to the second semiconductor film CH(WL)2 at the second potential. e The first memory cell MC1 at the intersection e During the write operation, an electrode (WL1) is applied to the second potential. e Apply a selection voltage (V) WH3 Electrode (WL1) is applied to the first potential. o Apply a voltage lower than the selected voltage (V) WH3 The non-selective voltage (V) L3 ). Here, V L3 <V WH3 V L3 The value is the low-level voltage V. SS , or 0V.

[0121] (Separating membrane SHE)

[0122] Figure 13 This is a top view of the selected gate lines SGD0 to SGD4 levels of the multilayer three-dimensional semiconductor memory according to the first embodiment. Figure 11 The three-dimensional composition in Figure 13 The area in the middle corresponds to region B, which is surrounded by a dashed line. The stacked three-dimensional semiconductor memory of the first embodiment is as follows... Figure 13The diagram shows multiple select gate lines SGD0 to SGD4 extending in the X direction. A breaking film SHE is disposed between select gate line SGD0 and select gate line SGD1, and is electrically insulated therefrom. A breaking film SHE is also disposed between select gate line SGD1 and select gate line SGD2. A breaking film SHE is also disposed between select gate line SGD2 and select gate line SGD3. A breaking film SHE is also disposed between select gate line SGD3 and select gate line SGD4. Select gate lines SGD1 to SGD3 are connected to select gate line select transistors SGSW1 to SGSW3, and can be controlled independently. The reason for separating select gate lines SGD0 to SGD4 with breaking films SHE is that if they were not separated, two local bit lines LBL would be connected to one bit line BL. By separating the selected gate lines SGD0 to SGD4 with the severing film SHE, the bit lines BL0 to BL3 can be connected to the local bit lines LBL0 to LBL3 respectively.

[0123] like Figure 13 As shown, in the stacked three-dimensional semiconductor memory of the first embodiment, the spacing of the bit lines BL is represented by XP1. Furthermore, the spacing of the word lines WL is represented by YP1. In the stacked three-dimensional semiconductor memory of the first embodiment, as... Figure 13 As shown, the spacing XP1 of the bit line BL is equal to the distance between the two local bit lines LBL. Therefore, the bit line BL can be formed wide and thick, and the wiring resistance of the bit line BL can be reduced.

[0124] like Figure 13 As shown, the multilayer three-dimensional semiconductor memory of the first embodiment includes an electrode (WL1) applied at a first potential. o A third potential-applying electrode (SGD1, SGD0) is disposed above the third potential-applying electrode, which is positioned along the Z-direction and extends in the X-direction. Figure 13 As shown, the stacked three-dimensional semiconductor memory of the first embodiment includes a splitting film SHE that extends in the X direction and contacts the third potential application electrodes (SGD1, SGD0), and the third potential application electrodes (SGD1, SGD0) are separated from each other in the Y direction by the splitting film SHE.

[0125] Figure 14 It is along Figure 12 Line II and Figure 13A cross-sectional view of line IV-IV. In the uppermost insulating layer 222 of the stacked body 22, select gate lines SGD0 and SGD1 are stacked. Select gate lines SGD0 and SGD1 select unit blocks CB0 to CB3. Select gate lines SGD0 and SGD1 are composed of plate-shaped conductive films extending in the XY direction. Hereinafter, select gate lines SGD0 and SGD1 will sometimes be referred to as conductive films SGD0 and SGD1. Conductive films SGD0 and SGD1 are formed of a material whose main component is a conductive material (e.g., a metal such as tungsten). Conductive films SGD0 and SGD1 utilize a segmentation film SHE (see reference). Figure 11 and Figure 13 The film is segmented in the Y direction. The segmented membrane SHE is disposed on the conductive membrane WL0. o WL0 e Above (on the +Z side), extending in the XZ direction, it reaches the uppermost insulating layer 222 of the stack 22. The segmentation film SHE is formed of an insulating material (e.g., silicon oxide). Thus, the select line gate lines SGD of each cell block are electrically insulated from each other.

[0126] In the stacked body 22, the word lines WL0 to WL63 are connected to the insulating layer 222 (see reference). Figure 14 The layers are repeatedly stacked in the Z-direction. The word lines WL0 to WL63 are composed of plate-shaped conductive films extending in the XY-direction. Hereinafter, the word lines WL0 to WL63 will sometimes be referred to as conductive film WL. Furthermore, the word lines WL0 to WL63 are separated into odd-number lines WL0. o ~WL63 o and even number lines WL0 e ~WL63 e In the laminate 22, multiple conductive films WL0 to WL63 are arranged separately from each other in the Z direction. Each conductive film WL0 to WL63 is formed of a material mainly composed of a conductive material (e.g., a metal such as tungsten). Each insulating layer 222 is formed of a material mainly composed of an insulating material (e.g., silicon oxide).

[0127] Figure 15 It is along Figure 12 Line II-II and Figure 13 A cross-sectional view of the VV line. (e.g.) Figure 15As shown, local source lines LSL0-LSL4 and local bit lines LBL0-LBL3 are arranged in the X direction. Local source lines LSL0-LSL4 are connected to source line SL in the negative Z direction via contact plug CP2. Local bit lines LBL0-LBL3 are connected to local bit line termination sections LBL0E-LBL3E in the +Z direction. Local bit lines LBL0-LBL3 and local bit line termination sections LBL0E-LBL3E are connected / disconnected via select transistors SG0-SG3 with semiconductor films CH (SG). Local bit line termination sections LBL0E-LBL3E are connected to bit lines BL0-BL3 via contact plug CP1.

[0128] Figure 16 It is along Figure 12 A cross-sectional view along line III-III. (See example...) Figure 16 As shown, word lines WL0 to WL63 and insulating layer 222 are repeatedly laminated in the Z direction. Word lines WL0 to WL63 are separated into odd-number lines WL0. o ~WL63 o Even number line WL0 e ~WL63 e The insulating layer 222 at the top of the stacked body 22 has select gate lines SGD1 and SGD2. Select gate lines SGD1 and SGD2 select cell blocks CB0 to CB3. Conductive films SGD1 and SGD2 are separated in the Y direction using a segmentation film SHE. The segmentation film SHE is disposed on conductive film WL0. o WL0 e Above (on the +Z side) and extending in the XZ direction, it reaches the uppermost insulating layer 222 of the stack 22. Thus, the selected gate lines SGD of each cell block are electrically insulated from each other.

[0129] Figure 17 It is along Figure 12 A cross-sectional view along line VI-VI. (See example...) Figure 17 As shown, multiple local bit lines LBL1 extending in the Z direction are arranged in the Y direction. In the +Y direction of the local bit line LBL1 of the 0th line sandwiched by the select gate line SGD1, the odd-numbered bit line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local bit line LBL1 of the 0th line sandwiched by the selected gate line SGD1, the even-numbered bit line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local bit line LBL1 of the first line sandwiched by the selected gate line SGD2, the even-numbered bit line WL0... e ~WL63 eAn insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local bit line LBL1 of the first line sandwiched by the selected gate line SGD2, the odd-number bit line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local bit line LBL1 of the second line sandwiched by the selected gate line SGD3, the odd-number bit line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local bit line LBL1 of the second line sandwiched by the selected gate line SGD3, the even-numbered bit line WL0... e ~WL63 e An insulating layer 222 is used to deposit layers in the Z direction. In the uppermost insulating layer 222 of the deposited layer 22, selector gate lines SGD0 to SGD4 are stacked in the Y direction using a segmentation film SHE. A local bit line LBL1 is connected to a local bit line termination portion LBL1E in the +Z direction. Regarding the local bit line LBL1 and the local bit line termination portion LBL1E, the local bit line termination portion LBL1E is connected to the bit line BL1 via a contact plug CP1.

[0130] Figure 18 It is along Figure 12 A sectional view along line VII-VII. (See example...) Figure 18 As shown, multiple local source lines LSL1 extending in the Z direction are arranged in the Y direction. In the +Y direction of the local source line LSL1 of the 0th line sandwiched by the selected gate line SGD1, the odd-numbered line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local source line LSL1 of the 0th line sandwiched by the selected gate line SGD1, the even-numbered line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local source line LSL1 of the first line sandwiched by the selected gate line SGD2, the even-numbered line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local source line LSL1 of the first line sandwiched by the selected gate line SGD2, the odd-number line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local source line LSL1 of the second line sandwiched by the selected gate line SGD3, the odd-number line WL0... o ~WL63 oAn insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local source line LSL1 of the second line sandwiched by the selected gate line SGD3, the even-numbered line WL0... e ~WL63 e An insulating layer 222 is used to deposit the stacked layers in the Z direction. At the top of the stacked layer 222, the insulating layer 222 contains selectable gate lines SGD0 to SGD4, which are separated in the Y direction by a segmentation film SHE. A local source line LSL1 is connected to the source line SL in the -Z direction via a contact plug CP2.

[0131] (Contact plug CP1)

[0132] like Figure 15 and Figure 17 As shown, a contact plug CP1 is disposed between bit lines BL0-BL3 and local bit line termination portions LBL0E-LBL3E. In this case, the upper end of the contact plug CP1 contacts bit lines BL0-BL3, and the lower end contacts local bit line termination portions LBL0E-LBL3E. At the intersection of the semiconductor film CH(SG) and the conductive films SGD0-SGD3 between the local bit line termination portions LBL0E-LBL3E and the local bit lines LBL0-LBL3, unit block selection transistors SG0-SG3 are formed. The local bit line termination portions LBL0E-LBL3E and the local bit lines LBL0-LBL3 can be electrically connected via the semiconductor film CH(SG). The contact plug CP1 is formed of a material whose main component is a conductive material (e.g., a metal such as tungsten).

[0133] (Contact plug CP2)

[0134] like Figure 15 and Figure 18 As shown, a contact plug CP2 is disposed between the source line SL and the local source line LSL. In this case, the upper end of the contact plug CP2 contacts the local source lines LSL0 to LSL4, and the lower end contacts the source line SL, thereby electrically connecting the source line SL and the local source lines LSL0 to LSL4. The contact plug CP2 is formed of a material whose main component is a conductive material (e.g., a metal such as tungsten).

[0135] (Effects of the first embodiment)

[0136] According to the first embodiment, a multilayer three-dimensional semiconductor memory capable of achieving high cell density can be provided.

[0137] (Second Implementation)

[0138] Figure 19 This is a top view of the word line levels of the multilayer three-dimensional semiconductor memory according to the second embodiment. Additionally, Figure 20This is a top view of the selected gate line level of the multilayer three-dimensional semiconductor memory according to the second embodiment. (As shown) Figure 19 and Figure 20 As shown, the stacked three-dimensional semiconductor memory of the second embodiment has the following structure: the local bit line LBL and the local source line LSL are arranged such that the even-numbered lines and the odd-numbered lines are offset in the X direction by a distance XP2 in the X direction. Here, the even-numbered lines refer to the odd-numbered lines WL0 and the even-numbered lines WL0 arranged on the -Y side relative to the odd-numbered lines WL0. e The configuration lines are local source lines LSL and local bit lines LBL, arranged alternately in a linear pattern along the X direction. The odd-numbered line is the one above the even-numbered line WL. e With respect to even-numbered lines WL e The configuration lines of local bit lines LBL and local source lines LSL, arranged alternately in a linear pattern along the X direction between the odd-numbered lines WL0 on the -Y side. For example, Figure 19 In the example, line 0 is the odd-number line WL10 and the even-number line WL1, which is positioned on the -Y side relative to the odd-number line WL10. e The local source lines LSL and local bit lines LBL are arranged alternately in a linear configuration along the X direction. The first line is the even-numbered line WL1. e Compared to the even-number line WL1 e The local bit line LBL and the local source line LSL are arranged alternately in a linear configuration along the X direction between the odd-numbered line WL10 on the -Y side. The second line is the configuration line between the odd-numbered line WL10 and the even-numbered line WL10 arranged on the -Y side relative to the odd-numbered line WL10. e The configuration lines are arranged alternately along the X-direction as local source lines (LSLs) and local bit lines (LBLs). In lines 0 and 2, LSL0, LBL1, LSL2, LBL3, LSL4, LBL5, LSL6, LBL7, and LSL8 are arranged sequentially. In line 1, LBL0, LSL1, LBL2, LSL3, LBL4, LSL5, LBL6, LSL7, and LSL8 are arranged sequentially.

[0139] like Figure 19 and Figure 20 As shown, in the stacked three-dimensional semiconductor memory of the second embodiment, the spacing of the bit line BL is represented by XP2. Furthermore, the spacing of the word line WL is represented by YP2.

[0140] like Figure 19 and Figure 20 As shown, the stacked three-dimensional semiconductor memory of the second embodiment includes multiple odd-number lines WL0 and even-number lines WL arranged parallel to each other in the Y direction. eThe local source line LSL and the local bit line LBL are arranged in the X-direction with even-numbered lines offset from odd-numbered lines. The X-direction spacing between the local source line LSL and the local bit line LBL is approximately half the X-direction spacing, represented by a distance XP2. Here, XP2 is spaced equal to the spacing of the bit line BL.

[0141] The second embodiment of the multilayer three-dimensional semiconductor memory eliminates the need for a segmented film SHE by staggering the local bit lines LBL and local source lines LSL in the X direction by a spacing XP2 in the X direction between the odd-numbered and even-numbered lines. Therefore, the spacing YP2 in the Y direction can be made to be the same as the spacing YP1 in the first embodiment (refer to...). Figure 13 Compared to reducing the width of the segmented membrane SHE by such a large amount, the cell size can be reduced accordingly.

[0142] Figure 21 It is along Figure 19 and Figure 20 The cross-sectional view along lines VIII-VIII shows the cross-sectional construction along the even-numbered line (the 0th line). Figure 21 Corresponding to the first embodiment Figure 15 The difference lies in reducing the spacing between bit lines BL0 to BL8, thus shrinking the size in the X direction. For example... Figure 21 As shown, the even-numbered local source lines LSL0 to LSL8 and the odd-numbered local bit lines LBL1 to LBL7 are arranged in the X direction. The even-numbered local source lines LSL0 to LSL8 are connected to the source line SL in the negative Z direction via contact plug CP2. The odd-numbered local bit lines LBL1 to LBL7 are connected to the local bit line termination portions LBL1E to LBL7E in the +Z direction. The local bit line termination portions LBL1E to LBL7E are connected to the odd-numbered bit lines BL1 to BL7 via contact plug CP1.

[0143] Figure 22 It is along Figure 19 and Figure 20 The sectional view along line IX-IX shows the cross-sectional construction along the odd-numbered line (the first line). For example... Figure 22 As shown, the even-numbered local bit lines LBL0 to LBL8 and the odd-numbered local source lines LSL1 to LSL7 are arranged in the X direction. The odd-numbered local source lines LSL1 to LSL7 are also connected to the source line SL in the negative Z direction via contact plug CP2. The even-numbered local bit lines LBL0 to LBL8 are connected to the local bit line termination portions LBL0E to LBL8E in the +Z direction. The local bit line termination portions LBL0E to LBL8E are connected to the even-numbered bit lines BL0 to BL8 via contact plug CP1.

[0144] Furthermore, when the local bit line LBL is arranged at the ends of each line in the X direction or the negative X direction, the local bit line can be set as a dummy bit line (a bit line that does not operate). In addition, it can be used as long as the current conducting in the unit transistor can be sufficiently ensured and it can operate.

[0145] In the stacked three-dimensional semiconductor memory of the second embodiment, the select gate lines SGD1 to SGD4 do not need to be separated using a splitting film SHE. The select gate lines SGD1 to SGD4 are connected to the select gate line select transistors SGSW1 to SGSW4 and can be controlled independently. The driving method is as follows: By driving any one of the select gate lines SGD1 to SGD4 located directly above the select word line WL that is set to ON, memory cells are connected to all bit lines BL0 to BL8 one by one. Furthermore, when driving any one of the select gate lines directly above the select word line WL that is not set to ON, memory cells are connected to half of the bit lines. From the perspective of a certain word line WL, the cell transistors MT and MT' on both sides are connected to different bit lines BL, so they can be set to ON simultaneously. Therefore, the select gate lines SGD1 to SGD4 do not need to be separated using a splitting film SHE.

[0146] (Effects of the second implementation method)

[0147] According to the second embodiment, a multilayer three-dimensional semiconductor memory can be provided that simplifies the structure by eliminating the need for a splitting film and allows for high cell density. Furthermore, since a splitting film is not required, the spacing YP in the Y direction can be reduced, thereby miniaturizing the cell size.

[0148] (Third Implementation)

[0149] Figure 23 This is a top view of the selected gate line level of the stacked three-dimensional semiconductor memory according to the third embodiment. The top view of the word line level is related to... Figure 12 (The first embodiment) is the same, so the illustration is omitted. Figure 24 It is along Figure 23 A cross-sectional view along the XX line. Figure 25 It is along Figure 23 A cross-sectional view along line XI-XI. (See example...) Figures 23-25 As shown, the stacked three-dimensional semiconductor memory of the third embodiment has multiple bit lines BL0 to BL7 extending in the Y direction. With respect to the even-numbered bit lines BL0 to BL6, local bit lines LBL0 to LBL6 belonging to the even-numbered bit lines are connected. With respect to the odd-numbered bit lines BL1 to BL7, local bit lines LBL1 to LBL7 belonging to the odd-numbered bit lines are connected.

[0150] In the stacked three-dimensional semiconductor memory of the third embodiment, odd-number lines WL o Even number line WL e The configurations of the local bit line (LBL) and the local source line (LSL) are the same as in the first embodiment. Furthermore, the configuration of the selected gate line (SGD) is the same as in the second embodiment. In the multilayer three-dimensional semiconductor memory of the third embodiment, the selected gate line (SGD) does not require a separation film (SHE).

[0151] like Figure 23 and Figure 24 As shown, in the stacked three-dimensional semiconductor memory of the third embodiment, the spacing of the bit lines BL is denoted by XP3. Furthermore, the spacing of the word lines WL is denoted by YP3. The spacing XP3 of the bit lines BL in the stacked three-dimensional semiconductor memory of the third embodiment is equal to the spacing XP2 of the bit lines BL in the stacked three-dimensional semiconductor memory of the second embodiment. Furthermore, the spacing YP3 of the word lines WL in the stacked three-dimensional semiconductor memory of the third embodiment is equal to the spacing YP2 of the word lines WL in the stacked three-dimensional semiconductor memory of the second embodiment.

[0152] In the stacked three-dimensional semiconductor memory of the third embodiment, such as Figure 23 and Figure 24 As shown, it includes a contact plug CP3 connected to bit lines BL0 to BL6, and metal layers CE0 to CE6 connected to the contact plug CP3. Instead of directly connecting the contact plug CP1, which is connected to the local bit line termination portions LBL0E to LBL6E, to the bit lines BL0 to BL6, it is offset in the -X direction by approximately half a distance XP3, separated by the metal layers CE0 to CE6 extending in the X direction, and then connected to the contact plug CP3 and the bit lines BL0 to BL6.

[0153] In the stacked three-dimensional semiconductor memory of the third embodiment, such as Figure 23 and Figure 25 As shown, the device includes a contact plug CP3 connected to bit lines BL1 to BL7, and metal layers CE1 to CE7 connected to the contact plug CP3. Instead of directly connecting the contact plug CP1, which is connected to the local bit line termination portions LBL1E to LBL7E, to the bit lines BL1 to BL7, the metal layers CE1 to CE7 extending in the X direction are offset in the +X direction by approximately half a distance XP3, and the device is connected to the contact plug CP3 and the bit lines BL1 to BL7.

[0154] like Figure 23 and Figure 24 As shown, the stacked three-dimensional semiconductor memory of the third embodiment has local bit lines LBL and local source lines LSL alternately arranged on each line.

[0155] Figure 26 It is along Figure 23 A cross-sectional view along line XII-XII. (See example...) Figure 26 As shown, multiple local bit lines LBL0, LBL1, and LBL0 extending in the Z direction are arranged in the Y direction. In the +Y direction of the local bit line LBL0 of the 0th line sandwiched between select gate line SGD1 and select gate line SGD2, the odd-number bit line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local bit line LBL0 of the 0th line sandwiched between select gate line SGD1 and select gate line SGD2, the even-numbered bit line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local bit line LBL1 of the first line sandwiched between select gate line SGD2 and select gate line SGD3, the even-number bit line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local bit line LBL1 of the first line sandwiched between select gate line SGD2 and select gate line SGD3, the odd-number line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local bit line LBL0 of the second line sandwiched between select gate line SGD3 and select gate line SGD4, the odd-number line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local bit line LBL0 of the second line sandwiched between select gate line SGD3 and select gate line SGD4, the even-number bit line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. Select gate lines SGD1 to SGD4 are deposited on the uppermost insulating layer 222 of the stacked body 22. A local bit line LBL0 is connected to a local bit line termination portion LBL0E in the +Z direction. The local bit line termination portion LBL0E is connected to the bit line BL0 via a contact plug CP1 and a metal layer CE0. A local bit line LBL1 is connected to a local bit line termination portion LBL1E in the +Z direction. The local bit line termination portion LBL1E is connected to the bit line BL1 via a contact plug CP1 and a metal layer CE1.

[0156] Figure 27 It is along Figure 23 A cross-sectional view of line XIII-XIII. (See example...) Figure 27As shown, multiple local source lines LSL2 extending in the Z direction are arranged in the Y direction. In the +Y direction of the local source line LSL2 of the 0th line sandwiched between the select gate line SGD1 and the select gate line SGD2, the odd-numbered line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local source line LSL2 of the 0th line sandwiched between select gate line SGD1 and select gate line SGD2, the even-number line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local source line LSL2 of the first line sandwiched between select gate line SGD2 and select gate line SGD3, the even-numbered line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local source line LSL2 of the first line sandwiched between select gate line SGD2 and select gate line SGD3, the odd-number line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. In the +Y direction of the local source line LSL2 of the second line sandwiched between select gate line SGD3 and select gate line SGD4, the odd-number line WL0... o ~WL63 o An insulating layer 222 is deposited in the Z direction. Additionally, in the -Y direction of the local source line LSL2 of the second line sandwiched between select gate line SGD3 and select gate line SGD4, the even-number line WL0... e ~WL63 e An insulating layer 222 is deposited in the Z direction. The local source line LSL2 is connected to the source line SL in the -Z direction via a contact plug CP2.

[0157] The third embodiment of the multilayer three-dimensional semiconductor memory does not require the local source line LSL and local bit line LBL to be staggered in the X direction by the even-numbered lines and the odd-numbered lines. Therefore, it also has the advantage of easier manufacturing compared to the multilayer three-dimensional semiconductor memory of the second embodiment.

[0158] In the stacked three-dimensional semiconductor memory of the third embodiment, the select gate lines SGD1 to SGD4 do not need to be separated using a splitting film SHE. The select gate lines SGD1 to SGD4 are connected to select gate line select transistors SGSW1 to SGSW4, and can be controlled independently. The driving method is the same as in the second embodiment.

[0159] In the stacked three-dimensional semiconductor memory of the third embodiment, the segmentation film SHE can be eliminated as in the second embodiment while the local bit line LBL of the first embodiment is configured.

[0160] (Effects of the third embodiment)

[0161] According to the third embodiment, a multilayer three-dimensional semiconductor memory can be provided that simplifies the structure by eliminating the need for a splitting film and allows for high cell density. Furthermore, since a splitting film is not required, the spacing YP in the Y direction can be reduced, thereby enabling miniaturization of the cell size. Additionally, the arrangement of local bit lines LBL and local source lines LSL can be made identical on both even-numbered and odd-numbered lines, simplifying the pattern layout and facilitating manufacturing processes.

[0162] (Fourth implementation: Connection configuration and construction)

[0163] Figure 28 The comparative example is a multilayered three-dimensional semiconductor memory cell array block BLKi, and includes peripheral select gate lines SGD0~SGD3 and word line WL0. o WL1 o A top view of the word line contacts CW0, CW1, ... . The cell array section shows bit lines BL0 to BLn-1, but internal details are omitted. In... Figure 28 When the selected gate lines SGD0 to SGD3 are configured as shown, the diameter of the stepped contact is as follows: Figure 28 As shown, the width is greater than that of the selected gate lines SGD0 to SGD3, thus making it impossible to obtain the stepped contacts of the selected gate lines SGD0 to SGD3.

[0164] Figure 29 These are the blocks BLKi and BLK(i+1) of the cell array of the multilayer three-dimensional semiconductor memory in the fourth embodiment, and are the peripheral select gate lines SGD0 to SGD3 and word line WL0. o WL1 o Select the top view of the gate line contacts CSG0~CSG3 and the word line contacts CW0, CW1, ... . Figure 29 As shown, in the multilayer three-dimensional semiconductor memory of the fourth embodiment, by sharing the select gate lines SGD0 to SGD3 of the peripheral portion with the adjacent blocks BLKi and BLK(i+1), the location of the select gate line contacts CSG0 to CSG3 can be ensured. Select gate line contacts CSG0 and CSG1 can be shared with the adjacent blocks BLKi and BLK(i+1). Select gate line contacts CSG2 and CSG3 can be shared with the adjacent blocks BLK(i-1) and BLK(i). Alternatively, they can be shared with the adjacent blocks BLK(i+1) and BLK(i+2).

[0165] Figure 30 It is a multilayered three-dimensional semiconductor memory according to the fourth embodiment, and it is along... Figure 29 A cross-sectional view of XIV-XIV. The cell array portion shows bit lines BL0-BLn-1 connected to local bit line termination portions LBL0E-LBL(n-1)E via local source lines LSL0-LSLn-1, local bit lines LBL0-LBLn-1, local bit line termination portions LBL0E-LBL(n-1)E, and contact plug CP1. Internal details are omitted, and the structures of embodiments 1-3 can be applied. In the multilayer three-dimensional semiconductor memory of embodiment 4, as... Figure 29 and Figure 30 As shown, the select gate line contacts CSG0 and CSG1 can be removed. Additionally, the odd-numbered lines WL0, which are stacked in a stepped manner... o ~WL63 o The peripheral part allows access to the character line contacts CW0 to CW63. Even number lines WL0... e ~WL63 e The surrounding parts are the same, so the illustration is omitted.

[0166] (Effects of the fourth embodiment)

[0167] According to the fourth embodiment, a multilayer three-dimensional semiconductor memory can be provided that simplifies the configuration of word line contacts and selectable gate line contacts in the peripheral area and enables high cell density.

[0168] Furthermore, in the resistive switching non-volatile memory of embodiments 1 to 3, the resistive switching film RE of the memory cell MC is formed of a phase change material, a superlattice film material, a magnetic material, or a resistive switching material. The phase change material includes a chalcogenide-based material, the superlattice film material includes a GeTe and SbTe stacked structure, the magnetic material is composed of a tunnel membrane sandwiched between a free layer and a plug layer, and the resistive switching material includes materials selected from NiO. X WO X TaO X TiO X HfO X ZnO X , TiON, Ag-GeSe, Cu-GeSe, FeO X GeO XAt least one of the groups consisting of STO and S2O. Furthermore, the storage element MR of the storage cell MC may be configured as follows: Specifically, in addition to including (I) the alloy-type phase transfer element (Ge2Sb2Te5), it also includes (II) alternating layers of GeTe and Sb2Te3 as interface-type phase transfer elements, (III) alternating layers of GeTe and BiSbTe as interface-type phase transfer elements, (IV) alternating layers of Ge, Sb, and Te, or chalcogenide materials, and (V) TiO2 as a resistive switching film. X WO X HfO X TaO X (V) is any one of the CoFe alloy, NiFe alloy, etc. used as MTJ elements.

[0169] In the resistive non-volatile memory of embodiments 1 to 3, the local source line LSL and the local bit line LBL are rectangular or approximately rectangular in shape on the XY plane, but are not necessarily limited to rectangles. They can also be circular, elliptical, oblong, or semi-circular. Figure 11 The prism shape can also be a cylindrical shape, etc.

[0170] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and also within the scope equivalent to the invention described in the claims.

[0171] [Explanation of Symbols]

[0172] 1. Storage System

[0173] 21 Semiconductor substrate

[0174] 22. Laminated body

[0175] 23-layer interlayer insulating film

[0176] 100-layer three-dimensional semiconductor memory

[0177] 108 Peripheral Circuits

[0178] 110-cell array

[0179] 120-line decoder

[0180] 120 o Odd Decoder

[0181] 120 e Even Decoder

[0182] 130 driver circuit

[0183] 140 Sensing Amplifier

[0184] Address Register 150

[0185] 160 Instruction Register

[0186] 170 Sequence Generator

[0187] 200 controller

[0188] 210 Host Interface Circuit

[0189] 220 Internal RAM

[0190] 222 Insulation layer

[0191] 230 processor

[0192] 240 Buffer Memory

[0193] 250 Memory Interface Circuit

[0194] 260 ECC circuit

[0195] 300 host

[0196] CB,CB0~CB9 unit blocks

[0197] BLK0~BLK(m-1),BLKi,BLK(i+1) blocks

[0198] CH,CH(SG),CH(WL) semiconductor film

[0199] GD gate insulator film

[0200] BL0~BL(n-1) bit lines

[0201] SL source line

[0202] Local bit lines LBL0~LBL8

[0203] Local source lines from LSL0 to LSL8

[0204] LBL0E~LBL(n-1)E Local bit line termination part

[0205] MC, MC0~MC63 memory units

[0206] MT,MT' unit transistor

[0207] RE, RE1, RE2, RE0~RE63 Resistive switching films (resistive switching elements)

[0208] WL0~WL63 letter lines (conductive film)

[0209] WL0 o ~WL(k-1) o Odd Number Line

[0210] WLO e ~WL(k-1) e Even number lines

[0211] SG0, SG1, SG2, SG3 select transistors

[0212] SGD0, SGD1, SGD2, SGD3, SGD4 Select gate lines (conductive films)

[0213] DF insulating film

[0214] SHE breaking membrane

[0215] HB1, HB2, HB3 thermal barrier films

[0216] HT heating film

[0217] CSG0, CSG1, CSG2, CSG3 select gate line contacts

[0218] CW0, CW1 word line contacts.

Claims

1. A stacked three-dimensional semiconductor memory, comprising: Semiconductor substrate; The first electrode line extends in a first direction orthogonal to the semiconductor substrate; The second electrode line is disposed adjacent to the first electrode line in a second direction orthogonal to the first direction, and extends in the first direction; The first resistive switching film extends in the first direction and contacts the second electrode line; The first semiconductor film is in contact with the first resistive switching film and the first electrode line; A first insulating layer extends in the first direction and is in contact with the first semiconductor film; The first potential-applying electrode extends in the second direction and contacts the first insulating layer; The second resistive switching film extends in the first direction and is disposed in the negative direction of the third direction, which is orthogonal to the first direction and the second direction, and is in contact with the second electrode line; The second semiconductor film is in contact with the second resistive switching film and the first electrode line; A second insulating layer extends in the second direction and is in contact with the second semiconductor film; and A second potential-applying electrode extends in the second direction and contacts the second insulating layer; and The first potential application electrode and the second potential application electrode are at electrically different nodes; The first electrode line is the source electrode line, and the second electrode line is the bit line.

2. The multilayer three-dimensional semiconductor memory according to claim 1, comprising: a third potential application electrode disposed above the first potential application electrode along the first direction and extending along the second direction; and Select a transistor and configure it at the position where the second semiconductor film intersects with the third potential application electrode.

3. The multilayer three-dimensional semiconductor memory according to claim 2, comprising a first memory cell disposed at a position where the second semiconductor film intersects with the second potential application electrode. When performing a write operation on the first storage unit A selection voltage is applied to the electrode at the second potential. A non-selection voltage lower than the selection voltage is applied to the electrode at the first potential.

4. The stacked three-dimensional semiconductor memory according to claim 3, wherein when reading the first memory cell, a first selected gate voltage is applied to the third potential application electrode, and when writing to the first memory cell, a second selected gate voltage higher than the first selected gate voltage is applied to the third potential application electrode.

5. The stacked three-dimensional semiconductor memory according to claim 3, wherein when reading the first memory cell, a first voltage is applied to the second potential application electrode, and when writing to the first memory cell, a second voltage higher than the first voltage is applied to the second potential application electrode.

6. The stacked three-dimensional semiconductor memory according to claim 3, comprising a third electrode line extending in the third direction and connected to the second electrode line in the first direction in which the second electrode line extends.

7. The stacked three-dimensional semiconductor memory according to claim 6, wherein when reading the first memory cell, a third voltage is applied to the third electrode line, and when writing to the first memory cell, a fourth voltage higher than the third voltage is applied to the third electrode line.

8. The stacked three-dimensional semiconductor memory according to claim 1, wherein the fourth electrode line is connected to the first electrode line in the negative direction of the first direction in which the first electrode line extends.

9. The multilayer three-dimensional semiconductor memory according to claim 2, comprising an insulating layer extending in the second direction and in contact with the third potential application electrode. The third potential applied electrode is separated from the insulating layer and thus separated from each other in the third direction.

10. The multilayer three-dimensional semiconductor memory according to claim 1, comprising a plurality of lines arranged parallel to each other in the third direction, the lines between the first potential application electrode and the second potential application electrode. The second direction of the first electrode line and the second electrode line is arranged such that the even-numbered lines are staggered from the odd-numbered lines.

11. The stacked three-dimensional semiconductor memory of claim 10, wherein the second direction of the second electrode line adjacent to the first electrode line is arranged such that the even-numbered lines are offset from the odd-numbered lines by half the distance between the first electrode line and the second electrode line in the second direction.

12. The multilayer three-dimensional semiconductor memory according to claim 11, comprising a plurality of third electrode lines extending in the third direction and connected to the second electrode line in the first direction in which the second electrode line extends. Regarding the even-numbered third electrode line, it is connected to the second electrode line belonging to the even-numbered line. The third electrode line, which is an odd-numbered line, is connected to the second electrode line, which is also an odd-numbered line.

13. The multilayer three-dimensional semiconductor memory according to claim 12, comprising: The second electrode line terminates at a point where the second electrode line extends in the first direction; The first electrode is connected to the termination portion of the second electrode line; The third electrode is connected to the even-numbered third electrode line; and The first metal layer is connected to the third electrode and extends in the negative direction of the second direction; The first electrode is connected to the third electrode at a position offset by half the spacing of the third electrode line in the negative direction of the second direction, separated by the first metal layer.

14. The stacked three-dimensional semiconductor memory according to claim 12, comprising: The second electrode line terminates at a point where the second electrode line extends in the first direction; The first electrode is connected to the termination portion of the second electrode line; The third electrode is connected to the odd-numbered third electrode line; and A second metal layer, connected to the third electrode, extends in the second direction; and The first electrode is connected to the third electrode at a position that is offset in the second direction by half the distance of the arrangement spacing of the third electrode line, through the second metal layer.

15. The multilayer three-dimensional semiconductor memory according to claim 1, further comprising: a first barrier film disposed between the first resistive switching film and the second electrode line; and The second barrier film is disposed between the first resistive switching film and the first semiconductor film.

16. The stacked three-dimensional semiconductor memory according to claim 15, further comprising a third barrier film disposed between the first semiconductor film and the first electrode line.

17. The multilayer three-dimensional semiconductor memory of claim 16, wherein the first barrier film, the second barrier film, and the third barrier film comprise materials selected from TiN, TaN, and TiO. X It is at least one of the groups consisting of C, CN, CW, and C-WN.

18. The stacked three-dimensional semiconductor memory according to claim 16, wherein the first barrier film, the second barrier film, and the third barrier film have a heating film.

19. The multilayer three-dimensional semiconductor memory of claim 18, wherein the heating film comprises germanium, tellurium, or a group III-V compound containing indium as an impurity.

20. The multilayer three-dimensional semiconductor memory according to any one of claims 1 to 19, wherein the first resistive switching film is formed of a phase change material, a superlattice film material, a magnetic material, or a resistive switching material. The phase change material comprises chalcogenide-based materials. The superlattice film material comprises a GeTe and SbTe stacked structure. The magnetic material is composed of a free layer and a plug layer sandwiching a tunnel membrane. The resistive switching material comprises NiO. X WO X TaO X TiO X HfO X ZnO X , TiON, Ag-GeSe, Cu-GeSe, FeO X GeO X At least one of the groups consisting of STO and STO.

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