Flip chip and method of manufacturing the same

Abstract

The application discloses a flip chip and a preparation method thereof, and belongs to the flip chip technical field. The method provided by the application is characterized in that first interconnection elements with a first compression strength are first bonded in pairs on a first group of adjacent substrates, and then second interconnection elements with a second compression strength are bonded in pairs on a second group of adjacent substrates, wherein the second group of adjacent substrates and the first group of adjacent substrates share one substrate, the second compression strength is smaller than the first compression strength and the first compression strength, and the second compression strength and the second compression strength are both smaller than the first compression strength and the first compression strength. Therefore, the application of the second compression strength will not cause the first interconnection elements to deform, that is, the interconnection elements bonded in the first flip bonding step will not deform in the subsequent flip bonding step, thereby helping to ensure that the spacing between the first group of adjacent substrates bonded in the first flip bonding step remains consistent.

Description

Technical Field

[0001] This application belongs to the field of flip chip technology, especially the field of superconducting quantum chip technology. In particular, this application relates to a flip chip and its fabrication method. Background Technology

[0002] Flip chip bonding is a microelectronic circuit interconnection technology that interconnects circuit structures located on the lower surface of a substrate with circuit structures located on the upper surface of another substrate using solder to form a stable and reliable mechanical and electrical connection. The main process method for flip chip bonding is thermoforming.

[0003] Quantum bits, located on quantum chips, are the basic units for performing quantum computing. To achieve large-scale expansion of qubits, quantum circuits on a substrate are typically interconnected by flip-chip bonding technology. However, when multiple layers are stacked through multiple bonding processes, the later flip-chip bonding process can easily affect the morphology of the earlier bonded interconnect components, thereby affecting the chip's performance parameters. Summary of the Invention

[0004] The purpose of this application is to provide a flip chip and a method for fabricating the same, which can achieve multilayer stacking without affecting the morphology of the previously soldered interconnect elements.

[0005] One aspect of this application provides a method for fabricating a flip chip, comprising:

[0006] First, the first interconnecting elements, located on a first set of adjacent substrates and having a first compressive strength, are joined together in pairs with a first pressure strength; and,

[0007] Then, the second interconnecting elements located on the second group of adjacent substrates and having the second compressive strength are joined together in pairs with the second pressure intensity. The second group of adjacent substrates and the first group of adjacent substrates share a common substrate. The second pressure intensity and the second compressive strength are both less than the first pressure intensity and the first compressive strength.

[0008] In some embodiments of the fabrication method described above, the cross-sectional area of ​​the second interconnecting element perpendicular to the axial direction is smaller than the cross-sectional area of ​​the first interconnecting element.

[0009] In some embodiments of the fabrication method described above, the number of second interconnect elements is less than the number of first interconnect elements.

[0010] In some embodiments of the preparation method described above, while applying a first pressure intensity to join the first interconnecting elements located on a first set of adjacent substrates and having a first compressive strength in pairs, the method further includes heating the first interconnecting elements in pairs at a first temperature.

[0011] In some embodiments of the preparation method described above, the first temperature is within 10°C lower than the melting point of the first interconnect element.

[0012] In some embodiments of the preparation method described above, while applying a second pressure intensity to join the second interconnecting elements located on the second set of adjacent substrates and having a second compressive strength in pairs, the method further includes: heating the second interconnecting elements located on the first layer at a second temperature, and heating the second interconnecting elements located on the second layer at a third temperature, wherein the distance between the first layer and the first interconnecting element is less than the distance between the second layer and the first interconnecting element, and the second temperature is lower than the third temperature.

[0013] In some embodiments of the preparation method described above, the second temperature is more than 10°C lower than the melting point of the first interconnecting element, and the third temperature is less than 10°C lower than the melting point of the second interconnecting element.

[0014] In some embodiments of the preparation method described above, both the first interconnecting element and the second interconnecting element are superconductors.

[0015] In some embodiments of the preparation method described above, the superconductor is indium, and the second temperature is 20°C to 30°C, and the third temperature is 150°C to 155°C.

[0016] Another aspect of this application provides a flip chip comprising: at least three stacked substrates, with adjacent substrates interconnected by opposing interconnect elements; wherein the interconnect elements include:

[0017] A first interconnecting element located on a first group of adjacent substrates, and a second interconnecting element located on a second group of adjacent substrates, wherein the second group of adjacent substrates and the first group of adjacent substrates share a common substrate, and the compressive strength of the first interconnecting element is greater than the compressive strength of the second interconnecting element.

[0018] For flip chips comprising at least three stacked substrates that require multiple flip-chip bonding steps, the flip-chip fabrication method provided in this application firstly bonds two pairs of first interconnect elements located on a first group of adjacent substrates with a first compressive strength using a first pressure intensity. Then, it bonds two pairs of second interconnect elements located on a second group of adjacent substrates with a second compressive strength using a second pressure intensity. The second group of adjacent substrates and the first group of adjacent substrates share a common substrate. Both the second pressure intensity and the second compressive strength are less than the first pressure intensity and the first compressive strength, respectively. Because the second pressure intensity and the second compressive strength are less than the first pressure intensity and the first compressive strength, applying the second pressure intensity will not cause deformation of the first interconnect elements. That is, the subsequent flip-chip bonding step will not cause softening or deformation of the interconnect elements bonded in the previous flip-chip bonding step, thereby helping to ensure that the spacing between the first group of adjacent substrates bonded in the previous flip-chip bonding step remains consistent. Therefore, when fabricating a flip chip through multiple flip-chip bonding steps, this application solves the problem in related technologies where the morphology of interconnect elements involved in the previous flip-chip bonding step easily changes in the subsequent flip-chip bonding step. Attached Figure Description

[0019] Figure 1 A schematic diagram of the operation of the inverted welding step in one embodiment provided in this application;

[0020] Figure 2 A schematic diagram of the operation of the post-flip welding step in one embodiment provided in this application;

[0021] Figure 3 This is a schematic diagram of a flip chip structure provided in one embodiment of this application.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1 – First substrate, 10 – First circuit, 11 – Lower first interconnect element;

[0024] 2 – Second substrate; 20 – Second circuit; 21 – Upper first interconnect element; 22 – Lower second interconnect element;

[0025] 3 – Third substrate, 30 – Third circuit, 31 – Upper second interconnect element;

[0026] 4 – First interconnect element; 5 – Second interconnect element. Detailed Implementation

[0027] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the various embodiments may be combined with and referenced to each other without contradiction.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0031] A quantum chip is the processor in a quantum computer that performs quantum calculations. The circuit structure that serves as the processing unit of the processor is usually called a qubit. A qubit can be understood as a two-level system that obeys the laws of quantum mechanics, and it can exist in any superposition of 0 and 1 states. Around the qubit are various circuit structures with different functions, such as the drive control signal line (xy-control line, also known as the xy control line or pulse modulation signal line) for XY rotation operations, the flux control signal line (z-control line, also known as the z control signal line or frequency modulation signal line) for Z rotation operations, the readout resonant cavity, and the coupler used for coupling connections between qubits. In a quantum chip, the circuit structures described above are generally referred to as quantum circuits.

[0032] Traditional quantum circuits are fabricated on a single substrate, resulting in limited space for forming qubits and hindering large-scale expansion of the number of qubits. To achieve large-scale qubit expansion, related technologies classify quantum circuits on different substrates and fabricate them on different substrates, then achieve stacked interconnection using flip-chip bonding technology. Flip-chip bonding, a microelectronic circuit interconnection technology, interconnects circuit structures located on the lower surface of one substrate with circuit structures located on the upper surface of another substrate using solder bumps, forming a stable and reliable mechanical and electrical connection. Compared to traditional wire bonding interconnection technology, flip-chip bonding technology offers higher density and increases the number of I / Os per unit area. Flip-chip bump fabrication is primarily done on a wafer or chip basis, which is more efficient than wire bonding interconnection, which uses single leads, thus reducing the cost of mass packaging.

[0033] When using flip-chip bonding technology to stack and interconnect three or more substrates to expand the number of qubits, multiple bonding processes are generally required to sequentially achieve the stacking and interconnection between different layers. Subsequent flip-chip bonding processes can easily affect the morphology and structure of components involved in earlier flip-chip bonding processes, thereby affecting chip performance parameters. For example, subsequent flip-chip bonding processes can easily change the height of interconnect components joined by earlier flip-chip bonding processes, thus affecting the consistency of the spacing between the two substrates interconnected in earlier flip-chip bonding processes, causing the substrates to tilt relative to each other. This ultimately leads to changes in chip performance parameters.

[0034] To avoid affecting the consistency of substrate spacing, this application provides a method for fabricating a flip chip and a flip chip.

[0035] The flip chip includes at least three stacked substrates formed through multiple flip-chip bonding steps. The substrates can be made of dielectric materials such as silicon or sapphire. Interconnect elements are formed on the substrates. The interconnect elements can be directly formed on the circuit structure on the substrates. Each flip-chip bonding step connects the interconnect elements on a set of adjacent substrates to achieve interconnection between the set of adjacent substrates. The set of adjacent substrates includes two substrates.

[0036] The flip-chip fabrication method involves first bonding two pairs of first interconnect elements located on a first group of adjacent substrates with a first compressive strength using a first pressure intensity, and then bonding two pairs of second interconnect elements located on a second group of adjacent substrates with a second compressive strength using a second pressure intensity. The second group of adjacent substrates shares a common substrate with the first group of adjacent substrates. Both the second pressure intensity and the second compressive strength are less than the first pressure intensity and the first compressive strength. Because the pressure intensity and compressive strength in the two steps are related by the fact that the second pressure intensity and the second compressive strength are both less than the first pressure intensity and the first compressive strength, applying the second pressure intensity will not cause deformation of the first interconnect elements. That is, the subsequent flip-chip bonding step will not cause softening or deformation of the interconnect elements bonded in the first flip-chip bonding step, thus helping to ensure that the spacing between the first group of adjacent substrates bonded in the first flip-chip bonding step remains consistent. The pressure intensity described above can be measured as the force per unit area acting on the interconnect element in a cross-section perpendicular to the pressure direction. The compressive strength is the pressure intensity limit that the interconnect element can withstand in its undeformed state.

[0037] The following description, in conjunction with the accompanying drawings, further illustrates this embodiment. The following description uses a three-layer flip chip as an example, in which the three layers are stacked and interconnected at the bottom, middle, and top positions. The substrate in the middle position is connected to the substrates above and below it through flip-chip interconnects. The substrate in the middle position and the substrate below it are defined as the first group of adjacent substrates, and the substrate in the middle position and the substrate above it are defined as the second group of adjacent substrates.

[0038] Figure 1 This is a schematic diagram of the operation of the flip-chip welding step in one embodiment of the present application.

[0039] Figure 2 This is a schematic diagram of the operation of the post-flip welding step in one embodiment of the present application.

[0040] Figure 3 This is a schematic diagram of a flip chip structure provided in one embodiment of this application.

[0041] Combination Figures 1 to 3 As shown, an embodiment of this application provides a method for fabricating a flip chip, including a pre-flip bonding step and a post-flip bonding step, wherein:

[0042] In the first flip-chip welding step, the first interconnecting elements 4 located on the first group of adjacent substrates and having a first compressive strength are joined in pairs with a first pressure strength. The first group of adjacent substrates includes a first substrate 1 and a second substrate 2. The first interconnecting elements 4 include a lower first interconnecting element 11 located on the first substrate 1 and an upper first interconnecting element 21 located on the second substrate 2. In this step, joining the lower first interconnecting element 11 and the upper first interconnecting element 21 in pairs can flip-chip weld the first substrate 1 and the second substrate 2 together.

[0043] In the subsequent flip-chip bonding step, the second interconnecting elements 5 located on the second set of adjacent substrates and having a second compressive strength are joined in pairs with a second pressure strength. The second set of adjacent substrates includes the second substrate 2 and the third substrate 3. The second interconnecting elements 5 include the lower second interconnecting element 22 located on the second substrate 2 and the upper second interconnecting element 31 located on the third substrate 3. In this step, joining the lower second interconnecting element 22 and the upper second interconnecting element 31 in pairs can flip-chip bond the second substrate 2 and the third substrate 3 to interconnect.

[0044] Furthermore, in the embodiments of this application, both the second pressure strength and the second compressive strength meet the following condition: they are both smaller than the first pressure strength and the first compressive strength.

[0045] For example, the lower first interconnect element 11 may be formed on the surface of the first substrate 1 or on the first circuit 10 on the surface of the first substrate 1. Similarly, the upper first interconnect element 21 may be formed on the surface of the second substrate 2 or on the second circuit 20 on the surface of the second substrate 2. The lower second interconnect element 22 may be formed on the surface of the second substrate 2 or on another second circuit 20 on the surface of the second substrate 2. The lower second interconnect element 31 may be formed on the surface of the third substrate 3 or on the third circuit 10 on the surface of the third substrate 3.

[0046] As described above, it can be understood that the second substrate 2 in this embodiment is shared by the second group of adjacent substrates and the first group of adjacent substrates. The method provided in this application includes a first flip-chip bonding step and a subsequent flip-chip bonding step. In the first flip-chip bonding step, a first pressure intensity is used to bond the first interconnect element 4 with a first compressive strength. In the subsequent flip-chip bonding step, a second pressure intensity is used to bond the second interconnect element 5 with a second strength. The second pressure intensity and the second compressive strength are both less than the first pressure intensity and the first compressive strength. Therefore, applying the second pressure intensity will not cause deformation of the first interconnect element 4. That is, the subsequent flip-chip bonding step will not cause softening and deformation of the first interconnect element 4 bonded in the first flip-chip bonding step, thereby helping to ensure that the spacing between the first group of adjacent substrates in the first flip-chip bonding step still maintains its original consistency. Therefore, when fabricating flip chips by performing multiple flip-chip bonding steps, this application solves the problem in the related art that the subsequent flip-chip bonding step easily leads to changes in the morphology of the interconnect elements involved in the first flip-chip bonding step.

[0047] To prevent the first substrate 1 and the second substrate 2 from tilting due to the pressure during the subsequent flip-chip bonding process, in some embodiments, the cross-sectional area of ​​the second interconnecting element 5 is smaller than that of the first interconnecting element 4. This allows for matching differentiated compressive strengths of the interconnecting elements in the two flip-chip bonding steps. It should be noted that this cross-section is perpendicular to the axial direction of the interconnecting element, such as the axial direction of the first interconnecting element 4 (lower first interconnecting element 11, upper first interconnecting element 21) and the second interconnecting element 5 (lower second interconnecting element 22, upper second interconnecting element 31). Figure 1 , Figure 2 and Figure 3 As shown, this cross-section is the transverse cross-section of the first interconnecting element 4 and the second interconnecting element 5. In some other embodiments, the number of second interconnecting elements 5 is less than the number of first interconnecting elements 4, so that the overall compressive strength of the interconnecting elements in the two flip-chip bonding steps is sufficiently differentiated to cope with different levels of pressure intensity, thereby helping to ensure the stability of the spacing between the first substrate 1 and the second substrate 2.

[0048] Thermo-pressure bonding is a commonly used process for flip chip soldering. Figure 2 As shown, the support stage applies relative directions (e.g.) Figure 2The force (in the direction indicated by the middle arrow) causes two interconnecting elements to be joined together. The working principle of thermocompression flip-chip bonding is as follows: Under certain pressure and temperature, ultrasonic energy is applied to the protruding elements on one substrate (i.e., the interconnecting elements described above). Within a certain time, the protruding elements generate a bonding force with the protruding elements on the other substrate, thereby achieving interconnection between the protruding elements on the two substrates. The interface bonding of protruding elements in thermocompression bonding is a frictional process. First, there is interface contact and pre-deformation, that is, under a given pressure, the protruding elements contact each other and are flattened and deformed to a certain extent. Then, there is ultrasonic action, which first removes the oxide and contaminant layer on the surface of the protruding elements. Then, the temperature rises sharply, the protruding elements deform, and the atoms of the protruding elements interpenetrate until they are within a certain range. Therefore, the key process parameters of thermocompression flip-chip bonding are pressure, temperature, ultrasonic power, and welding time.

[0049] The operation method of hot-press flip welding involves placing one substrate to be flip-assembled on a support platform, picking up another substrate with raised elements using a pick-up welding head, and aligning it with the raised element side down so that the two substrates are parallel and the welding positions are aligned. Parallelism between the substrates is crucial during flip welding. If they are not parallel, the deformation of the raised elements after welding will vary, resulting in different tensile strengths. Some welds may not meet the usage requirements. Therefore, parallelism is critical to weld quality. During ultrasonic hot pressing, the raised elements tend to melt under the influence of temperature and pressure. The deformation during this process is prone to tilting, making the impact of ultrasonic hot-press flip welding on the consistency of the inter-plate spacing particularly severe.

[0050] join Figure 2 and Figure 3 As shown, the upper first interconnect element 21 is located on the bottom surface of the intermediate substrate, and the lower second interconnect element 22 is located on the top surface of the intermediate substrate. That is, the upper first interconnect element 21 is on the surface opposite to the upper second interconnect element 22. It can be understood that the bottom and top here are relative to the embodiments provided in the accompanying drawings.

[0051] In embodiments of this application, to facilitate the pairwise bonding of the first interconnect elements 4 under a first strength during the flip-chip bonding step, while performing the step of applying a first pressure strength to bond the first interconnect elements 4 located on the first set of adjacent substrates and having a first compressive strength, the first interconnect elements 4 can also be heated at a first temperature. For example, both the lower first interconnect element 11 and the upper first interconnect element 21 can be heated at the first temperature. The lower first interconnect element 11 and the upper first interconnect element 21 have the same material structure, the difference being that one is formed on the first substrate 1 and the other is formed on the second substrate 2. Furthermore, to ensure that the lower first interconnect element 11 and the upper first interconnect element 21 can achieve effective wetting when receiving the heat provided by the first temperature, in some embodiments of this application, the first temperature is lower than the melting point of the first interconnect element 4 and within 10°C lower, for example, 10°C, 9°C, 8°C, 8.5°C, 7°C, etc., lower than the melting point. A temperature close to but not reaching the melting point allows the first interconnect element 4 to achieve a near-melting wetting. It should be noted that wetting refers to the process where the portion near the surface has melted and formed an adhesion layer on the surface of the base material by means of capillary force. The melted portion is close to the atoms of the base material and reaches the distance where atomic attraction takes effect.

[0052] For similar reasons, to facilitate the opposing bonding of the second interconnect elements in the subsequent flip-chip bonding step, the second interconnect elements 5 can be heated simultaneously with the step of applying a second pressure intensity to bond the second interconnect elements 5 located on the second set of adjacent substrates and having a second compressive strength in pairs. The inventors of this application have discovered that the heating temperature in the subsequent flip-chip bonding step easily changes the spacing between the first substrate 1 and the second substrate 2 that were previously flip-chip bonded, causing them to tilt relative to each other. To reduce the impact of heating on the aforementioned problem, in some embodiments of this application, the lower second interconnect element 22 located in the first layer is heated at a second temperature, and the upper second interconnect element 31 located in the second layer is heated at a third temperature. The lower second interconnect element 22 is located closer to the first interconnect element 4 than the upper second interconnect element 31. Furthermore, in this embodiment, the second temperature is lower than the third temperature, thereby creating a sufficiently large temperature difference in the direction from the second interconnect element 5 to the first interconnect element 4. This sufficiently large temperature difference further ensures that the first interconnect element 4, which has completed the opposing bonding, does not deform. The second temperature is 10°C or more lower than the melting point of the first interconnect element, for example, 10°C, 11°C, 12°C, 12.5°C, 14°C, etc., lower than the melting point. The third temperature is within 10°C lower than the melting point of the second interconnect element 5, for example, 10°C, 9°C, 8°C, 7.5°C, 6°C, etc., lower than the melting point.

[0053] See Figure 2 And compare Figure 1 As shown (relative to) Figure 1 , Figure 2 The end of the upper second interconnect element 31 is heated and wetted under the third temperature heating state (therefore it is distinguished in the figure). Since the heat provided by the third temperature can ensure that the upper second interconnect element 31 is heated and wetted, the wettability causes a part of the upper second interconnect element 31 near the end to melt and have adhesiveness and atomic penetration ability, thereby enabling the upper second interconnect element 31 to have the ability to be joined. Under the action of external force, the upper second interconnect element 31 comes into contact with the end of the lower second interconnect element 22 (which is heated under the second temperature heating state and has not reached the wetted state) and generates friction. Due to the joining ability described above, the two are joined together. In this process, the third temperature used is far away from the melting point of the first interconnect element 4, more than 10°C lower than the melting point, which ensures that the heat conducted will not cause the first interconnect element 4 to soften and deform. The first interconnect element 4 also still has a certain rigidity. Therefore, the preparation method of this embodiment avoids the change in the morphology and structure of the first interconnect element 4 during flip-chip bonding, which affects the performance parameters of the chip.

[0054] It should be noted that the first, second, and third temperatures can be provided by ultrasonic heating, plate heating, hot air heating, laser heating, etc. The specific implementation is not limited to the methods described above, as long as the required interconnect components can be heated to the specified temperatures. Furthermore, in the flip-chip soldering step, the first interconnect component 11 can be heated at one temperature while the first interconnect component 21 is heated at another temperature, with a sufficiently large difference between the two temperatures.

[0055] In some embodiments of this application, the first interconnect element 4 (lower first interconnect element 11, upper first interconnect element 21) and the second interconnect element 5 (lower second interconnect element 22, upper second interconnect element 31) are both superconductors. The superconductor can be formed from a superconducting material that exhibits superconductivity at temperatures equal to or below the critical temperature, for example, at approximately 10–100 millikrvin (mK) or approximately 4K, such as aluminum, niobium, tantalum, or titanium nitride, etc. In practice, the invention is not limited to these materials; any material exhibiting superconductivity at temperatures equal to or below the critical temperature can be used to form the superconductor. In some implementation examples, the first interconnect element 4 and the second interconnect element 5 can be made of indium (whose melting point is 157°C), and the third temperature is 150°C to 155°C (in specific implementations, one of the values ​​such as 150°C, 151°C, 152°C, 153°C, 154°C, and 155°C can be selected), and the second temperature is 20°C to 30°C (in specific implementations, one of the values ​​such as 20°C, 21°C, 23°C, 25°C, 28°C, and 30°C can be selected). In a preferred example, the third temperature is selected as 155°C and the second temperature is selected as 20°C. At this time, the second interconnect element made of indium can be bonded with high quality, and the first interconnect element is not deformed.

[0056] Another aspect of this application provides a flip chip prepared according to the method described above, the flip chip comprising: at least three stacked substrates, and adjacent substrates being interconnected by interconnecting elements; wherein the interconnecting elements comprise: a first interconnecting element 4 located on a first group of adjacent substrates, and a second interconnecting element 5 located on a second group of adjacent substrates, and the second group of adjacent substrates and the first group of adjacent substrates share a common substrate, and the compressive strength of the first interconnecting element 4 is greater than the compressive strength of the second interconnecting element 5.

[0057] See below again Figure 3 The flip chip comprises a first substrate 1, a second substrate 2, and a third substrate 3 stacked in a bottom, middle, and top configuration, respectively. The second substrate 2, located in the middle, is interconnected with the first substrate 1 via a first interconnect element 4, and the second substrate 2 and the third substrate 3 are interconnected via a second interconnect element 5.

[0058] The first interconnect element 4 includes a lower first interconnect element 11 located on the first substrate 1 and an upper first interconnect element 21 located on the second substrate 2, and the lower first interconnect element 11 and the upper first interconnect element 21 form an opposing engagement to flip-chip bond the first substrate 1 and the second substrate 2 together.

[0059] The second interconnecting element 5 includes a lower second interconnecting element 22 located on the second substrate 2 and an upper second interconnecting element 31 located on the third substrate 3, and the lower second interconnecting element 22 and the upper second interconnecting element 31 are opposed to each other to flip-chip weld interconnect the second substrate 2 and the third substrate 3.

[0060] Furthermore, the compressive strength of the first interconnect element 4 is greater than that of the second interconnect element 5.

[0061] The flip-chip described above has a multi-layered substrate with high spacing consistency, stable chip performance parameters, and is easy to fabricate. It has the same or similar beneficial effects as the aforementioned fabrication method embodiments, and therefore will not be elaborated upon further. For technical details not disclosed in the flip-chip embodiments of this application, those skilled in the art should refer to the description of the above fabrication method for understanding; for the sake of brevity, they will not be repeated here.

[0062] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for fabricating a flip chip, characterized in that, include: First, first interconnecting elements located on a first group of adjacent substrates and having a first compressive strength are joined together in pairs with a first pressure intensity, and simultaneously, the paired first interconnecting elements are heated with a first temperature within 10°C lower than the melting point of the first interconnecting elements; and, Then, the second interconnecting elements located on the second group of adjacent substrates and having a second compressive strength are joined together in pairs with a second pressure intensity. The second group of adjacent substrates and the first group of adjacent substrates share a substrate. The second pressure intensity and the second compressive strength are both less than the first pressure intensity and the first compressive strength. At the same time, the second interconnecting element located on the first layer is heated with a second temperature, and the second interconnecting element located on the second layer is heated with a third temperature. The distance between the first layer and the first interconnecting element is less than the distance between the second layer and the first interconnecting element. The second temperature is lower than the third temperature. The second temperature is more than 10°C lower than the melting point of the first interconnecting element, and the third temperature is less than 10°C lower than the melting point of the second interconnecting element. Both the first interconnect element and the second interconnect element are superconductors; The opposing joint is achieved through hot-press flip welding.

2. The method according to claim 1, characterized in that, The cross-sectional area of ​​the second interconnect element is smaller than that of the first interconnect element.

3. The method according to claim 1, characterized in that, The number of second interconnect elements is less than the number of first interconnect elements.

4. The method according to claim 1, characterized in that, The superconductor is indium, and the second temperature is 20℃~30℃, and the third temperature is 150℃~155℃.

5. A flip chip, characterized in that, include: At least three stacked substrates, with adjacent substrates interconnected by opposing interconnecting elements; wherein the interconnecting elements include: A first interconnecting element located on a first group of adjacent substrates, and a second interconnecting element located on a second group of adjacent substrates, wherein the second group of adjacent substrates and the first group of adjacent substrates share a common substrate, and the compressive strength of the first interconnecting element is greater than the compressive strength of the second interconnecting element; Both the first interconnect element and the second interconnect element are superconductors; The opposing joint is achieved by hot-press flip welding; While the first interconnecting elements on the first group of adjacent substrates are joined together, the first interconnecting elements are heated at a first temperature, which is within 10°C lower than the melting point of the first interconnecting elements. While the second interconnecting elements on the second set of adjacent substrates are joined, the second interconnecting elements located on the first layer are heated at a second temperature, and the second interconnecting elements located on the second layer are heated at a third temperature. The distance between the first layer and the first interconnecting element is less than the distance between the second layer and the first interconnecting element, and the second temperature is lower than the third temperature. The second temperature is more than 10°C lower than the melting point of the first interconnecting element, and the third temperature is less than 10°C lower than the melting point of the second interconnecting element.

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