Semiconductor device including a selector layer

Abstract

The present disclosure relates to semiconductor devices including a selector layer. A semiconductor device can include a first conductive layer, a second conductive layer spaced apart from the first conductive layer, a tunnel insulating layer disposed between the first conductive layer and the second conductive layer and positioned adjacent to the first conductive layer, a charge blocking layer disposed between the first conductive layer and the second conductive layer and positioned adjacent to the second conductive layer, and a selector layer disposed between the tunnel insulating layer and the charge blocking layer, wherein the semiconductor device functions as a self-selecting memory.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0033885, filed with the Korean Intellectual Property Office on March 18, 2022, the entirety of which is incorporated herein by reference. Technical Field

[0003] This patent document relates to storage circuits or storage devices and their applications in electronic devices or electronic systems. Background Technology

[0004] Recently, with the trend towards miniaturization, low power consumption, high performance, and multifunctionality in electrical appliances, semiconductor devices capable of storing information in various electrical appliances (such as computers and portable communication devices) have become in demand in this field, and such semiconductor devices have been studied. Such semiconductor devices include those that can store data by utilizing the characteristic that their resistance states can switch according to the applied voltage or current to produce different resistance states. Examples of these semiconductor devices include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses (E-fuse), etc. Summary of the Invention

[0005] In an embodiment, the semiconductor device may include: a first conductive layer; a second conductive layer spaced apart from the first conductive layer; a tunnel insulating layer disposed between the first and second conductive layers and disposed adjacent to the first conductive layer; a charge blocking layer disposed between the first and second conductive layers and disposed adjacent to the second conductive layer; and a selector layer disposed between the tunnel insulating layer and the charge blocking layer, wherein the semiconductor device serves as a self-selection memory.

[0006] In another embodiment, the semiconductor device may include: a tunnel insulating layer; a charge blocking layer; and a selector layer disposed between the tunnel insulating layer and the charge blocking layer, wherein the semiconductor device switches between different resistance states depending on whether a charge is trapped in a trap bit of the selector layer. Attached Figure Description

[0007] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 To show in more detail Figure 1 A cross-sectional view of the storage cell.

[0009] Figures 3A to 3D It is shown Figure 2 A view of the operation of the storage unit.

[0010] Figure 4 It is shown Figure 2 The current-voltage curve of the memory cell operation.

[0011] Figure 5A and Figure 5B This is a view illustrating a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0012] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0013] The accompanying drawings are not necessarily drawn to scale. In some instances, the scale of at least some structures in the drawings may have been exaggerated to clearly show the specific features of the described embodiments. When a particular example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positional relationship of such layers or the order of arrangement of the layers reflects the specific implementation used for the described or illustrated example, and different relative positional relationships or orders of arrangement of layers are possible. Furthermore, the described or illustrated example of a multilayer structure may not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, and the description or illustration may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0014] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0015] refer to Figure 1 The semiconductor device may include: a plurality of first conductive lines 110 disposed on a substrate 100 and extending parallel to each other in a first direction; a plurality of second conductive lines 150 disposed on the plurality of first conductive lines 110 and spaced perpendicularly to the plurality of first conductive lines 110 and extending parallel to each other in a second direction intersecting the first direction; and a memory cell MC disposed between the first conductive lines 110 and the second conductive lines 150 to overlap with the intersection regions of the first conductive lines 110 and the second conductive lines 150, respectively. The first direction and the second direction may be horizontal directions parallel to the surface of the substrate 100.

[0016] Substrate 100 may include a semiconductor material such as silicon. Furthermore, substrate 100 may include a desired underlying structure (not shown). For example, substrate 100 may include drive circuitry electrically connected to the first conductive line 110 and the second conductive line 150 to drive them.

[0017] A memory cell (MC) can be cylindrical and can be spaced apart from adjacent memory cells (MCs). Figure 1 In the diagram, the memory cell MC is shown as having a quadrilateral prism shape, having two sidewalls aligned with the two sidewalls of the second conductive line 150 in a first direction and two sidewalls aligned with the two sidewalls of the first conductive line 110 in a second direction. However, this disclosure is not limited thereto, and in other embodiments, the memory cell MC may have a cylindrical shape, etc.

[0018] The memory cell MC may include a stacked structure of a tunnel insulating layer 120, a selector layer 130, and a charge blocking layer 140, and thus can operate as a self-selecting memory that serves as both a storage element and a selector. More specifically, the self-selecting memory may have variable resistance characteristics to store different data by switching between different resistance states according to the voltage applied to the two ends of the memory cell MC (i.e., the first conductive line 110 and the second conductive line 150). Simultaneously, the self-selecting memory may have threshold switching characteristics, i.e., the characteristic of blocking or substantially limiting current when the magnitude of the applied voltage is less than a predetermined threshold and allowing a sudden increase in current when the magnitude of the applied voltage exceeds the threshold. This threshold may be referred to as a threshold voltage, and the self-selecting memory may be implemented in an on or off state based on the threshold voltage.

[0019] The threshold voltage of a self-selecting memory can depend on its resistance state. That is, a self-selecting memory can have different threshold voltages depending on different resistance states. For example, when the self-selecting memory is in a low-resistance state, it can have a first threshold voltage, and when it is in a high-resistance state, it can have a second threshold voltage different from the first threshold voltage. Therefore, it is possible for a self-selecting memory to simultaneously perform the functions of a storage element and a selector.

[0020] Therefore, data can be stored in each of the multiple storage cells MC used as self-selecting memory, and current leakage that may occur between storage cells MC sharing the first conductive line 110 or the second conductive line 150 can be prevented or reduced.

[0021] According to the embodiments disclosed herein, since the memory cell MC simultaneously functions as a memory element and as a selector, there is no need to manufacture another memory element or another selector, thereby simplifying the manufacturing process. Furthermore, since it is easy to implement a memory device with a cross-point structure including the memory cell MC, the integration density of the memory device can be increased or guaranteed.

[0022] The following section will describe in more detail the detailed structure of the memory cell MC, which includes the tunnel insulating layer 120, the selector layer 130, and the charge blocking layer 140, and how the memory cell MC is used as a self-selecting memory.

[0023] Figure 2 To show in more detail Figure 1 A cross-sectional view of the storage cell.

[0024] refer to Figure 2 The storage cell MC can be placed between the first conductive line 110 and the second conductive line 150, and can include a tunnel insulating layer 120, a selector layer 130 and a charge blocking layer 140.

[0025] Each of the first conductive line 110 and the second conductive line 150 may include a variety of conductive materials, such as metals (e.g., platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti), etc.), metal nitrides (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or combinations thereof.

[0026] Compared to the charge blocking layer 140, the tunnel insulating layer 120 may be disposed relatively adjacent to the first conductive line 110, and compared to the tunnel insulating layer 120, the charge blocking layer 140 may be disposed relatively adjacent to the second conductive line 150. A selector layer 130 may be disposed between the tunnel insulating layer 120 and the charge blocking layer 140. Although not shown, the memory cell MC may also include electrode materials disposed between the first conductive line 110 and the tunnel insulating layer 120 and / or between the second conductive line 150 and the charge blocking layer 140. The electrode materials may include a variety of conductive materials, such as metals (e.g., platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), or titanium (Ti)), metal nitrides (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), or combinations thereof. In another embodiment, the electrode material may include carbon.

[0027] The tunnel insulation layer 120 can initiate charge tunneling based on the voltage applied across the storage cell MC. The tunnel insulation layer 120 may include various insulating materials, such as silicon oxide, silicon nitride, or combinations thereof.

[0028] Selector layer 130 can be used to prevent current leakage that may occur between memory cells MC sharing the first conductive line 110 or the second conductive line 150. For this purpose, selector layer 130 may have threshold switching characteristics, i.e., the characteristic of blocking or substantially limiting current when the magnitude of the voltage applied across selector layer 130 is less than a predetermined threshold, and allowing a sudden increase in current when the magnitude of the applied voltage exceeds the threshold. This threshold may be referred to as the threshold voltage, and selector layer 130 may be implemented in an on or off state based on the threshold voltage. Selector layer 130 may include diodes, bidirectional threshold switching (OTS) materials (such as chalcogenide-based materials), mixed ion-electron conduction (MIEC) materials (such as metal chalcogenide-based materials), metal-insulator transition (MIT) materials (such as NbO2 or VO2), and tunneling insulating layers with relatively wide band gaps (such as SiO2 or Al2O3). In particular, the selector layer 130 may include a material that includes multiple trap bits capable of capturing charges transmitted through the tunnel insulation layer 120, such as, for example, an OTS material.

[0029] The charge blocking layer 140 can substantially block the movement of charge trapped in the selector layer 130 toward the second conductive line 150. That is, the charge escaping through the charge blocking layer 140 can be zero or less than the amount of charge tunneling through the tunnel insulating layer 120. The charge blocking layer 140 can include a variety of insulating materials, such as silicon oxide, silicon nitride, or combinations thereof. Unlike the tunnel insulating layer 120, the charge blocking layer 140 should suppress the movement of as much charge as possible. Therefore, the tunnel insulating layer 120 and the charge blocking layer 140 can be implemented asymmetrically to have different properties. For example, the thickness T2 of the charge blocking layer 140 can be greater than the thickness T1 of the tunnel insulating layer 120. In this case, the tunnel insulating layer 120 and the charge blocking layer 140 can include the same material, such as silicon dioxide. In another embodiment, the charge blocking layer 140 can include a material having a higher dielectric constant than that of the tunnel insulating layer 120. For example, tunnel insulating layer 120 may include silicon dioxide, and charge blocking layer 140 may include a high-k material having a higher dielectric constant than silicon dioxide, such as, for example, hafnium dioxide. In another example, tunnel insulating layer 120 and charge blocking layer 140 may include a high-k material having a higher dielectric constant than silicon dioxide, and the dielectric constant of charge blocking layer 140 may be higher than the dielectric constant of tunnel insulating layer 120. In another embodiment, charge blocking layer 140 may have a higher dielectric constant than tunnel insulating layer 120, and the thickness T2 of charge blocking layer 140 may be greater than the thickness T1 of tunnel insulating layer 120.

[0030] If only the selector layer 130 is applied between the first conductive line 110 and the second conductive line 150, that is, if the tunnel insulating layer 120 and the charge blocking layer 140 are omitted, the memory cell MC cannot perform the function of storing data, but can only perform the function of a selector. For example, when the selector layer 130 includes an OTS material, if the voltage applied through the first conductive line 110 and the second conductive line 150 reaches a threshold voltage, electrons can be trapped in the trap positions of the selector layer 130, and thus a rapid current flow can occur through the selector layer 130. That is, the selector layer 130 can be turned on. On the other hand, if the voltage applied to the first conductive line 110 and the second conductive line 150 is removed, electrons can be emitted from the trap positions of the selector layer 130, so that the selector layer 130 can be turned off. In this case, the memory cell MC may require additional storage elements.

[0031] In the disclosed embodiments, the memory cell MC can also be used as a memory element by adding a tunnel insulating layer 120 and a charge blocking layer 140 to both sides of the selector layer 130. Reference will be made below to... Figures 3A to 3D The function of the memory unit (MC) is described in more detail.

[0032] Figures 3A to 3D It is shown Figure 2 A view of the operation of the storage unit.

[0033] refer to Figure 3A The memory cell MC can have a state in which the charge is not trapped in the trap bits in the selector layer 130, i.e., a high-resistance state. This state can correspond to the initial state of the memory cell MC after it has been fabricated, or as will be described later. Figure 3D The state after the erase operation.

[0034] When no voltage is applied to the first conductive line 110 and the second conductive line 150, no charge flows through the tunnel insulating layer 120, and as a result, a high-resistance state can be maintained. The memory cell MC in the high-resistance state can have a second threshold voltage.

[0035] refer to Figure 3B A write operation can be performed by applying a write voltage to the first conductive line 110 and the second conductive line 150. A write operation can refer to the operation of changing the high-resistance state of the memory cell MC to a low-resistance state. For this purpose, a relatively positive voltage can be applied to the second conductive line 150 relative to the first conductive line 110. For example, a ground voltage can be applied to the first conductive line 110, and a write voltage indicated by +V can be applied to the second conductive line 150.

[0036] During a write operation, charge (such as, for example, electrons) can tunnel from the first conductive line 110 through the tunnel insulating layer 120 and can be introduced into the selector layer 130. The charge introduced into the selector layer 130 can be trapped in the trap bits of the selector layer 130. When the charge is trapped in all the trap bits of the selector layer 130, a rapid current flow may occur through the memory cell MC. That is, the memory cell MC can become a low-resistance state.

[0037] refer to Figure 3C Even when the write voltage applied to the first conductive line 110 and the second conductive line 150 is removed, the tunnel insulating layer 120 and the charge blocking layer 140 also limit the charge of the selector layer 130, thus allowing the memory cell MC to maintain a low-resistance state. The memory cell MC in the low-resistance state can have a first threshold voltage. The first threshold voltage can be less than a second threshold voltage.

[0038] refer to Figure 3D An erase operation can be performed by applying an erase voltage to the first conductive line 110 and the second conductive line 150. An erase operation can refer to the operation of changing the low-resistance state of the memory cell MC to a high-resistance state. For this purpose, a voltage relatively negative to the first conductive line 110 can be applied to the second conductive line 150. For example, a ground voltage can be applied to the first conductive line 110, and an erase voltage indicated by -V can be applied to the second conductive line 150. The erase voltage can be substantially the same in amplitude as the write voltage, but with the opposite polarity.

[0039] During the erase operation, the charge in the selector layer 130 can tunnel through the tunnel insulating layer 120 and escape to the first conductive line 110. Therefore, the trap bits in the selector layer 130 can be empty, and the current flow through the selector layer 130 can be blocked. That is, the memory cell MC can become a high-resistance state and return to normal. Figure 3A The state shown.

[0040] In summary, a write operation applying a negative or positive write voltage results in a memory cell MC with a low resistance state and a relatively small first threshold voltage, while during an erase operation applying an erase voltage with a polarity different from the write voltage, the memory cell MC can return to a high resistance state and have a relatively large second threshold voltage.

[0041] Figure 4 It is shown Figure 2 The current-voltage curve of the memory cell operation.

[0042] refer to Figure 4The memory cell in the high-resistance state HRS can have a second threshold voltage Vth2, and the memory cell in the low-resistance state LRS can have a first threshold voltage Vth1, the first threshold voltage Vth1 having an amplitude smaller than the second threshold voltage Vth2.

[0043] Write and erase operations can be performed on memory cells using voltages with the same amplitude but opposite polarity. Therefore, during a write operation, a positive write voltage Vwrite with an amplitude greater than or equal to the second threshold voltage Vth2 can be applied, while during an erase operation, a negative erase voltage Verase with an amplitude greater than or equal to the second threshold voltage Vth2 can be applied. Here, the write voltage Vwrite can correspond to... Figure 3B The voltage indicated by +V is used in the equation, while the erase voltage Verase can correspond to... Figure 3D The voltage indicated by -V.

[0044] During a read operation, a read voltage Vread with an amplitude between a first threshold voltage Vth1 and a second threshold voltage Vth2 can be applied. The polarity of the read voltage Vread can be the same as the polarity of the write voltage. That is, a positive read voltage Vread can be applied.

[0045] Additionally, in order to turn on the memory cells under negative voltage, a third threshold voltage Vth3 with an amplitude greater than the second threshold voltage Vth2 may be required. This is because a charge supply is needed to the selector layer 130 through the charge blocking layer 140 to turn on the memory cells under negative voltage.

[0046] Figure 5A and Figure 5B This is a view illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 5A It is a cross-sectional view, and Figure 5B yes Figure 5A A plan view taken along line H1-H1'. The main differences from the embodiments described above will be described.

[0047] refer to Figure 5A and Figure 5B A stacked structure ST, in which multiple second conductive layers 250 and multiple insulating layers 255 are alternately stacked, can be formed on the substrate 200. That is, the multiple second conductive layers 250 can extend in a horizontal direction parallel to the surface of the substrate 200.

[0048] Multiple holes H that penetrate the stacked structure ST and expose the substrate 200 can be formed in the stacked structure ST.

[0049] The charge blocking layer 240, the selector layer 230, the tunnel insulating layer 220, and the first conductive layer 210 can be sequentially formed on the sidewalls of each of the plurality of vias H. Therefore, the first conductive layer 210 can have a columnar shape extending in a direction perpendicular to the surface of the substrate 200, the tunnel insulating layer 220 can have a shape surrounding the sidewalls of the first conductive layer 210, the selector layer 230 can have a shape surrounding the sidewalls of the tunnel insulating layer 220, and the charge blocking layer 240 can have a shape surrounding the sidewalls of the selector layer 230.

[0050] Each of the plurality of second conductive layers 250 may substantially correspond to the second conductive line of the above embodiment (see reference). Figure 1 (150). Each of the plurality of first conductive layers 210 may substantially correspond to the first conductive line of the above embodiment (see reference 150). Figure 1 (110). The charge blocking layer 240, the selector layer 230, and the tunnel insulating layer 220 may substantially correspond to the charge blocking layer of the above embodiment (see reference 110). Figure 1 140), Selector layer (reference) Figure 1 130) and tunnel insulation (reference) Figure 1 (of 120).

[0051] The charge blocking layer 240, selector layer 230, and tunnel insulating layer 220 located between any of the first conductive layer 210 and any of the second conductive layer 250 can form a memory cell MC.

[0052] According to the embodiments described above in this disclosure, a semiconductor device including a memory cell used as a self-selecting memory can be provided, which has excellent operating characteristics and easy manufacturing process.

[0053] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the spirit and scope of this teaching as defined in the claims.

Claims

1. A semiconductor device, comprising: First conductive layer; A second conductive layer, which is spaced apart from the first conductive layer; A tunnel insulation layer is disposed between the first conductive layer and the second conductive layer and is positioned adjacent to the first conductive layer; A charge blocking layer is disposed between the first conductive layer and the second conductive layer and is configured to be adjacent to the second conductive layer; as well as A selector layer is disposed between the tunnel insulating layer and the charge blocking layer. The semiconductor device is used as a self-selection memory; The thickness of the charge blocking layer is greater than the thickness of the tunnel insulating layer, and The dielectric constant of the charge blocking layer is higher than that of the tunnel insulation layer.

2. The semiconductor device according to claim 1, wherein, The selector layer includes trap bits capable of capturing charge, and The semiconductor device switches between a low-resistance state and a high-resistance state based on the charge trapped at the trap site.

3. The semiconductor device according to claim 2, wherein, The first threshold voltage of the low resistance state is different from the second threshold voltage of the high resistance state.

4. The semiconductor device according to claim 3, wherein, The first threshold voltage is less than the second threshold voltage.

5. The semiconductor device according to claim 3, wherein, The semiconductor device changes from the high resistance state to the low resistance state under a write voltage of the first polarity, and changes from the low resistance state to the high resistance state under an erase voltage of the second polarity, which is different from the first polarity.

6. The semiconductor device according to claim 5, wherein, The magnitude of the write voltage is the same as the magnitude of the erase voltage.

7. The semiconductor device according to claim 5, wherein, The magnitude of the write voltage and the magnitude of the erase voltage are equal to or greater than the larger of the first threshold voltage and the second threshold voltage.

8. The semiconductor device according to claim 5, wherein, In a readout operation for reading the resistance state of the semiconductor device, a readout voltage having an amplitude between the first threshold voltage and the second threshold voltage is applied.

9. The semiconductor device according to claim 8, wherein, The polarity of the read voltage is the same as the first polarity.

10. The semiconductor device according to claim 1, wherein, The first conductive layer is formed on the substrate and extends in a first direction parallel to the surface of the substrate. The second conductive layer extends in a second direction, which is parallel to the surface of the substrate and intersects the first direction. The tunnel insulating layer, the charge blocking layer, and the selector layer overlap with the intersection region of the first conductive layer and the second conductive layer between the first conductive layer and the second conductive layer.

11. The semiconductor device according to claim 1, wherein, The first conductive layer comprises a plurality of first conductive layers stacked alternately on the substrate with insulating layers. The second conductive layer has a columnar shape that penetrates the plurality of first conductive layers, and The tunnel insulating layer, the charge blocking layer, and the selector layer are positioned between the first conductive layer and the second conductive layer.

12. A semiconductor device, comprising: Tunnel insulation layer; Charge blocking layer; as well as A selector layer is disposed between the tunnel insulating layer and the charge blocking layer. The semiconductor device switches between different resistance states depending on whether a charge is trapped in a trap bit of the selector layer; The thickness of the charge blocking layer is greater than the thickness of the tunnel insulating layer, and The dielectric constant of the charge blocking layer is higher than that of the tunnel insulation layer.

13. The semiconductor device according to claim 12, wherein, The amount of charge that tunnels through the tunnel insulation layer is greater than the amount of charge that escapes through the charge barrier layer.

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