Analog circuit design

Abstract

This application discloses an analog circuit design apparatus. The apparatus is configured to receive information representing technical requirements of an analog circuit, wherein the technical requirements include (i) at least one circuit performance requirement, and (ii) at least one manufacturing requirement of the analog circuit to satisfy a specific set of manufacturing process-related rules. The apparatus is configured to identify a plurality of potential analog circuit design architectures for satisfying the circuit performance requirement, wherein the plurality of potential analog circuit design architectures will satisfy at least one manufacturing requirement; and to select an initial analog circuit design architecture from the plurality of potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules.

Description

Technical Field

[0001] This disclosure relates to methods and systems for analog circuit design, and more particularly, to methods and systems for automating the design process of analog circuits. Background Technology

[0002] Analog components cause most chip production test failures and up to 95% of field failures. While circuit design for digital circuits has been automated to some extent recently, automation of analog circuit design has proven problematic, especially due to parasitic effects, for example. Traditional methods of analog circuit design may involve manual "best guess" estimations or specification of guard intervals by engineering teams relying on prior knowledge and experience, often resulting in over-design, inefficiency, or susceptibility to failure. Therefore, there is a desire to create a more efficient and reliable process for designing analog circuits. Summary of the Invention

[0003] Various aspects of the invention can be provided in combination with each other, and features of one aspect can be applied to other aspects.

[0004] In a first aspect, an analog circuit design apparatus is provided. The apparatus includes at least one design unit, which includes a processor and a communication interface, the processor being configured to: (a) The control communication interface receives information representing the technical requirements of the analog circuit, wherein the technical requirements include: (i) at least one circuit performance requirement, and (ii) at least one manufacturing requirement of the analog circuit to meet a specific set of manufacturing process-related rules; (b) Based on the received information, identify multiple potential analog circuit design architectures for meeting circuit performance requirements, wherein the multiple potential analog circuit design architectures will meet at least one manufacturing requirement; (c) Select an initial analog circuit design architecture from multiple potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules; (d) Generate a current design that satisfies the current analog circuit design architecture for analog circuits; (e) For the current design of the analog circuit, determine whether the current design will meet at least one circuit performance requirement; When it is determined that the current design for analog circuits does not meet the circuit performance requirements: (f) Selecting an alternative analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the alternative analog circuit design architecture depends on the set of manufacturing process-related rules, and (g) Repeat steps (d) and (e); and (h) Given that the current design of the analog circuit architecture meets the circuit performance requirements, output the design for the analog circuit.

[0005] The processor can also be configured as: (i) For each current design of analog circuits, determine the extent to which the current design conforms to at least one set of circuit performance requirements and manufacturing process-related rules; (j) Selecting an alternative analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the alternative analog circuit design architecture depends on the set of manufacturing process-related rules, and (k) Repeat steps (d) and (e) to generate multiple generated analog circuit designs; and (I) Select and output the design for the analog circuit that best meets at least one set of circuit performance requirements and manufacturing process-related rules from multiple generated analog circuit designs.

[0006] The selection of the analog circuit design architecture in steps (c) and / or (f) can be based on prioritizing multiple potential architectures, creating a priority list of potential analog circuit design architectures that have been identified as satisfying a set of manufacturing process-related rules. Machine learning models can be used to determine the priority list of potential analog circuit design architectures.

[0007] In some examples, the apparatus includes a main design unit and an auxiliary design unit, wherein the main design unit is configured as follows: (m) Based on the received information, multiple potential analog circuit design architectures are used to meet circuit performance requirements, wherein the multiple potential analog circuit design architectures will also meet manufacturing requirements; and (n) Select an initial analog circuit design architecture from multiple potential analog circuit design architectures as the current analog circuit design architecture, wherein each circuit design architecture includes multiple corresponding circuit parts; (o) For each of the multiple circuit sections, determine the corresponding circuit performance requirements for that circuit section, wherein the corresponding circuit performance requirements for each circuit section are determined based on a specific set of manufacturing process-related rules; and (p) Provide the corresponding circuit performance requirements for each circuit section to at least one of the multiple auxiliary design units; Furthermore, each of the multiple auxiliary design units in the analog circuit design device is configured as follows: (q) Based on the circuit performance requirements provided by the main design unit for the corresponding circuit section, design the corresponding circuit section among multiple circuit sections; and (r) Initial design of the output circuit section; The main design unit is also configured as follows: (s) Receive the corresponding design for each circuit section from each of the multiple auxiliary design units; and (t) Based on the corresponding design of each circuit section, generate the current analog circuit design for the analog circuit that satisfies the current analog circuit design architecture.

[0008] The main design unit can also be configured as: (u) Simulate the analog circuit based on the current analog circuit design to produce at least one simulation output; (v) Verify that the analog circuit meets the circuit performance requirements, and When the analog circuit meets the circuit performance requirements, the output generated is the design; and When the analog circuit does not meet the circuit performance requirements: Choosing an alternative analog circuit design architecture as the current analog circuit design architecture, wherein the choice of the alternative analog circuit design depends on the set of manufacturing process-related rules; and Repeat steps (d) to (e) and steps (m) to (v).

[0009] The main design unit can also be configured as: (w) Simulate the analog circuit based on the current analog circuit design to produce at least one simulation output; (x) Verify whether the analog circuit meets the circuit performance requirements of the analog circuit, and When the analog circuit meets the circuit performance requirements, the output generated is the design; and When the analog circuit does not meet the circuit performance requirements: For at least one affected circuit section among multiple circuit sections, the corrected circuit performance requirements for the affected circuit section are determined based on simulation output and circuit performance requirements. Provide revised circuit performance requirements for each affected circuit section to at least one corresponding auxiliary design unit; Receive the corresponding updated design for each affected circuit section from at least one corresponding auxiliary design unit; The current design of the analog circuit is updated using the corresponding updated design for each affected circuit section; and Repeat steps (w) to (x) for the updated set of designs.

[0010] Each of the multiple auxiliary design units can be configured to adapt the design of the corresponding part based on the difference between simulation behavior and circuit performance requirements.

[0011] In some examples, after at least one of the auxiliary design units has completed at least the initial design of a given circuit portion, at least one of the auxiliary design units is configured to adapt the current analog circuit design based on the context of the circuit portion corresponding to the at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated from the completed design of the given circuit portion completed by at least one of the auxiliary design units.

[0012] In some examples, after at least one of the auxiliary design units has completed at least the initial design of a given circuit portion, at least one of the auxiliary design units is configured to adapt the output initial design of the at least one auxiliary design unit based on the context of the circuit portion corresponding to the at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated by the completed design of the given circuit portion completed by at least one of the auxiliary design units.

[0013] Each auxiliary design unit is configured to repeat the steps of adapting the design of another circuit section when a modification to the design of one of the multiple circuit sections results in a change in the context of another circuit section.

[0014] Additionally or alternatively, each of the auxiliary design units is configured to repeat the steps of adapting the design of another circuit section only if the change in context is greater than a selected context change threshold level.

[0015] In some examples, the device is configured to obtain context by simulating the performance of a given section of the circuit.

[0016] On the other hand, a method for designing analog circuits is provided. The method includes: at a design unit comprising a processor and a communication interface, (a) The control communication interface receives information representing the technical requirements of the analog circuit, wherein the technical requirements include: (i) at least one circuit performance requirement, and (ii) at least one manufacturing requirement of the analog circuit to meet a specific set of manufacturing process-related rules; (b) Based on the received information, identify multiple potential analog circuit design architectures for meeting circuit performance requirements, wherein the multiple potential analog circuit design architectures will meet at least one manufacturing requirement; (c) Select an initial analog circuit design architecture from multiple potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules; (d) Generate a current design that satisfies the current analog circuit design architecture for analog circuits; (e) For the current design of the analog circuit, determine whether the current design will meet at least one circuit performance requirement; When it is determined that the current design for analog circuits does not meet the circuit performance requirements: (f) Selecting an alternative analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the alternative analog circuit design architecture depends on the set of manufacturing process-related rules, and (g) Repeat steps (d) and (e); and (h) Given that the current design of the analog circuit architecture meets the circuit performance requirements, output the design for the analog circuit.

[0017] The method may also include: (i) For the current design of the analog circuit, determine the extent to which the current design conforms to at least one set of circuit performance requirements and manufacturing process-related rules; (j) Selecting an alternative analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the alternative analog circuit design architecture depends on the set of manufacturing process-related rules, and (k) Repeat steps (d) and (e) to generate multiple generated analog circuit designs; and (I) Select and output the design for the analog circuit that best meets at least one set of circuit performance requirements and manufacturing process-related rules from multiple generated analog circuit designs.

[0018] At step (c) and / or step (f), the selection of the analog circuit design architecture is based on the prioritization of multiple potential architectures, and the prioritization creates a priority list of potential analog circuit design architectures that have been identified as satisfying a set of manufacturing process-related rules.

[0019] The method may also include: at the main design unit, (m) Based on the received information, identify multiple potential analog circuit design architectures to meet circuit performance requirements, wherein the multiple potential analog circuit design architectures will also meet manufacturing requirements; and (n) Select an initial analog circuit design architecture from multiple potential analog circuit design architectures as the current analog circuit design architecture, wherein each circuit design architecture includes multiple corresponding circuit parts; (o) For each of the multiple circuit sections, determine the corresponding circuit performance requirements for that circuit section, wherein the corresponding circuit performance requirements for each circuit section are determined based on a specific set of manufacturing process-related rules; and (p) Provide the corresponding circuit performance requirements for each circuit section to at least one of the multiple auxiliary design units; At each auxiliary design unit within the auxiliary design unit: (q) Based on the circuit performance requirements provided by the main design unit for the corresponding circuit section, design the corresponding circuit section among multiple circuit sections; and (r) Initial design of the output circuit section; The method also includes: at the main design unit, (s) Receive the corresponding design for each circuit section from each of the multiple auxiliary design units; and (t) Based on the corresponding design of each circuit section, generate the current analog circuit design for the analog circuit that satisfies the current analog circuit design architecture.

[0020] The method may also include: at the main design unit, (u) Simulate the analog circuit based on the current analog circuit design to produce at least one simulation output; (v) Verify that the analog circuit meets the circuit performance requirements, and When the analog circuit meets the circuit performance requirements, the output generated is the design; and When the analog circuit does not meet the circuit performance requirements: The selection of an alternative analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the alternative analog circuit design [based on the priority of multiple potential architectures] depends on a set of manufacturing process-related rules; and Repeat steps (d) to (e) and steps (m) to (v).

[0021] The method may also include: at the main design unit, (w) Simulate the analog circuit based on the current analog circuit design to produce at least one simulation output; (x) Verify whether the analog circuit meets the circuit performance requirements of analog circuits, and When the analog circuit meets the circuit performance requirements, the output generated is the design; and When the analog circuit does not meet the circuit performance requirements: For at least one affected circuit section among multiple circuit sections, the corrected circuit performance requirements for the affected circuit section are determined based on simulation output and circuit performance requirements. Provide revised circuit performance requirements for each affected circuit section to at least one corresponding auxiliary design unit; Receive the corresponding updated design for each affected circuit section from at least one corresponding auxiliary design unit; The current design of the analog circuit is updated using the corresponding updated design for each affected circuit section; and Repeat steps (w) to (x) for the updated set of designs.

[0022] The method may also include: at each of the multiple auxiliary design units, adapting the design of the corresponding part based on the difference between simulation behavior and circuit performance requirements, thereby adapting the design of the corresponding part based on simulation behavior.

[0023] The method may further include, after at least one of the auxiliary design units has completed at least an initial design of a given circuit portion, adapting the output initial design of at least one auxiliary design unit based on the context of the circuit portion corresponding to at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the auxiliary design units.

[0024] The method may further include, after at least one of the auxiliary design units has completed at least an initial design of a given circuit portion, adapting the output initial design of at least one auxiliary design unit based on the context of the circuit portion corresponding to at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the auxiliary design units.

[0025] The method may also include: at each of the auxiliary design units, in cases where a modification to the design of one of the multiple circuit sections results in a change in the context of another circuit section, repeating the steps of adapting the design of the other circuit section.

[0026] The method may also include, at each auxiliary design unit, repeating the steps of adapting the design of another circuit section only if the change in context exceeds a selected context change threshold level. In some examples, the context is obtained by simulating the performance of a given circuit section.

[0027] It should be understood that the method may also include: manufacturing analog circuits based on the output design.

[0028] In another aspect, a non-transitory computer-readable storage medium is provided, the computer-readable storage medium including a program for a computer configured to cause a processor to perform any of the methods described above. Attached Figure Description

[0029] Embodiments of this disclosure will now be described by way of example only, with reference to the accompanying drawings, in which: Figure 1A This is a functional schematic diagram of an exemplary analog circuit; Figure 1BIt is divided into concept blocks Figure 1A Functional diagram; Figure 2 It is a functional diagram of a computer-implemented hierarchical model used for designing analog circuits; Figure 3 It is used for design and Figure 2 or Figure 4 A functional schematic flowchart of a method for using analog circuits with a model; Figure 4 This is a functional schematic view of another exemplary implementation of a computer-generated model for designing analog circuits; Figure 5 It is used for example, using Figure 2 or Figure 4 A functional schematic flowchart of a method for designing analog circuits using an exemplary computer-implemented model; Figure 6A It is a hierarchical model implemented by a computer (e.g., reference). Figures 1A to 2 and Figures 4 to 5 Any part of the analog circuit design (from any of the described models); Figure 6B It includes Figure 6A Examples of analog circuits designed for the circuit section; and Figure 7 This is a schematic diagram of an exemplary method for training a machine learning model to rank architectures. Detailed Implementation

[0030] Figure 1A A simplified functional schematic diagram of an exemplary analog electronic circuit is shown, in which the analog electronic circuit is an analog-to-digital converter (ADC) 1000. Analog circuitry may include several parts or components, such as: a comparator 1001, a digital-to-analog converter (DAC) 1002, a level shifter 1003, and an operational amplifier (OP-AMP) 1004. While each part or component may initially be considered in isolation, the context or environment in which that part or component operates can influence how that component / block functions when applied in situ as a whole in a circuit. These influences include, for example, parasitic effects experienced by the circuit section and the circuit as a whole. The design of analog circuits has previously proven difficult to automate due to the complex feedback loops and mathematical relationships involved between the different parts / components.

[0031] Embodiments of the claims relate to a method and system for automating the design of analog circuits, thereby enabling the design of more efficient circuits. Specifically, embodiments of the claims relate to a method and system for automating the design of analog circuits, taking into account circuit performance requirements (e.g., as required by the customer) and manufacturing requirements (e.g., the manufacturing capabilities of the foundry to which the circuit will be manufactured). As mentioned above, conventional methods of analog circuit design often involve “best guess” estimations or specification protection performed manually by engineering teams relying on prior knowledge and experience. The result is often over-design and inefficient circuit design, or circuit design prone to failure. In cases where different circuit architectures need to be developed for different manufacturing requirements (e.g., foundry or Process Design Kit (PDK) requirements), if an analog circuit design suitable for multiple different foundries / PDKs has already been designed, this “compatible” circuit design can be selected for all foundries / PDKs, even if the “compatible” circuit design is not the most efficient circuit design for other foundries. This leads to inefficient circuit design. In contrast, in this application, the inventors have surprisingly developed a circuit design method contrary to conventional thinking, thereby selecting the most suitable architecture for analog circuit design for a specific foundry / PDK, rather than simply selecting a circuit design suitable for use with the foundry / PDK (and potentially many other foundries / PDKs). This method is contrary to conventional thinking because selecting the most suitable architecture may involve choosing a technically more complex but most efficient circuit design that is optimized in meeting its required manufacturing requirements (e.g., foundry / PDK requirements). In contrast, conventional analog circuit design methods tend to select the technically simplest design to meet its manufacturing requirements.

[0032] To achieve this solution, the inventors have developed a computer-implemented model in this application that delegates the design responsibility for parts or components of the analog circuit to corresponding cells or "blocks". Figure 2 An example of this model is shown in the figure. This hierarchical model involves the use of a main design unit and multiple auxiliary design units, wherein the main design unit is referred to as the “parent block” 900 and is used as the control entity, and the auxiliary design units are referred to as “child blocks” 950a-d, which receive instructions from the main design unit or the parent block about what these auxiliary design units need to design.

[0033] As a control entity, parent block 900 is configured to receive and process technical requirements, and obtain at least one circuit performance requirement and at least one manufacturing requirement for analog circuits to satisfy a specific set of manufacturing process-related rules. As mentioned above, the manufacturing process-related rules can be based on casting or process design kit (PDK) requirements 350. This will be described in more detail below. Figure 3 The process summarized in the text is the execution process of parent block 900.

[0034] Based on technical requirements, parent block 900 identifies multiple potential analog circuit design architectures to meet circuit performance requirements, and these architectures will satisfy at least one manufacturing requirement. As described below, parent block 900 can achieve this identification using a machine learning algorithm. Then, parent block 900 selects an initial analog circuit design architecture from these potential architectures as the current analog circuit design architecture. The selection of the initial analog circuit design depends on a specific set of manufacturing process-related rules.

[0035] Then, for the analog circuit, the model generates a current design that satisfies the current analog circuit design architecture. This is done by the parent block 900 instructing each auxiliary design unit or each sub-block in sub-blocks 950a-d to design the corresponding component or portion of the analog circuit based on instructions received from the parent block 900. The instructions may include circuit performance requirements (e.g., functional requirements) that the component or portion needs to meet.

[0036] Based on the received information, parent block 900 can achieve this by identifying multiple potential analog circuit design architectures that will meet manufacturing requirements and satisfy circuit performance requirements. Parent block 900 then selects an initial analog circuit design architecture from these multiple potential architectures as the current analog circuit design architecture, where each circuit design architecture includes multiple corresponding circuit sections. For each of these circuit sections, parent block 900 determines the corresponding circuit performance requirements based on a specific set of manufacturing process-related rules. Parent block 900 then provides each of the child blocks 950a-d with instructions that may include, for example, the corresponding circuit performance requirements for each circuit section. Based on the circuit performance requirements provided by parent block 900 for the corresponding circuit section, each of the child blocks 950a-d designs the corresponding circuit section among the multiple circuit sections and outputs the resulting initial design for the corresponding circuit section. The parent block 900 receives the corresponding design for each circuit section from each of the multiple child blocks 950a-d, and based on the corresponding design for each circuit section, the parent block 900 generates a current analog circuit design for the analog circuit that satisfies the current analog circuit design architecture.

[0037] In addition to the corresponding circuit performance requirements for each circuit section, the instructions provided by parent block 900 may also include information related to the context of each component or section of the circuit—in other words, the instructions provided by parent block 900 may also include: what that part or component of the circuit will experience when the part or component is placed in situ in the complete circuit (although in other examples the context may be provided as something other than the circuit performance requirements, in some examples it may be provided as part of the circuit performance requirements). The context may include parameters and variables experienced by the part or component of the circuit during use. The context of any given circuit section or component may be generated based on simulating the performance of one (or more) circuit sections or components interacting with that given circuit section or component, or even by simulating the complete circuit including that given circuit section or component. For example, parent block 900 may be configured to assemble a complete circuit based on the parts or components designed according to child blocks 950a-d and simulate the operation of the assembled circuit. The context of any given circuit section or component may additionally or alternatively be generated based on mathematical calculations or extractions.

[0038] Once an analog circuit design that meets the current analog circuit design architecture has been developed, the completed analog circuit design is tested to determine whether the current design will meet at least one circuit performance requirement. This test can be performed by parent block 900. Parent block 900 can implement this test by simulating the analog circuit based on the current analog circuit design to produce at least one simulation output, and then verifying whether the analog circuit meets the circuit performance requirements.

[0039] If the current design for the analog circuit is determined to be non-compliant with circuit performance requirements, the parent block selects an alternative analog circuit design architecture from multiple potential architectures as the current design architecture. This alternative architecture selection depends on a set of manufacturing process-related rules. The model then repeats the steps of generating a current design for the analog circuit that satisfies the current design architecture and testing the completed analog circuit design to determine if the current design will meet at least one circuit performance requirement. If the current design does not meet at least one circuit performance requirement, this process is repeated. However, if the current design does meet at least one circuit performance requirement, the parent block 900 outputs the design for the analog circuit.

[0040] When testing an analog circuit design architecture, in some examples, for the current analog circuit design, if it is determined that the current design meets at least one circuit performance requirement, then parent block 900 determines the extent to which the current design meets at least one circuit performance requirement and a set of manufacturing process-related rules. Parent block 900 can then select another analog circuit design architecture as the current analog circuit design architecture, where the selection of the other analog circuit design architecture depends on the set of manufacturing process-related rules; and if it is determined that the current design meets at least one circuit performance requirement, then parent block 900 determines the extent to which the current design meets at least one circuit performance requirement and a set of manufacturing process-related rules. The above process can be repeated to generate multiple generated analog circuit designs, where all generated analog circuit designs meet the circuit performance requirements; however, some may be more suitable for at least one circuit performance requirement and a set of manufacturing process-related rules than others. Parent block 900 can then select from the multiple generated analog circuit designs and output the design of the analog circuit that best meets at least one circuit performance requirement and a set of manufacturing process-related rules.

[0041] When parent block 900 selects an analog circuit design architecture, the selection can be based on prioritization of multiple potential architectures. For example, there may be a priority list of potential analog circuit design architectures that have been identified as satisfying a set of manufacturing process-related rules. This list may have already been populated by parent block 900, for example, based on previous iterations of the design process, or based on data provided to parent block 900 elsewhere. For example, as will be described in more detail below, a machine learning algorithm may determine the priority list of analog circuit design architectures based on at least one of the following: (i) at least one circuit performance requirement, and (ii) at least one manufacturing requirement of the analog circuit to satisfy a specific set of manufacturing process-related rules.

[0042] The hierarchical model implemented in the computer can be iterative. Once the parent block 900 has instructed each of the sub-blocks 950a-d to design its corresponding portion, it may be necessary to redesign the circuit and its corresponding portion to some extent—for example, by considering characteristics such as parasitic effects and / or context, where the context is caused by the design of corresponding circuit portions by other sub-blocks 950a-d. Redesign can occur before the parent block 900 determines whether the current design will meet at least one circuit performance requirement. For example, it may be necessary to adapt certain portions of the circuit—for example, due to the context provided by other designed circuit portions and / or estimated parasitic effects that a particular circuit portion or the entire analog circuit may experience. Therefore, the process of designing circuit portions for each sub-block in sub-blocks 950a-d can be repeated to adapt the design of one or more circuit portions, thereby considering, for example, context and / or estimated parasitic effects in an attempt to mitigate and reduce them. For example, sub-blocks 950a-d may iteratively repeat this process of adapting the design of circuit portions until any changes in estimated parasitic effects caused by any adjustments to any other part or component of the analog circuit have been taken into account. For example, the process can be repeated iteratively until any change in the estimated parasitic effect is less than a selected threshold level for the change in the parasitic effect.

[0043] The context and / or parasitic effects of any given circuit section can be generated based on simulating the performance of one (or more) circuit sections interacting with that given circuit section, or even by simulating the complete circuit including that given circuit section. For example, parent block 900 can be configured to assemble a complete circuit based on portions of the design of each sub-block in sub-blocks 950a-d, and simulate the operation of the assembled circuit. The parasitic effects of any given circuit section can additionally or alternatively be generated based on mathematical calculations or extractions. Additionally or alternatively, the parasitic effects of any given circuit section can be obtained by performing a lookup in a database of circuit designs and parasitic effects and / or predicted using a machine learning model. Parent block 900 can then verify whether the simulated circuit meets the circuit performance requirements. When the simulated circuit meets the circuit performance requirements, parent block 900 outputs the generated design. When the analog circuit fails to meet circuit performance requirements: For at least one affected circuit section among multiple circuit sections, a revised circuit performance requirement is determined based on the simulation output and circuit performance requirements; the revised circuit performance requirement for each affected circuit section is provided to at least one corresponding sub-block in sub-blocks 950a-d. In response, parent block 900 can receive the corresponding updated design for each affected circuit section from at least one corresponding sub-block in sub-blocks 950a-d, and update the current design of the analog circuit using the corresponding updated design for each affected circuit section. Then, for the updated current design of the analog circuit, parent block 900 can optionally determine whether the current design meets at least one circuit performance requirement, and optionally determine the extent to which the current design meets at least one circuit performance requirement and / or a set of manufacturing process-related rules.

[0044] This process is in Figure 3 This is illustrated schematically. For example... Figure 3As shown, information representing the technical requirements of analog circuit 350 is received. Technical requirement 350 includes (i) at least one circuit performance requirement and (ii) at least one manufacturing requirement for the analog circuit to meet a specific set of manufacturing process-related rules. In this case, at least one manufacturing requirement includes information related to the PDK. Technical requirement 350 is a process, and critical device physics is captured 301. This step may include: based on the received information, multiple potential analog circuit design architectures for meeting the circuit performance requirements, wherein the multiple potential analog circuit design architectures will meet at least one manufacturing requirement. Then, a current analog circuit design architecture is selected 303 from the multiple potential analog circuit design architectures, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules. Then, an analog circuit design that meets the current analog circuit design architecture is generated 305. Then, the designed circuit is analyzed 307 to determine whether the current design meets at least one circuit performance requirement for the current analog circuit design. If previous iterations of the analog circuit have been designed, the process compares the new (current) design with one (or more) previous designs to determine whether the current analog circuit design represents an improvement 309. If it is determined at step 309 that the current analog circuit design does indeed meet the circuit performance requirements, then the previous analog circuit design that does indeed meet the circuit characteristic requirements is output. Conversely, if the current analog circuit design does represent an improvement, then the circuit is examined to determine 311 whether there are feasible improvements to the circuit performance requirements. If it is determined that the circuit performance requirements can be improved, then the process redesigns the analog circuit based on the current design architecture. If it is determined that the circuit performance requirements cannot be improved, then 313 it is determined whether another architecture can be used to see if other architectures can represent an improved architecture. If other architectures are available, then the design process is repeated. If no other architectures are available, then the current analog circuit design is output.

[0045] The inventors have discovered that the use of this process and iterative hierarchical model advantageously allows for the automation of analog circuit design. Therefore, this means that over-designed analog circuits and / or circuits with unacceptable parasitic effects can be advantageously avoided, allowing for the design and creation of more efficient circuits. Furthermore, the inventors have recognized that designing and selecting analog circuits in this manner means that analog circuits best suited to both performance and manufacturing requirements can be designed. This implies that more efficient circuit architectures can be tailored to, for example, the requirements of each foundry or PDK, rather than simply using a generic architecture that may be compatible with foundry or PDK requirements but does not represent the optimal design (e.g., due to inefficiency, over-design, etc.).

[0046] As mentioned above, Figure 1AThis is an exemplary analog circuit architecture 1000, in which the analog circuit architecture 1000 is an analog-to-digital converter (ADC). Conceptually, a circuit architecture can be divided into functional blocks corresponding to different parts or components of the circuit, for example, based on the corresponding functions of the different parts or components. This layout of functional blocks or components can be considered a representation of an architecture. For example, an ADC may include a comparator 1001, a digital-to-analog converter (DAC) 1002, multiple level shifters 1003, and one or more operational amplifiers (OP-AMPs) 1004. Figure 1A In the example shown, the circuit can be conceptually divided into blocks that correspond to the different parts or components that make up the architecture. For example, as Figure 1B As shown, the comparator can be conceptually divided into a first "sub-block" 950a, the DAC into a second sub-block 950b, the level shifter into a third sub-block 950c, and the OP-AMP into a fourth sub-block 950d. The ADC as a whole can be conceptually classified into its own blocks (in... Figure 1B (This is marked as "parent block" 900). It should be understood that the ADC itself can form a conceptual block within a larger analog circuit.

[0047] If a circuit has a different architecture, it will be understood that the circuit can have different components and different arrangements and layouts of these components—for example, an OP-AMP1004 in one architecture can be replaced by two smaller OP-AMPs with lower gain to satisfy a specific set of manufacturing process-related rules. This may be because the manufacturing process-related rules specified by a foundry / PDK may imply that they are not supported. Figure 1A The gain of the OP-AMP1004 shown is such that, in order to achieve the same circuit performance requirements, it is replaced by using two OP-AMPs, each with a smaller gain. Figure 1A Gain is achieved using a single OP-AMP1004.

[0048] In another example, one PDK (e.g., PDK 180) can support a voltage of 1.8V, but a second PDK (e.g., PDK 28) can support a voltage of 0.9V. For the PDK supporting the lower voltage (i.e., PDK 28), the analog circuit design architecture can include an OTA-based amplifier with a source follower. While this architecture can also operate at higher voltages for the PDK 180, it is not the optimal architecture for the PDK 180; instead, folded cascading is more suitable and efficient. Folded cascading structures are more complex, and therefore, their use would be contrary to normal expectations if the models and processes described herein were not employed. This is why it can be said that this application relates to an approach to analog circuit design contrary to normal expectations.

[0049] As mentioned above, in in-situ use, there are interactions between the different blocks of an analog circuit. These in-situ interactions between blocks (which may include parasitic effects experienced when the individual parts are placed in the complete circuit), and therefore the parameters and variables experienced by each block when placed in the circuit, affect the performance of the circuit. For example, the specifications of the OP-AMP used in the circuit may depend on several parameters and variables caused by the selection and design of comparators, DACs, and / or level shifters, as well as the connections between them.

[0050] A non-exhaustive list of examples of parameters and variables that may affect the selection and design of these different blocks may include: silicon process, temperature range, output load, output impedance, input capacitance, input common-mode range, input differential swing, supply voltage, type of available transistors, output common-mode range, output swing, settling time, noise margin; power supply rejection ratio (PSRR); common-mode range-input (InputCMR); common-mode range-output (OutputCMR); linearity; maximum offset; bandwidth; minimum slew rate; intrinsic delay; minimum phase margin; effective power dissipation; quiescent power dissipation; IP3 point; filter center frequency; filter bandpass range; load step response; linear step response; output accuracy; noise figure; calibration range; background noise; signal-to-noise ratio (SNR); effective number of bits (ENOB); output frequency range; jitter - ptp; jitter - root mean square (RMS). (Square, RMS); Output ripple (ptp); Total harmonic distortion (THD); Startup time; Channel isolation; Reference voltage; Gain error; Offset error; Gain drift. These parameters and variables can be referred to as the "context" or environment in which the block exists. Understanding the context can improve circuit design in order to create optimal analog circuits. It should also be understood that some of these parameters and variables can form part of the circuit performance requirements.

[0051] As mentioned above, the manufacturing requirements for analog circuits can include or specify a particular set of manufacturing process-related rules. Manufacturing requirements can be specified by a process design kit (PDK) created by the foundry. The PDK can include any or a combination of physical constraints, SPICE models (simulation models), PCELLS and technical documents, rule sets, and schematic symbols.

[0052] However, it is understandable that analog circuit design is an iterative process, where the selection and adjustment of one block can affect the context of another block, and so on. Therefore, once the components of one block have been selected / adjusted to form a circuit section, the components of another block may need to be adjusted or reselected to account for the parasitic effects and / or context experienced by the complete circuit / circuit section to which that block belongs. Manually performing such an iterative process is impractical, error-prone, and can only be detected through communication.

[0053] As mentioned above, Figure 2 This is an exemplary computer implementation model in a method for designing automated analog circuits. Figure 2 It schematically shows in Figure 1B The blocks shown in the diagram and discussed above, as well as the interactions between blocks.

[0054] exist Figure 2 In the example shown, each block of the model is responsible for designing the components / functions indicated by that block. Figure 2 In this diagram, sub-block 1 (950a) is responsible for designing comparator 1001, sub-block 2 (950b) is responsible for designing DAC 1002, sub-block 3 (950c) is responsible for designing level shifter 1003, and sub-block 4 (950d) is responsible for designing OP-AMP 1004. Parent block 900 is responsible for the overall design of ADC 1000 and delegates the responsibility for designing parts / components / functions of the ADC to sub-blocks 950a-d. In some examples, parent block 900 can choose the required number of sub-blocks 950a-d, and the responsibilities assigned to each block. Although sub-blocks 950a-d are shown in sequence, it should be understood that this order does not necessarily represent the design order of the circuit parts. For example, parent block 900 may instruct sub-block 950d, responsible for the OP-AMP, to design that part of the circuit first. In some examples, sub-blocks 950a-d may be configured to design the output first and work backward from that output.

[0055] Although each corresponding circuit section can initially be designed independently by its respective block, when each corresponding circuit section is applied in situ to the entire circuit, the operating context of each corresponding circuit section can affect the operation of that circuit section and the entire circuit. Therefore, while the parent block can instruct each child block to design its corresponding section, once the parent block 900 assembles the initial version of the designed circuit based on the sections or components designed by the child blocks 950a-d, it is likely that circuit 1000 and its sections or components will need to be adapted to some extent or even redesigned to account for the parasitic effects and / or contexts generated by the sections designed by other child blocks 950a-d. As mentioned above, this will be an iterative process.

[0056] Therefore, parent block 900 is configured to act as a controller, processing and controlling the design process performed by each child block. To perform this function, such as... Figure 2 As shown, parent block 900 may include multiple different modules, each configured to perform a different function as part of the design process. Figure 2 The parent block includes the guidance module 901, the assembly module 902, and the verification and simulator module 903.

[0057] The guidance module 901 is configured to: receive the technical requirements of the circuit to be designed, including at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit to meet a specific set of manufacturing process-related rules, and convert these requirements into a set of instructions / standards that sub-blocks 950a-d need to meet when designing their respective circuit components. The guidance module 901 is also configured to: prepare instructions and send instructions to each sub-block in sub-blocks 950a-d, specifying what each sub-block needs to design and what standards need to be met during the design process. The instructions may also include the context of other design portions of the circuit designed by other sub-blocks, as well as the broader context of the circuit in which that component or portion of the circuit is intended to operate. For example, circuit performance requirements can be adjusted to take the context into account.

[0058] Assembly module 902 is configured to receive and organize all the corresponding designed parts or components of the analog circuit provided by each sub-block 950a-d, and assemble a complete analog circuit based on the corresponding designed parts or components. The complete analog circuit can then be tested by verification and simulator module 903.

[0059] Verification and simulation module 903 is configured to receive designed components from each sub-block and compare these components against a set of technical requirements to determine whether the designed portions or components are satisfactory. This is achieved by simulating the functionality of the assembled components using analog circuitry. Verification and simulation module 903 can determine whether the designed components / complete circuit design meets the technical requirements, for example, by verifying whether the corresponding circuit portions or components meet their corresponding circuit performance requirements and / or whether the designed analog circuit meets a specific set of manufacturing process-related rules. During this verification step, the extent to which the designed analog circuit meets these requirements can also be determined, for example, by assigning scores based on the degree of closeness to and / or exceedance of the requirements. Additionally or alternatively, verification and simulation module 903 can also perform verification checks to determine whether the designed circuit is effective in the sense that it can operate within certain technical limitations.

[0060] Verification and simulation module 903 can be configured to act as a "testbed" and simulate the functionality of assembled components of the circuit. Such simulation can generate, for example, parasitic effect information and / or contextual information, as well as information about the extent to which the design of the component / complete circuit meets technical requirements such as circuit performance requirements and / or a specific set of manufacturing process-related rules. For example, verification and simulation module 903 can be configured to obtain performance information by mathematically simulating one of the following in a virtual test bench: (i) the designed circuit portion and (ii) a complete simulated circuit including the designed circuit portion, where the performance information is, for example, information related to context and parasitic effects, which are the context and parasitic effects experienced by the simulated circuit if it includes the designed circuit portion. Additionally or alternatively, the verification and simulator module 903 may be configured to obtain performance information, such as performance information related to parasitic effects, by performing a lookup in a database of circuit designs and parasitic effects (e.g., by looking up similar generated designs in the database of circuit designs and parasitic effects). Parasitic effects are defined as the parasitic effects experienced by the simulated circuit if the simulated circuit will include the designed circuit portion. Additionally or alternatively, the verification and simulator module 903 may be configured to look up at least one circuit portion among similar corresponding circuit portions in the database of circuit designs and parasitic effects, and obtain performance information, such as performance information related to parasitic effects experienced by the generated design, based on the value of the parasitic effect obtained by looking up at least one of the corresponding circuit portions. In other examples, the verification and simulator module 903 is configured to obtain performance information, such as performance information related to parasitic effects experienced by the generated design, by using a machine learning model to predict the performance of the circuit.

[0061] The verification and simulator module 903 can also be configured to populate a database of circuit designs, for example, if the guidance module 901 instructs sub-blocks 950a-d to repeatedly design sections of the circuit based on (new or adapted) corresponding circuit performance requirements. The database of circuit designs can also include information related to the extent to which the circuit designs meet technical requirements.

[0062] Each sub-block in sub-block 950a-d also includes multiple different modules, each configured to perform a different function as part of the design process. Figure 2 In the example shown, each sub-block in sub-blocks 950a-d includes converter modules 951a-d, assembly modules 952a-d, and simulator modules 953a-d. It should be understood that in some examples, each sub-block in sub-blocks 950a-d may further include additional modules for indicating third-level design units or "grandchild" blocks, in a manner similar to... Figure 2The parent block 900 includes, in a similar manner, guidance modules for instruction and verification modules for validating the design process from child blocks 950a-d. (See reference) Figure 4 Section 6 will be described in more detail below.

[0063] The converter modules 951a-d of each sub-block 950a-d are configured to receive circuit performance requirements from the parent block 900 and optionally the context of the entire circuit as well as the context of other components of the circuit, and convert these into a set of requirements for designing a portion or component of the analog circuit to conform to these standards. It should be understood that in some examples, context information may be provided and received as part of the circuit performance requirements, but in other examples, context information may be provided separately from (e.g., separately from) the circuit performance requirements.

[0064] Assembly modules 952a-d are configured to select and / or design electronic components to meet requirements imposed upon them, which conform to the instructions / standards indicated by the context of the parent block and the entire circuit and / or the context of other components of the circuit.

[0065] Simulator modules 953a-d can also be configured to simulate how these components will operate in situ to check / verify the technical feasibility of the designed parts or components designed by the assembly modules. In some examples, simulator modules 953a-d can also obtain information related to parasitic effects of the corresponding circuit parts (of which the block has designed the corresponding circuit parts) in a manner similar to that of the verification and simulator module 903 of the parent block 900 described above. (It should be understood that in these examples, the verification and simulator module 903 of the parent block 900 may not need to obtain information related to parasitic effects, as this may have already been performed by the simulator module 953a-d of each of the child blocks 950a-d.)

[0066] In use, parent block 900 receives a set of technical requirements for the analog circuit 1000 to be designed. These technical requirements include at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit, to meet a specific set of manufacturing process-related rules. Figure 2 In the example shown, parent block 900 receives a set of technical requirements for the ADC to be designed, which have certain characteristics, including, for example, those specified by the foundry that will manufacture the ADC (i.e., manufacturing requirements).

[0067] The parent block 900 receives these requirements, and the guidance module 901 translates these requirements into a set of instructions / standards. As part of this process, the guidance module 901 selects an initial analog circuit design architecture from multiple potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on a set of manufacturing process-related rules.

[0068] These instructions / standards are then sent to each of the sub-blocks 950a-d. The guidance module 901 can send these instructions / standards to each of the sub-blocks 950a-d in parallel (i.e., all at once) or in series (e.g., where standards are sent to sub-block 1, then sub-block 2, then sub-block 3, and so on). In some examples, the guidance module 901 may wait until it receives the designed circuit from the first sub-block before sending the circuit performance requirements to the next sub-block, and in some examples, the guidance module may be configured to adjust the circuit performance requirements sent to the next sub-block based on the designed circuit received from the previous sub-block—in other words, based on the context of the designed circuit received from the previous sub-block.

[0069] In the example where instructions / standards are sent in series to sub-blocks 950a-d, the instructions / standards may include methods for distinguishing which parts of the circuit performance requirements are related to which sub-block within sub-blocks 950a-d—for example, the instructions / standards may include headers or flags identifying whether a specific part of the instructions / standards is related to sub-block 950a-d. These headers or flags may be determined by the parent block 900, and the instructions / standards may be adjusted accordingly to incorporate these headers or flags.

[0070] Each sub-block in sub-blocks 950a-d receives these instructions / standards from parent block 900, and the corresponding converter modules 951a-d convert these instructions / standards into a set of requirements for designing a portion or component of an analog circuit to meet the performance requirements of these circuits. Assembly modules 952a-d receive these requirements and design components / parts of a circuit that meet these requirements. It should be understood that this design process may include: searching a database of known circuit designs (or portions of circuit designs) and finding the circuit design that best matches the instructions / standards.

[0071] Then, simulator modules 953a-d simulate how these components / parts of the circuit will operate in situ to check the technical feasibility of the designed components / parts in the circuit designed by the assembly module and / or verify whether the corresponding designed circuit parts conform to the instructions / standards. If the designed circuit parts conform to their corresponding instructions / standards, then sub-blocks 950a-d are then configured to send or output the designed parts or components in the circuit back to parent block 900. If the designed circuit parts do not conform to their corresponding instructions / standards, then sub-blocks 950a-d are then configured to adapt the design of their circuit parts and repeat the process.

[0072] Once parent block 900 receives all designed parts or components of the circuit from all child blocks 950a-d, assembly module 902 of parent block 900 assembles the complete circuit (in this case, an ADC) according to the designed parts or components of each child block, and verifies whether the designed circuit meets the technical requirements through verification and emulation module 903. Verification and emulation module 903 achieves this by simulating the execution of the assembled circuit and comparing the simulated performance with circuit performance requirements and / or manufacturing requirements. For example, verification and emulation module 903 can determine whether the designed component / complete circuit design meets the technical requirements, for example, by verifying whether the designed circuit parts or components meet their corresponding circuit performance requirements and / or whether the designed analog circuit meets a specific set of manufacturing process-related rules. During this verification step, verification and emulation module 903 can also determine the extent to which the designed analog circuit meets these requirements by assigning scores based on the degree of closeness to meeting the requirements and / or whether the requirements are exceeded. Additionally or alternatively, the verification and simulator module 903 may also perform verification checks to determine whether the designed circuit is effective in the sense that it can operate within certain technical limitations. It should be understood that, in some examples, such simulated performance of the complete analog circuit design can be used to obtain parasitic effects and / or optional contextual information (e.g., for another design cell), and the parent block 900 may adjust circuit performance requirements based on the parasitic effects and / or optional contextual information obtained through simulation of the complete analog circuit design.

[0073] If the simulated performance of the designed circuit does not meet at least one circuit performance requirement (e.g., the simulated circuit parameters are greater than a threshold level different from the parameters indicated by the circuit performance requirements, such as parasitic effects exceeding the parasitic effect threshold level), then the verification module 903 transmits it to the guidance module 901. The guidance module 901 can then select another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design architecture depends on the set of manufacturing process-related rules.

[0074] In some examples, before selecting yet another analog circuit design architecture, parent block 900 (e.g., verification module 903 / guidance module 901) can be configured to determine which part or component of the circuit is responsible for the circuit failing to meet performance requirements (e.g., which part is responsible for most of the parasitic effects), and, if one (or more) child blocks 950a-d can be identified, parent block 900 can be configured to send the corrected circuit performance requirements only to the child block responsible for the non-compliant part or component of the circuit. However, in other examples, the corrected criteria can be sent back to all child blocks 950a-d. It will also be understood that, in some examples, parent block 900 can determine that additional and / or alternative child blocks 950a-d and / or grandchild blocks may be needed to design the relevant parts or components of the circuit, for example, to meet the corrected circuit performance requirements.

[0075] The process then continues iteratively, where the converter modules 951a-d of sub-blocks 950a-d receive these revised or adapted circuit performance requirements from the parent block 900 and convert them into a new set of instructions / standards for designing a portion or component of the analog circuit to meet these adapted circuit performance requirements. Assembly modules 952a-d receive these new instructions / standards and design components / parts of the circuit that meet these requirements. Simulator modules 953a-d can then simulate how the redesigned components / parts of the circuit will work in situ to check the technical feasibility of the designed components / parts of the circuit designed by the assembly modules. Sub-blocks 950a-d are then configured to send the (re)designed components / parts of the circuit back to the parent block 900.

[0076] Once parent block 900 receives all (re)designed components / parts of the circuit from all child blocks 950a-d, parent block 900 then assembles the complete circuit (in this case, an ADC) based on the components / parts designed by each child block. The parent block 900 then verifies the designed circuit against the circuit performance requirements via verification and simulation module 903. Verification and simulation module 903 can simulate the execution of the assembled circuit and compare the simulated performance with the circuit performance requirements. When the simulated circuit meets the circuit performance requirements, parent block 900 can output the generated design. When the simulated circuit does not meet the circuit performance requirements, for at least one affected circuit part among multiple circuit parts, parent block 900 can determine the corrected instructions / standards for the affected circuit part based on the simulation output and circuit performance requirements, and provide the corrected instructions / standards for each affected circuit part to at least one of the corresponding child blocks 950a-d. In return, parent block 900 can receive the corresponding updated design for each affected circuit section from at least one of the corresponding child blocks 950a-d, and use the corresponding updated design for each affected circuit section to update the current design of the analog circuit.

[0077] As mentioned above Figure 3 As shown, for the updated current design of the analog circuit, parent block 900 optionally determines 307 whether the current design will meet at least one circuit performance requirement, and optionally determines the extent to which the current design meets at least one circuit performance requirement and / or a set of manufacturing process-related rules. This process can be repeated to generate multiple generated analog circuit designs, all of which meet the circuit performance requirements, but some may be more suitable for meeting at least one circuit performance requirement and a set of manufacturing process-related rules than others. Parent block 900 then selects from the multiple generated analog circuit designs and outputs the design that best meets at least one circuit performance requirement and a set of manufacturing process-related rules.

[0078] It should be understood that sub-blocks 950a-d and / or parent block 900 may also include loop mitigation modules to stop the endless redesign loop from occurring. For example, a loop mitigation module may be configured to have a record of previously designed circuits and output a loop indication if a component / part or complete circuit of the redesigned circuit is identical to, or differs from, a component / part or complete circuit of the previously designed circuit only from, a component / part or complete circuit of the previously designed circuit by less than a selected difference threshold level. For example, parent block 900 may include a loop mitigation module and may be configured to: terminate the design process and accept the last designed circuit as the complete circuit upon receiving a loop indication from the loop mitigation module. Additionally or optionally, parent block 900 may be configured to: decrease the selected difference threshold level, for example, if the design process repeats a selected number of iterations. This may have the effect of finding an “optimal compromise” functional circuit that meets the technical requirements.

[0079] Figure 4 This is a functional schematic view of another example implementation of a computer-generated model for designing analog circuits. The implementation of this model is similar in many ways to... Figure 2 The model shown above, and the above for Figure 2 The functions described by parent block 900 and child blocks 950a-d in the text can be attributed to Figure 4 The parent and child blocks within. Furthermore... Figure 2 Some of the functions described in the main design unit or parent block 900 can be attributed to Figure 4 The auxiliary design unit or sub-block 950a-d in the design, wherein the sub-block further has a third-level design unit or "grandchild" block, etc.

[0080] More in detail, such as Figure 4 As shown, the model hierarchy includes a core design layer, which comprises main design units or parent blocks. Although in Figure 4 Only one parent block 900 is shown in the core design layer, but it should be understood that in some examples, there may be more than one parent block 900, for example, each parent block 900 can operate in parallel. For example, each parent block 900 can be configured to design different aspects of the analog circuit (e.g., aspects that are functionally and / or structurally different from each other).

[0081] The first design layer lies below the core design layer. The first design layer comprises auxiliary design units or child blocks 950 coupled to a parent block 900 in this case (the core design layer). In this example, there are six child blocks, all coupled to the parent block of the core design layer. The child blocks 950 are divided into two distinct groups: a first group comprising child blocks 1, 2, and 3; and a second group comprising child blocks 3, 4, and 5. Each child block 950 is coupled to the parent block 900. These two groups can represent different functional areas or regions of the analog circuitry in the parallel design indicated by the parent block 900.

[0082] In the example shown, sub-blocks 950 in the first group are coupled in parallel to the parent block 900 of the core design layer, and sub-blocks 950 in the second group are coupled in parallel to the parent block 900 of the core design layer. Sub-blocks 950 can be grouped in this way to design different regions or aspects of the analog circuit (e.g., aspects that differ from each other functionally and / or structurally). However, it should be understood that in some examples, not all sub-blocks 950 of the first design layer need to be coupled in parallel to the parent block of the core design layer. For example, sub-blocks 1 and 3 of the first design layer can be coupled to the parent block 900 of the core design layer, and sub-block 2 of the first design layer can be coupled in series to sub-blocks 1 and 3 of the first design layer, respectively.

[0083] The grouping of child blocks 950 can be determined by the parent block 900 of the core design layer. For example, the parent block 900 can be configured to group the child blocks of the first design layer to design different aspects of the analog circuit (e.g., aspects that are functionally and / or structurally different from each other). The parent block 900 of the core design layer can be configured to perform this grouping operation based on the determination of requirements from customer specifications.

[0084] The second design layer is located below the first design layer. The second design layer includes third-level design units or grandchild blocks 1, 2, 3, 4, 5, 6, 7, and 8 (960). Grandchild blocks 960 are coupled to sub-blocks of the upper layer (i.e., the first design layer). Not every sub-block of the first design layer is coupled to a grandchild block of the second design layer. In the example shown, grandchild blocks 1, 2, and 3 of the second design layer are coupled in parallel to sub-block 2 of the first design layer. However, as described above for sub-block 950 of the first design layer, it will be understood that in some examples, not all grandchild blocks of the second design layer need to be coupled in parallel to sub-blocks of the first design layer. For example, grandchild blocks 1 and 3 of the second design layer may be coupled to sub-block 2 of the first design layer, and grandchild block 2 of the second design layer may be coupled in series to grandchild blocks 1 and 3 of the second design layer, respectively.

[0085] Another (nth) design layer lies below the second design layer. The nth design layer comprises great-grandson block 1, great-grandson block 2, great-grandson block 3, and great-grandson block 4 970. Great-grandson block 970 is coupled to the grandson block 960 of the upper layer (i.e., the second design layer) in substantially the same manner as the grandson block 960 of the second design layer is coupled to the child block 950 of the first design layer. Therefore, it should be understood that multiple further design layers may exist below the second design layer, each comprising its own blocks coupled to the blocks of the upper layers.

[0086] Figure 4 The block hierarchy shown allows blocks at different layers of the model to be configured to design aspects or parts of analog circuits with varying degrees of complexity. For example, parent block 900 can be configured to design a complete analog circuit, child block 950 can be configured to design functional components of the analog circuit (e.g., op-amp, AC / DC converter, level shifter, comparator, voltage regulator, power switch, etc.), and grandchild block 960 can be configured to design components of the functional components (e.g., the arrangement of resistors, transistors, capacitors, diodes, inductors, etc. for the components).

[0087] The parent block 900 (of the core design layer) can be configured to: determine the complexity level of designing blocks for the selected layer, and / or a block of a layer can be configured to: determine the complexity level of designing blocks for the lower layer.

[0088] Alternatively or alternatively Figure 4 The block hierarchy structure shown allows blocks in different layers of the model to be configured to design aspects or parts of the analog circuit based on different functional or structural requirements. For example, one layer may include blocks configured to design aspects or parts of the analog circuit based on one functional requirement (e.g., size), and another layer may include blocks configured to design another functional requirement (e.g., current or voltage).

[0089] Figure 5 It is used for example, using Figure 2 or Figure 4 A functional schematic flowchart illustrating an exemplary method for designing analog circuits using an exemplary computer-implemented hierarchical model. Figure 5 The method is the same as the above regarding Figure 2 The methods described share many common characteristics.

[0090] At step 500, parent block 900 receives the technical requirements of the circuit to be designed, including at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit to meet a specific set of manufacturing process-related rules. Parent block 900 is configured to convert the technical requirements into a set of instructions / standards. As part of this process, guidance module 901 selects 502 an initial analog circuit design architecture from multiple potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules.

[0091] Parent block 900 may be additionally or optionally configured to determine whether to send these instructions / standards in parallel or in series to child block 950, and / or whether to send different sets of instructions / standards to lower-level child block 950.

[0092] At this stage, the parent block 900 can also be configured to determine the number of layers in the model—for example, based on the selected current analog circuit design architecture, or alternatively, each layer's blocks can be configured to determine whether lower-level blocks are needed when designing the portion of the circuit that is designed by the upper-level blocks.

[0093] Once parent block 900 has translated the technical requirements 502 into instructions / standards, parent block 900 then sends these instructions / standards 504 to child block 1 of the first design layer. These instructions / standards can specify how many child blocks 950 of the layer will be used, and which child block 950 will be responsible for designing which part of the analog circuit.

[0094] Upon receiving the standard, sub-block 1 designs the first part of the 506 analog circuit based on the received instructions / standard and according to the current analog circuit design architecture. It should be understood that sub-block 1 can be configured to design the first part of the analog circuit based on a subset / first part of the instructions / standards applicable to sub-block 1 as determined by the parent block.

[0095] Once sub-block 1 has designed the first part of the analog circuit, the instructions / standards received from parent block 900 can instruct sub-block 1 to send the designed first part of the circuit and the standards to the second sub-block (sub-block 2) on the same layer. Sub-block 2 can design the second part of the analog circuit based on the received instructions / standards, according to the current analog circuit design architecture. In some examples, sub-block 2 can design the second part of the analog circuit based on only a subset of the instructions / standards (e.g., only some instructions / standards applicable to the second part) or based on all instructions / standards.

[0096] Sub-block 2 further adjusts the design of the second part of the analog circuit based on the context generated by the first part of the designed analog circuit designed by sub-block 1. In some examples, this context can be expressed in the form of an adjusted set of standards—for example, sub-block 1 and / or the parent block can be configured to adjust the standards based on the context and / or parasitic effects provided by the first part of the designed circuit designed by sub-block 1, although it will be understood that in other examples, the context and / or parasitic effects can be provided / provided separately from the standards. For example, in an example where the parent block includes a verification and simulator module, the verification and simulator module can simulate the performance of the designed circuit portion or component to obtain context and / or parasitic information. Alternatively or additionally, in an example where each sub-block includes a verification and simulator module, the verification and simulator module can simulate the performance of the designed circuit portion or component to obtain context and / or parasitic information.

[0097] In some examples, sub-block 2 may determine that it needs to use lower-level blocks to design the circuit portion it is responsible for designing according to the current analog circuit design architecture, and / or determine whether to use these lower-level blocks in series and / or parallel. Additionally or alternatively, the criteria received by sub-block 2 may instruct (e.g., as determined by the parent block) that sub-block 2 use lower-level blocks to design the circuit portion it is responsible for designing (and whether to use these blocks in series or parallel). For example, as shown in Figure 6, sub-block 2 may optionally instruct 512 grandson blocks 1 and 2 to design a subset of the second part of the analog circuit. In such an example, sub-block 2 may optionally verify 513 whether the circuit portion designed by the lower-level blocks (in the illustrated example, grandson blocks 1 and 2) conforms to the instructions / standards required by the lower level.

[0098] Then, sub-block 2 sends the first part of the design, the second part of the design, and the instructions / standards to sub-block 3. In some examples, the instructions / standards may be modified by previous sub-blocks. For example, the instructions / standards may be modified by sub-block 1 and / or sub-block 2 before being sent to the next sub-level. For example, sub-block 2 may be configured to modify the instructions / standards sent to sub-block 3 based on the first part of the designed circuit and / or the second part of the designed circuit.

[0099] Then, sub-block 3 designs the first and / or second parts of the designed circuit based on the received instructions / standards and additionally or alternatively, and designs the third part of the 516 analog circuit according to the current analog circuit design architecture.

[0100] Sub-block 3 then sends the complete circuit to the parent block (518), and the parent block generates an initial design for the analog circuit based on the set of designs for the corresponding circuit parts, and determines (520) whether the currently designed complete circuit meets the circuit performance requirements. As mentioned above, the parent block can achieve this by using a verification and simulator to simulate the performance of the complete circuit.

[0101] If the designed complete circuit does not meet the circuit performance requirements, the parent block selects an alternative analog circuit design architecture, the selection of which depends on the set of manufacturing process-related rules. This process is then repeated, allowing the parent block to resend the 522 instruction / standard to child block 1 to redesign the new analog circuit according to the new analog circuit design architecture. As part of this process, the parent block can determine which additional or alternative child blocks (and / or grandchild blocks) need to be used.

[0102] It should be understood that, in the above examples, the first, second, third, and fourth parts of the analog circuit can be independent portions of the circuit and / or functionally interdependent. In other examples, the first, second, third, and fourth parts of the analog circuit can be selected subsets of the analog circuit. For example, the second part may include a portion of the first part, the third part may include a portion of the first part and a portion of the second part, and the fourth part may include a portion of the first part, a portion of the second part, and a portion of the third part.

[0103] Figure 6A The diagram shows an input buffer, a level shifter, a DAC, and a comparator. Each of these can form part of a complete analog circuit, for example... Figure 6B The complete ADC is shown in the image.

[0104] Figure 6A and 6B The example shown has been designed using a hierarchical model implemented in a computer as described above. The parent block (or main design unit) is responsible for designing the entire ADC, while the child blocks (or auxiliary design units) are responsible for the input buffer, level shifter, DAC, and comparator, respectively. The parent block receives the technical requirements from the user and translates them into circuit performance requirements, which each child block uses to design its corresponding circuit section. The context of other parts of the circuit is considered and used by the child blocks when designing their respective circuit sections. Once the parent block 900 has instructed each child block 950a-d to design its corresponding section or component, the circuit, and the circuit section, is redesigned to some extent so that the context provided by other parts of the circuit is used to design the corresponding circuit section and the entire circuit; therefore, the model is also iterative. As described above, each child block and / or parent block can also perform verification / validation to determine whether the designed partial / complete circuit meets the technical requirements imposed on that child block and / or parent block.

[0105] exist Figure 6B The circuit design shown includes two DACs because it provides the functionality of a differential ADC. Multiple input buffers (three in the example shown) are present because two buffers are used to buffer the two inputs, and the reference is also buffered as an input.

[0106] As described above, analog circuit design devices can utilize machine learning models to identify, select, and / or prioritize potential analog circuit design architectures.

[0107] Machine learning models can include neural networks. Neural networks can include at least one of the following: deep residual networks, high-speed networks, densely connected networks, and capsule networks.

[0108] For any network of this type, it can include multiple distinct neurons organized into different layers. Each neuron is configured to receive input data, process that input data, and provide output data. Each neuron can be configured to perform a specific operation on its input; for example, this could involve mathematical processing of the input data. The input data for each neuron can include the outputs from multiple other preceding neurons. As part of the neuron's operation on the input data, each input data stream (e.g., an input data stream from each preceding neuron that provides its output) is assigned a weight. Thus, the neuron's processing of the input data involves applying weights to different input data streams such that different input data items will contribute more or less to the neuron's total output. Adjustments to the neuron's input values, such as changes to the weights of the input values, can cause a change in the neuron's output value. The output data from each neuron can be sent to multiple subsequent neurons.

[0109] Neurons are organized in layers. Each layer contains multiple neurons that operate on data output from neurons in the previous layer and supplied to those neurons. Within each layer, there may be a large number of different neurons, each applying different weights to its input data and performing different operations on it. All neurons in a layer can have the same input data, and the outputs of all these neurons will be passed to neurons in subsequent layers.

[0110] Precise routing between neurons in different layers forms the main difference between capsule networks and deep residual networks (including variants such as high-speed networks and densely connected networks).

[0111] For residual networks, layers can be organized into blocks, such that the network comprises multiple blocks, each containing at least one layer. In a residual network, the output data from a neuron in one layer can follow more than one distinct path. In traditional neural networks (e.g., convolutional neural networks), the output data from one layer is passed to the next layer, continuing until the end of the network, so that each layer receives input from the layer immediately preceding it and provides output to the layer immediately following it. However, in residual networks, different routes may occur between layers. For example, the output from one layer may be passed to multiple different subsequent layers, and the input to one layer may be received from multiple different preceding layers.

[0112] In residual networks, neuron layers can be organized into distinct blocks, each block comprising at least one neuron layer. Blocks can be arranged as stacked layers, such that the output of one (or more) layer feeds into the input of the next block. The structure of a residual network can be such that the output from one block (or layer) is passed to the block (or layer) immediately following it and at least one subsequent block (or layer). Shortcuts can be introduced into the neural network to pass data from one layer (or block) to another, bypassing other layers (or blocks) in between. This allows for more efficient network training, for example, when dealing with very deep networks, as it enables addressing degradation-related problems during network training (discussed in more detail below). The arrangement of residual neural networks can generate branches such that the same input provided to one layer or block of layers is provided to at least one other layer or block of layers (e.g., allowing other layers to manipulate both the input and output data from a block of layers). This arrangement allows for deeper penetration of the network when using backpropagation to train it. For example, this is because during the learning process, layers or blocks of layers can take the inputs and outputs of the previous layer / block as inputs, and shortcuts can be used to provide deeper penetration when updating the weights of the network.

[0113] In capsule networks, layers can be nested within other layers to provide "capsules." Different capsules can be tailored to perform different tasks better than others. Capsule networks can provide dynamic routing between capsules so that, for a given task, it is assigned to the capsule most capable of handling it. For example, a capsule network can avoid routing the output of each neuron in a layer to each neuron in the next layer. Lower-level capsules are configured to send their input to higher-level (subsequent) capsules, which are determined to be the most likely to process that input. Capsules can predict the activity of higher-level capsules. For example, a capsule can output a vector whose direction represents a characteristic of the object in question. In response, each subsequent capsule can provide a probability as output, the probability that the capsule was trained to identify the object's presence in the input data. This information (e.g., the probability) can be fed back to the capsule, which can then dynamically determine routing weights and forward the input data to the subsequent capsule most likely to be the relevant capsule for processing that data.

[0114] For any type of neural network, multiple distinct layers with different functions may be included. A neural network may include at least one convolutional layer configured to convolve input data across its height and width. The neural network may also have multiple filtering layers, each comprising multiple neurons configured to focus on different portions of the input data and apply filters to those portions. The neural network may also include other layers for processing the input data, such as pooling layers (e.g., max pooling and global average pooling to introduce non-linearity), rectified linear unit (ReLU) layers, and loss layers; some of these layers may include regularization functions. The final block of layers may receive input from the last output layer (or from more layers if a branch exists). The final block may include at least one fully connected layer.

[0115] The final output layer may include a classifier, such as a softmax, sigmoid, or tanh classifier. Different classifiers can be suitable for different types of outputs. For example, a sigmoid classifier might be appropriate when the output is a binary classifier. The neural network of this disclosure can be configured to predict which analog circuit design architecture is likely to work based on at least one of circuit performance requirements and manufacturing requirements of the analog circuit for specifying a particular set of manufacturing process-related rules. The output of the neural network can provide an indication of probability that an analog circuit design architecture will satisfy both at least one manufacturing requirement and at least one circuit performance requirement. For example, the output of the neural network can provide an indication of the probability that an analog circuit design architecture will satisfy at least one circuit performance requirement, wherein it is known that the analog circuit design architecture will definitely satisfy at least one manufacturing requirement. Circuit design architectures can be prioritized or ordered according to the determined probabilities, such that, for example, when the parent block above selects a circuit design architecture from a plurality of circuit design architectures that will satisfy at least one manufacturing requirement, the circuit design architecture that has been determined to have the highest probability of satisfying at least one circuit performance requirement is selected first.

[0116] Figure 7 This is a schematic diagram of an example method for training a machine learning model to estimate the probability that an analog circuit design architecture meets at least one manufacturing requirement and at least one circuit performance requirement. The neural network 700 is configured to receive designed circuit portions and / or analog circuitry as input 710. The designed circuit portions and / or analog circuitry can be stored in a database and can already utilize the aforementioned references. Figures 1A to 6B The described computer-implemented model is designed using a hierarchical model of master and slave design units. Circuit components and / or analog circuitry can be vectorized and / or encoded, for example, by providing a binary format using one-hot encoding. This input is then fed into a set of 3D layers in a neural network. The network has several features that can change as the network is trained. For each neuron, there can be multiple weights, each applied to a corresponding input stream for output data, the input stream coming from neurons in previous layers. These weights are variables that can be modified to provide changes to the neural network's output. These weights can be modified in response to training so that they provide more accurate data. The modified weights, in response to the training of these weights, are called "learned" weights. Furthermore, while layer size and connectivity can be variables (which can be modified and learned during training, including connectivity enhancements), layer size and connectivity can also depend on the typical input data of the network.

[0117] To train a network, for example, by learning the values ​​of the weights, these weights are assigned initial values. These initial values ​​can essentially be random. However, to improve network training, appropriate initialization of these values ​​can be applied, such as Xavier / Glorot initialization. This initialization can suppress the situation where the initial random weights are too large or too small, and the neural network can never be properly trained to overcome these initial biases. This type of initialization can include assigning weights using a distribution with zero mean but a fixed variance.

[0118] Once weights have been assigned, the training data can be fed into the neural network 700. This can include running the neural network on a known designed circuit (and / or circuit segment) and its corresponding performance. Based on this information, a backpropagation optimization method, such as using gradient descent (e.g., stochastic gradient descent) and a loss function, is performed on the network to compare the predicted circuit performance with the expected or known circuit performance of that circuit segment / simulated circuit. For example, the expected or known circuit performance can be obtained using a virtual testbed. Algorithms such as mini-batch gradient descent, RMSprop, Adam, Adadelta, and Nesterov can be used in this process. This allows identification of the extent to which each distinct point (neuron) or path (between neurons in subsequent layers) in the network contributes to determining incorrect scores, thus enabling the determination of any weight adjustments needed. The weights can then be adjusted based on the calculated error. For example, minimizing or removing the contributions of neurons that contribute to or have the largest contribution to incorrect determinations.

[0119] After iteratively training the network with different designed circuit pairs (and / or circuit parts) and corresponding circuit performance, the weights can be updated 750 times, and this process can be repeated a large number of times. To suppress the possibility of overtraining the network, training variables such as learning rate and momentum can be modified and / or controlled to be at selected values. Furthermore, regularization techniques such as L2 or random deactivation can be used, which reduce the likelihood that different layers become too specific to the training data due to overtraining, rather than being generalizable to other similar data. Similarly, batch normalization can be used to aid training and improve accuracy. Typically, the weights are adjusted so that if the network is operated on the same training data again, it will produce the expected results. However, the extent to which this is true will depend on training variables, such as the learning rate.

[0120] It should be understood that increasing the depth of a neural network can cause problems during training, such as slower network delivery due to gradient message issues. However, this disclosure can provide networks with increased depth and accuracy without sacrificing the ability to adequately train the network.

[0121] The depth of the network can be chosen to strike a balance between accuracy and the time spent producing the output. Increasing the network depth can provide increased accuracy, although it can also increase the time spent producing the output. The use of branching structures (as opposed to convolutional neural networks) allows the network to be trained more thoroughly as its depth increases, which in turn increases the network's accuracy.

[0122] It should be understood that, in the context of this disclosure, a non-exhaustive list of example analog parameters that can form a standard basis includes: noise margin; power supply rejection ratio (PSRR); common-mode range-input (input CMR); common-mode range-output (output CMR); linearity; maximum offset; bandwidth; minimum slew rate; intrinsic delay; minimum phase margin; effective power consumption; quiescent power consumption; IP3 point; filter center frequency; filter bandpass range; load step response; linear step response; output accuracy; noise figure; calibration range; background noise; signal-to-noise ratio; ENOB; output frequency range; jitter-ptp; jitter-RMS; output ripple-ptp; total harmonic distortion; startup time; channel isolation; reference voltage; gain error; offset error; gain drift.

[0123] It will also be understood that design units (e.g., primary design units, secondary design units, and tertiary design units) can be implemented in software or hardware, for example, as dedicated circuitry. For instance, a design unit can be implemented as part of a computer system. The computer system may include buses or other communication mechanisms for transmitting information, data, signals, and messages between various components of the computer system. These components may include input / output (I / O) components that process user (i.e., sender, receiver, service provider) actions, such as selecting keys from a keypad / keyboard, selecting one or more buttons or links, and sending corresponding signals to the bus. I / O components may also include output components, such as display and cursor controls (e.g., keyboard, keypad, mouse, etc.). Transceivers or network interfaces can send and receive signals between the computer system and other devices, such as another user device, a merchant server, or a service provider server, via a network. In this embodiment, although other transmission media and methods may also be suitable, the transmission is wireless. The processor may be a microcontroller, a digital signal processor (DSP), or other processing component. The processor handles these different signals, such as those used for display on a computer system or those transmitted to other devices via a communication link. The processor can also control the transmission of information such as cookies or IP addresses to other devices.

[0124] Components of a computer system may also include system memory components (e.g., random access memory (RAM)), static storage components (e.g., read-only memory (ROM)), and / or disk drives (e.g., solid-state drives, hard disk drives). A computer system performs specific operations of the processor and other components by executing one or more sequences of instructions contained in the system memory components.

[0125] Logic can be encoded in a computer-readable medium, which can be any medium that participates in providing instructions to a processor for execution. Such a medium can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. In various embodiments, non-volatile media include optical discs or magnetic disks; volatile media include dynamic memory, such as system memory components; and transmission media include coaxial cables, copper wires, and optical fibers. In embodiments, the logic is encoded in a non-transitory computer-readable medium. In examples, the transmission medium can take the form of acoustic or optical waves, such as those generated during radio wave, optical, and infrared data communications.

[0126] Some common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, any other optical media, punched cards, paper tapes, any other physical media with a perforated pattern, RAM, programmable read-only memory (PROM), erasable PROM (EPROM), flash memory EPROM, any other memory chip or cassette tape, or any other media that a computer is adapted to read from.

[0127] In various embodiments of this disclosure, the execution of the instruction sequence implementing this disclosure can be performed by a computer system. In various other embodiments of this disclosure, multiple computer systems 600 coupled to a network (e.g., such as a LAN, WLAN, PTSN, and / or various other wired or wireless networks, including telecommunications, mobile, and cellular telephone networks) via communication links can cooperate to execute instruction sequences to practice this disclosure.

[0128] It will also be understood that aspects of this disclosure can be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, without departing from the spirit of this disclosure, the various hardware and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both. Where applicable, without departing from the scope of this disclosure, the various hardware and / or software components set forth herein can be separated into sub-components comprising software, hardware, or both. Furthermore, where applicable, it is contemplated that software components can be implemented as hardware components, and vice versa.

[0129] The software according to this disclosure, such as program code and / or data, may be stored on one or more computer-readable media. It is also contemplated that the software identified herein may be implemented using one or more general-purpose or special-purpose computers and / or networked and / or other computer systems. Where applicable, the order of the various steps described herein may be changed, may be combined into compound steps, and / or may be separated into sub-steps to provide the features described herein.

[0130] The various features and steps described herein can be implemented as a system comprising one or more memories storing the various information described herein, and one or more processors coupled to the one or more memories and a network. One or more processors can operate to perform the steps described herein as a non-transitory machine-readable medium comprising a plurality of machine-readable instructions, causing the one or more processors to perform methods including the steps described herein when the plurality of machine-readable instructions are executed by the one or more processors, and methods executed by one or more devices (e.g., hardware processors, user devices, servers, and other devices described herein).

[0131] Other examples and variations of the apparatus and methods described herein will be apparent to those skilled in the art in the context of this disclosure.

Claims

1. An analog circuit design apparatus, the analog circuit design apparatus comprising at least one design unit, the at least one design unit comprising a processor and a communication interface, the processor being configured to: a. Control the communication interface to receive information representing the technical requirements of the analog circuit, wherein... The technical requirements include at least one circuit performance requirement and at least one manufacturing requirement for the analog circuit, to meet a specific set of manufacturing process-related rules. b. Based on the received information, identify a plurality of potential analog circuit design architectures for meeting the at least one circuit performance requirement, wherein the plurality of potential analog circuit design architectures will meet the at least one manufacturing requirement; c. Select an initial analog circuit design architecture from the plurality of potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules; d. Generate a current design that satisfies the current analog circuit design architecture for the analog circuit; e. For the current design of the analog circuit, determine whether the current design will meet the performance requirements of at least one circuit; If it is determined that the current design for the analog circuit does not meet the performance requirements of at least one of the circuits: f. Select another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design architecture depends on the set of manufacturing process-related rules, and g. Repeat steps d and e; and h. If the current design of the analog circuit design architecture meets the performance requirements of at least one circuit, output the design for the analog circuit.

2. The analog circuit design apparatus according to claim 1, wherein, The processor is also configured to: i. For each current design of the analog circuit, determine the extent to which the current design conforms to the at least one circuit performance requirement and the set of manufacturing process-related rules; j. Select another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design architecture depends on the set of manufacturing process-related rules, and k. Repeat steps d and e to generate multiple generated analog circuit designs; as well as l. Select and output the design for the analog circuit that best meets the performance requirements of at least one circuit and the set of manufacturing process-related rules from the plurality of generated analog circuit designs.

3. The analog circuit design apparatus according to claim 1, wherein, At step c and / or step f, the selection of the analog circuit design architecture is based on the prioritization of the plurality of potential architectures, which creates a priority list of potential analog circuit design architectures that have been determined to satisfy the set of manufacturing process-related rules.

4. The analog circuit design apparatus according to claim 1, wherein, The analog circuit design device includes a main design unit and an auxiliary design unit, wherein the main design unit is configured as follows: m. Based on the received information, identify a plurality of potential analog circuit design architectures for meeting the at least one circuit performance requirement, wherein the plurality of potential analog circuit design architectures will also meet the at least one manufacturing requirement; and n. Select the initial analog circuit design architecture from the plurality of potential analog circuit design architectures as the current analog circuit design architecture, wherein each circuit design architecture includes a plurality of corresponding circuit parts; o. For each of the plurality of circuit sections, determine the corresponding circuit performance requirements for that circuit section, wherein the corresponding circuit performance requirements for each circuit section are determined based on the specific set of manufacturing process-related rules; and p. Provide the corresponding circuit performance requirements for each circuit section to at least one of the multiple auxiliary design units; Furthermore, each of the plurality of auxiliary design units in the analog circuit design apparatus is configured as follows: q. Based on the circuit performance requirements provided by the main design unit for the corresponding circuit section, design the corresponding circuit section among the multiple circuit sections; and r, Output the initial design results of the corresponding circuit section; The main design unit is further configured as follows: s. Receive the corresponding design for each circuit section from each of the plurality of auxiliary design units; and t. Based on the corresponding design of each circuit part, generate a current analog circuit design for the analog circuit that satisfies the current analog circuit design architecture.

5. The analog circuit design apparatus according to claim 4, wherein, The main design unit is also configured to: u. Simulate the analog circuit based on the current analog circuit design to generate at least one simulation output; v. Verify whether the analog circuit meets the performance requirements of at least one circuit, and When the analog circuit meets the performance requirements of at least one circuit, the generated design is output. as well as When the analog circuit does not meet the performance requirements of at least one of the circuits: Choose another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design depends on the set of manufacturing process-related rules; as well as Repeat steps d through e and steps m through v.

6. The analog circuit design apparatus according to claim 4, wherein, The main design unit is also configured to: w. Simulate the analog circuit based on the current analog circuit design to generate at least one simulation output; x. Verify whether the analog circuit meets at least one of the circuit performance requirements of the analog circuit, and When the analog circuit meets the performance requirements of at least one circuit, the generated design is output. as well as When the analog circuit does not meet the performance requirements of at least one of the circuits: For at least one of the plurality of circuit sections that is affected, a corrected circuit performance requirement for the affected circuit section is determined based on the at least one simulation output and the at least one circuit performance requirement; Provide at least one corresponding auxiliary design unit with the corrected circuit performance requirements for each affected circuit section; Receive the corresponding updated design for each affected circuit section from the at least one corresponding auxiliary design unit; The current design of the analog circuit is updated using the corresponding updated design for each affected circuit section; as well as Repeat steps w through x for the updated set of designs.

7. The analog circuit design apparatus according to claim 6, wherein, Each of the plurality of auxiliary design units is configured to adapt the design of the corresponding part based on the at least one simulation output by adapting the design of the corresponding part based on the difference between the at least one simulation output and the circuit performance requirements.

8. The analog circuit design apparatus according to claim 5, wherein, After at least one of the plurality of auxiliary design units has completed at least the initial design of a given circuit portion, at least one of the plurality of auxiliary design units is configured to adapt the current analog circuit design based on the context of the circuit portion corresponding to the at least one auxiliary design unit, wherein the context includes circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the plurality of auxiliary design units.

9. The analog circuit design apparatus according to claim 4, wherein, After at least one of the plurality of auxiliary design units has completed at least the initial design of a given circuit portion, at least one of the plurality of auxiliary design units is configured to adapt the output initial design of the at least one auxiliary design unit based on the context of the circuit portion corresponding to the at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated based on the completed design of the given circuit portion completed by at least one of the plurality of auxiliary design units.

10. The analog circuit design apparatus according to claim 8, wherein, Each of the plurality of auxiliary design units is configured to repeat the step of adapting the design of the other circuit part if a modification to the design of another circuit part results in a change in the context of the other circuit part.

11. The analog circuit design apparatus according to claim 9 or 10, wherein, Each of the plurality of auxiliary design units is configured to repeat the steps of adapting the design of another circuit section only if the change in the context is greater than a selected context change threshold level.

12. The analog circuit design apparatus according to claim 8, 9 or 10, wherein, The analog circuit design apparatus is configured to obtain the context by simulating the performance of the given circuit portion.

13. An analog circuit design method, the method comprising: In the design unit that includes the processor and communication interface, a. Control the communication interface to receive information representing the technical requirements of the analog circuit, wherein the technical requirements include: at least one circuit performance requirement, and at least one manufacturing requirement of the analog circuit, to meet a specific set of manufacturing process-related rules; b. Based on the received information, identify a plurality of potential analog circuit design architectures for meeting the at least one circuit performance requirement, wherein the plurality of potential analog circuit design architectures will meet the at least one manufacturing requirement; c. Select an initial analog circuit design architecture from the plurality of potential analog circuit design architectures as the current analog circuit design architecture, wherein the selection of the initial analog circuit design depends on the set of manufacturing process-related rules; d. Generate a current design that satisfies the current analog circuit design architecture for the analog circuit; e. For the current design of the analog circuit, determine whether the current design will meet the performance requirements of at least one circuit; If it is determined that the current design for the analog circuit does not meet the performance requirements of at least one of the circuits: f. Select another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design architecture depends on the set of manufacturing process-related rules, and g. Repeat steps d and e; and h. If the current design of the analog circuit design architecture meets the performance requirements of at least one circuit, output the design for the analog circuit.

14. The method of claim 13, further comprising: i. For each current design of the analog circuit, determine the extent to which the current design conforms to the at least one circuit performance requirement and the set of manufacturing process-related rules; j. Select another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design architecture depends on the set of manufacturing process-related rules, and k. Repeat steps d and e to generate multiple generated analog circuit designs; as well as l. Select and output the design for the analog circuit that best meets the performance requirements of at least one circuit and the set of manufacturing process-related rules from the plurality of generated analog circuit designs.

15. The analog circuit design method according to claim 13, wherein, At step c and / or step f, the selection of the analog circuit design architecture is based on the prioritization of the plurality of potential architectures, which creates a priority list of potential analog circuit design architectures that have been determined to satisfy the set of manufacturing process-related rules.

16. The analog circuit design method according to claim 15, further comprising: At the main design unit m. Based on the received information, identify a plurality of potential analog circuit design architectures for meeting the at least one circuit performance requirement, wherein the plurality of potential analog circuit design architectures will also meet the at least one manufacturing requirement; and n. Select the initial analog circuit design architecture from the plurality of potential analog circuit design architectures as the current analog circuit design architecture, wherein each circuit design architecture includes a plurality of corresponding circuit parts; o. For each of the plurality of circuit sections, determine the corresponding circuit performance requirements for that circuit section, wherein the corresponding circuit performance requirements for each circuit section are determined based on the specific set of manufacturing process-related rules; and p. Provide the corresponding circuit performance requirements for each circuit section to at least one of the multiple auxiliary design units; At each of the plurality of auxiliary design units: q. Based on the circuit performance requirements provided by the main design unit for the corresponding circuit section, design the corresponding circuit section among the multiple circuit sections; and r, Output the initial design results of the corresponding circuit section; It also includes: at the main design unit, s. Receive the corresponding design for each circuit section from each of the plurality of auxiliary design units; and t. Based on the corresponding design of each circuit part, generate a current analog circuit design for the analog circuit that satisfies the current analog circuit design architecture.

17. The analog circuit design method according to claim 16, further comprising: At the main design unit, u. Simulate the analog circuit based on the current analog circuit design to generate at least one simulation output; v. Verify whether the analog circuit meets the performance requirements of at least one circuit, and When the analog circuit meets the performance requirements of at least one circuit, the generated design is output. as well as When the analog circuit does not meet the performance requirements of at least one of the circuits: Choose another analog circuit design architecture as the current analog circuit design architecture, wherein the selection of the other analog circuit design depends on the set of manufacturing process-related rules; as well as Repeat steps d through e and steps m through v.

18. The analog circuit design method according to claim 16, further comprising: At the main design unit, w. Simulate the analog circuit based on the current analog circuit design to generate at least one simulation output; x. Verify whether the analog circuit meets at least one of the circuit performance requirements of the analog circuit, and When the analog circuit meets the performance requirements of at least one circuit, the generated design is output. as well as When the analog circuit does not meet the performance requirements of at least one of the circuits: For at least one of the plurality of circuit sections that is affected, a corrected circuit performance requirement for the affected circuit section is determined based on the at least one simulation output and the at least one circuit performance requirement; Provide at least one corresponding auxiliary design unit with the corrected circuit performance requirements for each affected circuit section; Receive the corresponding updated design for each affected circuit section from the at least one corresponding auxiliary design unit; The current design of the analog circuit is updated using the corresponding updated design for each affected circuit section; as well as Repeat steps w through x for the updated set of designs.

19. The analog circuit design method according to claim 18, further comprising: At each of the plurality of auxiliary design units, the design of the corresponding part is adapted based on the at least one simulation output by adapting the design of the corresponding part based on the difference between the at least one simulation output and the circuit performance requirements.

20. The analog circuit design method according to claim 16, further comprising: After at least one of the plurality of auxiliary design units has completed at least the initial design of a given circuit portion, the output initial design of the at least one auxiliary design unit is adapted based on the context of the circuit portion corresponding to the at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated based on the completed design of the given circuit portion completed by the at least one of the plurality of auxiliary design units.

21. The analog circuit design method according to claim 16, further comprising: After at least one of the plurality of auxiliary design units has completed at least the initial design of a given circuit portion, the output initial design of the at least one auxiliary design unit is adapted based on the context of the circuit portion corresponding to the at least one auxiliary design unit, wherein the context includes: circuit performance requirements generated based on the completed design of the given circuit portion completed by the at least one of the plurality of auxiliary design units.

22. The analog circuit design method according to claim 21, further comprising: At each of the plurality of auxiliary design units, if a modification to the design of one of the plurality of circuit sections results in a change in the context of another circuit section, the step of adapting the design of the other circuit section is repeated.

23. The analog circuit design method according to claim 21 or 22 further includes: At each of the plurality of auxiliary design units, the step of adapting the design of another circuit section is repeated only if the change in the context is greater than a selected context change threshold level.

24. The analog circuit design method according to claim 21 or 22, wherein, The context is obtained by simulating the performance of the given circuit section.

25. The method according to any one of claims 13 to 22, further comprising: Fabricate analog circuits according to the output design described.

26. A non-transitory computer-readable storage medium comprising a program for a computer, wherein, The program is configured to cause the processor to perform the method of any one of claims 13 to 25.

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