Apparatus, system, and method for testing a connection interface with circuit board circuitry to convey instructions

Abstract

A device, system and method for testing a connection interface of a circuit board by using a circuit on the circuit board to transmit a control command to a testing device connected to the connection interface through a memory on the circuit board, the testing device converting the control command to test the connection interface, without using external connection lines, and improving testing efficiency.

Description

Technical Field

[0001] A testing apparatus, system, and method thereof, particularly a apparatus, system, and method for testing connection interfaces by transmitting circuit instructions from a circuit board. Background Technology

[0002] Industry 4.0, also known as the Fourth Industrial Revolution, is not simply about creating new industrial technologies. Instead, it focuses on integrating existing industrial technologies, sales processes, and product experiences. Through artificial intelligence, it aims to build intelligent factories that are adaptive, resource-efficient, and ergonomic. Furthermore, it integrates customers and business partners into business and value processes to provide comprehensive after-sales service, thereby constructing a new, intelligent industrial world with awareness and consciousness.

[0003] As the wave of Industry 4.0 sweeps the globe, manufacturers are all optimizing their production transformation and enhancing their competitiveness through intelligent manufacturing. Intelligent manufacturing is built on sensing technology, network technology, automation technology, and artificial intelligence. It achieves intelligent product design and manufacturing, as well as enterprise management and services through processes of perception, human-machine interaction, decision-making, execution, and feedback.

[0004] The electronics assembly industry's characteristics of low profit margins and high sales volume, coupled with fierce price competition, drive businesses to pursue more effective control and optimization of raw materials and production tools, thereby maximizing the efficiency of factory production resources. This inevitably includes various circuit board testing processes on the production line of the electronics assembly industry. For example, when the circuit board is a motherboard, this also includes testing the memory connection interfaces on the motherboard.

[0005] One current method for testing memory connection interfaces on motherboards is to use a DummyDIMM as a test device to perform boundary scan testing on the memory connection interfaces. When performing boundary scan testing, it is usually necessary to interconnect the JTAG ports of all test devices; therefore, boundary scan JTAG connection cables need to be set up between each test device.

[0006] In practice, the limited space between memory connection interfaces, coupled with the presence of numerous JTAG cables, can lead to connection interruptions after prolonged testing. Furthermore, since JTAG is a serial signal, the more JTAG ports there are, the longer the JTAG cables become, and the lower the data communication frequency. Therefore, as the number of test devices connected to the memory connection interfaces increases, the JTAG communication rate decreases, resulting in longer testing times.

[0007] In summary, it is evident that existing technologies have long suffered from unstable connection conditions and testing times when using JTAG cables to perform boundary scan tests on memory connection interfaces. Therefore, it is necessary to propose improved technical methods to address this issue. Summary of the Invention

[0008] In view of the problem that the existing technology has unstable connection conditions and test time when using JTAG connection cables to perform boundary scan tests on memory connection interfaces, the present invention discloses an apparatus, system and method for testing connection interfaces by transmitting circuit instructions from a circuit board, wherein:

[0009] The apparatus for testing connection interfaces by transmitting circuit transmission commands from a circuit board disclosed in this invention includes at least: at least one pin for connecting to a memory connection interface on the circuit board under test corresponding to the device, and for connecting to an internal integrated circuit on the circuit board under test via the memory connection interface, and for transmitting control commands received by the device to other identical devices connected to the circuit board under test via the internal integrated circuit; and a processing module for converting the control commands into operation commands and executing the operation commands to test the memory connection interface.

[0010] The system for testing connection interfaces by transmitting circuit instructions on a circuit board disclosed in this invention includes at least: a circuit board under test, comprising multiple memory connection interfaces, the multiple memory connection interfaces being interconnected through an internal integrated circuit, wherein when a control instruction is transmitted to the internal integrated circuit, the internal integrated circuit transmits the control instruction to the multiple memory connection interfaces; multiple test devices, each test device being connected to a memory connection interface, and each test device including at least one pin, the at least one pin of each test device being interconnected through the internal integrated circuit, and used to receive control instructions through the internal integrated circuit, convert the control instructions into operation instructions, and execute the operation instructions to test the connected memory connection interfaces.

[0011] The method for testing connection interfaces by transmitting circuit instructions on a circuit board disclosed in this invention includes at least the following steps: connecting a circuit board under test (TBD) to multiple test devices; the TBD includes multiple memory connection interfaces corresponding to the multiple test devices; each test device is connected to a memory connection interface and each test device includes at least one pin; the at least one pin of each test device is interconnected through an internal integrated circuit; when a control instruction is transmitted to the internal integrated circuit, the internal integrated circuit transmits the control instruction to each memory connection interface, enabling each test device to obtain the control instruction through the connected memory connection interfaces; each test device converts the control instruction into an operation instruction and executes the operation instruction to test the connected memory connection interface.

[0012] The apparatus, system, and method disclosed in this invention are as described above. The difference between this invention and the prior art is that the present invention transmits control commands to the test device that is connected to the internal integrated circuit through the memory connection interface on the circuit board under test. The test device converts the control commands to test the connected memory connection interface, thereby solving the problems existing in the prior art and achieving the technical effect of improving test efficiency. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the components of the device for testing the connection interface by transmitting circuit instructions from a circuit board, as proposed in this invention.

[0014] Figure 2 This is a schematic diagram of the components of the circuit board under test proposed in this invention.

[0015] Figure 3A This is a flowchart of the method for testing connection interfaces using circuit transmission commands from a circuit board, as proposed in this invention.

[0016] Figure 3B This is a flowchart of a method for testing a memory connection interface by converting control commands using a testing device proposed in this invention.

[0017] The attached icon numbers are as follows:

[0018] 100 Test Device

[0019] 110 Connector

[0020] 111 Connector

[0021] 120 processing module

[0022] 121 Control Unit

[0023] 125 Programmable Logic Units

[0024] 190 connector

[0025] 200 Circuit Boards Under Test

[0026] 210 Processing Unit

[0027] 220 System Bus

[0028] 230 Memory Connection Interface

[0029] 231-238 Memory connection interface

[0030] 410 Signal Controller

[0031] 420 Access Controller

[0032] Step 310 Connect the circuit board under test to the testing device. The testing devices are connected via internal integrated circuits.

[0033] Step 320: Control commands are transmitted via the internal integrated circuit to the memory connection interface connected to the test device, enabling the test device to receive the control commands.

[0034] Step 330: The testing device selects and converts the control command into an operation command based on the target pin of the control command and executes the operation command to test the connected memory interface.

[0035] Step 331: The testing device switches the control command to an access command or a test command.

[0036] Step 333: When the control command is a access command, the testing device reads the signal of the target pin according to the access command.

[0037] Step 335: When the control command is a test command, the test device sends a test signal to the input pin of the target pin according to the test command, and obtains the result signal from the output pin of the target pin. Detailed Implementation

[0038] The features and implementation methods of the present invention will be described in detail below with reference to the accompanying drawings and embodiments. The content is sufficient to enable any person skilled in the art to easily and fully understand the technical means used by the present invention to solve the technical problem and to implement it accordingly, thereby achieving the effects that the present invention can achieve.

[0039] This invention utilizes an existing internal integrated circuit bus (I2C, also referred to as "internal integrated circuit" in this invention) on the circuit board under test (PCB) to transmit control commands to a test device connected to the PCB, enabling the test device to perform tests on the PCB according to the control commands. The PCB under test is a circuit board containing a memory connection interface providing a connection for dual in-line memory modules (DIMMs), and the test device is typically a corresponding memory test device.

[0040] The following is a preliminary step. Figure 1 The schematic diagram of the component of the device for testing the connection interface by transmitting circuit instructions on a circuit board proposed in this invention is combined with... Figure 2 The component schematic diagram of the circuit board under test provided in this invention is used to illustrate the system operation of this invention. For example... Figure 1 and Figure 2 As shown, the system of the present invention includes a test device 100, a circuit board under test 200, a signal controller 410, and an add-on access controller 420.

[0041] The test device 100 is connected to the memory connection interface 230 of the circuit board under test 200 and is responsible for testing the memory connection interface 230 of the circuit board under test 100. Generally speaking, the test device 100 can perform specific test operations and / or simulate the operation of the corresponding memory module to test the connected memory connection interface 230.

[0042] In some embodiments, the test apparatus 100 may further include a connector 110, a processing module 120, and an attachable connector 190. The connector 110 and the processing module 120, and the connector 190 and the processing module 120, may be connected by one or more circuits (not shown) disposed on the test apparatus 100.

[0043] Connector 110 is a component on the test apparatus 100 that connects to the memory connection interface 230 of the circuit board under test 200, and includes multiple pins (such as pin 111). The positions of the pins on connector 110 generally correspond to the pin positions of the memory module simulated by the test apparatus 100.

[0044] The processing module 120 can receive control commands through the connector 110 or the connector 190, and can convert the received control commands into operation commands and execute operation commands to test the memory connection interface 230 of the circuit board under test 100.

[0045] In some embodiments, the processing module 120 may include a control unit 121 and a programmable logic unit 125. However, the present invention is not limited thereto. Any software or hardware, or any combination of software, hardware, and firmware, that can perform the functions described by the control unit 121 and the programmable logic unit 125 can serve as the processing module 120. The control unit 121 may be a microcontroller unit (MCU), and the programmable logic unit 125 may be a complex programmable logic device (CPLD). However, the present invention is not limited to these descriptions.

[0046] The control unit 121 can receive control commands compatible with the internal integrated circuit via the connector 110 or connector 190, and can choose to convert the received control commands into operation commands compatible with the internal integrated circuit or into operation commands compatible with JTAG, depending on the target pin represented by the received control commands. More specifically, when the target pin represented by the control commands is a pin belonging to the internal integrated circuit, the control unit 121 can convert the control commands into access commands corresponding to the programmable logic unit 125 and enabling the programmable logic unit 125 to access the target pin using the internal integrated circuit. Alternatively, when the target pin represented by the control commands is a pin not belonging to the internal integrated circuit (such as a pin used for boundary scan) or the signal on the target pin may continuously change over time, the control commands can be converted from a format compatible with the internal integrated circuit to a test command that enables the programmable logic unit 125 to generate a test command using JTAG to test the target pin, i.e., a JTAG-compatible test command.

[0047] The control unit 121 can also load and execute pre-established test programs. Generally, test programs are used for boundary scan testing, but the present invention is not limited thereto. The control unit 121 can simulate a boundary scan element, so that after the test program is executed, it issues control commands corresponding to the target pins and compatible with JTAG to the boundary scan element simulated by the control unit 121. In this way, the control unit 121 can obtain the control commands generated by the test program through the simulated boundary scan element, and can convert the obtained control commands into access commands or directly use them as test commands.

[0048] The programmable logic unit 125 can execute operation instructions generated by the control unit 121. More specifically, when the operation instruction is an access instruction, the programmable logic unit 125 can generate access information compatible with the internal integrated circuit for reading and writing the target pin according to the access instruction, and can transmit the access information to the chip with the target pin through the internal integrated circuit to obtain the corresponding signal of the target pin, or can provide the specific signal represented by the access signal to the corresponding target pin; when the operation instruction is a test instruction, the programmable logic unit 125 can transmit the test signal represented by the test instruction to the input pin of the target pin through the JTAG connection port on the chip with the target pin, and can obtain the result signal from the output pin of the target pin through the JTAG connection port on the chip with the target pin.

[0049] Connector 190 is compatible with the internal integrated circuit and can receive control commands transmitted by signal controller 410. It can also be connected to other test devices connected to other memory connection interfaces 230 on the circuit board under test 200.

[0050] The circuit board under test (TBD) 200 may include a processing unit 210, a system bus 220, and a memory connection interface 230. Generally, the TBD 200 may include one or more memory connection interfaces, such as... Figure 2 As shown, the circuit board under test 200 includes eight memory connection interfaces (231-238). In most embodiments, the circuit board under test 200 is a motherboard.

[0051] The processing unit 210 can perform calculations and judgments, and can also be connected to the memory connection interface 230 (memory connection interface 231-238) via the system bus 220. It can transmit data or signals to the memory connection interface 230 (memory connection interface 231-238) and receive data or signals transmitted by the memory connection interface 230 (memory connection interface 231-238) via the system bus 220, for example, transmitting control signals to specific memory connection interfaces 231-238.

[0052] The processing unit 210 can also receive control signals transmitted by the access controller 420, and can convert the received control signals into corresponding control instructions to be transmitted to the memory connection interface 230.

[0053] In some embodiments, the processing unit 210 may be a central processing unit (CPU) or a microprocessor.

[0054] Memory connection interfaces 230 (memory connection interfaces 231-238) can be connected to the processing unit 210 via the system bus 220, or to an internal integrated circuit. In some embodiments, memory connection interfaces 231-234 can be interconnected via internal integrated circuits, and memory connection interfaces 235-238 can be interconnected via internal integrated circuits, while memory connection interfaces 231-234 and memory connection interfaces 235-238 are not connected. However, this invention is not limited thereto; for example, memory connection interfaces 231-238 can also be interconnected via internal integrated circuits. Generally, memory connection interface 230 is a memory connector.

[0055] The signal controller 410 is compatible with an internal integrated circuit; for example, the signal controller 410 can be an internal integrated circuit controller. The signal controller 410 can generate and transmit control commands, and can transmit the control commands to the test apparatus 100 via the internal integrated circuit that is directly connected to the connector 190 of the test apparatus 100.

[0056] Access controller 420 can generate and transmit control signals to processing unit 210 of circuit board under test 200. In some embodiments, access controller 420 may be a test access connection port (TAP) controller.

[0057] The operating apparatus and method of the present invention will then be explained using an embodiment, and please refer to [reference needed]. Figure 3A The flowchart illustrates the method for testing connection interfaces using circuit transmission commands from a circuit board, as proposed in this invention. In this embodiment, it is assumed that the testing device 100 is a DummyDIMM and the circuit board under test 200 is a motherboard, but this invention is not limited thereto.

[0058] First, multiple test devices 100 can be inserted into different memory connection interfaces 230 of the circuit board under test 200 to connect the circuit board under test 200 with the multiple test devices 100 (step 310). In this embodiment, it is assumed that the test devices 100 connected to the memory connection interfaces 231 to 234 of the circuit board under test 200 can be interconnected through internal integrated circuits on the circuit board under test 200, and the test devices 100 connected to the memory connection interfaces 235 to 238 of the circuit board under test 200 can be interconnected through internal integrated circuits on the circuit board under test 200.

[0059] After the circuit board under test 200 is connected to the test device 100 (step 310), the processing unit 210 of the circuit board under test 200 can transmit control commands to all test devices 100 through its internal integrated circuit (step 320). In this embodiment, the processing unit 210 can transmit control commands to the memory connection interface 231 and memory connection interface 235 of the circuit board under test 20 through its internal integrated circuit, so that the control commands are transmitted to the test devices 100 connected to the memory connection interface 231 or memory connection interface 235 through the memory connection interface 231 or memory connection interface 235. At the same time, the control commands can also be transmitted to the memory connection interfaces 232-234 and memory connection interfaces 236-238 respectively through the internal integrated circuit connected to the memory connection interface 231 or memory connection interface 235, so that the test devices 100 connected to the memory connection interfaces 232-234 or memory connection interfaces 236-238 can receive the control commands.

[0060] After the processing module 120 of the test apparatus 100 receives a control command from the internal integrated circuit connected to the memory connection interface 230 connected to the circuit board under test 200, the processing module 120 can select whether to use the control command as an operation command or convert the control command into an operation command according to the target pin of the control command, and can execute the generated operation command to test the memory connection interface 230 connected to the test apparatus 100 (step 330). In this embodiment, it is assumed that the processing module 120 includes a control unit 121 and a programmable logic unit 125, and can perform operations as follows: Figure 3BAs shown in the flowchart, after the control unit 121 receives the control command, it can select whether the target pin represented by the control command belongs to the internal integrated circuit and convert the control command into an access command corresponding to the programmable logic unit 125, or convert the control command compatible with the internal integrated circuit into a test command compatible with JTAG through the included signal conversion logic layer (step 331). The access command is then transmitted to the programmable logic unit 125 through the transmission channel corresponding to the internal integrated circuit or through the transmission channel corresponding to JTAG. When the control command is converted into an access command, The programmable logic unit 125 can generate corresponding access information compatible with the internal integrated circuit according to the access instruction so that the chip with the target pin can obtain the signal of the corresponding target pin (step 333), such as obtaining the signal of the GND pin; when the control instruction is converted into a test instruction, the programmable logic unit 125 can send a test signal to the input pin in the target pin through the JTAG connection port according to the test instruction (step 335), and obtain the result signal from the output pin in the target pin, that is, transmit the test signal and receive the result signal through the JTAG connection port on the chip with the target pin.

[0061] In addition, in the above embodiments, after the circuit board under test 200 is connected to the test device 100 (step 310), the processing module 120 of the test device 100 can also execute the test program. In this embodiment, assuming that the test program uses JTAG to connect to the memory interface 230 of the circuit board under test 200, after the test program is executed by the control unit 121 of the processing module 120, it can generate JTAG-compatible control instructions. The control unit 121 can obtain the control instructions generated by executing the test program through the boundary scan element simulated by the included boundary scan simulation layer, and can convert the obtained control instructions into access instructions compatible with the internal integrated circuit or directly use them as test instructions according to the target pin corresponding to the control instructions. Then, it can transmit the generated access instructions or test instructions to the programmable logic unit 125 through the transmission channel corresponding to the internal integrated circuit or JTAG. When the programmable logic unit 125 receives an access instruction, it can generate corresponding access information compatible with the internal integrated circuit according to the received access instruction so that the chip with the target pin can obtain the signal of the target pin. When the control instruction is converted into a test instruction, the programmable logic unit 125 can send a test signal to the input pin of the target pin through the JTAG connection port on the chip with the target pin according to the test instruction, and obtain the result signal from the output pin of the target pin.

[0062] Thus, through this invention, control commands can be transmitted from the existing internal integrated circuits on the circuit board under test to the test device connected to the memory connection interface of the circuit board under test, without the need to transmit control commands through external connection lines of the test device.

[0063] In summary, the difference between this invention and the prior art lies in the technical means of transmitting control commands from the existing internal integrated circuit on the circuit board under test to a test device connected to the internal integrated circuit via the memory connection interface on the circuit board under test. The test device then converts the control commands to test the connected memory connection interface. This technical means can solve the problem of unstable connection status and test time when using JTAG connection cables to perform boundary scan tests on the memory connection interface of the memory in the prior art, thereby achieving the technical effect of improving test efficiency.

[0064] Furthermore, the method of testing connection interfaces by transmitting circuit instructions on a circuit board according to the present invention can be implemented in hardware, firmware, software, or any combination of hardware, firmware, and software. It can also be implemented in a centralized manner in a computer device or in a decentralized manner with different components distributed among several interconnected computer devices.

[0065] While the embodiments disclosed in this invention are as described above, the content is not intended to directly limit the scope of patent protection for this invention. Any modifications or refinements made by those skilled in the art to which this invention pertains, in form and detail, without departing from the spirit and scope disclosed herein, shall fall within the scope of patent protection for this invention. The scope of patent protection for this invention shall still be determined by the appended claims.

Claims

1. A system for testing connection interfaces by transmitting circuitry commands from a circuit board, the system comprising at least: A circuit board under test includes multiple memory connection interfaces and at least one internal integrated circuit. The multiple memory connection interfaces are interconnected through the internal integrated circuit. When a control command is transmitted to the internal integrated circuit, the internal integrated circuit transmits the control command to the plurality of memory connection interfaces; and Multiple test devices are provided, each of which is connected to a memory connection interface. Each test device includes at least one pin, and the at least one pin of each test device is interconnected through an internal integrated circuit. The pin is used to receive a control command through the internal integrated circuit, select the control command as an operation command or convert the control command into an operation command according to a target pin corresponding to the control command, and execute the operation command to test the connected memory connection interface.

2. The system for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 1, wherein, Each of the test devices is further configured to convert the operation instruction into a corresponding access instruction and obtain the signal of the target pin according to the access instruction when the target pin belongs to the internal integrated circuit, and to convert the control instruction into the JTAG-compatible operation instruction when the target pin does not belong to the internal integrated circuit, and to send a test signal to the input pin of the target pin according to the operation instruction and obtain the result signal from the output pin of the target pin.

3. An apparatus for testing connection interfaces by transmitting circuitry commands from a circuit board, the apparatus comprising at least: At least one pin is provided for connecting to a memory interface on a circuit board under test (PCB), and for connecting to an internal integrated circuit (IC) on the PCB via the memory interface, enabling the device to interconnect with other devices connected to other memory interfaces on the PCB via the IC, and for receiving a control command transmitted to the IC; and A processing module, connected to the at least one pin, is configured to select, based on a target pin corresponding to the control instruction, whether to use the control instruction as an operation instruction or to convert the control instruction into an operation instruction, and to execute the operation instruction to test the memory connection interface.

4. The apparatus for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 3, wherein, The processing module also includes a control unit and a programmable logic unit. The control unit is used to treat the control instruction as an operation instruction when the target pin belongs to the internal integrated circuit, and to convert the control instruction into a JTAG-compatible operation instruction when the target pin does not belong to the internal integrated circuit. The programmable logic unit is used to convert the operation instruction into a corresponding access instruction when the target pin belongs to the internal integrated circuit and to obtain the signal of the target pin according to the access instruction. When the target pin does not belong to the internal integrated circuit, it sends a test signal to the input pin of the target pin according to the operation instruction and obtains the result signal from the output pin of the target pin.

5. The apparatus for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 3, wherein, The processing module is further used to simulate a boundary scan element, and to convert the control command into an operation command corresponding to the internal integrated circuit based on the boundary scan element when the control command is determined to be a test command.

6. The apparatus for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 3, wherein, The processing module is further used to load and execute a test program to test the memory connection interface.

7. A method for testing a connection interface using circuit transmission commands from a circuit board, the method comprising at least the following steps: A circuit board under test is connected to multiple test devices. The circuit board under test includes multiple memory connection interfaces corresponding to the multiple test devices and at least one internal integrated circuit. Each test device is connected to a memory connection interface, and each test device includes at least one pin. The at least one pin of each test device is interconnected with each other through the at least one internal integrated circuit. When a control command is transmitted to the internal integrated circuit, the internal integrated circuit transmits the control command to each of the memory connection interfaces, enabling each of the test devices to obtain the control command through the connected memory connection interfaces; and Each of the test devices selects the control command as an operation command or converts the control command into an operation command based on a target pin corresponding to the control command, and executes the operation command to test the connected memory connection interface.

8. The method for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 7, wherein, The steps of each test device converting the control command into the operation command and executing the operation command to test the connected memory connection interface are as follows: when the target pin belongs to the internal integrated circuit, each test device converts the control command into an access command and reads the signal of the target pin according to the access command; when the target pin does not belong to the internal integrated circuit, the control command is converted into the JTAG-compatible operation command, and a test signal is sent to the input pin of the target pin according to the operation command, and the result signal is obtained from the output pin of the target pin.

9. The method for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 7, wherein, The step of each test device in converting the control command into the operation command is as follows: when it is determined that the control command is a test command, a boundary scan element is simulated, and the control command is converted into the operation command corresponding to the internal integrated circuit based on the boundary scan element.

10. The method for testing connection interfaces by transmitting circuitry commands from a circuit board as described in claim 7, wherein, The step of transmitting the control command to the internal integrated circuit is as follows: a processing unit of the circuit board under test transmits the control command to the internal integrated circuit through the bus of the circuit board under test, or a signal controller connected to at least one of the test devices transmits the control command to the at least one of the connected test devices, so that the control command is transmitted to the internal integrated circuit through the at least one of the connected test devices.

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