A method and system for detecting defects in verilog code
Patent Information
- Application Number
- CN202310280811.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-21
- Publication Date
- 2026-10-30
- Estimated Expiration
- 2043-03-21
AI Technical Summary
然而作为一种常见的HDL，Verilog由于其复杂性，不能够作为现代电路设计流程的中间表示(IR)，不支持语义级的代码缺陷检测，无法实现缺陷检测规则的定制
[0041]通过将Verilog转换成CST和LLHD两种IR检测缺陷，实现了对Verilog代码中的语义级缺陷的检测；其中，不同的缺陷特征对应了CST表达中不同的标签或标签组，通过匹配CST表达文件中JSON节点的不同标签或标签组，可以检测到对应的缺陷；不同的缺陷特征对应了LLHD表达中的不同指令，通过提取LLHD表达中的不同指令，可以检测到对应的缺陷。
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Figure CN116795685B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of FPGA testing, and in particular relates to a method and system for detecting defects in Verilog code. Background Technology
[0002] As programmable logic device technology matures, its applications in military, defense, aviation, and aerospace fields are becoming increasingly widespread, especially in control, data processing and storage, instrumentation, communication, and digital signal processing.
[0003] Programmable logic device (PLD) software is characterized by compact code, reliability, and strict real-time requirements. Traditional testing methods mainly include dynamic testing and static testing. Dynamic testing primarily relies on simulation testing to check the correctness of the design's functions, performance, interfaces, and compliance with requirements, but it is difficult to perform code-level testing. Static testing, on the other hand, mainly targets defects in the code itself. It does not require running the code program and can comprehensively test the software code's standardization, accuracy, consistency, and other characteristics. Therefore, static testing has become an important means of detecting defects in PLD software code.
[0004] Using automated testing methods to detect software code defects in programmable logic devices is essential for improving the efficiency of static testing. Because Hardware Description Languages (HDLs) are highly complex, automated detection requires an intermediate representation (IR) upon which corresponding inspection rules are defined. In Verilog code analysis and testing, many semantic defects with certain characteristics and patterns, such as asynchronous reset signals not being released synchronously or glitches in input signals, are frequently detected. Automated discovery and localization of such defects can greatly improve testing efficiency. However, as a common HDL, Verilog, due to its complexity, cannot serve as an intermediate representation (IR) for modern circuit design flows, does not support semantic-level code defect detection, and cannot customize defect detection rules. Summary of the Invention
[0005] Based on the above analysis, this invention aims to provide a Verilog code defect detection method and system. It performs structural transformation on Verilog code and uses two IRs: JSON-formatted concrete syntax tree (CST expression) and low-level hardware description (LLHD expression). This method can detect semantic-level defects in Verilog code and supports the customization of defect detection rules.
[0006] This invention provides a method for detecting defects in Verilog code, specifically including the following steps:
[0007] Based on the defect detection requirements and the original Verilog code, the Verilog code to be detected is obtained;
[0008] Describe the first correspondence between Verilog reserved words, structures, and variable names and CST labels / label groups, the second correspondence between Verilog variable names and LLHD variable names, and the third correspondence between key-value pairs in CST expressions and LLHD expressions;
[0009] Based on the first correspondence, the Verilog code to be detected is converted into CST expression;
[0010] Based on the first correspondence, the second correspondence, and the third correspondence, the CST expression is converted into an LLHD expression;
[0011] Based on the defect detection requirements, defect detection functions corresponding to CST and / or LLHD expressions are written respectively. Based on the defect detection functions of the corresponding expressions, defects are detected in the CST or LLHD expressions to obtain the defect detection results of the Verilog code to be detected.
[0012] Furthermore, the CST expression includes multiple CST nodes; based on the first correspondence, the second correspondence, and the third correspondence, the CST expression is converted into an LLHD expression, including:
[0013] Based on the first correspondence, determine the Verilog statement type corresponding to each CST node;
[0014] Based on the Verilog statement type, the sub-label / sub-label group of the CST node, and the first correspondence, determine the Verilog variable name corresponding to the CST node;
[0015] Based on the Verilog variable name and the second correspondence, determine the LLHD variable name corresponding to the CST node;
[0016] Based on the expression information in the CST node and the third correspondence, the LLHD expression and delay information corresponding to the expression in the CST node are determined;
[0017] Based on the LLHD variable name, LLHD expression, and delay information, the CST node is converted into an LLHD instruction to obtain the LLHD expression corresponding to the CST node.
[0018] Furthermore, the defect detection results include the detected defects and the original Verilog code line where the defects are located.
[0019] Furthermore, when converting the CST expression to an LLHD expression, a fourth correspondence between CST nodes and LLHD instructions is described; based on the fourth correspondence, the original Verilog code line where the defect is located is obtained.
[0020] Furthermore, the original Verilog code line containing the defect is obtained, including:
[0021] For CST expressions, the Verilog line of code containing the defect is determined based on the start and end positions of the CST nodes where the defect is detected;
[0022] For LLHD expressions, the CST node corresponding to the defect is determined based on the detected defect and the fourth correspondence, and the Verilog code line to be detected where the defect is located is determined based on the start and end positions of the corresponding CST node.
[0023] The original Verilog line containing the defect is obtained based on the Verilog line to be detected where the defect is located.
[0024] Furthermore, the step of converting the Verilog code to be detected into a CST expression based on the first correspondence includes:
[0025] Based on the first correspondence, reserved words and structures in the Verilog code to be detected are marked using CST tags / tag groups;
[0026] Use CST tags / tag groups to identify variables in code blocks within the Verilog code to be tested;
[0027] Each line in the Verilog code block to be tested is converted into a JSON array of CST representations; where each word in the line corresponds to an element in the JSON array.
[0028] Furthermore, the process of obtaining the Verilog code to be detected based on the defect detection requirements and the original Verilog code includes:
[0029] Based on the defect detection requirements, determine whether the defect to be detected is "cross-clock domain output not registered" and whether the original Verilog code is at the RTL level:
[0030] If so, the original Verilog code is converted to a netlist level to obtain the Verilog code to be tested;
[0031] If not, then the original Verilog code is the Verilog code to be tested.
[0032] This invention also provides a Verilog code defect detection system, comprising:
[0033] The Verilog code preprocessing module is used to obtain the Verilog code to be detected based on the defect detection requirements and the original Verilog code;
[0034] The relation mapping description module is used to describe and store the first correspondence between Verilog reserved words, structures, and variable names and CST tags / tag groups, the second correspondence between Verilog variable names and LLHD variable names, the third correspondence between key-value pairs in CST expressions and LLHD expressions, and the fourth correspondence between CST nodes and LLHD instructions.
[0035] The CST conversion module is used to convert the Verilog code to be detected into a CST expression based on the first correspondence.
[0036] The LLHD conversion module is used to convert the CST expression into an LLHD expression based on the first correspondence, the second correspondence, and the third correspondence.
[0037] The defect detection module is used to perform defect detection on the CST expression and / or the LLHD expression based on the defect detection requirements and the fourth correspondence, as well as the defect detection function corresponding to the CST expression and / or the LLHD expression, and obtain the defect detection result.
[0038] Furthermore, the fourth correspondence is obtained by converting the CST expression into an LLHD expression.
[0039] Furthermore, the defect detection requirements include the type and name of the defect to be detected.
[0040] The present invention can achieve at least one of the following beneficial effects:
[0041] By converting Verilog into two types of IR (Inspection and Detection) – CST and LLHD – semantic-level defects in Verilog code can be detected. Different defect features correspond to different tags or tag groups in the CST expression, and the corresponding defects can be detected by matching different tags or tag groups in the JSON nodes of the CST expression file. Different defect features correspond to different instructions in the LLHD expression, and the corresponding defects can be detected by extracting the different instructions in the LLHD expression.
[0042] By writing a corresponding defect detection function based on each defect feature, and inputting the defect detection function with CST expression and / or LLHD expression, defect detection can be achieved by matching the CST expression and / or LLHD expression with the defect features, thus realizing the customization of defect detection rules.
[0043] By describing the correspondence between Verilog code, CST expression, and LLHD expression, the corresponding Verilog code line can be located after a defect is detected by CST or LLHD expression.
[0044] Because LLHD expressions separate the control flow and data flow of Verilog designs through LLHD instructions, matching defect features using LLHD expressions avoids the need to match multiple nested labels when using CST expressions to detect defect features. This makes it easier to write defect detection functions and improves the efficiency of customizing defect detection rules.
[0045] Other features and advantages of the invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained from what is particularly pointed out in the description, claims, and drawings. Attached Figure Description
[0046] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0047] Figure 1 This is a flowchart of the code defect detection method in an embodiment of the present invention;
[0048] Figure 2 This is an example diagram illustrating the expression of CST in step S02 of the method embodiment of the present invention;
[0049] Figure 3 and Figure 4 This is an example diagram illustrating the expression of CST in step S04 of an embodiment of the present invention. Detailed Implementation
[0050] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0051] Method Implementation Examples
[0052] A specific embodiment of the present invention discloses a Verilog code defect detection method, which specifically includes the following steps:
[0053] S01. Based on the defect detection requirements and the original Verilog code, the Verilog code to be detected is obtained.
[0054] Specifically, defect detection requirements include the type and name of the defect to be detected.
[0055] Specifically, the code level of the Verilog code to be detected corresponds to the defect to be detected.
[0056] Specifically, the raw Verilog code level includes RTL level and netlist level. When it is necessary to detect the defect "output not registered across clock domains", if the raw Verilog code is at the RTL level, it needs to be converted to the netlist level to obtain the Verilog code to be detected; if the raw Verilog code is already at the netlist level, no conversion is needed, and the raw Verilog code is the Verilog code to be detected.
[0057] Preferably, the method for converting RLT-level Verilog code to netlist-level code is as follows: integrate the RTL processing front-end tool DFE through the Tool Command Language (TCL) framework, input the RLT-level Verilog code to be converted, export the flattened netlist, and obtain netlist-level Verilog code.
[0058] Specifically, when the defect to be detected is another type of defect, there is no need to convert the Verilog code level; the original Verilog code is the Verilog code to be detected.
[0059] Step S02: Describe the first correspondence between Verilog reserved words, structures, and variable names and CST labels / label groups, describe the second correspondence between Verilog variable names and LLHD variable names, and describe the third correspondence between key-value pairs in CST expressions and LLHD expressions.
[0060] It should be noted that the terms "first," "second," and "third" do not imply any corresponding relationship, but are merely used to distinguish different correspondences.
[0061] Specifically, a mapping table is compiled to describe the first correspondence between Verilog reserved words, structure or variable names and CST labels / label groups; wherein, the Verilog variable name refers to the signal name described in Verilog;
[0062] Specifically, a Verilog variable name and LLHD variable name mapping table is compiled to describe the second correspondence; wherein, the LLHD variable name refers to the signal name described by LLHD.
[0063] Specifically, an LLHD expression generation function is written to describe the third correspondence. By calling the LLHD expression generation function, key-value pairs in the CST expression, such as numerical expressions, conditional expressions, and signal connection expressions, can be converted into their corresponding LLHD expressions. Step S03: Based on the first correspondence, the Verilog code to be tested is converted into a CST expression.
[0064] Specifically, based on the first correspondence, CST tags / tag groups are used to mark reserved words and structures in the code block; CST tags / tag groups are used to identify variables in the code block; each sentence in the Verilog code to be detected is converted into a JSON array of CST expressions, where each word in the sentence corresponds to an element of the corresponding JSON array.
[0065] For example, in Verilog, `begin` indicates the start of a code block and is marked with the tag "tag:"kBegin" when converted to CST; in Verilog, `@` indicates a list of sensitive signals, i.e., a structure, and is marked with the tag "tag:"kEventControl" when converted to CST.
[0066] Examples such as Figure 2 This demonstrates the CST representation of an always block:
[0067] The collapsed lines 644-760 correspond to the list of sensitive signals in the Verilog language's always block, which is marked with the tag "kEventControl" in the figure; lines 765-771 describe the Verilog language's begin reserved word (begin is used to indicate the start of a Verilog block), and the corresponding CST JSON element is marked with the tag "kBegin" in line 772. Figure 2 In each JSON node, "end" and "start" indicate the start and end positions of the word in the corresponding Verilog code. "end" and "start" are used to restore the CST expression to Verilog code later.
[0068] Step S04: Based on the first correspondence, the second correspondence, and the third correspondence, convert the CST expression to the LLHD expression.
[0069] Specifically, step S04 includes the following steps:
[0070] S04-1. Based on the first correspondence, determine the Verilog statement type corresponding to each CST node;
[0071] S04-2. Based on the Verilog statement type, the sub-label / sub-label group of the CST node, and the first correspondence, determine the Verilog variable name corresponding to the CST node;
[0072] S04-3. Based on the Verilog variable name and the second correspondence, determine the LLHD variable name corresponding to the CST node;
[0073] S04-4. Based on the expression information in the CST node and the third correspondence, determine the LLHD expression and delay information corresponding to the expression in the CST node;
[0074] S04-5. Based on the LLHD variable name, LLHD expression and delay information, convert the CST node into an LLHD instruction, that is, the LLHD expression corresponding to the CST node.
[0075] To obtain the original Verilog line of code where the defect is located, S04-6 can be included after S04-5;
[0076] S04-6, Describe the fourth correspondence between CST nodes and LLHD instructions.
[0077] For example, the CST expression corresponding to a non-blocking assignment statement in Verilog (such as...) Figure 3 The conversion of (as shown) to the corresponding LLHD expression includes:
[0078] S04-1' Based on the first correspondence, determine the Verilog statement type corresponding to each CST node.
[0079] Specifically, the label of the CST node is: [Tag::NONBLOCKING_ASSIGNMENT_STATEMENT]. Based on this label and the first correspondence, it is determined that the CST node corresponds to a non-blocking assignment statement in Verilog.
[0080] S04-2' Based on the Verilog statement type, the sub-label / sub-label group of the CST node, and the first correspondence, determine the Verilog variable name corresponding to the CST node.
[0081] For example, based on the sub-label group [Tag::LP_VALUE,Tag::REFERENCE_CALL_BASE,Tag::REFERENCE,Tag::LOCAL_ROOT,Tag::UNQUALIFIED_ID,Tag::SYMBOL_IDENTIFIER,] in the CST node and the first correspondence, the corresponding Verilog variable name is determined to be rst_reg1, which is the lvalue of the corresponding non-blocking assignment statement in Verilog;
[0082] S04-3' Determine the LLHD variable name corresponding to the CST node based on the Verilog variable name and the second correspondence;
[0083] For example, based on the Verilog variable name and the second correspondence, the LLHD variable name corresponding to the Verilog variable rst_reg1 is determined to be rst_reg1. It should be noted that in this example, the Verilog variable name and the corresponding LLHD variable name are the same, but for other signal names, the corresponding Verilog variable name and LLHD variable name may be the same or different.
[0084] Based on the expression information in the CST node and the third correspondence, S04-4' determines the LLHD expression and delay information corresponding to the expression in the CST node.
[0085] For example, based on the key-value pair "text:rst_n" in the CST expression of this node (such as... Figure 4 As shown in the figure, the corresponding LLHD expression is obtained as %rst_n.prb3. Specifically, since the Verilog non-blocking assignment statement does not have latency information, and the corresponding CST node does not have an expression that reflects latency information, the latency information is taken as 0, and the corresponding LLHD latency information is represented as %v28.
[0086] S04-5' Based on the LLHD variable name, LLHD expression and delay information, convert the CST node into an LLHD instruction, that is, the LLHD expression corresponding to the CST node.
[0087] The CST expression includes multiple CST nodes. Based on the LLHD expression corresponding to each CST node, the LLHD expression corresponding to the CST expression is obtained.
[0088] For example, based on the LLHD lvalue variable name, rvalue expression, and delay information of a non-blocking assignment statement, the corresponding LLHD instruction, i.e., the LLHD expression, is obtained, represented as:
[0089] drv%rst_reg1,%rst_n.prb3,%v28;
[0090] Here, drv is an LLHD instruction type, i.e., assignment, which means driving a variable; the variable being driven is rst_reg1, and the value used to drive it is rst_n.prb3, which is obtained from the rst_n signal; %v28 is the delay information, and the delay here is 0.
[0091] S04-6' describes the fourth correspondence between CST nodes and LLHD instructions.
[0092] For example, the CST node corresponding to this non-blocking assignment statement is as follows: Figure 3 As shown, the corresponding LLHD command is drv%rst_reg1,%rst_n.prb3,%v28; the two are in a one-to-one correspondence.
[0093] Step S05: Based on the defect detection requirements, write defect detection functions for the corresponding CST expression and / or LLHD expression respectively, and perform defect detection on the CST expression or the LLHD expression based on the defect detection functions of the corresponding expressions to obtain the defect detection results of the Verilog code to be detected.
[0094] Step S05 includes the following steps:
[0095] S05-1. Based on the defect detection requirements, for each type of defect to be detected, write corresponding defect detection functions in CST and / or LLHD expressions.
[0096] Specifically, for semantic-level defects in Verilog code, the corresponding CST expressions represent these defect characteristics through labels or label groups; when writing defect detection functions, matching the CST expressions with the labels or label groups corresponding to different defects can detect whether the corresponding defects exist.
[0097] For example, a detection function for the defect "bitwise operators appear in the conditional expression" is written. The function algorithm includes: determining the tag group of the CST expression corresponding to the conditional expression in the Verilog code; matching the tag group starting from the root node of the JSON array of the CST expression; and continuing to match the corresponding tags of "bitwise AND, bitwise OR, bitwise NOT operators" in the CST nodes that match the tag group. When the corresponding tag is matched, it indicates that the defect "bitwise operators appear in the conditional expression" is met.
[0098] Specifically, for semantic-level defects in Verilog code, the corresponding LLHD expressions reveal these defect characteristics through the variables and operations of the corresponding instructions. When writing defect detection functions, matching the variables and operations of the instructions corresponding to different defects with the LLHD expressions can detect whether the corresponding defects exist in the Verilog code.
[0099] For example, write a detection function for the defect "asynchronous reset not released synchronously":
[0100] The detection principle of "asynchronous reset not released synchronously" is:
[0101] When converting the rising edge, falling edge, and level signals in the always statement of each block of Verilog code to LLHD expression, all possible reset signals are generated.
[0102] For each possible reset signal in the LLHD expression, it is necessary to check whether it includes a release operation instruction. The release operation includes reading / driving a net from a net, reading / writing a register from a net, and reading a register / driving a net. The corresponding LLHD instructions are (Opcode::Prb, Opcode::Drv), (Opcode::Prb, Opcode::St), and (Opcode::Drv, Opcode::St). For each possible reset signal in the LLHD expression, if at least one release operation instruction exists, the possible reset signal is considered to have been released; otherwise, the possible reset signal is considered not to have been released, i.e., a defect is detected.
[0103] Based on the above principle, the algorithm of the defect "asynchronous reset not released synchronously" detection function includes: matching all possible reset signals in the LLHD expression; matching the release operation instruction for the matched possible reset signals; and for reset signals that do not have a release instruction, they meet the characteristics of the defect "asynchronous reset not released synchronously".
[0104] S05-2. Input the CST expression or LLHD expression into the corresponding defect detection function to perform defect detection and obtain the detected defects.
[0105] Specifically, the CST expression and / or LLHD expression are input into the corresponding defect detection function for defect detection. When the CST tag / tag group or LLHD instruction matches the defect characteristics, the corresponding defect is detected.
[0106] For example, for the defects in Table 1, automatic defect detection is achieved by detecting CST expressions.
[0107] Table 1. Defects detected by CST expression
[0108]
[0109] For example, for the defects in Table 2, automatic defect detection is achieved by detecting LLHD expressions.
[0110] Table 2 Defects detected by LLHD expression
[0111]
[0112]
[0113] It should be noted that: CST expressions use a multi-level nested JOSN format. Automatic defect detection by detecting CST expressions is achieved by matching different labels or label groups corresponding to different defects. Its advantage is that the algorithm for writing defect detection functions is simple, but it may encounter scenarios that require matching multi-level nested labels. On the other hand, LLHD expressions use LLHD instructions to separate the control flow and data flow of the Verilog design. By using LLHD expressions to match defect features, it can avoid the scenario where multi-level nested labels need to be matched when using CST expressions to detect defect features. Moreover, due to the separation of control flow and data flow, it is more suitable for detecting defects involving signal operations.
[0114] For example, as shown in Tables 1 and 2, when the defect to be detected included in the detection requirements is only listed in Table 1, the automatic detection of the defect is completed by detecting the CST expression; when the defect to be detected is only listed in Table 2, the automatic detection of the defect is completed by detecting the LLHD expression; when the defect to be detected is listed in both Table 1 and Table 2, the automatic detection of the defect is completed by detecting both the CST expression and the LLHD expression.
[0115] S05-3. Based on the detected defect and the fourth correspondence, obtain the original Verilog code line where the defect is located.
[0116] Specifically, for CST expressions, the start and end positions of the CST nodes where defects are detected are extracted, thereby obtaining the Verilog code line containing the defect corresponding to that CST node.
[0117] For LLHD expressions, based on the detected defective LLHD instructions, the CST node corresponding to the LLHD instructions is obtained based on the fourth correspondence. Then, the start and end positions of the CST node are extracted to obtain the Verilog code line containing the defect.
[0118] Specifically, for Verilog code lines containing defects: if the Verilog code has been converted from RTL level to netlist level in step S01, then existing technical tools are used to convert the Verilog code containing defects to RTL level, thus obtaining the original Verilog code line corresponding to the defect; if it has not been converted in step S01, then the Verilog code line containing defects is the original Verilog code line corresponding to the defect.
[0119] This embodiment discloses a Verilog code defect detection method. By converting Verilog into two intermediate expressions, CST and LLHD, defects are detected, thus realizing the detection of semantic-level defects in Verilog code. By writing corresponding defect detection functions according to each defect feature, the defect detection rules are customized. By describing the correspondence between Verilog code, CST expression, and LLHD expression, the original Verilog code corresponding to the defect can be located according to the correspondence after the defect is detected.
[0120] Because LLHD expressions separate the control flow and data flow of Verilog designs through LLHD instructions, matching defect features using LLHD expressions avoids the need to match multiple nested labels when using CST expressions to detect defect features. This makes it easier to write defect detection functions and improves the efficiency of customizing defect detection rules.
[0121] System Implementation Examples
[0122] A Verilog code defect detection system includes a Verilog code preprocessing module, a relation comparison module, a CST expression conversion module, an LLHD expression conversion module, and a defect detection module, wherein:
[0123] The Verilog code preprocessing module is used to obtain the Verilog code to be detected based on the defect detection requirements and the original Verilog code; the defect detection requirements include the type and name of the defect to be detected.
[0124] The relation mapping module is used to describe and store the first correspondence between Verilog reserved words, structures, and variable names and CST labels / label groups, the second correspondence between Verilog variable names and LLHD variable names, the third correspondence between key-value pairs in CST expressions and LLHD expressions, and the fourth correspondence between CST nodes and LLHD instructions.
[0125] The CST conversion module is used to convert the Verilog code to be detected into a CST expression based on the first correspondence.
[0126] The LLHD conversion module is used to convert the CST expression into an LLHD expression based on the first correspondence, the second correspondence, and the third correspondence.
[0127] The defect detection module is used to perform defect detection on the CST expression and / or the LLHD expression based on the defect detection requirements and the fourth correspondence, as well as the defect detection function corresponding to the CST expression and / or the LLHD expression, and obtain the defect detection result.
[0128] The fourth correspondence is obtained by converting the CST expression into an LLHD expression.
[0129] Compared to existing technologies, the beneficial effects of the Verilog code defect detection system provided in this embodiment are basically the same as those of the method embodiment, and will not be elaborated here.
[0130] It should be noted that the above embodiments are based on the same inventive concept, and any parts not described repeatedly can be referenced from each other.
[0131] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for detecting defects in Verilog code, characterized in that, Includes the following steps: Based on the defect detection requirements and the original Verilog code, the Verilog code to be detected is obtained. Specifically, based on the defect detection requirements, it is determined whether the defect to be detected is "cross-clock domain output not registered" and whether the original Verilog code is at the RTL level. If so, the original Verilog code is converted to the netlist level to obtain the Verilog code to be detected. If not, the original Verilog code is the Verilog code to be detected. Describe the first correspondence between Verilog reserved words, structures, and variable names and CST labels / label groups, the second correspondence between Verilog variable names and LLHD variable names, and the third correspondence between key-value pairs in CST expressions and LLHD expressions; Based on the first correspondence, the Verilog code to be detected is converted into a CST representation; the CST representation is a concrete syntax tree in JSON format, including multiple CST nodes; Based on the first, second, and third correspondences, the CST expression is converted into an LLHD expression. When converting the CST expression to an LLHD expression, for each CST node in the CST expression, the following conversion is performed: Based on the first correspondence, the Verilog statement type corresponding to the CST node is determined; based on the Verilog statement type, the sub-label / sub-label group of the CST node, and the first correspondence, the Verilog variable name corresponding to the CST node is determined; based on the Verilog variable name and the second correspondence, the LLHD variable name corresponding to the CST node is determined; based on the expression information in the CST node and the third correspondence, the LLHD expression and latency information corresponding to the expression in the CST node are determined; based on the LLHD variable name, LLHD expression, and latency information, the CST node is converted into an LLHD instruction to obtain the LLHD expression corresponding to the CST node. Based on defect detection requirements, defect detection functions corresponding to CST and / or LLHD expressions are written respectively. Defect detection is performed on the CST or LLHD expressions based on the corresponding defect detection functions to obtain the defect detection results of the Verilog code to be detected. When converting the CST expression to LLHD expression, a fourth correspondence between CST nodes and LLHD instructions is described. The defect detection results include the detected defects and the original Verilog code line where the defects are located. Obtaining the original Verilog code line where the defects are located includes: for CST expressions, determining the Verilog code line where the defects are located based on the start and end positions of the CST node where the defects are detected; for LLHD expressions, determining the CST node corresponding to the defects based on the detected defects and the fourth correspondence, and determining the Verilog code line where the defects are located based on the start and end positions of the corresponding CST node; obtaining the original Verilog code line where the defects are located based on the Verilog code line where the defects are located.
2. The defect detection method according to claim 1, characterized in that, The defect detection results include the detected defects and the original Verilog code line where the defects are located.
3. The defect detection method according to claim 1, characterized in that, The step of converting the Verilog code to be detected into CST expression based on the first correspondence includes: Based on the first correspondence, reserved words and structures in the Verilog code to be detected are marked using CST tags / tag groups; Use CST tags / tag groups to identify variables in code blocks within the Verilog code to be tested; Each line in the Verilog code block to be tested is converted into a JSON array of CST representations; where each word in the line corresponds to an element in the JSON array.
4. A Verilog code defect detection system, characterized in that, include: The Verilog code preprocessing module is used to obtain the Verilog code to be detected based on the defect detection requirements and the original Verilog code. Specifically, based on the defect detection requirements, it determines whether the defect to be detected is "cross-clock domain output not registered" and whether the original Verilog code is at the RTL level. If so, the original Verilog code is converted to the netlist level to obtain the Verilog code to be detected; otherwise, the original Verilog code is the Verilog code to be detected. The relation mapping description module is used to describe and store the first correspondence between Verilog reserved words, structures, and variable names and CST tags / tag groups, the second correspondence between Verilog variable names and LLHD variable names, the third correspondence between key-value pairs in CST expressions and LLHD expressions, and the fourth correspondence between CST nodes and LLHD instructions. The CST conversion module is used to convert the Verilog code to be detected into a CST expression based on the first correspondence; the CST expression is a concrete syntax tree in JSON format, including multiple CST nodes; The LLHD conversion module is used to convert the CST expression into an LLHD expression based on the first correspondence, the second correspondence, and the third correspondence. When converting the CST expression into an LLHD expression, for each CST node in the CST expression, the following conversions are performed: Based on the first correspondence, the Verilog statement type corresponding to the CST node is determined; based on the Verilog statement type, the sub-label / sub-label group of the CST node, and the first correspondence, the Verilog variable name corresponding to the CST node is determined; based on the Verilog variable name and the second correspondence, the LLHD variable name corresponding to the CST node is determined; based on the expression information in the CST node and the third correspondence, the LLHD expression and latency information corresponding to the expression in the CST node are determined; based on the LLHD variable name, the LLHD expression, and the latency information, the CST node is converted into an LLHD instruction to obtain the LLHD expression corresponding to the CST node. A defect detection module is used to perform defect detection on the CST expression and / or the LLHD expression based on defect detection requirements and the fourth correspondence, as well as the defect detection function corresponding to the CST expression and / or LLHD expression, to obtain defect detection results; when converting the CST expression to an LLHD expression, it describes the fourth correspondence between CST nodes and LLHD instructions; the defect detection results include the detected defects and the original Verilog code line where the defects are located. Obtaining the original Verilog code line where the defects are located includes: for CST expressions, determining the Verilog code line to be detected based on the start and end positions of the CST node where the defects are detected; for LLHD expressions, determining the CST node corresponding to the defects based on the detected defects and the fourth correspondence, and determining the Verilog code line to be detected based on the start and end positions of the corresponding CST node; and obtaining the original Verilog code line where the defects are located based on the Verilog code line to be detected.
5. The defect detection system according to claim 4, characterized in that, The fourth correspondence is obtained by converting the CST expression into an LLHD expression.
6. The defect detection system according to claim 5, characterized in that, The defect detection requirements include the type and name of the defect to be detected.