Memory system and control method of memory system

Abstract

A memory system capable of determining which data is lost and a control method of the memory system. A controller of the memory system writes data received from a host to a first write target block in response to a write command specifying a logical address received from the host. The controller manages a first list containing a plurality of logical addresses corresponding to write-pending data for which a write to the first write target block is received from the host and completed and a first storage position information indicating a storage position of a beginning of a write-pending area in the first write target block in which the write of the data is pending. The controller writes the first list and the first storage position information to a nonvolatile memory using power from a capacitor in the event of a power failure without a notice from the host.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-041509 (filed on March 16, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a memory system for controlling non-volatile memory and a method for controlling the memory system. Background Technology

[0004] In recent years, memory systems with non-volatile memory have become widely used. As one type of such memory system, solid-state drives (SSDs) with NAND flash memory are known.

[0005] In storage systems like SSDs, there are situations where power-loss protection features (sometimes called PLP) are used to handle unexpected power outages.

[0006] The power failure protection function uses the power stored in the capacitor to write incomplete data stored in the register to the non-volatile memory.

[0007] However, the amount of data that can be written to non-volatile memory using the power stored in the capacitor is limited to a certain upper limit. Therefore, if a large amount of data is written without completion, there is a possibility that some of this incomplete data will be lost. Summary of the Invention

[0008] One embodiment of the present invention aims to solve the problem of providing a memory system capable of determining which data is lost, and a control method for the memory system.

[0009] According to one embodiment, a memory system capable of connecting to a host includes a non-volatile memory comprising multiple blocks and a controller. The controller, in response to receiving a write command from the host at a specified logical address, writes data received from the host into a first write target block allocated from the multiple blocks. The controller manages a first list and first storage location information. The first list contains multiple logical addresses corresponding to incomplete write data received from the host but not yet written to the first write target block. The first storage location information indicates the storage location at the beginning of the incomplete write region of data within the first write target block. In the event of a power outage where power to the memory system is cut off without prior notice from the host, the controller uses power from a capacitor storing power supplied to the memory system to write the first list and the first storage location information into the non-volatile memory. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an example configuration of an information processing system that includes a memory system with an implementation method.

[0011] Figure 2 This is a block diagram illustrating an example of the configuration of a NAND flash memory die included in a memory system according to an embodiment.

[0012] Figure 3 This is a diagram illustrating an example of the configuration of blocks of NAND flash memory included in a memory system according to an embodiment.

[0013] Figure 4 This is a block diagram illustrating an example of the relationship between multiple channels and multiple NAND flash memory dies used in a memory system implemented in an embodiment.

[0014] Figure 5 This is a diagram illustrating an example of the configuration of a superblock used in a memory system in an implementation, and an example of the relationship between each of the multiple storage locations contained in the superblock and each of the multiple offsets.

[0015] Figure 6 This diagram illustrates an example of a write operation and power-loss protection (PLP) operation performed on a target block in a memory system of an implementation.

[0016] Figure 7 This is a diagram illustrating an example of the relationship between write target blocks and logical addresses (LBA lists) managed in a memory system of an implementation.

[0017] Figure 8 This is another example of the relationship between write target blocks and LBA lists managed in the memory system of the implementation.

[0018] Figure 9 This is a diagram illustrating an example of the configuration of a ring cache used to maintain an LBA list in a memory system according to an implementation.

[0019] Figure 10 This is a flowchart illustrating the steps of a data writing operation performed in the memory system of the implementation method.

[0020] Figure 11 This is a flowchart illustrating the steps of a PLP operation performed in the memory system of the implementation method.

[0021] Figure 12 This is a flowchart illustrating the steps of an LBA notification action performed in the memory system of the implementation.

[0022] Figure 13 This is a flowchart illustrating the steps of a data readout operation performed in the memory system of the implementation method.

[0023] Explanation of reference numerals in the attached figures

[0024] 1…Information processing system, 2…Host, 3…Memory system, 4…Bus, 5…Controller, 6…Non-volatile memory, 7…DRAM, 8…Power supply circuit, 21…Processor, 22…Memory, 50…Internal bus, 51…Host interface, 52…CPU, 53…SRAM, 54…DMAC, 55…ECC circuit, 56…DRAM interface, 57…NAND interface, 71…L2P table, 72…Block management table, 81…Capacitor, 531…Internal cache Detailed Implementation

[0025] The embodiments will now be described with reference to the accompanying drawings.

[0026] Figure 1 This is a block diagram illustrating a configuration example of the information processing system 1, which includes the memory system 3 of the embodiment. The memory system 3 of the embodiment is a storage device that includes non-volatile memory 6.

[0027] The information processing system 1 includes a host (host device) 2 and a memory system 3. The host 2 and the memory system 3 can be connected via a bus 4.

[0028] Host 2 is an information processing device. Host 2 is, for example, a personal computer or a server computer. Host 2 accesses memory system 3. Specifically, host 2 sends commands to memory system 3 to write data, i.e., write commands. In addition, host 2 sends commands to memory system 3 to read data, i.e., read commands.

[0029] The memory system 3 is a semiconductor storage device. For example, the memory system 3 is a solid-state drive (SSD). The memory system 3 includes non-volatile memory 6. The memory system 3 writes data to the non-volatile memory 6. Furthermore, the memory system 3 reads data from the non-volatile memory 6.

[0030] Bus 4, for example, is based on PCI Express. TM (PCIe TM Bus 4 is a standard bus. It connects host 2 and memory system 3. Bus 4 is used for sending data and input / output (I / O) commands from host 2 to memory system 3, and for sending data and responses from memory system 3 to host 2. I / O commands are used to write or read data from non-volatile memory 6. I / O commands include write commands and read commands.

[0031] Next, the internal structure of host 2 will be described. Host 2 includes a processor 21 and a memory 22.

[0032] Processor 21 is, for example, a CPU (Central Processing Unit). Processor 21 communicates with memory system 3 via bus 4. Processor 21 executes software (host software) loaded into memory 22 from memory system 3 or other storage devices connected to host 2. Host software includes an operating system, file system, device drivers, or application programs.

[0033] Memory 22 is, for example, volatile memory. Memory 22 is, for example, dynamic random access memory (DRAM).

[0034] Next, the internal structure of the memory system 3 will be described. The memory system 3 includes a controller 5 and non-volatile memory 6. An example of non-volatile memory 6 is NAND flash memory. Hereinafter, non-volatile memory 6 will be referred to as NAND memory 6.

[0035] Controller 5 is a memory controller. Controller 5 is, for example, a semiconductor device such as a System-on-a-Chip (SoC). Controller 5 is electrically connected to NAND flash memory 6. Controller 5 performs data writing and reading from NAND flash memory 6. Furthermore, controller 5 communicates with host 2 via bus 4. The physical interface connecting controller 5 and NAND flash memory 6 may use, for example, a Toggle NAND flash interface or an Open NAND Flash Interface (ONFI). The functions of each part of controller 5 can be implemented through dedicated hardware, a processor executing programs, or a combination thereof.

[0036] NAND memory 6 can be, for example, a two-dimensional or three-dimensional flash memory. NAND memory 6 contains multiple blocks. Each block is the smallest unit for erasing data stored in NAND memory 6; in other words, it is the unit of data erasure.

[0037] In addition to the controller 5 and the non-volatile memory 6, the memory system 3 may also include dynamic random access memory (DRAM) 7. DRAM 7 is volatile memory. A portion of the storage area of ​​DRAM 7 may also be used, for example, as an internal cache 73 to temporarily hold write data received from the host 2 or read data read from the NAND memory 6.

[0038] The memory system 3 also includes a power supply circuit 8. The power supply circuit 8 is a power control circuit. For example, the power supply circuit 8 supplies power from the host 2 to each component of the memory system 3, such as the controller 5, the NAND memory 6, and the DRAM 7.

[0039] Next, the internal structure of controller 5 will be described. Controller 5 includes a host interface (host I / F) 51, a CPU 52, static RAM (SRAM) 53, a direct memory access controller (DMAC) 54, an ECC (Error Checking and Correction) circuit 55, a DRAM interface (DRAM I / F) 56, and a NAND interface (NAND I / F) 57. These components within controller 5 are interconnected via an internal bus 50. Power is also supplied to this internal bus 50 from the power supply circuit 8.

[0040] Host interface 51 is a hardware interface circuit. Host interface 51 performs communication with host 2. Host interface 51, for example, receives I / O commands from host 2. In addition, host interface 51 sends responses to host 2 for the received I / O commands.

[0041] CPU 52 is the processor. CPU 52 controls host interface 51, SRAM 53, DMAC 54, ECC circuit 55, DRAM interface 56, and NAND interface 57. CPU 52 loads the control program (firmware) stored in NAND memory 6 or ROM (not shown) into SRAM 53 and performs various processes by executing the firmware. Alternatively, the firmware can also be loaded into DRAM 7.

[0042] CPU 52, for example, acts as a Flash Translation Layer (FTL) to manage the data stored in NAND memory 6 and the blocks contained in NAND memory 6. The management of the data stored in NAND memory 6 includes, for example, the management of mapping information representing the correspondence between logical addresses and physical addresses. A logical address is an address used by host 2 to access NAND memory 6. A logical address is, for example, an LBA (Logical Block Address). A physical address is an address representing the physical storage location contained in NAND memory 6. CPU 52 uses a Logical-to-Physical Translation Table (L2P table) 71 to manage the mapping between logical addresses and physical addresses. Furthermore, the management of blocks contained in NAND memory 6 includes, for example, garbage collection, management of bad blocks, and wear leveling. CPU 52 uses a block management table 72 to perform the management of blocks contained in NAND memory 6.

[0043] SRAM 53 is a volatile memory. SRAM 53 is used, for example, as a working area of ​​CPU 52. In addition, SRAM 53 includes an internal cache 531. The internal cache 531 is a storage area that temporarily holds data associated with write commands received from host 2.

[0044] DMAC 54 is a circuit that performs direct memory access (DMA). DMAC 54 performs data transfers between host 2's memory 22 and DRAM 7 or SRAM 53.

[0045] ECC circuit 55 is a circuit that performs data encoding and decoding. When writing data to NAND memory 6, ECC circuit 55 performs encoding processing. In encoding processing, ECC circuit 55 appends ECC parity check as a redundancy code to the data to be written. ECC circuit 55 uses the ECC parity check appended to the data read from NAND memory 6 to perform decoding processing. In decoding processing, ECC circuit 55 corrects errors in the read data.

[0046] DRAM interface 56 is the circuitry that controls DRAM 7. DRAM interface 56 stores data into DRAM 7. In addition, DRAM interface 56 reads data stored in DRAM 7.

[0047] NAND interface 57 is a circuit that controls NAND memory 6. NAND interface 57 includes, for example, NAND controllers 571-0, 571-1, 571-2, ..., 571-31. Each NAND controller 571-0, 571-1, 571-2, ..., 571-31 is connected to one or more flash memory dies contained in NAND memory 6 via one of the corresponding channels ch0, ch1, ch2, ..., ch31. Flash memory dies are also called flash memory chips. NAND controllers 571-0, 571-1, 571-2, ..., 571-31 control, for example, flash memory dies (#0) 61-0, flash memory dies (#1) 61-1, ..., flash memory dies (#31) 61-31 contained in NAND memory 6.

[0048] Next, the information stored in DRAM 7 will be explained. The information stored in DRAM 7 includes L2P table 71 and block management table 72. Some or all of L2P table 71 and block management table 72 may also be stored in SRAM 53 instead of DRAM 7.

[0049] L2P table 71 manages the mapping between logical addresses and physical addresses using a sector-like unit of size.

[0050] Block management table 72 manages the blocks contained in the NAND memory 6. For example, block management table 72 manages whether each block is usable. Furthermore, block management table 72 can also manage whether each block is subject to power failure protection.

[0051] The memory system 3 also includes a capacitor 81. The capacitor 81 is a component capable of storing electrical energy. The capacitor 81 is electrically connected to the power supply circuit 8. When the power supply voltage supplied from the host 2 decreases without warning from the host 2, the power supply circuit 8 supplies the electrical energy stored in the capacitor 81 to the various components of the memory system 3. The electrical energy stored in the capacitor 81 can, for example, be used by the controller 5 to perform an LBA list saving operation.

[0052] Next, the LBA list saving operation performed by controller 5 will be explained. The LBA list saving operation is performed to identify data lost due to unexpected power outages. An unexpected power outage is the phenomenon of power supply to the memory system 3 being cut off without prior notice from host 2 (power cut-off warning notification). The power cut-off warning notification is a notification that power supply to the memory system 3 is about to be disconnected. Before powering off host 2, host 2 sends a power cut-off warning notification to memory system 3, informing memory system 3 that power supply to memory system 3 is about to be disconnected. The power cut-off warning notification can be, for example, a Shutdown Notification as defined by the NVMe standard, or a STANDBYIMMEDIATE command as defined by the SATA standard.

[0053] Controller 5 receives a write command from host 2 for writing data to NAND memory 6. The write command specifies the start logical address (start LBA), data size, and data pointer. The start LBA represents the logical address at which the write data associated with the write command should be written; in other words, it is the initial logical block where the write data should be written. The data size indicates the size of the write data. The data size can be represented, for example, by the number of LBAs. The data pointer is a cached address representing the location on memory 22 of host 2 where the write data is stored. The write command may also include an identifier specifying the target region. The identifier specifying the target region may be, for example, a logical address specifying a region defined by the zoned namespace standard, a namespace identifier identifying the namespace, or a stream identifier identifying the stream.

[0054] Controller 5, in response to a write command receiving a specified LBA (Start LBA) from host 2, executes a data write operation on NAND memory 6. During the data write operation, controller 5 writes the write data received from host 2 to a write target block allocated from among multiple blocks contained in NAND memory 6. That is, controller 5 selects a block from among the multiple blocks contained in NAND memory 6, and assigns the selected block as the write target block. The write target block is the block where data should be written. The write target block is, for example, a superblock. Alternatively, the write target block can also be a physical block. Controller 5 can also be simultaneously assigned multiple write target blocks corresponding to different regions. The LBA list saving operation will be explained below with regard to a single write target block.

[0055] Controller 5 manages the LBA list corresponding to the write target block. The LBA list contains multiple LBAs corresponding to incomplete write data received from host 2 but not yet written to the write target block. Writing data to the write target block is performed from the beginning to the end of the write target block. Therefore, a write target block in progress includes write-complete areas, write-incomplete areas, and data-unclaimed areas. The write-complete area is the area where the host has completed receiving the data to be written and the writing to the write target block is complete. The data stored in the write-complete area is readable data. The write-incomplete area is the area where the host 2 has completed receiving the data to be written and the writing to the write target block is incomplete (the area where the incomplete write data should have been written). If the data to be written has been received and the write-complete data to the write target block does not exist, then all areas specified by host 2 corresponding to the write target of the data become write-incomplete areas. The data-unclaimed area is the area where the data to be written has not yet been received from host 2, but will be written if received. Furthermore, receiving data from host 2 is also called receiving data from host 2. Furthermore, data that has not yet been received from host 2 is referred to as unreceived data or data not received, while data that has been received from host 2 is referred to as data received or data received.

[0056] In the event of a power outage without prior notice from host 2, or in other words, an unexpected power outage, the lost data corresponds to the data in the incomplete write area. Therefore, controller 5 uses an LBA list to manage multiple LBAs, each corresponding to data to be written to the incomplete write area, i.e., incomplete write data. Specifically, the LBA list contains a set of remaining LBAs, obtained by removing the sets of LBAs corresponding to data received from host 2 and written to the target block, excluding the sets of LBAs corresponding to data that can be read from the target block after the write to the target block is complete. Here, the data received from host 2 and written to the target block includes complete write data (received from host 2 and written to the target block) and incomplete write data (received from host 2 and written to the target block but not yet completed).

[0057] Furthermore, controller 5 manages location information representing the storage location at the beginning of the incomplete write region. This location information is represented by the block address of the target block and the offset within the target block. The offset represents the distance between the storage location at the beginning of the incomplete write region and the storage location at the beginning of the target block.

[0058] In the event of an unexpected power outage, controller 5 uses power from capacitor 81 to write the LBA list, rather than writing incomplete data, to NAND memory 6. Specifically, controller 5 uses power from capacitor 81 to write the LBA list, along with location information indicating the beginning of the incomplete write area, to NAND memory 6.

[0059] Thus, by writing the LBA list to the NAND memory 6, it is possible to definitively identify data lost due to an unexpected power outage. The size of the LBA list is sufficiently small compared to the size of the incomplete data to be written. Therefore, the LBA list can be written to the NAND memory 6 within a limited time using the power of capacitor 81.

[0060] Furthermore, by writing location information indicating the beginning of an incomplete write region to the NAND memory 6, it is possible to determine the memory location where the write was interrupted due to an unexpected power outage.

[0061] After power is restored to memory system 3, controller 5 can perform recovery processing using the saved LBA list and location information. For example, controller 5 can also perform the process of reporting the LBA corresponding to the lost data to host 2. In addition, controller 5 can also perform the process of setting the memory location where the write was interrupted as an error location.

[0062] Next, an example of the configuration of the flash memory die 61 contained in the NAND memory 6 will be described. Figure 2 This is a block diagram illustrating an example of the configuration of the flash memory die 61 of the NAND memory 6 included in the memory system 3 of the first embodiment.

[0063] Here, we focus on flash memory die (#0) 61-0 to describe the structure of flash memory die 61. Other flash memory dies also have the same structure as flash memory die (#0) 61-0. Flash memory die (#0) 61-0 includes peripheral circuitry 611-0 and a memory cell array 612-0.

[0064] Peripheral circuitry 611-0 controls the memory cell array 612-0. Peripheral circuitry 611-0 includes, for example, row decoders, column decoders, sense amplifiers, latch circuits, and voltage generation circuits. In response to addresses and commands received from the NAND controller 571-0, peripheral circuitry 611-0 performs programming, reading, or erasing operations on the memory cell array 612-0.

[0065] The memory cell array 612-0 contains multiple planes. A structure with multiple planes is called a multiplane structure. The memory cell array 612-0 enables multiple planes (here, PLANE#0 and PLANE#1) to operate in parallel.

[0066] The plane of memory cell array 612-0 contains multiple blocks (BLK0, BLK1, BLK2, ...). A block BLK is a collection of non-volatile memory cell transistors (hereinafter referred to simply as memory cell transistors or memory cells). Each block contains multiple string units (SU0, SU1, SU2, SU3). Each string unit SU is a collection of memory cell transistors. Each string unit SU contains multiple NAND strings NS (also simply referred to as strings). Each NAND string NS is a collection of memory cell transistors.

[0067] exist Figure 2 The example illustrates the case where each block contains four string units SU0, SU1, SU2, and SU3. However, the number of string units SU in each block can be either three or less, or more than five. Alternatively, a structure can be used where each block contains only one string unit SU. That is, each block contains more than one string unit SU.

[0068] Next, we will explain the composition of a block. Figure 3 This is a diagram illustrating an example of the configuration of blocks of the NAND memory 6 included in the memory system 3 of the embodiment.

[0069] exist Figure 3 This section focuses on describing the structure of block BLK0. Other blocks have the same structure as block BLK0. Block BLK0 contains four string units (SU0, SU1, SU2, SU3). The four string units (SU0, SU1, SU2, SU3) are arranged in a horizontal direction orthogonal to the stacking direction (vertical direction) of the multiple word lines WL0 to WL7. Each string unit SU contains multiple NAND strings NS. One end of each NAND string NS is connected to the corresponding bit line among the multiple bit lines (BL0 to BL(L-1)). Each NAND string NS extends vertically. The control gates of the multiple memory cell transistors contained in each NAND string NS are respectively connected to the multiple word lines (WL0, WL1, ..., WL7).

[0070] Next, the relationship between the multiple channels and the multiple flash memory dies 61 will be explained. Figure 4 This is a diagram illustrating an example of the relationship between multiple channels ch.0, ch.1, ..., ch.31 and multiple flash memory dies 61 (61-0, 61-1, ..., 61-31) used in the memory system 3 of the embodiment.

[0071] exist Figure 4 In this structure, each of the 32 flash memory dies 61 has a multi-plane structure comprising two planes (PLANE#0 and PLANE#1). Each plane contains multiple blocks BLK0 to BLKx-1. Each block BLK0 to BLKx-1 contains multiple word lines. Each word line is connected to four memory cell groups corresponding to four serial units (SU0, SU1, SU2, SU3). Each block BLK0 to BLKx-1 is the unit for data erasure operations. Blocks BLK0 to BLKx-1 are also referred to as physical blocks, physical memory blocks, erasure blocks, or flash memory blocks, respectively.

[0072] Each of the 32 flash memory dies 61 can operate in parallel. Moreover, within each flash memory die 61, two planes can operate in parallel.

[0073] To execute data write operations on multiple physical blocks in parallel, controller 5 manages multiple block groups. A block group consists of multiple physical blocks capable of performing parallel operations. Hereinafter, the block group will be referred to as a superblock.

[0074] Next, we will explain the construction example of a superblock. Figure 5 This is a diagram illustrating an example of the configuration of a superblock in the memory system 3 of the implementation method, and an example of the relationship between each of the multiple storage locations contained in the superblock and each of the multiple offsets.

[0075] Here, we envision the case where a superblock SB0 is constructed from block BLK0 of plane #0 (PLANE#0) and block BLK0 of plane #1 (PLANE#1) contained in any flash memory die 61.

[0076] Each block contains four string units (SU0, SU1, SU2, and SU3). Furthermore, each string unit is connected to multiple word lines (WL0, WL1, ...).

[0077] When writing data to the superblock SB0 using a four-level cell storage (QLC) model where each storage cell stores 4 bits of data, data corresponding to four pages (lower, middle, upper, and higher) is written to a group of storage cells connected to a word line and contained within a string of cells. A page is, for example, 16KB in size. A page contains multiple sectors. For example, with a sector size of 4KB, a page contains four sectors. Therefore, the group of storage cells connected to a word line and contained within a string of cells contains 16 storage locations corresponding to 16 sectors.

[0078] Hereinafter, the group of memory cells connected to the word line WLn and contained in the string cell SUM (hereinafter referred to as MG) will be denoted as MG(WLn, SUm).

[0079] The physical address of a storage location x in superblock SB0 is represented by the block address of superblock SB0 and the offset of storage location x relative to the beginning of the block. The offset is represented by a multiple of the sector.

[0080] The offset of each storage location is set based on the order in which data is written to each sector.

[0081] Controller 5 first performs the write of four pages (lower, middle, upper, and higher) of data for the MG (WL0, SU0) of block BLK0 in plane #0, and then performs the write of four pages (lower, middle, upper, and higher) of data for the MG (WL0, SU0) of block BLK0 in plane #1. The MG (WL0, SU0) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1 contain a total of 32 storage locations (=4 sectors × QLC (four pages) × 2 planes). Therefore, a total of 32 offsets (+0 to +31) are set for the MG (WL0, SU0) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1. For example, in the MG (WL0, SU0) of block BLK0 in plane #0, offsets can be set for the four sectors of the lower page (+0 to +3), for the four sectors of the middle page (+4 to +7), for the four sectors of the upper page (+8 to +11), and for the four sectors of the higher page (+12 to +15). Furthermore, in the MG (WL0, SU0) of block BLK0 in plane #1, offsets can be set for the four sectors of the lower page (+16 to +19), for the four sectors of the middle page (+20 to +23), for the four sectors of the upper page (+24 to +27), and for the four sectors of the higher page (+28 to +31).

[0082] Next, controller 5 performs the writing of four pages of data to the MG (WL0, SU1) of block BLK0 in plane #0, and the writing of four pages of data to the MG (WL0, SU1) of block BLK0 in plane #1. Therefore, a total of 32 offsets (+32 to +63) are set for the MG (WL0, SU1) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1. For example, in the MG (WL0, SU1) of block BLK0 in plane #0, offsets (+32 to +35) can be set for the four sectors of the lower page, offsets (+36 to +39) can be set for the four sectors of the middle page, offsets (+40 to +43) can be set for the four sectors of the upper page, and offsets (+44 to +47) can be set for the four sectors of the higher page. Furthermore, in the MG (WL0, SU1) of block BLK0 in plane #1, the offsets (+48 to +51) can be set for the 4 sectors of the lower page, the offsets (+52 to +55) can be set for the 4 sectors of the middle page, the offsets (+56 to +59) can be set for the 4 sectors of the upper page, and the offsets (+60 to +69) can be set for the 4 sectors of the higher page.

[0083] Next, controller 5 performs the writing of four pages of data to the MG (WL0, SU2) of block BLK0 in plane #0, and the writing of four pages of data to the MG (WL0, SU2) of block BLK0 in plane #1. Therefore, a total of 32 offsets (+64 to +95) are set for the MG (WL0, SU2) of block BLK0 in plane #0 and the MG (WL0, SU2) of block BLK0 in plane #1. For example, in the MG (WL0, SU2) of block BLK0 in plane #0, offsets (+64 to +67) can be set for the four sectors of the lower page, offsets (+68 to +71) can be set for the four sectors of the middle page, offsets (+72 to +75) can be set for the four sectors of the upper page, and offsets (+76 to +79) can be set for the four sectors of the higher page. Furthermore, in the MG (WL0, SU2) of block BLK0 in plane #1, the offsets (+80 to +83) can be set for the 4 sectors of the lower page, the offsets (+84 to +87) can be set for the 4 sectors of the middle page, the offsets (+88 to +91) can be set for the 4 sectors of the upper page, and the offsets (+92 to +95) can be set for the 4 sectors of the higher page.

[0084] Next, controller 5 performs the writing of four pages of data to the MG (WL0, SU3) of block BLK0 in plane #0, and the writing of four pages of data to the MG (WL0, SU3) of block BLK0 in plane #1. Therefore, a total of 32 offsets (+96 to +127) are set for the MG (WL0, SU3) of block BLK0 in plane #0 and the MG (WL0, SU3) of block BLK0 in plane #1. For example, in the MG (WL0, SU3) of block BLK0 in plane #0, offsets (+96 to +99) can be set for the four sectors of the lower page, offsets (+100 to +71) can be set for the four sectors of the middle page, offsets (+72 to +103) can be set for the four sectors of the upper page, and offsets (+104 to +107) can be set for the four sectors of the higher page. Furthermore, in the MG (WL0, SU3) of block BLK0 in plane #1, the offsets (+112 to +115) can be set for the 4 sectors of the lower page, the offsets (+116 to +119) can be set for the 4 sectors of the middle page, the offsets (+120 to +123) can be set for the 4 sectors of the upper page, and the offsets (+124 to +127) can be set for the 4 sectors of the higher page.

[0085] Next, controller 5 performs a four-page data write to the MG (WL1, SU0) of block BLK0 in plane #0 and a four-page data write to the MG (WL1, SU0) of block BLK0 in plane #1. Therefore, a total of 32 offsets (+128 to +159) are set for the MG (WL1, SU0) of block BLK0 in plane #0 and the MG (WL1, SU0) of block BLK0 in plane #1.

[0086] Next, the programming operations in multiple stages will be explained. When writing data via QLC mode, the controller 5 uses multiple stages of programming operations, including at least a first stage and a second stage, to perform data writing operations for multiple memory cell groups contained in the target block. In the first stage of programming, four pages of data to be written are transferred to the NAND memory 6, and these four pages of data are written to the memory cell group MG(WLn, SUm) of the target block. In the first stage of programming, the threshold voltage of each memory cell is roughly set. In this state, data cannot be read normally from each memory cell. In the second stage of programming, the same four pages of data transferred in the first stage of programming are transferred to the NAND memory 6 again, and these four pages of data are written to the memory cell group MG(WLn, SUm) for which the first stage of programming has been performed. In the second stage of programming, the threshold voltage of each memory cell is set to the target threshold voltage corresponding to the data to be written. If the second stage of programming is completed, data can be correctly read from the memory cell group MG(WLn, SUm).

[0087] The second-stage programming action for memory cell group MG(WLn, SUm) is performed after the first-stage programming action for another memory cell group MG(WL(n+1), SUm) that belongs to the same string cell SUm as memory cell group MG(WLn, SUm) and is connected to the word line WL(n+1) after the word line WLn connected to memory cell group MG(WLn, SUm).

[0088] Programming actions can be performed in multiple stages, such as fuzzy-fine programming. Fuzzy-fine programming includes fuzzy programming and fine programming. Fuzzy programming is the first-stage programming action, which roughly sets the threshold voltage of each memory cell. Fine programming is the second-stage programming action, which adjusts the threshold voltage of each memory cell and sets it to the target threshold voltage.

[0089] The fuzzy-fine programming action for writing to the target block is performed as follows. Hereinafter, we assume that controller 5 will... Figure 5 The superblock SB0 shown is allocated as a write target block.

[0090] (1) First, perform fuzzy programming operations for MG (WL0, SU0) of block BLK0 in plane #0 and MG (WL0, SU0) of block BLK0 in plane #1. Here, write data of eight pages in size is transferred to NAND memory 6. The page size is equivalent to the number of strings contained in a string unit SU, that is, the number of memory units contained in a memory unit group MG.

[0091] (2) Next, perform fuzzy programming operations for MG (WL0, SU1) of block BLK0 in plane #0 and MG (WL0, SU1) of block BLK0 in plane #1.

[0092] (3) Next, perform fuzzy programming operations for MG (WL0, SU2) of block BLK0 in plane #0 and MG (WL0, SU2) of block BLK0 in plane #1.

[0093] (4) Next, perform fuzzy programming operations for MG (WL0, SU3) of block BLK0 in plane #0 and MG (WL0, SU3) of block BLK0 in plane #1.

[0094] (5) After the fuzzy programming actions for MG(WL0, SU0) to MG(WL0, SU3) of block BLK0 in plane #0 and MG(WL0, SU0) to MG(WL0, SU3) of block BLK0 in plane #1 are completed, the fuzzy programming actions for MG(WL1, SU0) of block BLK0 in plane #0 and MG(WL1, SU0) of block BLK0 in plane #1 are executed.

[0095] (6) After completing the fuzzy programming operations for the MG (WL1, SU0) of block BLK0 in plane #0 and the MG (WL1, SU0) of block BLK0 in plane #1, fine programming operations are performed for the MG (WL0, SU0) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1. Here, the same write data used in the fuzzy programming operations for the MG (WL0, SU0) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1 is transferred to the NAND memory 6 again. Moreover, fine programming operations for the MG (WL0, SU0) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1 are performed. If the fine-tuning operation is completed, the writing to the MG (WL0, SU0) of block BLK0 in plane #0 and the MG (WL0, SU0) of block BLK0 in plane #1 is completed. That is, the data written to the MG (WL0, SU0) of block BLK0 in plane #0 and the data written to the MG (WL0, SU0) of block BLK0 in plane #1 become readable data that can be read normally from the NAND memory 6.

[0096] (7) Next, perform fuzzy programming operations for MG (WL1, SU1) of block BLK0 in plane #0 and MG (WL1, SU1) of block BLK0 in plane #1.

[0097] (8) After the fuzzy programming operations for the MG (WL1, SU1) of block BLK0 in plane #0 and the MG (WL1, SU1) of block BLK0 in plane #1 are completed, the fine programming operations for the MG (WL0, SU1) of block BLK0 in plane #0 and the MG (WL0, SU1) of block BLK0 in plane #1 are performed. If the fine programming operation is completed, the writing to the MG (WL0, SU1) of block BLK0 in plane #0 and the MG (WL0, SU1) of block BLK0 in plane #1 is completed. That is, the data written to the MG (WL0, SU1) of block BLK0 in plane #0 and the data written to the MG (WL0, SU1) of block BLK0 in plane #1 become readable data that can be read normally from the NAND memory 6.

[0098] Next, we will explain the write operation and power-loss protection (PLP) operation performed on the target block. Figure 6This is a diagram illustrating an example of a write operation and a PLP operation performed on a target block in memory system 3.

[0099] Controller 5 is capable of performing two PLP actions. One PLP action is to back up the LBA list in the event of an unexpected power outage (first PLP action). The other PLP action is to complete the write of incomplete data to the NAND memory 6 in the event of an unexpected power outage (second PLP action).

[0100] The controller 5 manages a set of first blocks that are controlled to be written through a first mode, and a set of second blocks that complete the writing of incomplete data to the NAND memory 6. The first mode is a mode that backs up a list of LBAs corresponding to the incomplete data that is received from the host 2 and is not yet written to the NAND memory 6.

[0101] Hereinafter, blocks belonging to the set of the second block will be referred to as blocks of the PLP object, and blocks belonging to the set of the first block will be referred to as blocks outside the PLP object.

[0102] exist Figure 6 The example shown illustrates how controller 5 allocates 20 superblocks (SB0-SB19) and one Single-Level Memory Cell (SLC) block as write target blocks. An SLC block is a block for writing data using SLC mode, where each memory cell stores one bit of data. Superblocks SB0-SB14 are blocks for PLP objects. Superblocks SB15-SB19 are blocks outside of PLP objects.

[0103] First, we will explain the case of writing data to blocks of PLP objects, such as superblock SB0.

[0104] (1) Each time a write command is received from host 2, controller 5 stores the data received from host 2 in internal cache 531. Controller 5 waits until the amount of data to be written is stored in internal cache 531. In the case of writing data to superblock SB0 via QLC mode when the page size is 4 sectors (=16KB), the write size is 32 sectors (=4 sectors × 2 planes × 4 (QLC)). Controller 5 waits until the amount of data to be written to superblock SB0 (32 sectors) is accumulated in internal cache 531.

[0105] (2-a) After the 32 sectors of data written to superblock SB0 are accumulated in the internal buffer 531, the controller 5 performs a fuzzy programming operation to write 32 sectors of data to superblock SB0. For example, four pages (=16 sectors) of data are written to the MG(WL0, SU0) of block #0 of superblock SB0. In addition, four pages (=16 sectors) of data are written to the MG(WL0, SU0) of block #1 of superblock SB0. The fine programming operation for the MG(WL0, SU0) of block #0 can be performed after the fuzzy programming operation for the MG(WL0, SU1) to MG(WL0, SU3) and MG(WL1, SU0) of block #0 is performed. Similarly, the fine-grained programming operations for MG(WL0, SU0) of block #1 can also be performed after the fuzzy programming operations for MG(WL1, SU0) to MG(WL0, SU3), and MG(WL1, SU0) of block #1 are executed. Therefore, if a write to superblock SB0 is performed, a total of 160 sectors (= 4 sectors × 2 planes × 4 (QLC) × 5 string units) of data during the write operation to superblock SB0 is maintained in internal buffer 531.

[0106] (3-a) In the event of an unexpected power outage during the write process, the controller 5 uses power from the capacitor 81 to write the incomplete write data to the NAND memory 6 from the superblock SB0. The incomplete write data can be written to either the superblock SB0 or ​​to a single-level cell (SLC) block of the NAND memory 6. An SLC block is a block of data written in SLC mode, where one bit of data is stored in each cell.

[0107] The following describes the case of writing data to blocks outside the PLP object, such as superblock SB15. An LBA list is allocated for superblock SB15.

[0108] (1) Each time a write command is received from host 2, controller 5 stores the data received from host 2 in internal buffer 531.

[0109] (2-b) Each time data written to superblock SB15 is stored in internal cache 531, controller 5 appends the set of LBAs corresponding to the data stored in internal cache 531 to the LBA list corresponding to superblock SB15. Furthermore, controller 5 manages the association between the location information (superblock address SBA, offset) indicating the beginning of the unfinished write region of superblock SB15 and the LBA list. Controller 5 waits until 32 sectors of data written to superblock SB15 are accumulated in internal cache 531.

[0110] (3-b) After the 32 sectors of data written to superblock SB15 are accumulated in internal buffer 531, controller 5 performs a fuzzy programming operation to write 32 sectors of data to superblock SB15. For example, four pages (=16 sectors) of data are written to the MG (WL0, SU0) of block #0 in superblock SB15. In addition, four pages (=16 sectors) of data are written to the MG (WL0, SU0) of block #1 in superblock SB15. Fine programming operations for the MG (WL0, SU0) of block #0 can be performed after the fuzzy programming operations for MG (WL0, SU1) to MG (WL0, SU3) and MG (WL1, SU0) of block #0 are performed. Similarly, the fine-grained programming operations for the MG (WL0, SU0) of block #1 can also be performed after the fuzzy programming operations for MG (WL1, SU0) to MG (WL0, SU3) and MG (WL1, SU0) of block #1. Therefore, if a write to superblock SB15 is performed, a total of 160 sectors (4 sectors × 2 planes × 4 (QLC) × 5 string units) of data being written to superblock SB15 are maintained in the internal buffer 531. Furthermore, the 160 LBAs corresponding to each of the 160 sectors are sets of LBAs corresponding to the data being written to superblock SB15. These 160 LBAs are maintained in the LBA list corresponding to superblock SB15. In addition, the LBA list corresponding to superblock SB15 also maintains LBAs corresponding to data received from host 2 that has been completed but for which writing to superblock SB15 has not yet begun. With a write size of 32 sectors for superblock SB15, the maximum size of data that has been received but not yet written is 32 sectors. Therefore, the maximum number of LBAs in the LBA list corresponding to superblock SB15 is 192 (=4 sectors × 2 planes × 4 (QLC) × (5 string units + 1)).

[0111] (4-b) In the event of an unexpected power outage during the write process, the controller 5 uses power from the capacitor 81 to write to the NAND memory 6 the set of LBAs contained in the LBA list corresponding to the superblock SB15, and the location information (superblock address SBA, offset) indicating the beginning of the unfinished write region of the superblock SB15. The set of LBAs and the location information can also be written to the SLC blocks of the NAND memory 6.

[0112] Next, the relationship between the target block and the logical address (LBA list) will be explained. Figure 7 This is a diagram illustrating an example of the relationship between write target blocks and logical addresses (LBA lists) managed in the memory system 3 of the implementation method.

[0113] When a superblock outside a PLP object is assigned as a write target block, an LBA list is allocated to the superblock.

[0114] The LBA list is used to maintain multiple LBAs corresponding to each of the data that has been received from host 2 and is still pending when written to the superblock.

[0115] The superblock contains a "Write Incomplete" area and a "Write Data Not Received / Not Written" area. The "Write Incomplete" area is the area where incomplete write data received from host 2 and destined for the superblock should be written.

[0116] The “Write incomplete” area includes the “Write data received completed / Write in progress” area and the “Write data received completed / Not written” area.

[0117] The "Write Data Received Complete / Write in Progress" area is the region where the write operation is in progress. With a page size of 4 sectors, when writing data to the superblock using fuzzy-fine programming and QLC mode, the size of the "Write Data Received Complete / Write in Progress" area is 160 sectors (=4 sectors × 2 planes × 4 (QLC) × 5 string cells).

[0118] The "Write Data Received Complete / Not Written Area" is the area where write data has been received from host 2 but writing has not yet begun. With a page size of 4 sectors, when writing data to the superblock via QLC mode using fuzzy-fine programming, the maximum size of the "Write Data Received Complete / Not Written Area" is 32 sectors (=4 sectors × 2 planes × 4 (QLC)).

[0119] Therefore, the size of the "written incomplete" area is 192 sectors (=4 sectors × 2 planes × 4 (QLC) × (5 string cells + 1)).

[0120] Furthermore, when writing data to the superblock using full sequence programming actions in TLC mode, three pages of data are written to the memory cell group to complete the write of three pages of data. Therefore, the size of the "Write Data Receipt Complete / Write in Progress" area is 24 sectors (= 4 sectors × 2 planes × 3 (TLC) × 1 string cell). Additionally, the maximum size of the "Write Data Receipt Complete / Not Written Area" is 24 sectors (= 4 sectors × 2 planes × 3 (TLC)).

[0121] Therefore, the size of the "written incomplete" area is 48 sectors (=4 sectors × 2 planes × 4 (QLC) × (1 string cell + 1)).

[0122] The following scenario envisions writing data to a superblock using fuzzy-fine programming actions via QLC mode.

[0123] The 160 LBAs (LBA#0~#31, LBA#32~#63, LBA#64~#95, LBA#96~#127, LBA#128~#159) contained in the LBA list are the LBAs corresponding to the incomplete write data received from host 2 but not yet written to the superblock.

[0124] For example, the initial 32 LBAs #0 to #31 are the LBAs corresponding to the data written to the 32 storage locations of the superblock corresponding to offsets #0 to #31. Offsets #0 to #31 are... Figure 5 The offsets +0 to +31 in the description indicate the storage locations.

[0125] The 32 LBAs following LBAs #0 to #31, and LBAs #32 to #63, are the LBAs corresponding to the data written to the 32 storage locations of the superblock corresponding to offsets #32 to #63. Offsets #32 to #63 are... Figure 5 The offset of +32 to +63 indicates the storage location.

[0126] The 32 LBAs following LBAs #32 to #63, and LBAs #64 to #95, are the LBAs corresponding to the data written to the 32 storage locations of the superblock corresponding to offsets #64 to #95. Offsets #64 to #95 are... Figure 5 The offset of +64 to +95 indicates the storage location.

[0127] The 32 LBAs following LBAs #64 to #95, and LBAs #96 to #127, are the LBAs corresponding to the data written to the 32 storage locations of the superblock corresponding to offsets #96 to #127. Offsets #96 to #127 are... Figure 5 The offset of +96 to +127 indicates the storage location.

[0128] The 32 LBAs following LBAs #96 to #127, LBAs #128 to #159, are the LBAs corresponding to the data written to the 32 storage locations of the superblock corresponding to offsets #128 to #159. Offsets #128 to #159 are... Figure 5 The offset of +128 to +159 in the description indicates the storage location.

[0129] Furthermore, after the data written to the "Write Data Receipt Completed / Unwritten Area" is stored in the internal buffer 531, the LBAs (e.g., LBA#160~#n) corresponding to the stored data are appended to the LBA list. At this time, offsets #160~#n can also be appended to the LBA list along with LBA#160~#n.

[0130] Thus, in the LBA list, the LBAs (LBA#0~#159, #160~#n) corresponding to the incomplete write data are arranged in the same order as the order in which the incomplete write data was written to the incomplete write region; in other words, they are arranged in the same order as the offsets #0~#159, #160~#n. Furthermore, the LBA list can retain not only LBA#0~#159, #160~#n, but also offsets #0~#159, #160~#n.

[0131] The LBA list is managed by two pointers, P1 and P2. Pointer P1 indicates the position of the next LBA to be deleted or retrieved from the LBA list. Pointer P2 indicates the position to store the new LBA.

[0132] In addition, Figure 7 In the code, the location information indicating the beginning of the incomplete region is represented by the superblock address SBA and offset #0.

[0133] Figure 8 This is another example of the relationship between write target blocks and logical addresses (LBA lists) managed in the memory system 3 of the implementation.

[0134] exist Figure 8 The example shows the situation where the writing of 32 sectors of data corresponding to LBA#0 to #31 is completed and the 32 sectors of data can be read.

[0135] The first 32 storage locations of the superblock are designated as the "Write Complete / Readable" area. This area stores data that has been written successfully and can be read from the superblock. If 32 sectors of data can be read, the 32 LBAs #0 to #31 corresponding to the readable data are removed from the LBA list. This ensures an empty area in the LBA list for storing the new 32 LBAs. Additionally, the location information indicating the beginning of the incomplete write area is used to advance the write size (32 sectors).

[0136] exist Figure 8 In the LBA list, 160 LBAs #32 to #191 are maintained as LBAs corresponding to the data being written to the "Write Data Complete / Write in Progress" area.

[0137] In addition, after the data written to the “Write Data Receipt Completed / Not Written Area” is stored in the internal cache 531, the LBAs (e.g., LBA#192 to #m) corresponding to the stored data are appended to the LBA list.

[0138] In the event of an unexpected power outage while the LBA list contains LBA#32~#191 and LBA#192~#m, LBA#32~#191 and LBA#192~#m, along with location information (super block address SBA, offset #32) indicating the beginning of the incomplete writing region, are written to NAND memory 6.

[0139] Furthermore, after the entire superblock's data has been written, the entire superblock becomes a "write complete / readable" area. In this case, the LBA list is empty. Moreover, controller 5 releases the allocation of the LBA list for that superblock. The LBA list released from the superblock's allocation is then allocated to the newly allocated superblock for the target block being written.

[0140] Next, the results of the ring buffer will be explained. Figure 9 This is a diagram illustrating an example of the configuration of a circular buffer used to maintain an LBA list.

[0141] A circular buffer contains multiple entries, for example, 192 entries. Each entry in the circular buffer represents a region that holds an LBA (Level 1 Entrance). Pointer P1 represents the entry that stores the next LBA that has been deleted or retrieved from the circular buffer. Pointer P1 is also called the head pointer. Pointer P2 represents the pointer used to store the next entry in the new LBA. Pointer P2 is also called the tail pointer.

[0142] exist Figure 9 In (A), LBA is stored in items #0 to #q, which are indicated by pointers P1 to P2.

[0143] If new data is received from host 2 and written to the superblock, then as follows Figure 9 As shown in (B), the LBAs corresponding to the received data are appended to the circular buffer. The value of pointer P2 is incremented by the number of appended LBAs. Figure 9 In (B), LBA is stored in items #0 to #r, which are indicated by pointer P1 to the incremented pointer P2.

[0144] After the fine-grained programming of the data corresponding to the 32 LBAs corresponding to items #0 to #31 is completed, as follows: Figure 9 As shown in (C), the value of pointer P1 is incremented and updated to 32. Therefore, since items #0 to #31 are freed, 32 LBAs are removed from the circular buffer. Figure 9 In (C), LBA is stored in items #32 to #s, which are indicated by the incremented pointers P1 to P2. At this time, pointer P2 is also updated.

[0145] If the value of pointer P2 is incremented by 1 to become 192, then the value of pointer P2 is reset to zero. Therefore, LBAs can be appended to the empty entries at the beginning of the circular buffer. Figure 9 (D) illustrates the situation after appending an LBA to the empty entry at the beginning of such a circular buffer. Figure 9 In (D), pointer P1 represents item #32, and pointer P2 represents the state of item #t (<32). Thus, in Figure 9 In (D), LBA is stored in items #32 to #191 and items #0 to #t respectively.

[0146] Next, the order of data writing actions will be explained. Figure 10 This is a flowchart showing the sequence of data write operations performed in the memory system 3 of the embodiment.

[0147] Controller 5 determines whether it has received a write command from host 2 (S101).

[0148] If no write command is received (No in S101), controller 5 waits until a write command is received.

[0149] Upon receiving a write command (Yes in S101), controller 5 receives write data from host 2 (S102). Controller 5 stores the received data in internal buffer 531.

[0150] The controller 5 determines whether the target block for writing the received write data is a PLP object (S103).

[0151] If the target block to be written is a PLP object (yes in S103), the controller 5 determines whether the written data has reached the write size (S104). For example, the write size is the data size of 32 sectors.

[0152] If the amount of data written has not reached the write size (no in S104), the controller 5 waits until it receives a subsequent write command (returns to S101).

[0153] If the amount of data written reaches the write size (yes in S104), the controller 5 performs a write operation to write the write size of the write data to the NAND memory 6 (S105).

[0154] Then, controller 5 ends the data writing operation (end).

[0155] If the target block to be written is not a PLP object (not in S103), controller 5 appends the LBA specified by the received write command and the offset corresponding to the storage location where the write data is written to the LBA list (S106). Controller 5 selects the LBA list corresponding to the target block to be written. Furthermore, controller 5 appends the LBA and the offset to the selected LBA list. In addition, controller 5 increments the pointer P2 of the LBA list based on the appended LBAs.

[0156] Controller 5 determines whether the written data has reached the write size (S107).

[0157] If the amount of data written has not reached the write size (no in S107), the controller 5 waits until it receives a subsequent write command (returns to S101).

[0158] If the amount of data written reaches the write size (yes in S107), the controller 5 performs a write operation to write the write size of the write data to the NAND memory 6 (S108).

[0159] Controller 5 determines whether there is data that can be read through the write operation performed in S108 (S109). Controller 5 determines whether a fuzzy write operation was performed in the write operation in S108.

[0160] If no data can be read (no in S109), controller 5 ends the data writing operation (end).

[0161] If readable data exists (yes in S109), controller 5 removes the LBA corresponding to the readable data from the LBA list and updates the storage location information corresponding to the LBA list (S110). Controller 5 increments the pointer P1 of the LBA list corresponding to the write target block.

[0162] Then, controller 5 ends the data writing operation (end).

[0163] Next, the steps of the PLP operation will be explained. Figure 11 This is a flowchart illustrating the steps of the PLP operation performed in the memory system 3 of the embodiment.

[0164] Controller 5 determines whether an unexpected power outage has occurred (S201). Controller 5 determines whether the power supply to the memory system 3 was cut off without notification from the host 2.

[0165] If no unexpected power outage occurs (no in S201), controller 5 waits.

[0166] In the event of an unexpected power outage (Yes in S201), the controller 5 selects an arbitrary block from the write target block (S202).

[0167] Controller 5 determines whether the selected block is a PLP object (S203).

[0168] If the selected block is not a PLP object (not in S203), the controller 5 writes the LBA list and position information (SBA, offset) into the SLC block (S204). The controller 5 makes the data non-volatile by writing the information stored in the LBA list corresponding to the selected block and the position information into the SLC block.

[0169] Controller 5 determines whether to select to write all target blocks (S205).

[0170] If there are write target blocks that have not yet been selected (no in S205), controller 5 selects any block from the unselected write target blocks (S202).

[0171] If the selected block is a PLP object (yes in S203), the controller 5 completes the writing of the incomplete data corresponding to the selected block (S206). For example, the controller 5 sets the selected block to a closed state by writing the incomplete data and virtual data to the selected block. In addition, the controller 5 can also write the incomplete data to the SLC block.

[0172] Then, controller 5 determines whether to select to write all target blocks (S205).

[0173] If all target blocks are selected to be written (yes in S205), controller 5 ends the PLP action (end).

[0174] Next, the steps for the LBA notification action will be explained. Figure 12 This is a flowchart illustrating the steps of the LBA notification action performed in the memory system 3 of the embodiment.

[0175] If power is restored to memory system 3 (yes in S301), controller 5 determines whether LBA list information exists in the SLC block (S302).

[0176] If LBA list information exists in the SLC block (yes in S302), controller 5 updates L2P table 71 (S303). Controller 5 stores an error value in the L2P table 71 corresponding to the LBA contained in the LBA list information. The error value can be, for example, a magic number representing an invalid physical address (PBA).

[0177] Controller 5 notifies host 2 of the LBA list information (S304). Controller 5 responds to a command received from host 2 to retrieve the log of memory system 3, providing host 2 with the LBA list information. Alternatively, controller 5 may perform the step of notifying host 2 of the LBA list information before executing step S303.

[0178] Then, controller 5 ends the LBA notification action (end).

[0179] Furthermore, if the LBA list information is not present in the SLC block (not in S302), the controller 5 terminates the LBA notification action (end).

[0180] Next, the steps for the data reading process will be explained. Figure 13 This is a flowchart illustrating the steps of a data readout operation performed in the memory system 3 of the embodiment.

[0181] Controller 5 determines whether it has received a read command from host 2 (S401).

[0182] If no read command is received (no in S401), controller 5 waits until a read command is received.

[0183] Upon receiving a read command (yes in S401), controller 5 determines whether the read object LBA corresponds to an invalid PBA (S402). Controller 5 obtains the PBA corresponding to the LBA specified in the read command by referring to L2P table 71. Controller 5 then determines whether the obtained PBA is an invalid value.

[0184] If the read object LBA corresponds to an invalid PBA (yes in S402), the controller 5 notifies the host 2 of an error (S403). In response to the received read command, the controller 5 sends an error notification to the host 2.

[0185] Then, controller 5 ends the reading action (end).

[0186] If the read object LBA does not correspond to an invalid PBA (no in S402), the controller 5 performs a read operation (S404). The controller 5 reads the data stored in the storage location represented by the PBA corresponding to the read object LBA.

[0187] The controller 5 sends the read data to the host 2 (S405).

[0188] Then, controller 5 ends the reading action (end).

[0189] As explained above, according to this embodiment, the controller 5 uses power from the capacitor 81 to write an LBA list containing sets of LBAs corresponding to incomplete write data, and location information indicating the beginning of the incomplete write region, to the NAND memory 6. Thus, by writing the LBA list to the NAND memory 6, data lost due to unexpected power outages can be definitively identified.

[0190] Therefore, even if incomplete data is lost due to an unexpected power outage, the controller 5 can still provide the host 2 with LBA information corresponding to the lost data.

[0191] Furthermore, by writing location information indicating the beginning of an incomplete write region to the NAND memory 6, it is possible to determine the memory location where the write was interrupted due to an unexpected power outage.

[0192] Furthermore, by establishing a correspondence between the LBA corresponding to the lost data and an invalid PBA (magic number), the controller 5 can notify of errors even when it receives a read command specifying that LBA. This prevents the controller 5 from reading erroneous data and sending it to the host 2.

[0193] While several embodiments of the invention have been described, these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A memory system capable of connecting to a host computer, characterized in that, have: Non-volatile memory, containing multiple blocks; as well as The controller, in response to receiving a write command for a specified logical address from the host, writes data received from the host into a first write target block allocated from the plurality of blocks. The controller manages a first list and first storage location information. The first list contains multiple logical addresses corresponding to incomplete write data that has been received from the host but has not yet been written to the first write target block. The first storage location information indicates the storage location at the beginning of the incomplete write region in the first write target block where the data has not yet been written. In the event of a power outage in which power to the memory system is cut off without prior notice from the host, the controller uses power from a capacitor that stores power supplied to the memory system to write the first list and the first storage location information to the non-volatile memory.

2. The memory system as claimed in claim 1, wherein, The first list includes a set of remaining logical addresses, excluding the set of logical addresses corresponding to data that has been received from the host and should be written to the first write target block, and the set of logical addresses corresponding to data that has been written to the first write target block and can be read from the first write target block.

3. The memory system as claimed in claim 1, wherein, The plurality of logical addresses contained in the first list are arranged in the same order as the order in which the incomplete write data was written to the incomplete write region.

4. The memory system of claim 1, wherein, The controller is further configured to provide the host with the first list stored in the non-volatile memory as information representing data lost due to the power outage after power is restored to the memory system.

5. The memory system of claim 1, wherein, The controller is further configured as follows: A logical-to-physical address translation table is used to manage the mapping between the logical addresses used by the host to access the memory system and the physical addresses of the non-volatile memory. After power is restored to the memory system, based on the first list stored in the non-volatile memory, values ​​representing errors are stored in the entries of the logical-physical address translation table corresponding to each of the plurality of logical addresses contained in the first list.

6. The memory system of claim 1, wherein, The controller is further configured to manage a set of first blocks controlled for writing via a first mode and a set of second blocks controlled for writing via a second mode. The first mode is a mode that, in the event of a power outage, backs up a list of logical addresses corresponding to incomplete write data received from the host but whose write to the non-volatile memory is incomplete. The second mode is a mode that, in the event of a power outage, completes the write of the incomplete write data to the non-volatile memory.

7. The memory system of claim 1, wherein, The first storage location information includes the block address of the first write target block and the offset of the storage location of the beginning of the incomplete writing area relative to the storage location of the beginning of the first write target block.

8. The memory system of claim 1, wherein, The first target block to be written is a block group containing multiple physical blocks.

9. A memory system capable of connecting to a host computer, characterized in that, have: Non-volatile memory, containing multiple blocks; A capacitor, which stores the power supplied to the memory system; and The controller is electrically connected to the non-volatile memory and controls the non-volatile memory. The controller is configured as follows: One of the plurality of blocks is assigned as the first write target block; Each time a write command for a specified logical address is received from the host, the data associated with the write command is stored in an internal cache. The set of logical addresses corresponding to the data stored in the internal cache is appended to a first list, which is a list for maintaining multiple logical addresses corresponding to the incomplete write data received from the host and not yet written to the first write target block. Each time the size of the unwritten data stored in the internal cache reaches the write size of the non-volatile memory, data with the write size is written to the first write target block; If the amount of data to be written can be read from the first write target block, the set of logical addresses corresponding to the data that can be read is deleted from the first list, and the storage position represented by the first storage position information is advanced by the amount of the write size in a manner that the storage position represented by the first storage position information is represented by the first storage position information at the beginning of the incomplete write area of ​​the first write target block. In the event of a power outage in which power to the memory system is disconnected without prior notice from the host, the power from the capacitor is used to write the first list and the first storage location information to the non-volatile memory.

10. The memory system of claim 9, wherein, The plurality of logical addresses contained in the first list are arranged in the same order as the order in which the incomplete write data was written to the incomplete write region.

11. The memory system of claim 9, wherein, The controller is further configured to provide the host with the first list stored in the non-volatile memory as information representing data lost due to the power outage after power is restored to the memory system.

12. The memory system of claim 9, wherein, The controller is further configured as follows: A logical-to-physical address translation table is used to manage the mapping between the logical addresses used by the host to access the memory system and the physical addresses of the non-volatile memory. After power is restored to the memory system, based on the first list stored in the non-volatile memory, values ​​representing errors are stored in the entries of the logical-physical address translation table corresponding to each of the plurality of logical addresses contained in the first list.

13. The memory system of claim 9, wherein, The controller is further configured to manage a set of first blocks controlled for writing via a first mode and a set of second blocks controlled for writing via a second mode. The first mode is a mode that, in the event of a power outage, backs up a list of logical addresses corresponding to incomplete write data received from the host but whose write to the non-volatile memory is incomplete. The second mode is a mode that, in the event of a power outage, completes the write of the incomplete write data to the non-volatile memory.

14. The memory system of claim 9, wherein, The first storage location information includes the block address of the first write target block and the offset of the storage location of the beginning of the incomplete writing area relative to the storage location of the beginning of the first write target block.

15. A method for controlling a memory system, comprising a memory system including a non-volatile memory containing multiple blocks, characterized in that, include: One of the plurality of blocks is assigned as the first write target block; Each time a write command for a specified logical address is received from the host, the data associated with the write command is stored in the internal cache of the memory system; The set of logical addresses corresponding to the data stored in the internal cache is appended to a first list, which is a list for maintaining multiple logical addresses corresponding to the incomplete write data received from the host and not yet written to the first write target block. Each time the size of the unwritten data stored in the internal cache reaches the write size of the non-volatile memory, data with the write size is written to the first write target block; If the amount of data to be written can be read from the first write target block, the set of logical addresses corresponding to the data that can be read is deleted from the first list, and the storage position represented by the first storage position information is advanced by the amount of the write size in a manner that the storage position represented by the first storage position information is represented by the first storage position information at the beginning of the incomplete write area of ​​the first write target block. In the event of a power outage in which power to the memory system is cut off without prior notice from the host, the first list and the first storage location information are written to the non-volatile memory using power from the capacitor that stores power supplied to the memory system.

16. The control method for a memory system as described in claim 15, wherein, The plurality of logical addresses contained in the first list are arranged in the same order as the order in which the incomplete write data was written to the incomplete write region.

17. The control method for a memory system as described in claim 15, wherein, Also includes: After power is restored to the memory system, the host is provided with the first list stored in the non-volatile memory as information representing the data lost due to the power outage.

18. The control method for a memory system as described in claim 15, wherein, Also includes: A logical-to-physical address translation table is used to manage the mapping between the logical addresses used by the host to access the memory system and the physical addresses of the non-volatile memory. After power is restored to the memory system, based on the first list stored in the non-volatile memory, values ​​representing errors are stored in the entries of the logical-physical address translation table corresponding to each of the plurality of logical addresses contained in the first list.

19. The control method for a memory system as described in claim 15, wherein, Also includes: The management controls the writing of a set of first blocks through a first mode and the writing of a set of second blocks through a second mode. The first mode is a mode that backs up a list of logical addresses corresponding to incomplete write data received from the host but not yet written to the non-volatile memory in the event of a power outage. The second mode is a mode that completes the writing of the incomplete write data to the non-volatile memory in the event of a power outage.

20. The control method for a memory system as described in claim 15, wherein, The first storage location information includes the block address of the first write target block and the offset of the storage location of the beginning of the incomplete writing area relative to the storage location of the beginning of the first write target block.

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