A method and system for handling digital-to-analog interface windings in a multi-voltage domain SoC chip

Abstract

This invention provides a method and system for handling analog-to-digital interface winding in a multi-voltage domain SoC chip. First, the winding list of analog circuits in the chip is obtained based on the chip's packaging information, and the chip layout is determined. Then, based on the positions and connections of the output pins of multiple IPs in the winding list and the output pins of multiple IOs in the layout, the positions of the IP output pins are automatically adjusted to be closer to the IO output pins. Next, the correct output pin names are determined, and the signal line names are obtained. The analog-to-digital interface type of the signal lines is automatically determined. Multiple voltage domains are divided into multiple winding regions based on the analog-to-digital interface type and the voltage value of the voltage domain. Finally, winding parameters are set for the signal lines in each winding region based on the current in the winding list. Then, the winding of the signal lines in each winding region is automatically completed based on the winding region and the winding parameters, avoiding mutual interference between signals, ensuring signal integrity, and saving winding resources.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and specifically to a method and system for handling the winding of digital-to-analog interfaces in a multi-voltage domain SoC chip. Background Technology

[0002] In multi-voltage domain SoC chips, the routing of digital-to-analog interfaces needs to consider requirements such as line width, spacing, whether isolation is required, and avoiding crossing different voltage regions.

[0003] Currently, existing EDA tools only differentiate between clock and general signal winding during the routing process. They lack specific settings for windings with special requirements, necessitating the writing of custom scripts. Furthermore, they don't actively distinguish between analog and digital windings; they simply use common winding rules from the tech lef file to wind them together. This not only fails to meet the wire width requirements of some signals but also causes interference between digital and analog signals, affecting signal transmission rate and even signal integrity.

[0004] Existing winding processes have some drawbacks. They cannot automatically distinguish between different signals, resulting in messy winding that can cause digital and analog signals to interfere with each other, affecting signal transmission rate and even integrity. Summary of the Invention

[0005] To address the problems of mutual interference between digital and analog signals in existing winding processes, which affects signal transmission rate and integrity, this invention provides a winding processing method for digital-to-analog interfaces in multi-voltage domain SoC chips. Based on the winding list of analog circuits in the SoC chip and the chip layout plan, specific methods such as position adjustment, region division, and parameter setting are used to extract analog signal windings separately and process them first, avoiding mutual interference between signals and ensuring signal integrity. This invention also relates to a winding processing system for digital-to-analog interfaces in multi-voltage domain SoC chips.

[0006] The technical solution of the present invention is as follows:

[0007] A method for handling the digital-to-analog interface winding in a multi-voltage domain SoC chip, characterized by comprising the following steps:

[0008] Parameter acquisition steps: Obtain the winding list of analog circuits in the multi-voltage domain SoC chip based on the packaging information of the multi-voltage domain SoC chip, and determine the chip layout plan;

[0009] Position adjustment steps: Based on the position and connection relationship between the output pins of multiple IPs in the routing list and the output pins of multiple IOs in the layout plan, automatically adjust the position of the IP output pins to be closer to the IO output pins;

[0010] The area division steps are as follows: The system automatically determines whether the name of each output pin is correct. If it is incorrect, an error is reported, and the system continues to determine whether the name of the next output pin is correct until the name of an output pin is found to be correct. Then, the system obtains the name of the signal line used to connect the IP output pin and the IO output pin, and automatically determines the digital-to-analog interface type of the signal line. Based on the digital-to-analog interface type of the signal line and the voltage value of the voltage domain, the system divides multiple voltage domains to obtain multiple winding areas.

[0011] Parameter setting and winding steps: Set the winding parameters for the signal lines in each winding area according to the current in the winding list, and then automatically complete the winding of the signal lines in each winding area according to each winding area and the winding parameters.

[0012] Preferably, the region division step, which involves dividing multiple voltage domains, includes:

[0013] Determine whether the digital-to-analog interface type of the signal line is a digital signal line or an analog signal line. If the digital-to-analog interface type of the signal line is a digital signal line, then divide each voltage domain according to the voltage value of the voltage domain. If the voltage value of a certain voltage domain is the first value, then divide the voltage domain into the first winding region. If the voltage value of a certain voltage domain is the second value, then divide the voltage domain into the second winding region.

[0014] If the digital-to-analog interface type of the signal line is an analog signal line, then the voltage domains are divided according to the voltage values ​​of the voltage domains. If the voltage value of a certain voltage domain is the third value, then the voltage domain is divided into the third winding region. If the voltage value of a certain voltage domain is the fourth value, then the voltage domain is divided into the fourth winding region.

[0015] Preferably, in the parameter setting and winding steps, the winding parameters include the winding width and the winding distance.

[0016] Preferably, in the parameter setting and winding steps, setting winding parameters for the signal lines in each winding region includes:

[0017] Based on the current value in the voltage domain, the winding width and winding distance of the signal lines in each winding region are set. If the current value is a first current value, the winding width and winding distance of the signal lines in each winding region are set to a first width and a first distance, respectively. If the current value is a second current value, the winding width and winding distance of the signal lines in each winding region are set to a second width and a second distance, respectively.

[0018] Preferably, in the parameter setting and winding steps, it is also determined whether to add a shielding mesh to each signal line based on the winding width and winding distance. If the winding width of a certain signal line is greater than or equal to a preset width threshold and the winding distance is greater than or equal to a preset distance threshold, then a shielding mesh is added to that signal line.

[0019] A winding processing system for digital-to-analog interface in a multi-voltage domain SoC chip, characterized in that it includes a parameter acquisition module, a position adjustment module, a region division module, and a parameter setting and winding module connected in sequence.

[0020] The parameter acquisition module obtains the winding list of analog circuits in the multi-voltage domain SoC chip based on the packaging information of the multi-voltage domain SoC chip, and determines the chip layout plan.

[0021] The position adjustment module automatically adjusts the position of the IP output pins to be closer to the IO output pins based on the position and connection relationship between the output pins of multiple IPs in the winding list and the output pins of multiple IOs in the layout plan.

[0022] The region division module automatically determines whether the name of each output pin is correct. If it is incorrect, an error is reported, and the module continues to determine whether the name of the next output pin is correct until the name of an output pin is determined to be correct. Then, it obtains the name of the signal line used to connect the IP output pin and the IO output pin, and automatically determines the digital-to-analog interface type of the signal line. Based on the digital-to-analog interface type of the signal line and the voltage value of the voltage domain, it divides multiple voltage domains to obtain multiple winding regions.

[0023] The parameter setting and winding module sets the winding parameters for the signal lines in each winding area according to the current in the winding list, and then automatically completes the winding of the signal lines in each winding area based on the winding area and the winding parameters.

[0024] Preferably, in the region division module, dividing multiple voltage domains includes:

[0025] Determine whether the digital-to-analog interface type of the signal line is a digital signal line or an analog signal line. If the digital-to-analog interface type of the signal line is a digital signal line, then divide each voltage domain according to the voltage value of the voltage domain. If the voltage value of a certain voltage domain is the first value, then divide the voltage domain into the first winding region. If the voltage value of a certain voltage domain is the second value, then divide the voltage domain into the second winding region.

[0026] If the digital-to-analog interface type of the signal line is an analog signal line, then the voltage domains are divided according to the voltage values ​​of the voltage domains. If the voltage value of a certain voltage domain is the third value, then the voltage domain is divided into the third winding region. If the voltage value of a certain voltage domain is the fourth value, then the voltage domain is divided into the fourth winding region.

[0027] Preferably, the winding parameters include winding width and winding distance.

[0028] Preferably, in the parameter setting and winding module, setting winding parameters for the signal lines in each winding region includes:

[0029] Based on the current value in the voltage domain, the winding width and winding distance of the signal lines in each winding region are set. If the current value is a first current value, the winding width and winding distance of the signal lines in each winding region are set to a first width and a first distance, respectively. If the current value is a second current value, the winding width and winding distance of the signal lines in each winding region are set to a second width and a second distance, respectively.

[0030] Preferably, in the parameter setting and winding module, it is also determined whether to add a shielding mesh to each signal line based on the winding width and winding distance. If the winding width of a certain signal line is greater than or equal to a preset width threshold and the winding distance is greater than or equal to a preset distance threshold, then a shielding mesh is added to that signal line.

[0031] The beneficial effects of this invention are as follows:

[0032] This invention provides a method for handling the analog-to-digital interface routing in a multi-voltage domain SoC chip. Based on the routing list of analog circuits and the chip layout plan in the multi-voltage domain SoC chip, and according to the position and connection relationship between the output pins of multiple IPs in the routing list and the output pins of multiple IOs in the layout plan, the method automatically adjusts the position of the IP output pins to be closer to the IO output pins. This allows for closer routing, saves routing resources, reduces signal transmission distance, and minimizes interference from surrounding signals during transmission. Furthermore, the method automatically checks whether the names of each output pin are correct; if incorrect, an error is reported, and the method continues to check the next output pin. The process involves verifying the correctness of each output pin's name until a correct name is found. Then, the names of the signal lines connecting the IP and IO output pins are retrieved, and the analog-to-digital interface type of the signal lines is automatically determined. Based on the analog-to-digital interface type and voltage values, multiple voltage domains are divided into multiple winding regions, preventing interference between windings from different voltage domains. Finally, winding parameters are set for the signal lines in each winding region based on the current in the winding list. Then, the winding of the signal lines in each winding region is automatically completed based on the winding region and its parameters. This invention extracts analog signal windings separately for priority processing, separating analog and digital signal windings. This avoids mutual interference between signals, ensures signal integrity, saves winding resources, and prevents excessive DRC (Digital Control Circle) errors.

[0033] This invention also relates to a digital-to-analog interface routing processing system in a multi-voltage domain SoC chip. This system corresponds to the aforementioned shortest path planning method and can be understood as a system that implements the aforementioned shortest path planning method. It includes a parameter acquisition module, a position adjustment module, a region division module, and a parameter setting and routing module connected in sequence. Each module works in concert with the others. Based on the routing list of analog circuits in the SoC chip and the chip layout plan, specific methods such as position adjustment, region division, and parameter setting are used to extract the analog signal routing separately and process it first, avoiding mutual interference between signals and ensuring signal integrity. Attached Figure Description

[0034] Figure 1 This is a flowchart of the digital-to-analog interface winding processing method in the multi-voltage domain SoC chip of the present invention.

[0035] Figure 2 This is a schematic diagram of the layout planning and winding area of ​​the present invention.

[0036] Figure 3 This is a preferred flowchart of the digital-to-analog interface winding processing method in the multi-voltage domain SoC chip of the present invention.

[0037] Figure 4This is a schematic diagram showing the connection relationship between the IP output pins and the IO output pins of this invention.

[0038] Figure 5 This is a schematic diagram of the winding effect of the present invention. Detailed Implementation

[0039] The present invention will now be described with reference to the accompanying drawings.

[0040] This invention relates to a method for handling the winding of digital-to-analog interfaces in a multi-voltage domain SoC chip. The flowchart of this method is shown below. Figure 1 As shown, the steps are as follows:

[0041] I. Data Acquisition Steps: Based on the package information of the multi-voltage domain SoC chip, obtain the routing list of analog circuits in the multi-voltage domain SoC chip and determine the chip layout plan. Specifically, firstly, obtain the routing list of analog circuits in the multi-voltage domain SoC chip based on the package information, defining a pin routing information constraint. Then, determine the chip layout plan (floorplan) based on the package information of the multi-voltage domain SoC chip. The output pin routings of the analog circuits are categorized and organized into routing lists, as shown in Table 1.

[0042] Table 1

[0043]

[0044]

[0045] In this context, net refers to the signal line, digital / analog refers to the digital or analog signal line, voltage refers to voltage, electric current refers to current, and shielding net refers to the shielding mesh.

[0046] Position adjustment steps: Based on the positions and connections between the output pins of multiple IPs in the routing list and the output pins of multiple IOs in the layout plan, the positions of the IP output pins are automatically adjusted to be closer to the IO output pins. In other words, the positions of the IP output pins are adjusted according to the floorplan and constraints (the positions and connections between pins in the routing list, as well as digital / analog, voltage, and other information).

[0047] Specifically, such as Figure 2As shown, first, the output pins of IP and IO in the routing list are captured, selected, and highlighted (hi ​​light). Then, using jumpers, the positions and connections between the IP and IO pins are checked. The positions of the IP's output pins are adjusted to be as close as possible to the output pins of the related IO. That is, when the number of IP output pins and the number of IO output pins connected to them are the same, the positions of the IP's output pins can be set to correspond one-to-one with the positions of the IO's output pins, and the shortest straight-line distance between the IP's output pins and the IO's output pins should be less than a preset first distance threshold, for example, less than 50µm. For example, if the IP's output pins C1, C2, C3, C4, and C5 are connected to the IO's output pins I23, I24, I25, I26, and I27 respectively, adjusting the positions of C1, C2, C3, C4, and C5 to correspond to the positions of the output pins I23, I24, I25, I26, and I27 respectively, this allows for closer routing, saves routing resources, and reduces the signal transmission distance.

[0048] When there are many IO output pins connected to the IP output pin and their locations are scattered, place the IP output pin at the position with the largest number of associated IO output pins, and ensure that the shortest straight-line distance between the IP output pin and the IO output pin is less than a preset second distance threshold, for example, less than 60µm. Figure 2 As shown, the IO output pins related to IP output pins D1, D2, D3, D4, and D5 are located at the bottom and bottom right corners, i.e. Figure 2 Among the I1, I2, I3, I4, I5, I12, I13, and I14 pins, since the number of I1, I2, I3, I4, and I5 located at the bottom of the diagram is the largest, placing the IP output pins D1, D2, D3, D4, and D5 at the bottom of the diagram can reduce the signal transmission distance and reduce excessive interference from surrounding signals during transmission.

[0049] Furthermore, due to chip design requirements, IP output pins B1, B2, and B3 need to be connected to IO output pins I28, I38, and I0 respectively during packaging; therefore, they are placed in... Figure 2 The position shown is on the left.

[0050] The region division process involves automatically checking the names of each output pin. If an incorrect name is found, an error is reported, and the process continues checking the name of the next output pin until a correct name is found. Then, the names of the signal lines used to connect the IP and IO output pins are obtained, and the analog-to-digital interface type of the signal lines is automatically determined. Based on the analog-to-digital interface type and the voltage value of the voltage domain, multiple voltage domains are divided into multiple winding regions. This method delineates multiple winding regions based on signal lines in different voltage domains, preventing interference between windings from different voltage domains.

[0051] Specifically, such as Figure 3 As shown, the system first automatically checks if the names of multiple output pins (pinname) are correct. If a pinname is incorrect, an error is reported, and the system jumps to the next line to check if the next pin name is correct, until a correct pin name is found. If the pinname is correct, the system retrieves the next element—the net name of the signal line used to connect the IP pin and the IO pin. Then, it determines whether the signal line's digital-to-analog interface type is Digital or Analog. If the signal line's digital-to-analog interface type is Digital, it further divides each voltage domain according to its voltage value (Voltage). If the voltage value of a voltage domain is the first value (1.5V), then that voltage domain is designated as the first winding region (i.e., the winding region is the 1.5V digital region). If the voltage value of a voltage domain is the second value (5V), then that voltage domain is designated as the second winding region (i.e., the winding region is box3, corresponding to 5V). (digital); If the digital-to-analog interface type of the signal line is analog signal line A, then divide each voltage domain according to the voltage value of the voltage domain. If the voltage value of a certain voltage domain is the third value, i.e. 5V, then divide the voltage domain into the third winding area (i.e., the winding area is box1, corresponding to 5V analog). If the voltage value of a certain voltage domain is the fourth value, i.e. 2.5V, then divide the voltage domain into the fourth winding area (i.e., the winding area is box2, corresponding to 2.5V analog).

[0052] Among them, such as Figure 2 As shown, the first group of signal lines, net_group1{NC1 NC2 NC3 NC4 NC5}, has a winding area of ​​box1; the second group of signal lines, net_group2{NB1 NB2 NB3}, has a winding area of ​​box2; and the third group of signal lines, net_group3{ND1 ND2 ND3 ND4 ND5}, has a winding area of ​​box3. The connection relationships between the IP output pins and IO output pins of each winding area are as follows: Figure 4As shown.

[0053] Parameter setting and winding steps: Based on the current in the winding list, set the winding parameters for the signal lines in each winding region. Then, based on preset limiting attributes, each winding region, and the winding parameters, automatically complete the winding of the signal lines in each winding region. Preferably, the winding parameters include winding width and winding distance.

[0054] This means that, based on constraints, scripts automatically set winding parameters: winding width, spacing, and whether to add a shielding net, etc. Alternatively, it can be described as setting the width, spacing, and shielding net based on the digital / analog, voltage, electric current, and shielding net parameters in the winding list. Depending on the signal strength requirements, different signal traces are configured with different winding widths and spacings, and a protective shielding net is added. Specifically, for example... Figure 3 As shown, based on the current value (Electriccurrent) in the voltage domain, the winding width and winding distance of the signal lines in each winding region are set. If the current value is the first current value, i.e., 5mA, then the winding width and winding distance of the signal lines in each winding region are set to the first width and the first distance, respectively; that is, the winding width is set to width = 3um and the winding distance is set to spacing = 1.5um. If the current value is the second current value, i.e., 10mA, then the winding width and winding distance of the signal lines in each winding region are set to the second width and the second distance, respectively; that is, the winding width is set to width = 5um and the winding distance is set to spacing = 1.5um. Furthermore, based on the winding width and winding distance, it is determined whether to add a shielding net (sheildingnet) to each signal line. If the winding width of a signal line is greater than or equal to a preset width threshold and the winding distance is greater than or equal to a preset distance threshold, then a shielding net (sheildingnet) is added to that signal line. The shielding net (sheildingnet) is equal to the grounding wire (VSS). That is:

[0055] First group of signal lines: net_group1{NC1 NC2 NC3 NC4 NC5} / / width 5um, spacing 1.5um, shielding net VSS;

[0056] Second group of signal lines: net_group2{NB1 NB2 NB3} / / width 3um, spacing 1.5um, shielding net VSS;

[0057] The third group of signal lines: net_group3{ND1 ND2 ND3 ND4 ND5} / / width 1um, spacing 1um, shielding net VSS;

[0058] Finally, before winding the analog signal lines, pre-wind them and set limiting properties such as the `fixed` property and `don'ttouch` property to ensure that they will not be affected during subsequent clock and normal signal winding. After completing the signal line winding, the result should look like this: Figure 5 As shown.

[0059] This invention also relates to a digital-to-analog interface winding processing system in a multi-voltage domain SoC chip. This system corresponds to the aforementioned digital-to-analog interface winding processing method in a multi-voltage domain SoC chip, and can be understood as a system implementing the aforementioned method. The system includes a parameter acquisition module, a position adjustment module, a region division module, and a parameter setting and winding module connected sequentially. Specifically,

[0060] The parameter acquisition module obtains the winding list of analog circuits in the multi-voltage domain SoC chip based on the packaging information of the multi-voltage domain SoC chip, and determines the chip layout plan.

[0061] The position adjustment module automatically adjusts the position of the IP output pins to be closer to the IO output pins based on the position and connection relationship between the output pins of multiple IPs in the winding list and the output pins of multiple IOs in the layout plan.

[0062] The region division module automatically determines whether the name of each output pin is correct. If it is incorrect, an error is reported, and the module continues to determine whether the name of the next output pin is correct until the name of an output pin is determined to be correct. Then, it obtains the name of the signal line used to connect the IP output pin and the IO output pin, and automatically determines the digital-to-analog interface type of the signal line. Based on the digital-to-analog interface type of the signal line and the voltage value of the voltage domain, it divides multiple voltage domains to obtain multiple winding regions.

[0063] The parameter setting and winding module sets the winding parameters for the signal lines in each winding area according to the current in the winding list, and then automatically completes the winding of the signal lines in each winding area based on the winding area and the winding parameters.

[0064] Preferably, in the region division module, dividing multiple voltage domains includes:

[0065] Determine whether the digital-to-analog interface type of the signal line is a digital signal line or an analog signal line. If the digital-to-analog interface type of the signal line is a digital signal line, then divide each voltage domain according to the voltage value of the voltage domain. If the voltage value of a certain voltage domain is the first value, then divide the voltage domain into the first winding region. If the voltage value of a certain voltage domain is the second value, then divide the voltage domain into the second winding region.

[0066] If the digital-to-analog interface type of the signal line is an analog signal line, then the voltage domains are divided according to the voltage values ​​of the voltage domains. If the voltage value of a certain voltage domain is the third value, then the voltage domain is divided into the third winding region. If the voltage value of a certain voltage domain is the fourth value, then the voltage domain is divided into the fourth winding region.

[0067] Preferably, the winding parameters include the winding width and the winding distance.

[0068] Preferably, in the parameter setting and winding module, setting winding parameters for the signal lines in each winding region includes:

[0069] Based on the current value in the voltage domain, the winding width and winding distance of the signal lines in each winding region are set. If the current value is a first current value, the winding width and winding distance of the signal lines in each winding region are set to a first width and a first distance, respectively. If the current value is a second current value, the winding width and winding distance of the signal lines in each winding region are set to a second width and a second distance, respectively.

[0070] Preferably, in the parameter setting and winding module, it is also determined whether to add a shielding mesh to each signal line based on the winding width and winding distance. If the winding width of a certain signal line is greater than or equal to a preset width threshold and the winding distance is greater than or equal to a preset distance threshold, then a shielding mesh is added to that signal line.

[0071] This invention provides an objective and scientific method and system for handling analog-to-digital interface windings in multi-voltage domain SoC chips. Based on the winding parameter list of analog circuits in the SoC chip and the chip layout planning, it uses specific methods such as position adjustment, area division, and parameter setting to extract analog signal windings separately for priority processing. This solves the problems of the original winding process not being able to automatically distinguish between them, the windings being messy, and the interference between digital and analog signals, affecting the signal transmission rate and even the integrity. It avoids mutual interference between signals and ensures the integrity of the signal.

[0072] It should be noted that the specific embodiments described above enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although the present invention has been described in detail with reference to the accompanying drawings and embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention. In short, all technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the present invention patent.

Claims

1. A method for handling the winding of digital-to-analog interface in a multi-voltage domain SoC chip, characterized in that, Includes the following steps: Parameter acquisition steps: Obtain the winding list of analog circuits in the multi-voltage domain SoC chip based on the packaging information of the multi-voltage domain SoC chip, and determine the chip layout plan; Position adjustment steps: Based on the position and connection relationship between the output pins of multiple IPs in the routing list and the output pins of multiple IOs in the layout plan, automatically adjust the position of the IP output pins to be closer to the IO output pins; The region division process involves: automatically determining the correctness of each output pin name; if incorrect, an error is reported, and the process continues to check the name of the next output pin until a correct name is found. Then, the names of the signal lines used to connect the IP and IO output pins are obtained, and the digital-to-analog interface type of the signal lines is automatically determined. Based on the digital-to-analog interface type and voltage value of the voltage domain, multiple voltage domains are divided to obtain multiple winding regions. The division of multiple voltage domains includes: Determine whether the digital-to-analog interface type of the signal line is a digital signal line or an analog signal line. If the digital-to-analog interface type of the signal line is a digital signal line, then divide each voltage domain according to the voltage value of the voltage domain. If the voltage value of a certain voltage domain is the first value, then divide the voltage domain into the first winding region. If the voltage value of a certain voltage domain is the second value, then divide the voltage domain into the second winding region. If the digital-to-analog interface type of the signal line is an analog signal line, then the voltage domains are divided according to the voltage values ​​of the voltage domains. If the voltage value of a certain voltage domain is the third value, then the voltage domain is divided into the third winding region. If the voltage value of a certain voltage domain is the fourth value, then the voltage domain is divided into the fourth winding region. Parameter setting and winding steps: Set the winding parameters for the signal lines in each winding area according to the current in the winding list, and then automatically complete the winding of the signal lines in each winding area according to each winding area and the winding parameters.

2. The method for handling digital-to-analog interface windings in a multi-voltage domain SoC chip according to claim 1, characterized in that, In the parameter setting and winding steps, the winding parameters include the winding width and the winding distance.

3. The method for handling digital-to-analog interface windings in a multi-voltage domain SoC chip according to claim 2, characterized in that, In the parameter setting and winding steps, setting winding parameters for the signal lines in each winding region includes: Based on the current value in the voltage domain, the winding width and winding distance of the signal lines in each winding region are set. If the current value is a first current value, the winding width and winding distance of the signal lines in each winding region are set to a first width and a first distance, respectively. If the current value is a second current value, the winding width and winding distance of the signal lines in each winding region are set to a second width and a second distance, respectively.

4. The method for handling digital-to-analog interface windings in a multi-voltage domain SoC chip according to claim 3, characterized in that, In the parameter setting and winding steps, it is also determined whether to add a shielding mesh to each signal line based on the winding width and winding distance. If the winding width of a signal line is greater than or equal to a preset width threshold and the winding distance is greater than or equal to a preset distance threshold, then a shielding mesh is added to that signal line.

5. A digital-to-analog interface winding processing system in a multi-voltage domain SoC chip, characterized in that, It includes a parameter acquisition module, a position adjustment module, a region division module, and a parameter setting and winding module connected in sequence. The parameter acquisition module obtains the winding list of analog circuits in the multi-voltage domain SoC chip based on the packaging information of the multi-voltage domain SoC chip, and determines the chip layout plan. The position adjustment module automatically adjusts the position of the IP output pins to be closer to the IO output pins based on the position and connection relationship between the output pins of multiple IPs in the winding list and the output pins of multiple IOs in the layout plan. The region division module automatically checks the name of each output pin for correctness. If incorrect, it reports an error and continues checking the name of the next output pin until a correct name is found. Then, it retrieves the name of the signal line used to connect the IP output pin and the IO output pin, automatically determines the digital-to-analog interface type of the signal line, and divides multiple voltage domains based on the signal line's digital-to-analog interface type and voltage value, resulting in multiple winding regions. The division of multiple voltage domains includes: Determine whether the digital-to-analog interface type of the signal line is a digital signal line or an analog signal line. If the digital-to-analog interface type of the signal line is a digital signal line, then divide each voltage domain according to the voltage value of the voltage domain. If the voltage value of a certain voltage domain is the first value, then divide the voltage domain into the first winding region. If the voltage value of a certain voltage domain is the second value, then divide the voltage domain into the second winding region. If the digital-to-analog interface type of the signal line is an analog signal line, then the voltage domains are divided according to the voltage values ​​of the voltage domains. If the voltage value of a certain voltage domain is the third value, then the voltage domain is divided into the third winding region. If the voltage value of a certain voltage domain is the fourth value, then the voltage domain is divided into the fourth winding region. The parameter setting and winding module sets the winding parameters for the signal lines in each winding area according to the current in the winding list, and then automatically completes the winding of the signal lines in each winding area based on the winding area and the winding parameters.

6. The digital-to-analog interface winding processing system in a multi-voltage domain SoC chip according to claim 5, characterized in that, The winding parameters include the winding width and the winding distance.

7. The digital-to-analog interface winding processing system in a multi-voltage domain SoC chip according to claim 6, characterized in that, In the parameter setting and winding module, setting winding parameters for signal lines in each winding region includes: Based on the current value in the voltage domain, the winding width and winding distance of the signal lines in each winding region are set. If the current value is a first current value, the winding width and winding distance of the signal lines in each winding region are set to a first width and a first distance, respectively. If the current value is a second current value, the winding width and winding distance of the signal lines in each winding region are set to a second width and a second distance, respectively.

8. The digital-to-analog interface winding processing system in a multi-voltage domain SoC chip according to claim 7, characterized in that, In the parameter setting and winding module, it is also determined whether to add a shielding mesh to each signal line based on the winding width and winding distance. If the winding width of a signal line is greater than or equal to a preset width threshold and the winding distance is greater than or equal to a preset distance threshold, then a shielding mesh is added to that signal line.

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