Display panel and display device

Abstract

This application provides a display panel and a display device. One display cycle of the display panel includes N subframes, at least one of which is a target subframe. The display panel includes multiple partitions arranged along a first direction. Each partition includes at least one pixel circuit. Within the target subframe, a pixel circuit in one partition receives a light emission control signal including M enable level pulses, where M is an integer greater than 1. The multiple partitions include a first partition and a second partition. Within the target subframe, the p-th enable level pulse of the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse of the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time, where p ≠ q, 1 ≤ p ≤ M, 1 ≤ q ≤ M, and both p and q are integers. This application can improve the display uniformity of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Technology

[0002] With the continuous improvement of display technology, people's requirements for display devices are also constantly increasing. Among various display technologies, self-emissive display panels have been widely used in various electronic devices, including computers, mobile phones and other electronic products, due to their advantages such as self-emission, thinness, low power consumption, high contrast, high color gamut and flexible display.

[0003] The self-emissive display panel may include, for example, organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), and micro light-emitting diodes (Micro LEDs).

[0004] However, the inventors of this application have discovered that current display panels (such as self-emissive display panels) have problems such as large voltage drops on power signal lines and poor display uniformity when displaying. Summary of the Invention

[0005] This application provides a display panel and a display device that can improve the display uniformity of the display panel.

[0006] In a first aspect, embodiments of this application provide a display panel. One display cycle of the display panel includes N subframes, at least one of the N subframes being a target subframe. The display panel includes multiple partitions arranged along a first direction. Each partition includes at least one pixel circuit. Within the target subframe, a light emission control signal received by a pixel circuit in one partition includes M enable level pulses, where M is an integer greater than 1. The multiple partitions include a first partition and a second partition. Within the target subframe, the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse in the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time, where p ≠ q, 1 ≤ p ≤ M, 1 ≤ q ≤ M, and both p and q are integers.

[0007] Secondly, embodiments of this application provide a display device, which includes a display panel as provided in the first aspect.

[0008] The inventors of this application have discovered that, in related technologies, the sub-pixels in a display panel that are in a light-emitting state are usually concentrated in the same area (called the light-emitting area). When the light-emitting area is far from the power supply terminal that provides the power signal, the power signal lines between the sub-pixels in the light-emitting area and the power supply terminal are long, resulting in a large trace impedance for the power signal lines connected to all the sub-pixels in the light-emitting area, which in turn leads to a large voltage drop on the power signal lines.

[0009] In view of this, embodiments of this application provide a display panel and a display device. One display cycle of the display panel includes N subframes, at least one of the N subframes being a target subframe. Within the target subframe, a pixel circuit in a partition receives a light emission control signal including M enable level pulses, where M is an integer greater than 1. Within the target subframe, the p-th enable level pulse of the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse of the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time, where p ≠ q, 1 ≤ p ≤ M, 1 ≤ q ≤ M, and p and q are both integers. Since the light emission control signal received by a pixel circuit in a partition within the target subframe includes M enable level pulses, where M is an integer greater than 1, the sub-pixel corresponding to the pixel circuit can emit light multiple times within the target subframe. Within the target subframe, the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse in the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time. This allows the p-th emission of the sub-pixel corresponding to the pixel circuit in the first partition to overlap with the q-th emission of the sub-pixel corresponding to the pixel circuit in the second partition, where p≠q. This disperses the original light-emitting area into at least two discontinuous partitions, such as the first partition and the second partition. Because the distance between at least a portion of the light-emitting area and the power supply terminal becomes closer, the trace impedance of the power signal lines connecting the sub-pixels in at least a portion of the light-emitting area decreases, thereby reducing the voltage drop on the power signal lines and improving the display uniformity of the display panel. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram illustrating the display effect of a display panel in related technologies;

[0012] Figure 2 This is a schematic diagram illustrating the brightness relationship of a display panel in related technologies;

[0013] Figure 3 A timing diagram illustrating a screen display cycle of a display panel provided in an embodiment of this application;

[0014] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0015] Figure 5 A waveform diagram of the light emission control signal in the target subframe;

[0016] Figure 6 Another structural schematic diagram of the display panel provided in the embodiments of this application;

[0017] Figure 7 This is another waveform diagram of the light emission control signal in the target subframe;

[0018] Figure 8 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0019] Figure 9 This is another waveform diagram of the light emission control signal in the target subframe;

[0020] Figure 10 Another timing diagram illustrating a screen display cycle of the display panel provided in the embodiments of this application;

[0021] Figure 11 This is another waveform diagram of the light emission control signal in the target subframe;

[0022] Figure 12 This is another waveform diagram of the light emission control signal in the target subframe;

[0023] Figure 13 This is another waveform diagram of the light emission control signal in the target subframe;

[0024] Figure 14 This is another waveform diagram of the light emission control signal in the target subframe;

[0025] Figure 15 This is another waveform diagram of the light emission control signal in the target subframe;

[0026] Figure 16 This is another waveform diagram of the light emission control signal in the target subframe;

[0027] Figure 17 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0028] Figure 18 This is another waveform diagram of the light emission control signal in the target subframe;

[0029] Figure 19 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0030] Figure 20 This is another waveform diagram of the light emission control signal in the target subframe;

[0031] Figure 21 This is another waveform diagram of the light emission control signal in the target subframe;

[0032] Figure 22 This is another waveform diagram of the light emission control signal in the target subframe;

[0033] Figure 23 This is another waveform diagram of the light emission control signal in the target subframe;

[0034] Figure 24 This is another waveform diagram of the light emission control signal in the target subframe;

[0035] Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0036] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0038] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0039] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0040] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0041] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0042] Figure 1 This is a schematic diagram illustrating one display effect of a display panel in related technologies. For example... Figure 1 As shown, in related technologies, sub-pixels in a display panel are typically illuminated row by row; for example, when a sub-pixel in one row is illuminating, the sub-pixel in the next row is illuminated. Therefore, there are situations where multiple adjacent rows of sub-pixels illuminate simultaneously. Spatially, this results in illuminated sub-pixels in the display panel typically clustered in the same area (called the luminous area), such as... Figure 1 The light-emitting region FG is shown. When the light-emitting region FG is far from the power supply terminal P that provides the power signal, the power signal line between the sub-pixels in the light-emitting region FG and the power supply terminal P ( Figure 1 The traces of the power signal lines connected to all sub-pixels in the light-emitting area are relatively long, resulting in a large voltage drop on the power signal lines and poor display uniformity of the display panel.

[0043] Figure 2 This is a schematic diagram illustrating the brightness relationship of a display panel in related technologies. Figure 2 The horizontal axis represents the distance between the light-emitting area and the power supply terminal, and the vertical axis represents the brightness of the light-emitting area. For example... Figure 2As shown, when the light-emitting area is far from the power supply, the brightness of the light-emitting area is low due to the large voltage drop on the power signal line. Furthermore, the brightness of the light-emitting area changes as the distance between it and the power supply changes. If the sub-pixels in the light-emitting state are typically concentrated in the same light-emitting area, then the brightness variation of the light-emitting area will be more pronounced as the distance between it and the power supply changes, resulting in poor display uniformity of the display panel.

[0044] In view of the inventors’ above-mentioned research findings, the present application provides a display panel and a display device that can solve the technical problem of poor display uniformity of display panels in related technologies.

[0045] The technical concept of this application embodiment is as follows: Within the target subframe, the light emission control signal received by a pixel circuit in a partition includes M enable level pulses, where M is an integer greater than 1. Therefore, the sub-pixel corresponding to the pixel circuit can emit light multiple times within the target subframe. Within the target subframe, the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse in the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time. This allows the p-th light emission of the sub-pixel corresponding to the pixel circuit in the first partition to overlap with the q-th light emission of the sub-pixel corresponding to the pixel circuit in the second partition, where p≠q. This disperses the original light-emitting area into at least two discontinuous partitions, such as the first partition and the second partition. In this way, since the distance between at least a portion of the light-emitting area and the power supply terminal becomes closer, the trace impedance of the power signal lines connected to the sub-pixels in at least a portion of the light-emitting area becomes smaller, thereby reducing the voltage drop on the power signal lines and improving the display uniformity of the display panel.

[0046] The display panel provided in the embodiments of this application will be described first below.

[0047] Figure 3 This is a timing diagram illustrating a display cycle of a screen provided in an embodiment of this application. For example... Figure 3 As shown, a display period H of the display panel can include N subframes h. The size of N can be flexibly adjusted according to the actual situation, and this application embodiment does not limit it. For example, N can be an integer greater than 1. A display period H can be understood as the period of displaying one frame, that is, one frame. One frame can be divided into N subframes h. At least one of the N subframes h is the target subframe hm.

[0048] Figure 4 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 4As shown, the display panel 40 may include a plurality of partitions F arranged along a first direction Y. Exemplarily, the first direction Y includes, but is not limited to, the column direction of the display panel 40. Each partition F may include at least one pixel circuit (…). Figure 4 (Not shown).

[0049] Figure 5 This is a waveform diagram of the emission control signal in the target subframe. (Combined with...) Figures 3 to 5 As shown, within the target subframe hm, the emission control signal received by a pixel circuit in partition F may include M enable level pulses m, where M is an integer greater than 1. The size of M can be flexibly adjusted according to actual conditions, and this embodiment does not limit it. Figure 3 The example shown uses M=4, but M can also be other values, and this application does not limit this. The light-emitting control signal can control the light-emitting control transistor in the pixel circuit to turn on / off. For example, when the light-emitting control signal is an enable level pulse, it can control the light-emitting control transistor in the pixel circuit to turn on, thereby causing the pixel circuit to provide driving current to the light-emitting element to drive the light-emitting element to emit light.

[0050] Figure 3 and Figure 5 The example shown uses a P-type transistor as the light-emitting control transistor and a low-level pulse m as the enable pulse. However, when the light-emitting control transistor is an N-type transistor, the enable pulse m can also be a high-level pulse. This application does not limit this.

[0051] Combination Figures 3 to 5 As shown, multiple partitions F may include a first partition F1 and a second partition F2. The first partition F1 and the second partition F2 can be different partitions F. In some examples, the first partition F1 and the second partition F2 can be non-contiguous partitions F, that is, the first partition F1 and the second partition F2 can be separated by at least one partition F. Within the target subframe hm, the p-th enable level pulse (e.g., ...) in the emission control signal received by the pixel circuit in the first partition F1... Figure 5 The enable level pulse mp shown is the qth enable level pulse in the light emission control signal received by the pixel circuit in the second partition F2 (e.g., Figure 5 The enable level pulses (mq) shown overlap at least partially in time. Where p ≠ q, 1 ≤ p ≤ M, 1 ≤ q ≤ M, and p and q are both integers.

[0052] Since the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition F1 overlaps at least partially in time with the q-th enable level pulse in the light emission control signal received by the pixel circuit in the second partition F2, the p-th light emission of the sub-pixel corresponding to the pixel circuit in the first partition F1 overlaps with the q-th light emission of the sub-pixel corresponding to the pixel circuit in the second partition F2. Furthermore, since p ≠ q, the first partition F1 and the second partition F2 are separated by at least one partition F, meaning that the first partition F1 and the second partition F2 are discontinuous partitions F. In this way, the light emission area can be distributed across at least two discontinuous partitions, such as the first partition F1 and the second partition F2.

[0053] The display panel provided in this application embodiment includes N subframes in one display cycle, and at least one of the N subframes is a target subframe. Within the target subframe, the light emission control signal received by a pixel circuit in a partition includes M enable level pulses, where M is an integer greater than 1. Within the target subframe, the p-th enable level pulse of the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse of the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time, where p ≠ q, 1 ≤ p ≤ M, 1 ≤ q ≤ M, and both p and q are integers. Since the light emission control signal received by a pixel circuit in a partition within the target subframe includes M enable level pulses, where M is an integer greater than 1, the sub-pixel corresponding to the pixel circuit can emit light multiple times within the target subframe. Within the target subframe, the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse in the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time. This allows the p-th emission of the sub-pixel corresponding to the pixel circuit in the first partition to overlap with the q-th emission of the sub-pixel corresponding to the pixel circuit in the second partition, where p≠q. This disperses the original light-emitting area into at least two discontinuous partitions, such as the first partition and the second partition. Because the distance between at least a portion of the light-emitting area and the power supply terminal becomes closer, the trace impedance of the power signal lines connecting the sub-pixels in at least a portion of the light-emitting area decreases, thereby reducing the voltage drop on the power signal lines and improving the display uniformity of the display panel.

[0054] like Figure 4 As shown, according to some embodiments of this application, optionally, multiple partitions F may include a third partition F3, with the first partition F1 and the second partition F2 separated by the third partition F3. The third partition F3 can be any partition F located between the first partition F1 and the second partition F2. Embodiments of this application do not limit the number of third partitions F3; the third partition F3 may include one partition F, or it may include two or more partitions F.

[0055] Combination Figure 4 and Figure 5 As shown, within the target subframe hm, the M enable level pulses in the light emission control signal received by the pixel circuit in the third partition F3 are all the same as the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition F1 (e.g., ...). Figure 5 The enable level pulses shown (mp) do not overlap in time.

[0056] That is, within the target subframe hm, when the sub-pixel corresponding to the pixel circuit in the first partition F1 emits light for the p-th time, the sub-pixel in the third partition F3 does not emit light. Thus, the emitting area is distributed across at least two discontinuous partitions, such as the first partition F1 and the second partition F2. Because the distance between at least a portion of the emitting area and the power supply terminal becomes closer, the trace impedance of the power signal lines connecting the sub-pixels in at least a portion of the emitting area decreases, thereby reducing the voltage drop on the power signal lines and improving the display uniformity of the display panel.

[0057] In some embodiments, within the target subframe hm, the M enable level pulses in the light emission control signal received by the pixel circuit in the third partition F3 can also be synchronized with the qth enable level pulse in the light emission control signal received by the pixel circuit in the second partition F2 (e.g., ...). Figure 5 The enable level pulses (mq) shown do not overlap in time. That is, within the target subframe hm, when the sub-pixel corresponding to the pixel circuit in the second partition F2 emits light for the qth time, the sub-pixel in the third partition F3 does not emit light.

[0058] Figure 6 This is another structural schematic diagram of the display panel provided in an embodiment of this application. For example... Figure 6 As shown, according to some embodiments of this application, optionally, the plurality of partitions F may further include at least one fourth partition F4. This application does not limit the number of fourth partitions F4; the display panel 40 may include one fourth partition F4 or multiple fourth partitions F4. Along the first direction Y, the fourth partition F4 may be located between the first partition F1 and the second partition F2. Alternatively, along the first direction Y, the fourth partition F4 may be located on the side of the second partition F2 away from the first partition F1. Alternatively, along the first direction Y, the fourth partition F4 may be located on the side of the first partition F1 away from the second partition F2.

[0059] For example, such as Figure 6As shown, when the display panel 40 includes multiple fourth partitions F4, some of the fourth partitions F4 may be located between the first partition F1 and the second partition F2, while other fourth partitions F4 may be located on the side of the second partition F2 away from the first partition F1 and / or on the side of the first partition F1 away from the second partition F2. For example, when the display panel includes multiple fourth partitions F4, all of the fourth partitions F4 may be located on the side of the second partition F2 away from the first partition F1. For example, when the display panel includes multiple fourth partitions F4, all of the fourth partitions F4 may be located on the side of the first partition F1 away from the second partition F2; this embodiment does not limit this.

[0060] Figure 7 This is another waveform diagram of the illumination control signal in the target subframe. Combined with... Figure 6 and Figure 7 As shown, the time interval during which the p-th enable level pulse mp (hereinafter referred to as the p-th enable level pulse mp) in the light emission control signal received by the pixel circuit in the first partition F1 overlaps with the q-th enable level pulse mq (hereinafter referred to as the q-th enable level pulse mq) in the light emission control signal received by the pixel circuit in the second partition F2 is the target time interval t1.

[0061] During the target time period t1, one of the enable level pulses m in the light emission control signal received by the pixel circuit in the fourth partition F4 at least partially overlaps with the p-th enable level pulse mp in time. That is, within the target subframe hm, when the p-th light emission of the sub-pixel corresponding to the pixel circuit in the first partition F1 occurs, in addition to the light emission of the sub-pixel in the second partition F2, the sub-pixel in the fourth partition F4 is also emitting light. In this way, the light emission area is distributed across a larger number of discontinuous partitions, such as the first partition F1, the second partition F2, and at least one fourth partition F4. This results in a more uniform distribution of the light emission area, which is beneficial for further improving the display uniformity of the display panel. Furthermore, since the distance between at least some of the light emission areas and the power supply terminal becomes closer, the trace impedance of the power signal lines connected to the sub-pixels in at least some of the light emission areas becomes smaller, thereby reducing the voltage drop on the power signal lines.

[0062] According to some embodiments of this application, optionally, when the display panel includes multiple light-emitting zones F such as a first zone F1, a second zone F2, and a fourth zone F4, the interval between two adjacent light-emitting zones F is the same. Thus, since the interval between two adjacent light-emitting zones F is the same, the distribution of the light-emitting area is more uniform, which is beneficial to further improving the display uniformity of the display panel.

[0063] Figure 8 This is another schematic diagram of the structure of the display panel provided in an embodiment of this application. For example... Figure 8As shown, for example, according to some embodiments of this application, optionally, along the first direction Y, the fourth partition F4 is located on the side of the second partition F2 away from the first partition F1. Wherein, the minimum interval Δh1 between the first partition F1 and the second partition F2 is the same as the minimum interval Δh2 between the second partition F2 and the fourth partition F4.

[0064] like Figure 8 As shown, when the display panel includes multiple fourth partitions F4, the minimum interval Δh2 between the second partition F2 and the fourth partition F4 can be the interval between the fourth partition F4 closest to the second partition F2 and the second partition F2. Furthermore, the minimum interval Δh3 between two adjacent fourth partitions F4 can also be the same as the minimum interval Δh1 between the first partition F1 and the second partition F2.

[0065] Thus, since the minimum interval Δh1 between the first partition F1 and the second partition F2 is the same as the minimum interval Δh2 between the second partition F2 and the fourth partition F4, the distribution of the light-emitting area is more uniform, which is beneficial to further improve the display uniformity of the display panel.

[0066] See also Figure 8 According to some embodiments of this application, optionally, partition F may include at least one row of pixel circuits 80. One row of pixel circuits 80 may include multiple pixel circuits 80 arranged along a second direction X. The second direction X intersects the first direction Y. It should be noted that... Figure 8 The example shown is a partition F that includes one row of pixel circuits 80. However, a partition F may also include multiple rows of pixel circuits 80. This application does not limit this.

[0067] The number of rows of pixel circuits 80 between the first partition F1 and the second partition F2 can be the same as the number of rows of pixel circuits 80 between the second partition F2 and the fourth partition F4. For example, along the first direction Y, there can be K rows of pixel circuits 80 between the first partition F1 and the second partition F2, and there can also be K rows of pixel circuits 80 between the second partition F2 and the fourth partition F4, where K is a positive integer.

[0068] like Figure 8 As shown, when the display panel includes multiple fourth zones F4, the number of rows of pixel circuits 80 between the second zone F2 and the fourth zone F4 can specifically be the number of rows of pixel circuits 80 between the fourth zone F4 closest to the second zone F2 and the second zone F2. That is, the number of rows of pixel circuits 80 between the fourth zone F4 closest to the second zone F2 and the second zone F2 is equal to the number of rows of pixel circuits 80 between the first zone F1 and the second zone F2. Furthermore, the number of rows of pixel circuits 80 between two adjacent fourth zones F4 can also be the same as the number of rows of pixel circuits 80 between the first zone F1 and the second zone F2.

[0069] Thus, since the number of rows of pixel circuits 80 between the first partition F1 and the second partition F2 is the same as the number of rows of pixel circuits 80 between the second partition F2 and the fourth partition F4, the light-emitting area is distributed more evenly, which is beneficial to further improve the display uniformity of the display panel.

[0070] According to some embodiments of this application, optionally, the number of rows of pixel circuits 80 in the first partition F1 can be the same as the number of rows of pixel circuits 80 in the second partition F2. When the display panel includes a fourth partition F4, the number of rows of pixel circuits 80 in the fourth partition F4 can also be the same as the number of rows of pixel circuits 80 in the first partition F1.

[0071] In this way, the width of each light-emitting zone F along the first direction Y can be the same or similar, making the distribution of the light-emitting area more uniform and helping to further improve the display uniformity of the display panel.

[0072] See also Figure 8 According to some embodiments of this application, optionally, the multiple partitions F may include multiple fourth partitions F4, and two adjacent fourth partitions F4 may be separated by at least one partition F.

[0073] Figure 9 This is another waveform diagram of the illumination control signal in the target subframe. Combined with... Figure 8 and Figure 9 As shown, during the target time period t1, the order of the enable level pulses m that at least partially overlap with the p-th enable level pulse mp in time is different in different fourth partitions F4.

[0074] For example, taking a display panel comprising two fourth zones F4, during the target time period t1, the u1th enable level pulse mu1 in the light emission control signal received by the pixel circuit in one of the fourth zones F4 at least partially overlaps with the pth enable level pulse mp in the first zone F1, and the u2th enable level pulse mu2 in the light emission control signal received by the pixel circuit in the other fourth zone F4 at least partially overlaps with the pth enable level pulse mp in the first zone F1. Where u1≠u2≠p≠q, 1≤u1≤M, 1≤u2≤M, and u1 and u2 are both integers.

[0075] Because the p-th enable pulse mp of the first partition F1, the q-th enable pulse mq of the second partition F2, the enable pulse mu1 of one fourth partition F4, and the enable pulse mu2 of another fourth partition F4 overlap in time, the p-th emission of the sub-pixel corresponding to the pixel circuit in the first partition F1, the q-th emission of the sub-pixel corresponding to the pixel circuit in the second partition F2, the u1-th emission of the sub-pixel corresponding to the pixel circuit in one fourth partition F4, and the u2-th emission of the sub-pixel corresponding to the pixel circuit in another fourth partition F4 overlap. Furthermore, since u1 ≠ u2 ≠ p ≠ q, adjacent fourth partitions F4 can be separated by at least one partition F, the first partition F1 and the second partition F2 can be separated by at least one partition F, and the second partition F2 and the fourth partition F4 can be separated by at least one partition F. In this way, the luminous area can be distributed across multiple discontinuous partitions, such as the first partition F1, the second partition F2, and the fourth partition F4. Thus, the luminous area is distributed across a larger number of discontinuous partitions. This results in a more uniform distribution of the light-emitting areas, which helps to further improve the display uniformity of the display panel. In addition, since the distance between at least some of the light-emitting areas and the power supply terminal is reduced, the trace impedance of the power signal lines connecting the sub-pixels in at least some of the light-emitting areas is reduced, thereby reducing the voltage drop on the power signal lines.

[0076] The inventors of this application further realized that in some subframes, the duty cycle of the emission control signal may be relatively small. In the embodiments of this application, the duty cycle of the emission control signal can be understood as the proportion of the enable level in the emission control signal. The larger the duty cycle of the emission control signal, the longer the emission time of each row of sub-pixels, and correspondingly, the more overlapping emission times of adjacent rows of sub-pixels. Spatially, this means that there are more rows of sub-pixels in the emission state, and the larger the area (or range) of the emission region. Conversely, the smaller the duty cycle of the emission control signal, the smaller the area of ​​the emission region, that is, the fewer sub-pixels in the emission region.

[0077] When the number of sub-pixels in the light-emitting region is small, the voltage drop on the power signal line is small because the number of sub-pixels driven by the power signal line is small.

[0078] In view of this, this application considers that when the duty cycle of the light emission control signal is small, a single light emission scheme can be adopted to further reduce the control difficulty while ensuring that the voltage drop on the power signal line is small.

[0079] Figure 10 This is another timing diagram illustrating a screen display cycle of the display panel provided in an embodiment of this application. For example... Figure 10 As shown, at least one of the N subframes h is a fixed target subframe hg.

[0080] Within a fixed target subframe hg, the duty cycle of the emission control signal received by the pixel circuit in partition F is less than a first preset threshold. That is, within a fixed target subframe hg, the duty cycle of the emission control signal is small. The value of the first preset threshold can be flexibly adjusted according to actual conditions, and this embodiment does not limit it.

[0081] Within a fixed target subframe hg, the emission control signal received by the pixel circuit in partition F may include one enable level pulse m. That is, within a fixed target subframe hg, the sub-pixel corresponding to the pixel circuit in each partition F can emit light only once, achieving single emission.

[0082] like Figure 10 As shown, within a fixed target subframe hg, multiple partitions F can sequentially receive enable level pulses m. That is, along the first direction (e.g., Figure 8 (As shown in the Y direction), each partition F can be lit up sequentially. The illumination time of adjacent partitions F may or may not overlap, and this embodiment does not limit this.

[0083] Figure 11 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 11 As shown, according to some embodiments of this application, optionally, the target subframe hm may include a first target subframe hm1 and a second target subframe hm2. The first target subframe hm1 and the second target subframe hm2 are different subframes h.

[0084] Within the first target subframe hm1, the duty cycle of the light emission control signal received by the pixel circuit in partition F is the first duty cycle. The light emission control signal received by a pixel circuit in partition F includes M1 enable level pulses m.

[0085] Within the second target subframe hm2, the duty cycle of the light emission control signal received by the pixel circuit in partition F is the second duty cycle. The light emission control signal received by one pixel circuit in partition F includes M2 enable level pulses m.

[0086] The first duty cycle differs from the second duty cycle. For example, the emission time of a row of subpixels in partition F of the first target subframe hm1 is different from the emission time of a row of subpixels in partition F of the second target subframe hm2. Accordingly, M1 ≠ M2, and both M1 and M2 are integers greater than 1. The sizes of M1 and M2 can be flexibly adjusted according to actual conditions, and this application embodiment does not limit this.

[0087] Thus, when the duty cycle of the light emission control signal corresponding to different target subframes is different, the duty cycle requirements of different target subframes can be met by flexibly adjusting the number of enable level pulses of the light emission control signal, such as making the duty cycle of the light emission control signal of the target subframe reach the desired target duty cycle.

[0088] It should be noted that in some other embodiments of this application, in addition to the first target subframe hm1 and the second target subframe hm2, the target subframe hm may also include, for example, a third target subframe to an N1th target subframe, where N1 is an integer greater than or equal to 3. The duty cycles of the light emission control signals corresponding to the third target subframe to the N1th target subframe may be different, and different from the first duty cycle and the second duty cycle. Accordingly, the number of enable level pulses of the light emission control signals corresponding to the third target subframe to the N1th target subframe may also be different, and different from M1 and M2.

[0089] See also Figure 11 According to some embodiments of this application, optionally, the pulse width W2 of the enable level pulse m in the second target subframe hm2 may be different from the pulse width W1 of the enable level pulse m in the first target subframe hm1.

[0090] For example, when the duty cycle of the light emission control signal is large, the pulse width of the enable level pulse m of the light emission control signal can also be large.

[0091] Thus, when the duty cycle of the light emission control signal corresponding to different target subframes is different, by flexibly adjusting the pulse width of the enable level pulse of the light emission control signal in different target subframes, for example, the difference between the number of enable level pulses of the light emission control signal corresponding to different target subframes can be reduced, thereby making the number of partitions of the light emission area similar in different target subframes, which helps to reduce the difficulty of light emission control.

[0092] According to some other embodiments of this application, optionally, the pulse width W2 of the enable level pulse m in the second target subframe hm2 may also be the same as the pulse width W1 of the enable level pulse m in the first target subframe hm1.

[0093] Thus, since the pulse width W2 of the enable level pulse m in the second target subframe hm2 is the same as the pulse width W1 of the enable level pulse m in the first target subframe hm1, it is beneficial to make the width of the light-emitting partition (such as the first partition and the second partition) along the first direction in the second target subframe hm2 the same as the width of the light-emitting partition (such as the first partition and the second partition) along the first direction in the first target subframe hm1, thereby reducing the width jump of the light-emitting partition in different target subframes and improving the display stability of the display panel.

[0094] See also Figure 11 In some specific embodiments, optionally, the first duty cycle can be less than the second duty cycle, that is, the emission time of a row of sub-pixels in partition F of the first target subframe hm1 can be less than the emission time of a row of sub-pixels in partition F of the second target subframe hm2. Correspondingly, M1 can be less than M2. That is, the number of enable level pulses of the emission control signal corresponding to the first target subframe hm1 can be less than the number of enable level pulses of the emission control signal corresponding to the second target subframe hm2.

[0095] Thus, on the one hand, since the first duty cycle is smaller than the second duty cycle, setting M1 smaller than M2 can satisfy the duty cycle requirements of different target sub-frames. For example, it can ensure that the duty cycle of the light emission control signal of the first target sub-frame reaches the desired first duty cycle, and that the duty cycle of the light emission control signal of the second target sub-frame reaches the desired second duty cycle. On the other hand, as the duty cycle of the light emission control signal increases, by increasing the number of enable level pulses of the light emission control signal corresponding to the target sub-frame, the number of light emission times of sub-pixels in each partition within the target sub-frame can be increased. This helps to distribute the light emission area to a larger number of partitions, making the distribution of the light emission area more uniform, and further improving the display uniformity of the display panel.

[0096] See also Figure 11 In some specific embodiments, optionally, when the first duty cycle is less than the second duty cycle, the pulse width W2 of the enable level pulse m in the second target subframe hm2 can be greater than or equal to the pulse width W1 of the enable level pulse m in the first target subframe hm1. Figure 11 Taking the example where the pulse width W2 of the enable level pulse m in the second target subframe hm2 is greater than the pulse width W1 of the enable level pulse m in the first target subframe hm1, the example is illustrated. However, in other embodiments, the pulse width W2 of the enable level pulse m in the second target subframe hm2 may also be equal to the pulse width W1 of the enable level pulse m in the first target subframe hm1.

[0097] In other words, when the duty cycle of the light emission control signal is large, the pulse width of the enable level pulse m of the light emission control signal can also be set to be large.

[0098] Thus, when the duty cycle of the light emission control signal corresponding to different target subframes is different, by flexibly adjusting the pulse width of the enable level pulse of the light emission control signal in different target subframes, for example, the difference between the number of enable level pulses of the light emission control signal corresponding to different target subframes can be reduced, thereby making the number of partitions of the light emission area similar in different target subframes, which helps to reduce the difficulty of light emission control.

[0099] Figure 12This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 12 As shown, according to some embodiments of this application, optionally, the target subframe hm may include a first target subframe hm1 and a second target subframe hm2. The first target subframe hm1 and the second target subframe hm2 are different subframes h. Figure 11 The difference between the illustrated embodiment and the one shown is that, in Figure 12 In the embodiment shown, the number of enable level pulses of the light emission control signal corresponding to the first target subframe hm1 can be the same as the number of enable level pulses of the light emission control signal corresponding to the second target subframe hm2.

[0100] Specifically, within the first target subframe hm1, the light emission control signal received by a pixel circuit in partition F includes M1 enable level pulses m. Within the second target subframe hm2, the light emission control signal received by a pixel circuit in partition F includes M1 enable level pulses m, where M1 is an integer greater than 1. The size of M1 can be flexibly adjusted according to actual conditions, and this embodiment does not limit it.

[0101] The pulse width W2 of the enable level pulse m in the second target subframe hm2 can be different from the pulse width W1 of the enable level pulse m in the first target subframe hm1.

[0102] In this way, by flexibly adjusting the pulse width of the enable level pulse of the light emission control signal, the duty cycle requirements of different target subframes can be met, such as making the duty cycle of the light emission control signal of the target subframe reach the desired target duty cycle.

[0103] In some specific embodiments, optionally, within the first target subframe hm1, the duty cycle of the light emission control signal received by the pixel circuit in partition F is a first duty cycle. Within the second target subframe hm2, the duty cycle of the light emission control signal received by the pixel circuit in partition F is a second duty cycle. That is, the duty cycle of the light emission control signal corresponding to the first target subframe hm1 is the first duty cycle, and the duty cycle of the light emission control signal corresponding to the second target subframe hm2 is the second duty cycle.

[0104] The first duty cycle can be smaller than the second duty cycle. For example, the emission time of a row of sub-pixels in partition F of the first target subframe hm1 is less than the emission time of a row of sub-pixels in partition F of the second target subframe hm2. The magnitudes of the first and second duty cycles can be flexibly adjusted according to actual conditions, and this application embodiment does not limit this.

[0105] Accordingly, the pulse width W2 of the enable level pulse m in the second target subframe hm2 can be greater than the pulse width W1 of the enable level pulse m in the first target subframe hm1.

[0106] That is, when the duty cycle of the light emission control signal is large, the pulse width of the enable level pulse m of the light emission control signal can also be set to be large.

[0107] Thus, on the one hand, when the duty cycles of the illumination control signals corresponding to different target subframes are different, the duty cycle requirements of different target subframes can be met by flexibly adjusting the pulse width of the enable level pulses of the illumination control signals in different target subframes. For example, the duty cycle of the illumination control signal in the first target subframe can reach the desired first duty cycle, and the duty cycle of the illumination control signal in the second target subframe can reach the desired second duty cycle. On the other hand, the number of enable level pulses of the illumination control signals corresponding to different target subframes is the same, which can make the number of partitions in the illumination area the same in different target subframes, thus reducing the difficulty of illumination control.

[0108] Figure 13 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 13 As shown, according to some embodiments of this application, optionally, the target subframe hm may include X different sub-target subframes hz, where the X sub-target subframes hz are different subframes h, and X is an integer greater than or equal to 2. For example, the first target subframe described above can be regarded as a sub-target subframe hz, and the second target subframe described above can also be regarded as a sub-target subframe hz.

[0109] In X different sub-target subframes hz, the duty cycles of the emission control signals corresponding to at least two sub-target subframes hz are in different duty cycle ranges. The ranges of these different duty cycle ranges vary; for example, multiple duty cycle ranges can be preset, such as 10%–15%, 16%–20%, and so on. For instance, when the duty cycle of the emission control signal corresponding to the sub-target subframe hz is 12%, it falls within the 10%–15% duty cycle range. Similarly, when the duty cycle of the emission control signal corresponding to the sub-target subframe hz is 18%, it falls within the 16%–20% duty cycle range. It should be noted that the aforementioned 12%, 18%, 10%–15%, and 16%–20% are merely examples and do not constitute a limitation of this application.

[0110] In some specific embodiments, the duty cycles of the light emission control signals corresponding to the X sub-target sub-frames hz can be in different duty cycle ranges. Of course, the duty cycles of the light emission control signals corresponding to some sub-target sub-frames hz can also be in the same duty cycle range. This application does not limit this.

[0111] The number of enable level pulses can vary depending on the duty cycle interval. Specifically, the number of enable level pulses can be the number of enable level pulses of the emission control signal received by a pixel circuit in partition F within a sub-target subframe hz.

[0112] For example, when the duty cycle of the illumination control signal corresponding to sub-target subframe hz1 is in duty cycle interval A1, the illumination control signal received by a pixel circuit in partition F within sub-target subframe hz1 may include a1 enable level pulses m. When the duty cycle of the illumination control signal corresponding to sub-target subframe hz2 is in duty cycle interval A2, the illumination control signal received by a pixel circuit in partition F within sub-target subframe hz2 may include a2 enable level pulses m. a1 ≠ a2, and a1 and a2 are both integers greater than 1.

[0113] In this way, by pre-setting multiple different duty cycle intervals, each duty cycle interval corresponds to a different number of enable level pulses. The number of enable level pulses for each sub-target subframe hz can be quickly determined based on the duty cycle interval of the emission control signal. When the duty cycles of the emission control signals for different target subframes are different, the number of enable level pulses can be flexibly adjusted to meet the duty cycle requirements of different target subframes, such as ensuring that the duty cycle of the emission control signal for the target subframe reaches the desired target duty cycle.

[0114] Figure 14 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 14 As shown, according to some embodiments of this application, optionally, within the same target subframe hm, the pulse width W of the enable level pulses m of multiple partitions F can be the same. Specifically, for any one of the multiple partitions F, the pulse width W of the M enable level pulses m of the light emission control signal received by the pixel circuit in that partition F can be the same.

[0115] Thus, within the same target subframe hm, since the pulse width W of the enable level pulse m of multiple partitions F is the same, this can be reflected in space as such that the width of different light-emitting partitions F (such as the first partition F1 and the second partition F2) is the same along the first direction, making the distribution of the light-emitting area more uniform, which is beneficial to further improve the display uniformity of the display panel.

[0116] See also Figure 14According to some embodiments of this application, optionally, within the same target subframe hm, the time interval T between two adjacent enable level pulses m corresponding to multiple partitions F is the same. Specifically, within the same target subframe hm, for any one of the multiple partitions F, the time interval T between two adjacent enable level pulses m of the M enable level pulses of the light emission control signal received by the pixel circuit in that partition F can be the same.

[0117] Thus, within the same target subframe hm, since the time interval T between two adjacent enable level pulses m corresponding to multiple partitions F is the same, spatially, this can result in the same spacing between two adjacent luminous partitions F, making the luminous area distribution more uniform and further improving the display uniformity of the display panel.

[0118] Combination Figure 8 and Figure 14 As shown, partition F may include at least one row of pixel circuits 80. Each row of pixel circuits 80 may include at least one pixel circuit 80 arranged along a second direction X. The second direction X intersects the first direction Y. Figure 8 The following example illustrates a partition F comprising a row of pixel circuits 80.

[0119] According to some embodiments of this application, the time interval T can optionally be determined based on the following expression:

[0120] Δt×k=T (1)

[0121] Where Δt represents the time difference between the start time of the first enable level pulse m1 of the light emission control signal received by the pixel circuit of the i-th row within the same target subframe and the start time of the first enable level pulse m1 of the light emission control signal received by the pixel circuit of the (i+1)-th row, i is a positive integer, for example i can be equal to 1, k represents the row number of the pixel circuit between the two sub-pixels where the enable level pulses overlap in time, and T represents the time interval.

[0122] Δt and k can be flexibly set according to the actual situation, that is, Δt and k can be preset, and this application embodiment does not limit this. After Δt and k are determined, the time interval T can be calculated, for example, based on the above expression (1).

[0123] Depend on Figure 14It can be seen that the time interval T calculated according to expression (1) is used to set the time interval between two adjacent enable level pulses m. For example, it can make the f1 enable level pulse mf1 of the j-th row pixel circuit and the f2 enable level pulse mf2 of the s-th row pixel circuit at least partially overlap in time. j≠s, f1≠f2, and j, s, f1 and f2 are all positive integers. Since the pulse width W of the enable level pulses m of multiple partitions F is the same, the time interval T between two adjacent enable level pulses m of multiple partitions F is the same. Therefore, the f1+n enable level pulse mf1+n of the j-th row pixel circuit also overlaps at least partially in time with the f2+n enable level pulse mf2+n of the s-th row pixel circuit. n is a positive integer, so that at least two partitions F emit light in the same time period.

[0124] Figure 15 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 15 As shown, according to some embodiments of this application, optionally, within the same target subframe hm, the pulse widths W of the M enable level pulses m of the light emission control signal received by the pixel circuit in partition F can be different. For example, the pulse widths W of the M enable level pulses m can increase or decrease. As another example, among the M enable level pulses m, the pulse width W of the odd-numbered enable level pulse m can be a first pulse width, and the pulse width W of the even-numbered enable level pulse m can be a second pulse width, where the first pulse width and the second pulse width are different. There are various ways to implement the different pulse widths W of the M enable level pulses m, which will not be listed here.

[0125] In this way, the pulse width W of the M enable level pulses m of the light emission control signal received by the pixel circuit in partition F can be flexibly adjusted so that the duty cycle of the light emission control signal reaches the desired target duty cycle.

[0126] Figure 16 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 16As shown, according to some embodiments of this application, optionally, within the same target subframe hm, the time interval T between two adjacent enable level pulses m of the M enable level pulses m of the light emission control signal received by the pixel circuit in partition F can be different. For example, the time interval T between two adjacent enable level pulses m of the M enable level pulses m can increase or decrease. As another example, in the M-1 time intervals T corresponding to the M enable level pulses m, the odd-numbered time interval T can be a first time interval, and the even-numbered time interval T can be a second time interval, where the first time interval and the second time interval are different. There are various ways to implement different time intervals T between two adjacent enable level pulses m of the M enable level pulses m, which will not be listed here.

[0127] Thus, by adjusting the time interval T between two adjacent enable level pulses m in the M enable level pulses m, the spacing between two adjacent light-emitting partitions can be flexibly adjusted to meet the needs of different situations.

[0128] Figure 17 This is another schematic diagram of the structure of the display panel provided in an embodiment of this application. For example... Figure 17 As shown, according to some embodiments of this application, optionally, partition F may include at least two rows of pixel circuits 80. Figure 17 The example shown is a partition F comprising two rows of pixel circuits 80. Each row of pixel circuits 80 may include at least one pixel circuit 80 arranged along a second direction X, which intersects with a first direction Y. Each row of pixel circuits 80 may be electrically connected to a light emission control signal line EM, which provides a light emission control signal to the row of pixel circuits 80.

[0129] Figure 18 This is another waveform diagram of the illumination control signal in the target subframe. Combined with... Figure 17 and Figure 18 As shown, Figure 18 A row of light emission control signals represents the light emission control signals received by a row of pixel circuits. The k-th enable level pulse m of the light emission control signals received by two adjacent rows of pixel circuits in the same partition F overlaps at least partially in time, 1≤k≤M, where k is an integer.

[0130] For example, the first enable level pulse m of the light emission control signal received by the first row pixel circuit 80 in the same partition F at least partially overlaps in time with the first enable level pulse m of the light emission control signal received by the second row pixel circuit 80 in the same partition F. The second enable level pulse m of the light emission control signal received by the first row pixel circuit 80 in the same partition F at least partially overlaps in time with the second enable level pulse m of the light emission control signal received by the second row pixel circuit 80 in the same partition F. ... The Mth enable level pulse m of the light emission control signal received by the first row pixel circuit 80 in the same partition F at least partially overlaps in time with the Mth enable level pulse m of the light emission control signal received by the second row pixel circuit 80 in the same partition F.

[0131] Thus, for each partition F, when the sub-pixel corresponding to the pixel circuit in the current row emits light, the sub-pixel corresponding to the pixel circuit in the next row is also lit, thereby avoiding brightness jumps, achieving a smooth brightness transition, and further improving display quality.

[0132] Figure 19 This is another schematic diagram of the structure of the display panel provided in an embodiment of this application. For example... Figure 19 As shown, according to some embodiments of this application, optionally, partition F may include at least one row of pixel circuitry 80. Figure 19 The example shown is a partition F comprising three rows of pixel circuits 80. Each row of pixel circuits 80 may include at least one pixel circuit 80 arranged along a second direction X, which intersects with a first direction Y. Each row of pixel circuits 80 may be electrically connected to a light emission control signal line EM, which provides a light emission control signal to the row of pixel circuits 80.

[0133] Multiple partitions F can include a first subpartition Fz1 and a second subpartition Fz2, where the first subpartition Fz1 and the second subpartition Fz2 are adjacent but different partitions F. It should be noted that, for the sake of simplicity, Figure 19 Taking two adjacent partitions F as an example, the first subpartition Fz1 and the second subpartition Fz2 are shown. However, the first subpartition Fz1 can be any partition, such as any partition F other than the last partition Fe, while the second subpartition Fz2 can be any partition F adjacent to the first subpartition Fz1.

[0134] Figure 20 This is another waveform diagram of the illumination control signal in the target subframe. Combined with... Figure 19 and Figure 20 As shown, Figure 20The light emission control signal in the middle row represents the light emission control signal received by the pixel circuit 80 in a row. According to some embodiments of this application, optionally, the k-th enable level pulse m of the light emission control signal received by the last row pixel circuit in the first sub-partition Fz1 and the k-th enable level pulse m of the light emission control signal received by the first row pixel circuit in the second sub-partition Fz2 overlap at least partially in time, 1≤k≤M, where k is an integer.

[0135] For example, the first enable level pulse m of the light emission control signal received by the last row pixel circuit 80 in the first sub-partition Fz1 at least partially overlaps in time with the first enable level pulse m of the light emission control signal received by the first row pixel circuit 80 in the second sub-partition Fz2. The second enable level pulse m of the light emission control signal received by the last row pixel circuit 80 in the first sub-partition Fz1 at least partially overlaps in time with the second enable level pulse m of the light emission control signal received by the first row pixel circuit 80 in the second sub-partition Fz2. ... The Mth enable level pulse m of the light emission control signal received by the last row pixel circuit 80 in the first sub-partition Fz1 at least partially overlaps in time with the Mth enable level pulse m of the light emission control signal received by the first row pixel circuit 80 in the second sub-partition Fz2.

[0136] In this way, when the sub-pixel corresponding to the last row of pixel circuits in the first sub-partition Fz1 emits light, the sub-pixel corresponding to the first row of pixel circuits in the second sub-partition Fz2 is lit, thereby avoiding brightness jumps when switching partitions, achieving a smooth transition of brightness between different partitions, and further improving display quality.

[0137] See also Figure 19 According to some embodiments of this application, the partition F may optionally include a multi-row pixel circuit 80. Figure 19 For example, a partition F comprising three rows of pixel circuits 80 is illustrated. The number of rows of pixel circuits 80 in different partitions F may be the same or different, and this embodiment does not limit this. Each row of pixel circuits 80 may include at least one pixel circuit 80 arranged along a second direction X, which intersects with the first direction Y. Each row of pixel circuits 80 may be electrically connected to a light emission control signal line EM, which can provide a light emission control signal to the row of pixel circuits 80.

[0138] The first partition F1 may include Z1 row pixel circuits 80, which receive Z1 emission control signals, and one row pixel circuit 80 receives one emission control signal. Within the target subframe, each emission control signal may include M enable level pulses, where M is an integer greater than 1.

[0139] Figure 21 This is another waveform diagram of the illumination control signal in the target subframe. Combined with... Figure 20 and Figure 21 As shown, according to some embodiments of this application, optionally, the p-th enable level pulse mp of the Z1 light emission control signals received by the first partition F1 overlaps in the first time period dt1.

[0140] The second partition F2 may include Z2 row pixel circuits 80, which receive Z2 emission control signals, and one row pixel circuit 80 receives one emission control signal. Within the target subframe, each emission control signal may include M enable level pulses, where M is an integer greater than 1. The q-th enable level pulse mq among the Z2 emission control signals received by the second partition F2 overlaps in the second time interval dt2. Here, Z1 and Z2 are both integers greater than 1. Z1 and Z2 may be the same or different; this embodiment does not limit this. For example, in... Figure 20 and Figure 21 In the illustrated embodiment, both Z1 and Z2 can be 3.

[0141] like Figure 21 As shown, the first time period dt1 and the second time period dt2 can at least partially overlap.

[0142] Thus, since the first time period dt1 and the second time period dt2 at least partially overlap, during the time period when the first time period dt1 and the second time period dt2 overlap, the sub-pixels corresponding to the Z1 row pixel circuit 80 in the first partition F1 and the Z2 row pixel circuit 80 in the second partition F2 can both emit light.

[0143] Figure 22 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 22 As shown, according to some embodiments of this application, M may optionally include M3 or M4.

[0144] At the first brightness level L1, within the target subframe hm, the emission control signal received by a pixel circuit in partition F may include M3 enable level pulses m.

[0145] At the second brightness level L2, within the target subframe hm, the emission control signal received by a pixel circuit in partition F may include M4 enable level pulses m.

[0146] The first brightness level is different from the second brightness level. That is, the brightness displayed by the display panel at the first brightness level can be different from the brightness displayed by the display panel at the second brightness level. Accordingly, M3 ≠ M4. The sizes of M3 and M4 can be flexibly adjusted according to actual conditions, and this application embodiment does not limit this.

[0147] Thus, by flexibly adjusting the number of enable level pulses of the light emission control signal at different brightness levels, the duty cycle of the light emission control signal can be adjusted, thereby meeting the brightness requirements of different brightness levels, such as enabling each brightness level to reach its desired target brightness.

[0148] See also Figure 22 According to some embodiments of this application, optionally, the pulse width W4 of the enable level pulse m corresponding to the second brightness level L2 can be the same as the pulse width W3 of the enable level pulse m corresponding to the first brightness level L1.

[0149] In this way, the duty cycle of the light emission control signal can be adjusted simply by flexibly adjusting the number of enable level pulses of the light emission control signal, thereby meeting the brightness requirements of different brightness levels, without having to adjust the pulse width of the enable level pulses of the light emission control signal, which can reduce the complexity of the light emission control signal.

[0150] Figure 23 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 23 As shown, according to some other embodiments of this application, optionally, the pulse width W4 of the enable level pulse m corresponding to the second brightness level L2 may be different from the pulse width W3 of the enable level pulse m corresponding to the first brightness level L1.

[0151] In this way, by flexibly adjusting the number of enable level pulses and the pulse width of the enable level pulses of the light emission control signal, the duty cycle of the light emission control signal can be adjusted, thereby meeting the brightness requirements of different brightness levels.

[0152] See also Figure 22 or Figure 23 In some specific embodiments, the second brightness level L2 can be greater than the first brightness level L1. That is, the brightness displayed by the display panel at the second brightness level can be greater than the brightness displayed by the display panel at the first brightness level. Correspondingly, M4 can be greater than M3.

[0153] Thus, when the brightness level corresponds to a higher brightness, the duty cycle of the light emission control signal can be increased by increasing the number of enable level pulses of the light emission control signal, thereby meeting the brightness requirements of different brightness levels. For example, the first brightness level can reach the desired first target brightness, and the second brightness level can reach the desired second target brightness, with the second target brightness being greater than the first target brightness.

[0154] See also Figure 23When the second brightness level L2 is greater than the first brightness level L1, the pulse width W4 of the enable level pulse m corresponding to the second brightness level L2 can be greater than or equal to the pulse width W3 of the enable level pulse m corresponding to the first brightness level L1.

[0155] That is, when the brightness level corresponds to a higher brightness, the pulse width of the enable level pulse m of the light emission control signal can also be set to a larger value.

[0156] Thus, when the brightness level corresponds to a higher brightness, by increasing the number of enable level pulses of the light emission control signal and increasing the pulse width of the enable level pulses of the light emission control signal, it is possible to better ensure that the duty cycle of the light emission control signal can reach the target duty cycle, thereby meeting the brightness requirements of different brightness levels, such as enabling the second brightness level to reach the desired second target brightness.

[0157] Figure 24 This is another waveform diagram of the illumination control signal in the target subframe. For example... Figure 24 As shown, with Figure 22 The difference between the illustrated embodiment and the one shown is that, in Figure 24 In the embodiment shown, the number of enable level pulses of the light emission control signal corresponding to the first brightness level can be the same as the number of enable level pulses of the light emission control signal corresponding to the second brightness level.

[0158] Specifically, at the first brightness level L1, within the target subframe hm, the emission control signal received by a pixel circuit in partition F includes M enable level pulses m. At the second brightness level L2, within the target subframe hm, the emission control signal received by a pixel circuit in partition F includes M enable level pulses m.

[0159] The first brightness level L1 is different from the second brightness level L2. That is, the brightness displayed by the display panel at the first brightness level can be different from the brightness displayed by the display panel at the second brightness level. Accordingly, the pulse width W3 of the enable level pulse m of the light emission control signal for the first brightness level L1 can be different from the pulse width W4 of the enable level pulse m of the light emission control signal for the second brightness level L2.

[0160] Thus, by flexibly adjusting the pulse width of the enable level pulse of the light emission control signal at different brightness levels, the duty cycle of the light emission control signal can be adjusted, thereby meeting the brightness requirements of different brightness levels, such as enabling each brightness level to reach its desired target brightness.

[0161] See also Figure 24In some specific embodiments, optionally, the second brightness level L2 can be greater than the first brightness level L1. That is, the brightness displayed by the display panel at the second brightness level L2 can be greater than the brightness displayed by the display panel at the first brightness level L1. Correspondingly, the pulse width W4 of the enable level pulse m corresponding to the second brightness level L2 can be greater than the pulse width W3 of the enable level pulse m corresponding to the first brightness level L1.

[0162] Thus, when the brightness level corresponds to a higher brightness, by increasing the pulse width of the enable level pulse of the light emission control signal, the duty cycle of the light emission control signal can be increased, thereby meeting the brightness requirements of different brightness levels, such as enabling the first brightness level to reach the desired first target brightness, enabling the second brightness level to reach the desired second target brightness, and the second target brightness being greater than the first target brightness.

[0163] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 25 , Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 25 The provided display device 1000 includes the display panel 40 provided in any of the above embodiments of this application. Figure 25 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 40 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 40 in the above embodiments. These descriptions will not be repeated here.

[0164] It should be understood that the top view structure and timing of the display panel provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0165] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0166] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, One display cycle of the display panel includes N subframes, and at least one of the N subframes is a target subframe; The display panel includes multiple partitions arranged along a first direction, each partition including at least one pixel circuit. Within the target subframe, the light emission control signal received by one pixel circuit in the partition includes M enable level pulses, where M is an integer greater than 1. The plurality of partitions include a first partition and a second partition. Within the target subframe, the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition and the q-th enable level pulse in the light emission control signal received by the pixel circuit in the second partition at least partially overlap in time, where p ≠ q, 1 ≤ p ≤ M, 1 ≤ q ≤ M, and p and q are both integers. The plurality of partitions includes a third partition, and the first partition and the second partition are separated by the third partition; Within the target subframe, the M enable level pulses in the light emission control signal received by the pixel circuit in the third partition do not overlap in time with the p-th enable level pulse in the light emission control signal received by the pixel circuit in the first partition.

2. The display panel according to claim 1, characterized in that, The plurality of partitions includes at least one fourth partition; The time interval during which the p-th enable level pulse and the q-th enable level pulse overlap is the target time interval; During the target time period, one of the enable level pulses of the light emission control signal received by the pixel circuit in the fourth partition at least partially overlaps with the p-th enable level pulse in time.

3. The display panel according to claim 2, characterized in that, Along the first direction, the fourth partition is located on the side of the second partition away from the first partition, and the minimum interval between the first partition and the second partition is the same as the minimum interval between the second partition and the fourth partition.

4. The display panel according to claim 3, characterized in that, The partition includes at least one row of the pixel circuit, and the number of rows of the pixel circuit between the first partition and the second partition is the same as the number of rows of the pixel circuit between the second partition and the fourth partition.

5. The display panel according to claim 2, characterized in that, The plurality of partitions includes a plurality of the fourth partitions, and adjacent two fourth partitions are separated by at least one partition. During the target time period, the order of the enable level pulses that at least partially overlap with the p-th enable level pulse in time is different in different fourth partitions.

6. The display panel according to claim 1, characterized in that, At least one of the N subframes is a fixed target subframe; Within the fixed target subframe, the light emission control signal received by the pixel circuit in the partition includes one enable level pulse, and the duty cycle of the light emission control signal received by the pixel circuit in the partition is less than a first preset threshold. Within the fixed target subframe, the plurality of partitions sequentially receive the enable level pulse.

7. The display panel according to claim 1, characterized in that, The target subframe includes a first target subframe and a second target subframe, wherein the first target subframe and the second target subframe are different subframes; Within the first target subframe, the duty cycle of the light emission control signal received by the pixel circuit in the partition is the first duty cycle, and the light emission control signal received by one pixel circuit in the partition includes M1 enable level pulses; Within the second target subframe, the duty cycle of the light emission control signal received by the pixel circuit in the partition is the second duty cycle. The light emission control signal received by one pixel circuit in the partition includes M2 enable level pulses. The first duty cycle is different from the second duty cycle. M1 ≠ M2. M1 and M2 are both integers greater than 1.

8. The display panel according to claim 7, characterized in that, The pulse width of the enable level pulse in the second target subframe is the same as the pulse width of the enable level pulse in the first target subframe, or the pulse width of the enable level pulse in the second target subframe is different from the pulse width of the enable level pulse in the first target subframe.

9. The display panel according to claim 7, characterized in that, The first duty cycle is less than the second duty cycle, and M1 is less than M2.

10. The display panel according to claim 9, characterized in that, The pulse width of the enable level pulse in the second target subframe is greater than or equal to the pulse width of the enable level pulse in the first target subframe.

11. The display panel according to claim 1, characterized in that, The target subframe includes a first target subframe and a second target subframe. Within the first target subframe, the light emission control signal received by a pixel circuit in the partition includes M1 enable level pulses. Within the second target subframe, the light emission control signal received by a pixel circuit in the partition includes M1 enable level pulses, where M1 is an integer greater than 1; The pulse width of the enable level pulse in the second target subframe is different from the pulse width of the enable level pulse in the first target subframe.

12. The display panel according to claim 11, characterized in that, Within the first target subframe, the duty cycle of the light emission control signal received by the pixel circuit in the partition is the first duty cycle; Within the second target subframe, the duty cycle of the light emission control signal received by the pixel circuit in the partition is the second duty cycle; The first duty cycle is less than the second duty cycle, and the pulse width of the enable level pulse in the second target subframe is greater than the pulse width of the enable level pulse in the first target subframe.

13. The display panel according to claim 1, characterized in that, The target subframe includes X different sub-target subframes, where X is an integer greater than or equal to 2. The duty cycles of the light emission control signals corresponding to at least two of the sub-target sub-frames are in different duty cycle ranges, and the number of enable level pulses corresponding to the different duty cycle ranges is different. The number of enable level pulses is the number of enable level pulses of the light emission control signal received by one pixel circuit of the partition within one of the sub-target sub-frames.

14. The display panel according to claim 1, characterized in that, The enable level pulses of the multiple partitions have the same pulse width.

15. The display panel according to claim 14, characterized in that, The time interval between two adjacent enable level pulses corresponding to the plurality of partitions is the same.

16. The display panel according to claim 15, characterized in that, The partition includes at least one row of pixel circuits, and each row of pixel circuits includes at least one pixel circuit arranged along a second direction, which intersects the first direction; The time interval is determined according to the following expression: Wherein, Δt represents the time difference between the start time of the first enable level pulse of the light emission control signal received by the pixel circuit in the i-th row within the same target subframe and the start time of the first enable level pulse of the light emission control signal received by the pixel circuit in the (i+1)-th row, i is a positive integer, k represents the row number of the pixel circuit between the two rows of sub-pixels where the enable level pulses overlap in time, and T represents the time interval.

17. The display panel according to claim 1, characterized in that, The pulse widths of the M enable level pulses are different.

18. The display panel according to claim 1, characterized in that, The time interval between any two adjacent enable level pulses in the M enable level pulses is different.

19. The display panel according to claim 1, characterized in that, The partition includes at least two rows of pixel circuits, and each row of pixel circuits includes at least one pixel circuit arranged along a second direction, which intersects the first direction; The kth enable level pulse of the light emission control signal received by the pixel circuits of two adjacent rows in the same partition overlaps at least partially in time, 1≤k≤M, where k is an integer.

20. The display panel according to claim 1, characterized in that, The partition includes at least one row of pixel circuits, and each row of pixel circuits includes at least one pixel circuit arranged along a second direction, which intersects the first direction; The plurality of partitions includes a first sub-partition and a second sub-partition, wherein the first sub-partition and the second sub-partition are adjacent but different partitions; The kth enable level pulse of the light emission control signal received by the pixel circuit in the last row of the first sub-partition and the kth enable level pulse of the light emission control signal received by the pixel circuit in the first row of the second sub-partition overlap at least partially in time, 1≤k≤M, where k is an integer.

21. The display panel according to claim 1, characterized in that, The partition includes multiple rows of the pixel circuits, and each row of the pixel circuits includes at least one pixel circuit arranged along a second direction, which intersects the first direction; The first partition includes the pixel circuits in row Z1, which receive Z1 light emission control signals, and the pixel circuits in row Z1 receive one light emission control signal. The p-th enable level pulses in the Z1 light emission control signals overlap in a first time period. The second partition includes the pixel circuits in row Z2, which receive Z2 light emission control signals, and the pixel circuits in row Z2 receive one light emission control signal. The qth enable level pulse in the Z2 light emission control signals overlaps in the second time period, and Z1 and Z2 are both integers greater than 1. The first time period and the second time period at least partially overlap.

22. The display panel according to claim 1, characterized in that, M includes M3 or M4; At the first brightness level, within the target subframe, the light emission control signal received by a pixel circuit in the partition includes M3 enable level pulses; At the second brightness level, within the target subframe, the light emission control signal received by a pixel circuit in the partition includes M4 enable level pulses; The first brightness level is different from the second brightness level, M3 ≠ M4.

23. The display panel according to claim 22, characterized in that, The pulse width of the enable level pulse corresponding to the second brightness level is different from the pulse width of the enable level pulse corresponding to the first brightness level, or the pulse width of the enable level pulse corresponding to the second brightness level is the same as the pulse width of the enable level pulse corresponding to the first brightness level.

24. The display panel according to claim 22, characterized in that, The second brightness level is greater than the first brightness level, and M4 is greater than M3.

25. The display panel according to claim 24, characterized in that, The pulse width of the enable level pulse corresponding to the second brightness level is greater than or equal to the pulse width of the enable level pulse corresponding to the first brightness level.

26. The display panel according to claim 1, characterized in that, At the first brightness level, within the target subframe, the light emission control signal received by a pixel circuit in the partition includes M enable level pulses; At the second brightness level, within the target subframe, the light emission control signal received by a pixel circuit in the partition includes M enable level pulses; The first brightness level is different from the second brightness level, and the pulse width of the enable level pulse of the light emission control signal of the first brightness level is different from the pulse width of the enable level pulse of the light emission control signal of the second brightness level.

27. The display panel according to claim 26, characterized in that, The second brightness level is greater than the first brightness level, and the pulse width of the enable level pulse corresponding to the second brightness level is greater than the pulse width of the enable level pulse corresponding to the first brightness level.

28. A display device, characterized in that, Includes the display panel as described in any one of claims 1-27.

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