A shift register unit, a gate driving circuit and a display device

Abstract

The application provides a shift register unit, a gate drive circuit and a display device. The shift register unit comprises an input module, a first control module, a second control module, a third control module, a first output module, a second output module, a first capacitor, a second capacitor and a third capacitor; wherein the input module controls the potential of a first node, the first control module controls the potential of a second node, and the second control module and the third control module control the potential of a third node; one end of the first capacitor is connected to the first node; one end of the second capacitor is connected to the second node; and one end of the third capacitor is connected to the third node. The shift register unit provided by the application optimizes the voltage waveform of the first node, and further optimizes the output signal waveform of the shift register unit, thereby avoiding abnormal output of the shift register unit signal and abnormal display of the picture.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to a shift register unit, a gate driving circuit, and a display device. Background Technology

[0002] The display device includes not only a display panel, but also a gate driving circuit (also called a row driving circuit) and a source driving circuit (also called a column driving circuit) that control the display of the display panel, which have a pixel array. The display panel uses a row-by-row scanning display method, in which the gate driving circuit is used to generate scanning signals to turn on each row of pixels in sequence, while the source driving circuit is used to provide data signals to a row of pixels when it is turned on to realize the display of the pixels.

[0003] The gate drive circuit includes a shift register, which contains multiple cascaded shift register units. Each shift register unit typically consists of several transistors. By inputting a clock signal and an input signal (i.e., a start pulse signal) to the circuit, it outputs a level signal at the output terminal.

[0004] A shift register unit is disclosed in Chinese patent CN105741749B. Figure 1 The diagram shows the voltage waveform of the fourth node N4 in the shift register unit of patent CN105741749B, with the horizontal axis representing time and the vertical axis representing voltage. Figure 1 As shown, the voltage at node N4 will switch between high and low levels with the clock signal c1, synchronously forming the upward and downward waveforms shown in the dashed box. There is a risk point in this circuit: when the downward pull of the clock signal c1 is too large, it will cause transistor M2 to turn on abnormally, resulting in abnormal output of the shift register unit's output signal, thus causing abnormal display of the screen. Summary of the Invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a shift register unit, a gate driving circuit and a display device. The provided shift register unit can optimize the waveform of the output signal, avoid abnormal output of the shift register unit signal and avoid abnormal display of the display screen.

[0006] This invention provides a shift register unit, comprising: An input module is used to transmit the input signal to the first node in response to a first clock signal; A first control module is configured to transmit a first voltage signal to a second node in response to a first clock signal; and to transmit the first clock signal to the second node in response to a signal at the input terminal. The second control module is used to transmit the first voltage signal to the third node in response to the second clock signal; The third control module is used to transmit the second voltage signal to the third node in response to the signal from the first node; The first output module is used to respond to the signal of the third node to transmit the second voltage signal to the output terminal; The second output module is used to respond to the signal of the first node to transmit the first voltage signal to the output terminal; The first capacitor is connected between the first node and the second voltage signal lead; The second capacitor is connected between the second clock signal lead and the second node; The third capacitor is connected between the second voltage signal lead and the third node.

[0007] In some embodiments, the input module includes a first transistor, the control terminal of the first transistor is connected to a first clock signal lead, a first terminal of the first transistor is connected to the input terminal, and a second terminal of the first transistor is connected to the first node.

[0008] In some embodiments, the input module further includes a second transistor, the control terminal of the second transistor being connected to a first voltage signal lead, the first terminal of the second transistor being connected to the second terminal of the first transistor, and the second terminal of the second transistor being connected to the first node.

[0009] In some embodiments, the input module includes a third transistor, the control terminal of which is connected to the second node, the first terminal of which is connected to the second voltage signal lead, and the second terminal of which is connected to the first terminal of the first capacitor.

[0010] In some embodiments, the input module further includes a fourth transistor and a fifth transistor, wherein the control terminal of the fourth transistor is connected to the second clock signal lead, the first terminal of the fourth transistor is connected to the second voltage signal lead, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor; The control terminal of the fifth transistor is connected to the second node, and the second terminal of the fifth transistor is connected to the first node.

[0011] In some embodiments, the first control module includes a sixth transistor, the control terminal of the sixth transistor is connected to a first clock signal lead, the first terminal of the sixth transistor is connected to a first voltage signal lead, and the second terminal of the sixth transistor is connected to the second node.

[0012] In some embodiments, the first control module further includes a seventh transistor, the control terminal of which is connected to the first voltage signal lead, the first terminal of which is connected to the second node, and the second terminal of which is connected to the second terminal of the second capacitor.

[0013] In some embodiments, the first control module further includes an eighth transistor, the control terminal of which is connected to the input terminal, the first terminal of which is connected to the first clock signal lead, and the second terminal of which is connected to the second node.

[0014] In some embodiments, the second control module includes a ninth transistor, the control terminal of the ninth transistor being connected to the first terminal of the second capacitor and to the second clock signal lead, the first terminal of the ninth transistor being connected to the first voltage signal lead, and the second terminal of the ninth transistor being connected to the third node.

[0015] In some embodiments, the second control module further includes a tenth transistor, the control terminal of which is connected to the second terminal of the second capacitor, the first terminal of which is connected to the second terminal of the ninth transistor, and the second terminal of which is connected to the third node.

[0016] In some embodiments, the third control module includes an eleventh transistor, the control terminal of which is connected to the first node, the first terminal of which is connected to the second voltage signal lead, and the second terminal of which is connected to the third node.

[0017] In some embodiments, a twelfth transistor is further included, wherein the control terminal of the twelfth transistor is connected to the first node, the first terminal of the twelfth transistor is connected to the second clock signal lead, and the second terminal of the twelfth transistor is connected to the first terminal of the first capacitor.

[0018] In some embodiments, the first output module includes a thirteenth transistor, the control terminal of the thirteenth transistor is connected to the third node, the first terminal of the thirteenth transistor is connected to the second voltage signal lead, and the second terminal of the thirteenth transistor is connected to the output terminal; The second output module includes a fourteenth transistor, the control terminal of which is connected to the first node, the first terminal of which is connected to a first voltage signal lead, and the second terminal of which is connected to the output terminal.

[0019] This invention also provides a gate driving circuit, including the shift register unit described above.

[0020] This invention also provides a display device, including the gate driving circuit described above.

[0021] The shift register unit, gate driving circuit, and display device provided by this invention have the following advantages: The shift register unit provided by this invention optimizes the voltage waveform of the first node, thereby optimizing the output signal waveform of the shift register unit, avoiding abnormal output of the shift register unit signal, and avoiding abnormal display of the screen. Attached Figure Description

[0022] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0023] Figure 1 This is a voltage waveform diagram of the fourth node of a shift register unit in the prior art; Figure 2 This is a circuit diagram of a shift register unit provided in an embodiment of the present invention; Figure 3 This is a timing diagram of a shift register unit according to an embodiment of the present invention; Figures 4 to 9 yes Figure 2 A schematic diagram showing the circuit control of the shift register unit in each step; Figure 10 yes Figure 2 The output signal waveform of the first node N1 in the shift register unit; Figure 11 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention; Figure 12 yes Figure 11 The signal waveform output by the gate drive circuit; Figure 13 This is a circuit diagram of a shift register unit according to another embodiment of the present invention. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. The words “or” and “or” in the specification may mean “and” or “or”.

[0025] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0026] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0027] The transistors used in the embodiments of this invention can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their characteristics, transistors can be classified into N-type and P-type; the following embodiments use P-type transistors for illustration. In the embodiments of this invention, the control terminal is the source, the first terminal is the source, and the second terminal is the drain. When a low level is input to the gate of the P-type transistor, the source and drain are turned on. It should be noted that, in the embodiments of this invention, assuming all transistors are P-type, the operating level refers to the effective level at which the P-type transistor is turned on, i.e., a low level; the non-operating level refers to a high level.

[0028] To address the problems of existing technologies, this invention provides a shift register unit, such as... Figure 2 As shown, the shift register unit includes: The input module is used to transmit the input signal STE to the first node N1 in response to the first clock signal CKE1. A first control module is configured to transmit a first voltage signal VEE to a second node N2 in response to the first clock signal CKE1; and to transmit the first clock signal CKE1 to the second node N2 in response to the input signal STE. The second control module is used to transmit the first voltage signal VEE to the third node N3 in response to the second clock signal CKE2. The third control module is used to respond to the signal of the first node N1 to transmit the second voltage signal VDD to the third node N3; The first output module is used to respond to the signal of the third node N3 to transmit the second voltage signal VDD to the output terminal; The second output module is used to respond to the signal of the first node N1 to transmit the first voltage signal VEE to the output terminal; The first capacitor C1 is connected between the first node N1 and the second voltage signal lead; The second capacitor C2 is connected between the second clock signal lead and the second node; The third capacitor C3 is connected between the second voltage signal lead and the third node.

[0029] Among them, the first voltage signal VEE is a low-level signal, the second voltage signal VDD is a high-level signal, and the first clock signal and the second clock signal are pulse signals with the same frequency but opposite phase.

[0030] Please continue reading. Figure 2 Specifically, the input module includes a first transistor T1, the control terminal of the first transistor T1 is connected to a first clock signal lead, the first terminal of the first transistor T1 is connected to the input terminal, and the second terminal of the first transistor T1 is connected to the first node N1.

[0031] The input module further includes a second transistor T2, the control terminal of the second transistor T2 is connected to the first voltage signal lead, the first terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the second terminal of the second transistor T2 is connected to the first node N1.

[0032] The input module includes a third transistor T3, the control terminal of which is connected to the second node, the first terminal of which is connected to the second voltage signal lead, and the second terminal of which is connected to the first terminal of the first capacitor C1.

[0033] The input module further includes a fourth transistor T4 and a fifth transistor T5. The control terminal of the fourth transistor T4 is connected to the second clock signal lead, the first terminal of the fourth transistor T4 is connected to the second voltage signal lead, and the second terminal of the fourth transistor T4 is connected to the first terminal of the fifth transistor T5. The control terminal of the fifth transistor T5 is connected to the second node N2, and the second terminal of the fifth transistor T5 is connected to the first node N1.

[0034] The first control module includes a sixth transistor T6. The control terminal of the sixth transistor T6 is connected to the first clock signal lead, the first terminal of the sixth transistor T6 is connected to the first voltage signal lead, and the second terminal of the sixth transistor T6 is connected to the second node N2.

[0035] The first control module further includes a seventh transistor T7, the control terminal of the seventh transistor T7 is connected to the first voltage signal lead, the first terminal of the seventh transistor T7 is connected to the second node N2, and the second terminal of the seventh transistor T7 is connected to the second terminal of the second capacitor C2.

[0036] The first control module further includes an eighth transistor T8, the control terminal of which is connected to the input terminal, the first terminal of which is connected to the first clock signal lead, and the second terminal of which is connected to the second node N2.

[0037] The second control module includes a ninth transistor T9. The control terminal of the ninth transistor T9 is connected to the first terminal of the second capacitor C2 and to the second clock signal lead. The first terminal of the ninth transistor T9 is connected to the first voltage signal lead, and the second terminal of the ninth transistor T9 is connected to the third node N3.

[0038] The second control module also includes a tenth transistor T10. The control terminal of the tenth transistor T10 is connected to the second terminal of the second capacitor C2 and the second terminal of the seventh transistor T7. The first terminal of the tenth transistor T10 is connected to the second terminal of the ninth transistor T9. The second terminal of the tenth transistor T10 is connected to the third node N3.

[0039] The third control module includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the first node N1, the first terminal of the eleventh transistor T11 is connected to the second voltage signal lead, and the second terminal of the eleventh transistor T11 is connected to the third node N3.

[0040] The shift register unit also includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is connected to the first node N1. The first terminal of the twelfth transistor T12 is connected to the second clock signal lead. The second terminal of the twelfth transistor T12 is connected to the first terminal of the first capacitor C1.

[0041] The first output module includes a thirteenth transistor T13. The control terminal of the thirteenth transistor T13 is connected to the third node N3. The first terminal of the thirteenth transistor T13 is connected to the second voltage signal lead. The second terminal of the thirteenth transistor T13 is connected to the output terminal. The second output module includes a fourteenth transistor T14, the control terminal of the fourteenth transistor T14 is connected to the first node N1, the first terminal of the fourteenth transistor T14 is connected to the first voltage signal lead, and the second terminal of the fourteenth transistor T14 is connected to the output terminal.

[0042] Figure 3 The timing diagram of the shift register unit is shown, combined with... Figure 3 The working principle of the shift register unit is explained. It should be noted that, for ease of understanding, high-level signals are represented by "H" and low-level signals by "L" in the accompanying diagram.

[0043] Figure 4 This diagram illustrates the on / off switching of the circuitry within the shift register unit during the first step (Step 1) operation. Figure 4As shown, the input signal STE is high, the first clock signal CKE1 is low, and the second clock signal CKE2 is high. When STE is high, the eighth transistor T8 is off; when CKE2 is high, the fourth transistor T4 and the ninth transistor T9 are off. When CKE1 is low, the first transistor T1 and the sixth transistor T6 are on; the first voltage signal VEE is continuously low, therefore, the second transistor T2 and the seventh transistor T7 are always on. With the first transistor T1 and the second transistor T2 on, the high-level input signal STE is transmitted to the first node N1 through the first transistor T1 and the second transistor T2. At this time, the first node N1 is high, and the high level of the first node N1 keeps the twelfth transistor T12 and the fourteenth transistor T14 off during this stage. The sixth transistor T6 and the seventh transistor T7 are turned on. The first voltage signal VEE is transmitted to the second node N2 through the sixth transistor T6 and the seventh transistor T7. The second node N2 is connected to the second terminal of the second capacitor C2. The second clock signal CKE2 is connected to the first terminal of the second capacitor C2. Under the action of the second clock signal CKE2 and the first voltage signal VEE, the second capacitor C2 is charged. The first terminal of the second capacitor C2 is at a high level, and the second terminal of the second capacitor C2 is at a low level. When the second node N2 is at a low level, the third transistor T3, the fifth transistor T5, and the tenth transistor T10 are turned on. The second voltage signal VDD is transmitted to the first terminal of the first capacitor C1 through the third transistor T3. At this time, both the first terminal and the second terminal of the first capacitor C1 are at a high level. In the previous moment, the thirteenth transistor T13 was in the off state. Therefore, in Step 1, neither the first output module nor the second output module of the shift register unit has a signal output, and the output signal Eout remains at the low potential of the previous moment.

[0044] Figure 5This diagram illustrates the on / off control of the circuit within the shift register unit during Step 2. At this moment, the first clock signal CKE1 is high, the second clock signal CKE2 is low, the input signal STE is high, and the second node N2 remains low due to the action of the second capacitor C2. Similar to Step 1, when the first clock signal CKE1 is high, the first transistor T1 and the sixth transistor T6 are off; when STE is high, the eighth transistor T8 is off. When the second clock signal CKE2 and the second node N2 are low, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are on, and the second voltage signal VDD is transmitted to the first node N1. The first node N1 may remain high at this time, thus the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are off. Under the influence of the second clock signal CKE2 and the low level of the second node N2, the first voltage signal VEE is transmitted to the third node N3, the third capacitor C3 is charged, the first terminal of the third capacitor C3 is at a high level, the second terminal of the third capacitor C3 is at a low level, the third node N3 is at a low potential, the thirteenth transistor T13 is turned on, the second voltage signal VDD is transmitted to the output terminal through the thirteenth transistor T13, and the output signal Eout outputs a high level signal VDD.

[0045] In Step 2, the potential of the first node N1, which controls the fourteenth transistor T14 to turn on, will continuously receive a high-level signal VDD transmitted through the fourth transistor T4 and the fifth transistor T5. The first terminal of the first capacitor C1 will also continuously transmit a high-level signal VDD through the third transistor T3. Therefore, when the first node N1 is working in Step 2, it will remain at a high level without any pull-down effect, and the fourteenth transistor can be controlled to remain in the off state in Step 2.

[0046] Figure 6This diagram illustrates the on / off control of the circuit within the shift register unit during Step 3. At this moment, the first clock signal CKE1 is low, the second clock signal CKE2 is high, and the input signal STE is high; the working principle is the same as in Step 1, and will not be repeated here. At this moment, transistors T1, T2, T3, T5, T6, T7, T10, and T13 are turned on, while transistors T4, T8, T9, T11, T12, and T14 are turned on. The high-level input signal STE is transmitted to the first node N1 through transistors T1 and T2. The potential of the second node N2 is low, and the potential of the third node N3 is low due to the action of the third capacitor C3. Therefore, the second voltage signal VDD is transmitted to the output terminal through the thirteenth transistor, and the output signal Eout is a high-level signal VDD.

[0047] The first node N1 remains at a high level throughout the Step 3 phase and is not affected by pull-down, which can control the fourteenth transistor to remain in the off state throughout the Step 3 phase.

[0048] Figure 7 This diagram illustrates the on / off control of the circuit within the shift register unit during Step 4. At this moment, the first clock signal CKE1 is high, the second clock signal CK2 is low, and the input signal STE is high, operating on the same principle as in Step 1, and will not be repeated here. At this moment, transistors T2, T3, T4, T5, T7, T9, T10, T12, and T13 are turned on; transistors T1, T6, T8, T11, and T14 are turned off. At this moment, a high-level signal VDD is continuously output to the first node N1 through transistors T4 and T5. The potential of the second node N2 and the third node N3 is low. The second voltage signal VDD is transmitted to the output terminal through the thirteenth transistor T13, and the output signal Eout is a high-level signal VDD.

[0049] The first node N1 remains at a high level throughout the Step 4 phase and is not affected by pull-down, which can control the fourteenth transistor to remain in the off state throughout the Step 4 phase.

[0050] Figure 8This diagram illustrates the on / off control of the circuit within the shift register unit during Step 5. At this moment, the first clock signal CKE1 is low, the second clock signal CKE2 is high, and the input signal STE is low. The principle is the same as in Step 1, and will not be repeated here. At this moment, transistors T1, T2, T3, T5, T6, T7, T8, T10, T11, T12, and T14 are turned on, while transistors T4, T9, and T13 are turned off. Simultaneously, node N1 is low, node N2 is low, and node N3 is high; the first voltage signal VEE is transmitted to the output terminal through transistor T14, and the output signal Eout is a low-level signal VEE.

[0051] Figure 9 This diagram illustrates the on / off control of the circuit within the shift register unit during Step 6. At this moment, the first clock signal CKE1 is high, the second clock signal CKE2 is low, and the input signal STE is low. The principle is the same as in Step 1, and will not be repeated here. At this moment, transistors T1, T3, T5, T6, T10, and T13 are off, while transistors T2, T4, T7, T8, T9, T11, T12, and T14 are on. At this moment, node N1 is low, node N2 is high, node N3 is high, and the first voltage signal VEE is transmitted to the output terminal through transistor T14. The output signal Eout is a low-level signal VEE.

[0052] The shift register unit repeats steps 5 and 6 in the subsequent working steps, which will not be described in detail here, until the next frame of the screen begins to be displayed, at which point steps 1 to 4 are restarted.

[0053] To further explore the technical effects of the shift register unit provided in this embodiment of the invention, a simulation experiment was conducted to test the voltage waveform of the first node N1 during operation. Figure 10 The voltage waveform of the first node N1 during the operating phase is shown. Figure 10 As shown, during the stage where the shift register unit outputs a high-level signal ( Figure 10As shown in the dashed box, the voltage waveform output by the first node N1 does not show a significant pull-down waveform, therefore it will not cause the fourteenth transistor T14 to turn on abnormally, and will not cause the shift register unit to output abnormal signals.

[0054] like Figure 11 As shown, this embodiment of the invention also provides a gate driving circuit, including the shift register unit as described above. Multiple shift register units are electrically connected in a cascaded manner. The input terminal in of the first-stage shift register unit is connected to the start pulse signal STE. Except for the last-stage shift register unit, the output terminal out of each of the other shift register units is connected to the input terminal in of the next-stage shift register unit.

[0055] Specifically, Figure 11 Taking a four-stage cascaded shift register unit as an example, the input signal STE at the input terminal in of the first-stage shift register unit SR1 is the start pulse signal; the output signal Eout1 at the output terminal out of the first-stage shift register unit SR1 is used as the input signal of the second-stage shift register unit SR2, and the output terminal out of the first-stage shift register unit SR1 is connected to the input terminal in of the second-stage shift register unit SR2; the output signal Eout2 at the second-stage shift register unit SR2 is used as the input signal of the third-stage shift register unit SR3, and the output terminal out of the second-stage shift register unit SR2 is connected to the input terminal in of the third-stage shift register unit SR3; the output signal Eout3 at the third-stage shift register unit SR3 is used as the input signal of the fourth-stage shift register unit SR4, and the output terminal out of the third-stage shift register unit SR3 is connected to the input terminal in of the fourth-stage shift register unit SR4… and so on, forming a gate drive circuit.

[0056] like Figure 11As shown, the gate drive circuit further comprises a clock signal generating unit (not shown in the figure), wherein the clock signal generating unit is configured to generate a first clock signal CKE1 and a second clock signal CKE2. Specifically, the first clock signal CKE1 and the second clock signal CKE2 in the first-stage shift register unit SR1 are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal generating unit; the first clock signal CKE1 and the second clock signal CKE2 in the second-stage shift register unit SR2 are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal unit; the first clock signal CKE1 and the second clock signal CKE2 in the third-stage shift register unit SR3 are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal unit; the first clock signal CKE1 and the second clock signal CKE2 in the fourth-stage shift register unit SR4 are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal unit; and so on, the first clock signal CKE1 and the second clock signal CKE2 in the n-th stage shift register unit SRn are respectively the first clock signal CKE1 and the second clock signal CKE2 generated by the clock signal unit; the first clock signal CKE1 and the second clock signal CKE2 of SRn+1 in the (n+1)-th stage shift register unit are respectively the second clock signal CKE2 and the first clock signal CKE1 generated by the clock signal generating unit.

[0057] Figure 12 shows Figure 11 is an output signal waveform diagram of four-stage shift register units in the gate drive circuit shown in, as Figure 12 shown, the voltage waveforms of the four-stage shift register units are output normally and have effective output, so abnormal display of a display screen will not be caused.

[0058] An embodiment of the present invention further provides a display device, comprising the gate drive circuit as described above, and turning on gate scan lines in the display device row by row by using a signal output from each shift register unit, that is, a signal output from an output signal terminal of each shift register unit is a gate scan line signal of each row of pixel units. Further, the display device further comprises a source drive circuit configured to provide data voltages to corresponding pixel units when the gate scan lines are turned on.

[0059] as shown in Figure 13 , another embodiment of the present invention provides a shift register unit. Compared with Figure 2 the shift register unit shown in Figure 13 , the shift register unit in eliminates the fourth transistor T4 and the fifth transistor T5, but can achieve the same function as Figure 2The shift register unit in the embodiment achieves the same technical effect, but due to the reduction in the number of transistors in the shift register unit, the circuit layout area is reduced, thereby reducing the size of the OLED screen bezel and achieving a narrow bezel effect for the display device.

[0060] The shift register unit, gate driving circuit, and display device provided by this invention have the following advantages: The shift register unit provided by this invention optimizes the voltage waveform of the first node, thereby optimizing the output signal waveform of the shift register unit, avoiding abnormal output of the shift register unit signal, and avoiding abnormal display of the screen.

[0061] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that, include: An input module is used to transmit an input signal to a first node in response to a first clock signal. The input module includes a third transistor, the control terminal of which is connected to a second node, the first terminal of which is connected to a second voltage signal lead, and the second terminal of which is connected to the first terminal of a first capacitor. The first control module is configured to transmit the first voltage signal to the second node in response to the first clock signal; The first control module also includes an eighth transistor, the control terminal of which is connected to the input terminal, the first terminal of which is connected to the first clock signal lead, and the second terminal of which is connected to the second node. The second control module is used to transmit the first voltage signal to the third node in response to the second clock signal; The third control module is used to transmit the second voltage signal to the third node in response to the signal from the first node; The first output module is used to respond to the signal of the third node to transmit the second voltage signal to the output terminal; The second output module is used to respond to the signal of the first node to transmit the first voltage signal to the output terminal; A first capacitor is connected between the first node and the second voltage signal lead, and the second end of the first capacitor is connected to the first node; The second capacitor is connected between the second clock signal lead and the second node; The third capacitor is connected between the second voltage signal lead and the third node; The twelfth transistor has its control terminal connected to the first node, its first terminal connected to the second clock signal lead, and its second terminal connected to the first terminal of the first capacitor.

2. The shift register unit according to claim 1, characterized in that, The input module includes a first transistor, the control terminal of the first transistor is connected to a first clock signal lead, the first end of the first transistor is connected to the input terminal, and the second end of the first transistor is connected to the first node.

3. The shift register unit according to claim 2, characterized in that, The input module further includes a second transistor, the control terminal of which is connected to a first voltage signal lead, the first terminal of which is connected to the second terminal of the first transistor, and the second terminal of which is connected to the first node.

4. The shift register unit according to claim 1, characterized in that, The input module further includes a fourth transistor and a fifth transistor. The control terminal of the fourth transistor is connected to the second clock signal lead, the first terminal of the fourth transistor is connected to the second voltage signal lead, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor. The control terminal of the fifth transistor is connected to the second node, and the second terminal of the fifth transistor is connected to the first node.

5. The shift register unit according to claim 1, characterized in that, The first control module includes a sixth transistor, the control terminal of which is connected to the first clock signal lead, the first terminal of which is connected to the first voltage signal lead, and the second terminal of which is connected to the second node.

6. The shift register unit according to claim 5, characterized in that, The first control module further includes a seventh transistor, the control terminal of which is connected to the first voltage signal lead, the first terminal of which is connected to the second node, and the second terminal of which is connected to the second terminal of the second capacitor.

7. The shift register unit according to claim 1, characterized in that, The second control module includes a ninth transistor. The control terminal of the ninth transistor is connected to the first terminal of the second capacitor and to the second clock signal lead. The first terminal of the ninth transistor is connected to the first voltage signal lead, and the second terminal of the ninth transistor is connected to the third node.

8. The shift register unit according to claim 7, characterized in that, The second control module further includes a tenth transistor, the control terminal of which is connected to the second terminal of the second capacitor, the first terminal of which is connected to the second terminal of the ninth transistor, and the second terminal of which is connected to the third node.

9. The shift register unit according to claim 8, characterized in that, The third control module includes an eleventh transistor, the control terminal of which is connected to the first node, the first terminal of which is connected to the second voltage signal lead, and the second terminal of which is connected to the third node.

10. The shift register unit according to claim 1, characterized in that, The first output module includes a thirteenth transistor, the control terminal of which is connected to the third node, the first terminal of which is connected to the second voltage signal lead, and the second terminal of which is connected to the output terminal. The second output module includes a fourteenth transistor, the control terminal of which is connected to the first node, the first terminal of which is connected to a first voltage signal lead, and the second terminal of which is connected to the output terminal.

11. A gate driving circuit, characterized in that, Includes the shift register unit as described in any one of claims 1-10.

12. A display device, characterized in that, Includes the gate drive circuit as described in claim 11.

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